Transistor and preparation method thereof
By forming an MgN surface treatment layer and an Mg-doped GaN nucleation layer on the surface of the buffer layer, the current leakage problem caused by buffer layer defects is solved, and the reliability and stability of the transistor are significantly improved.
Patent Information
- Application Number
- CN202411970208.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-30
- Publication Date
- 2025-05-09
AI Technical Summary
In the prior art, the defect density of the buffer layer is high, which easily leads to ions diffusion in the substrate, causing current leakage, and reducing the reliability of the transistor.
The surface treatment layer is formed on the surface of the buffer layer as MgN, and the first nucleation layer is stacked in sequence as Mg-doped GaN nucleation layer and the second nucleation layer as GaN nucleation layer, forming a Mg/MgN dense layer, dividing the influence of the oxygen or nitrogen layer, improving ion diffusion, and providing a unified N hanging bond for facilitating GaN epitaxial growth.
It significantly improves the current leakage phenomenon, improves the reliability of the transistor, forms a high-quality high-resistance layer, weakens the possibility of charge filling under dynamic operation, and improves the stability and reliability of the device.
Smart Images
Figure CN119967848A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a transistor and a method for preparing the same. Background Art
[0002] Gallium nitride is widely used in semiconductors, such as transistors.
[0003] The related art provides a transistor structure, including a buffer layer, a nucleation layer, a channel layer and a barrier layer. The buffer layer, the nucleation layer, the channel layer and the barrier layer are stacked in sequence.
[0004] In the related art, the buffer layer has a high defect density, which makes it easy for ions in the substrate to diffuse into it, resulting in current leakage and reducing the reliability of the transistor. Summary of the invention
[0005] The disclosed embodiment provides a transistor and a method for manufacturing the same, which can significantly improve the current leakage phenomenon and enhance the reliability. The technical solution is as follows:
[0006] In one aspect, a transistor is provided, comprising:
[0007] A buffer layer, a surface treatment layer, a first nucleation layer, a second nucleation layer, a channel layer and a barrier layer;
[0008] The surface treatment layer is located on the surface of the buffer layer, the first nucleation layer, the second nucleation layer, the channel layer and the barrier layer are sequentially stacked on the surface treatment layer, the surface treatment layer is a MgN layer, the first nucleation layer is a Mg-doped GaN nucleation layer, and the second nucleation layer is a GaN nucleation layer.
[0009] Optionally, the thickness of the surface treatment layer is 1 to 10 nm.
[0010] Optionally, the doping concentration of Mg ions in the first nucleation layer is 1×10 17 ~1×10 18 cm -3 .
[0011] Optionally, along the direction from the surface treatment layer to the second nucleation layer, the doping concentration of Mg ions in the first nucleation layer gradually decreases.
[0012] Optionally, the thickness of the first nucleation layer is 100-500 nm, and the thickness of the second nucleation layer is 1-2 μm.
[0013] In another aspect, a method for manufacturing a transistor includes:
[0014] Making a buffer layer;
[0015] Making a surface treatment layer on the buffer layer, wherein the surface treatment layer is a MgN layer;
[0016] Fabricating a first nucleation layer on the surface treatment layer, wherein the first nucleation layer is a Mg-doped GaN nucleation layer;
[0017] Fabricating a second nucleation layer on the first nucleation layer, wherein the second nucleation layer is a GaN nucleation layer;
[0018] forming a channel layer on the second nucleation layer;
[0019] A barrier layer is formed on the channel layer.
[0020] Optionally, a surface treatment layer is formed on the buffer layer, comprising:
[0021] Under the condition of a growth temperature of 800-1000° C., the buffer layer is subjected to Mg ion surface treatment to obtain the surface treatment layer.
[0022] Optionally, forming a first nucleation layer on the surface treatment layer comprises:
[0023] Under the condition of a growth temperature of 1000-1100° C., a first nucleation layer with a thickness of 100-500 nm is grown.
[0024] Optionally, the doping concentration of Mg ions in the first nucleation layer is 1×10 17 ~1×10 18 cm -3 .
[0025] Optionally, along the direction from the surface treatment layer to the second nucleation layer, the doping concentration of Mg ions in the first nucleation layer gradually decreases.
[0026] The technical solution provided by the embodiments of the present disclosure brings the following beneficial effects:
[0027] In the disclosed embodiment, a surface treatment layer is formed on the surface of the buffer layer, the surface treatment layer is a layer of MgN, a first nucleation layer and a second nucleation layer are sequentially stacked on the surface treatment layer, the first nucleation layer is a Mg-doped GaN nucleation layer, and the second nucleation layer is a GaN nucleation layer. The first nucleation layer and the surface treatment layer form a Mg / MgN dense layer, which on the one hand spatially separates the influence of the oxygen layer or the nitrogen layer on the epitaxial layer (channel layer and barrier layer), and improves the leakage caused by ion diffusion; on the other hand, it provides a unified N hanging bond to facilitate the subsequent GaN epitaxial growth. In addition, the incorporation of Mg has a certain delayed effect, which will compensate a certain number of electrons in the GaN epitaxial layer to form a high-quality high-resistance layer. The doping amount of Mg is less than that of conventional C and Fe doping, which reduces the possibility of charge filling under dynamic operation, and the stability and reliability of the device operation are better. BRIEF DESCRIPTION OF THE DRAWINGS
[0028] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.
[0029] Figure 1 is a schematic structural diagram of a transistor provided by an embodiment of the present disclosure;
[0030] Figure 2 is a schematic structural diagram of a transistor provided by an embodiment of the present disclosure;
[0031] Figure 3 is a flow chart of a transistor manufacturing method provided by an embodiment of the present disclosure;
[0032] Figure 4 is a flow chart of another transistor manufacturing method provided by an embodiment of the present disclosure;
[0033] Figure 5 It is a schematic diagram of ion diffusion after adding a surface treatment layer and a first nucleation layer provided in an embodiment of the present disclosure;
[0034] Figure 6 It is a schematic diagram of the leakage of transistors at different voltages provided by the related technology;
[0035] Figure 7 It is a schematic diagram of the leakage condition of the transistor provided by the embodiment of the present disclosure at different voltages.
[0036] The reference numerals are as follows:
[0037] 100: substrate; 101: buffer layer; 102: surface treatment layer; 103: first nucleation layer; 104: second nucleation layer; 105: channel layer; 106: barrier layer; 107: P-GaN layer; 108: first electrode; 109: second electrode; 110: control electrode; 111: passivation layer;
[0038] 201: Mg ion. DETAILED DESCRIPTION
[0039] In order to make the objectives, technical solutions and advantages of the present disclosure more clear, the embodiments of the present disclosure will be further described in detail below with reference to the accompanying drawings.
[0040] Figure 1 is a schematic diagram of the structure of a transistor provided by an embodiment of the present disclosure. Figure 1The transistor includes: a buffer layer 101 , a surface treatment layer 102 , a first nucleation layer 103 , a second nucleation layer 104 , a channel layer 105 and a barrier layer 106 .
[0041] Among them, the surface treatment layer 102 is located on the surface of the buffer layer 101, the first nucleation layer 103, the second nucleation layer 104, the channel layer 105 and the barrier layer 106 are stacked on the surface treatment layer 102 in sequence, the surface treatment layer 102 is a MgN layer, the first nucleation layer 103 is a Mg-doped GaN nucleation layer, and the second nucleation layer 104 is a GaN nucleation layer.
[0042] In the disclosed embodiment, a surface treatment layer is formed on the surface of the buffer layer, the surface treatment layer is a layer of MgN, a first nucleation layer and a second nucleation layer are sequentially stacked on the surface treatment layer, the first nucleation layer is a Mg-doped GaN nucleation layer, and the second nucleation layer is a GaN nucleation layer. The first nucleation layer and the surface treatment layer form a Mg / MgN dense layer, which on the one hand spatially separates the influence of the oxygen layer or the nitrogen layer on the epitaxial layer (channel layer and barrier layer), and improves the leakage caused by ion diffusion; on the other hand, it provides a unified N hanging bond to facilitate the subsequent GaN epitaxial growth. In addition, the incorporation of Mg has a certain delayed effect, which will compensate a certain number of electrons in the GaN epitaxial layer to form a high-quality high-resistance layer. The doping amount of Mg is less than that of conventional C and Fe doping, which reduces the possibility of charge filling under dynamic operation, and the stability and reliability of the device operation are better.
[0043] Figure 2 is a schematic diagram of the structure of a transistor provided by an embodiment of the present disclosure. Figure 2 The transistor may further include a substrate 100 , a buffer layer 101 , a surface treatment layer 102 , a first nucleation layer 103 , a second nucleation layer 104 , a channel layer 105 and a barrier layer 106 which are sequentially stacked on the substrate 100 .
[0044] In the embodiment of the present disclosure, the substrate 100 may be a single crystal substrate or a composite substrate, and may have a size of 2 to 8 inches.
[0045] Exemplarily, the substrate 100 is a single crystal substrate with a size of 5 inches.
[0046] In the embodiment of the present disclosure, the substrate 100 may be a Si substrate or a sapphire substrate.
[0047] Exemplarily, the substrate 100 is a sapphire substrate.
[0048] In the embodiment of the present disclosure, the buffer layer 101 may be an AlGaN buffer layer, and the thickness of the buffer layer 101 may be 10-50 nm.
[0049] Exemplarily, the thickness of the buffer layer 101 is 30 nm.
[0050] In the embodiment of the present disclosure, the thickness of the surface treatment layer 102 may be 1-10 nm.
[0051] In this implementation, a surface treatment layer of the above thickness is selected to be grown on the buffer layer, which can satisfy the aforementioned anti-diffusion function and will not cause the overall size of the transistor to be too large due to the layer being too thick.
[0052] Exemplarily, the thickness of the surface treatment layer 102 is 5 nm.
[0053] In the embodiment of the present disclosure, the doping concentration of Mg ions in the first nucleation layer 103 may be 1×10 17 ~1×10 18 cm -3 .
[0054] In this implementation, the first nucleation layer with the above-mentioned doping concentration is selected, and Mg ions can be introduced to provide holes to compensate for excess electrons to form high resistance and reduce leakage, making the transistor more stable under long-term power operation conditions.
[0055] In the embodiment of the present disclosure, the doping concentration of Mg ions in the first nucleation layer 103 gradually decreases along the direction from the surface treatment layer 102 to the second nucleation layer 104, so that the transition from Mg-doped GaN to GaN can be more natural.
[0056] For example, along the direction from the surface treatment layer 102 to the second nucleation layer 104, the doping concentration of Mg ions in the first nucleation layer 103 increases from 1×10 18 cm -3 Gradually reduced to 1×10 17 cm -3 .
[0057] In other examples, along the direction from the surface treatment layer 102 to the second nucleation layer 104 , the doping concentration of Mg ions in the first nucleation layer 103 may also gradually increase or remain constant, and the present disclosure does not limit this.
[0058] For example, the doping concentration of Mg ions is kept at 1×10 17 cm -3 constant.
[0059] In the embodiment of the present disclosure, the thickness of the first nucleation layer 103 may be 100-500 nm.
[0060] In this implementation, the first nucleation layer of the above thickness can form a Mg / MgN dense layer with the surface treatment layer, thereby reducing the risk of leakage and preventing the overall size of the transistor from being too large due to the layer being too thick.
[0061] Exemplarily, the thickness of the first nucleation layer 103 is 300 nm.
[0062] In the embodiment of the present disclosure, the second nucleation layer 104 may be a GaN layer, that is, a non-doped GaN layer.
[0063] In the embodiment of the present disclosure, the thickness of the second nucleation layer 104 may be 1-2 um.
[0064] In this implementation, the second nucleation layer of the above thickness is used, which can improve the film stress condition and enhance the crystal quality, while also preventing the overall size of the transistor from being too large due to the layer being too thick.
[0065] Exemplarily, the thickness of the second nucleation layer 104 is 2 um.
[0066] In the embodiment of the present disclosure, the transistor may also include a P-GaN layer 107, a first electrode 108, a second electrode 109, a control electrode 110 and a passivation layer 111, the P-GaN layer 107 is located on the barrier layer 106, the passivation layer 111 covers the barrier layer 106 and the P-GaN layer 107, the first electrode 108 and the second electrode 109 are connected to the barrier layer 106 through the passivation layer 111, and the control electrode 110 is connected to the P-GaN layer 107 through the passivation layer 111.
[0067] In the embodiment of the present disclosure, the channel layer 105 may be a GaN channel layer, and the thickness of the channel layer 105 may be 100-500 nm.
[0068] Exemplarily, the thickness of the channel layer 105 is 300 nm.
[0069] In the embodiment of the present disclosure, the barrier layer 106 may be an AlGaN barrier layer, and the thickness of the barrier layer 106 may be 20-30 nm.
[0070] Exemplarily, the thickness of the barrier layer 106 is 25 nm.
[0071] In the embodiment of the present disclosure, the molar amount of Al in the barrier layer 106 is 0.2-0.3.
[0072] Exemplarily, the molar amount of Al in the barrier layer 106 is 0.25.
[0073] In the embodiment of the present disclosure, the thickness of the P-GaN layer 107 may be 1-5 nm.
[0074] Exemplarily, the thickness of the P-GaN layer 107 is 3 nm.
[0075] In the embodiment of the present disclosure, one of the first electrode 108 and the second electrode 109 is a source electrode, and the other is a drain electrode; the control electrode 110 is a gate electrode.
[0076] In the embodiment of the present disclosure, the passivation layer 111 may be a silicon oxide, silicon nitride, gallium nitride or aluminum nitride layer.
[0077] By way of example, the passivation layer 111 may be a silicon oxide layer.
[0078] Figure 3 is a flow chart of a transistor manufacturing method provided by an embodiment of the present disclosure. Figure 3 The method steps include:
[0079] S11. Making a buffer layer.
[0080] In the embodiment of the present disclosure, the growth temperature of the buffer layer may be 500-700°C.
[0081] Exemplarily, the growth temperature of the buffer layer may be 600°C.
[0082] In the embodiment of the present disclosure, the buffer layer may be an AlGaN buffer layer, and the thickness of the buffer layer may be 10 to 50 nm.
[0083] Exemplarily, the thickness of the buffer layer is 30 nm.
[0084] S12, making a surface treatment layer on the buffer layer, wherein the surface treatment layer is a MgN layer.
[0085] In the disclosed embodiment, the buffer layer is subjected to Mg ion surface treatment at a growth temperature of 800 to 1000° C. to obtain the surface treated layer. The surface treated layer prepared under the above conditions can increase the hole mobility of GaN-based semiconductor devices and improve device performance.
[0086] Exemplarily, under the condition of a growth temperature of 900° C., the buffer layer is subjected to Mg ion surface treatment to obtain the surface treated layer.
[0087] In the embodiment of the present disclosure, the thickness of the surface treatment layer may be 1-10 nm.
[0088] In this implementation, a surface treatment layer of the above thickness is selected to be grown on the buffer layer, which can satisfy the aforementioned anti-diffusion function and will not cause the overall size of the transistor to be too large due to the layer being too thick.
[0089] Exemplarily, the thickness of the surface treatment layer is 5 nm.
[0090] S13, making a first nucleation layer on the surface treatment layer, the first nucleation layer being a Mg-doped GaN nucleation layer.
[0091] In the embodiment of the present disclosure, under the condition of a growth temperature of 1000-1100° C., a first nucleation layer with a thickness of 100-500 nm is grown.
[0092] In this implementation, the first nucleation layer manufactured under the above conditions can form a Mg / MgN dense layer with the surface treatment layer to improve the stability of the transistor.
[0093] In the embodiment of the present disclosure, the doping concentration of Mg ions in the first nucleation layer 103 may be 1×10 17 ~1×10 18 cm -3 .
[0094] In this implementation, the first nucleation layer with the above-mentioned doping concentration is selected, and Mg ions can be introduced to provide holes to compensate for excess electrons to form high resistance and reduce leakage, making the transistor more stable under long-term power operation conditions.
[0095] In the embodiment of the present disclosure, the doping concentration of Mg ions in the first nucleation layer gradually decreases along the direction from the surface treatment layer to the second nucleation layer, which can make the transition from Mg-doped GaN to GaN more natural.
[0096] For example, along the direction from the surface treatment layer to the second nucleation layer, the doping concentration of Mg ions in the first nucleation layer increases from 1×10 18 cm -3 Gradually reduced to 1×10 17 cm -3 .
[0097] In other examples, along the direction from the surface treatment layer to the second nucleation layer, the doping concentration of Mg ions in the first nucleation layer can also be gradually increased or kept constant. 17 cm -3 This disclosure is not intended to be limiting.
[0098] S14, fabricating a second nucleation layer on the first nucleation layer, wherein the second nucleation layer is a GaN nucleation layer.
[0099] In the embodiment of the present disclosure, the growth temperature of the second nucleation layer may be 900-1100°C.
[0100] Exemplarily, the growth temperature of the second nucleation layer is 1000°C.
[0101] In the embodiment of the present disclosure, the thickness of the second nucleation layer may be 1-2 um.
[0102] S15, forming a channel layer on the second nucleation layer.
[0103] In the embodiment of the present disclosure, the channel layer may be a GaN channel layer, and the thickness of the channel layer may be 100 to 500 nm.
[0104] Exemplarily, the thickness of the channel layer is 300 nm.
[0105] S16. Fabricating a barrier layer on the channel layer.
[0106] In the embodiment of the present disclosure, the barrier layer may be an AlGaN barrier layer, and the thickness of the barrier layer may be 20-30 nm.
[0107] Exemplarily, the thickness of the barrier layer is 25 nm.
[0108] In the embodiment of the present disclosure, the molar amount of Al in the barrier layer is 0.2-0.3.
[0109] Exemplarily, the molar amount of Al in the barrier layer is 0.25.
[0110] In the disclosed embodiment, a surface treatment layer is formed on the surface of the buffer layer, the surface treatment layer is a layer of MgN, a first nucleation layer and a second nucleation layer are sequentially stacked on the surface treatment layer, the first nucleation layer is a Mg-doped GaN nucleation layer, and the second nucleation layer is a GaN nucleation layer. The first nucleation layer and the surface treatment layer form a Mg / MgN dense layer, which on the one hand spatially separates the influence of the oxygen layer or the nitrogen layer on the epitaxial layer (channel layer and barrier layer), and improves the leakage caused by ion diffusion; on the other hand, it provides a unified N hanging bond to facilitate the subsequent GaN epitaxial growth. In addition, the incorporation of Mg has a certain delayed effect, which will compensate a certain number of electrons in the GaN epitaxial layer to form a high-quality high-resistance layer. The doping amount of Mg is less than that of conventional C and Fe doping, which reduces the possibility of charge filling under dynamic operation, and the stability and reliability of the device operation are better.
[0111] Figure 4 is a flow chart of another transistor manufacturing method provided by an embodiment of the present disclosure. Figure 4 The method steps include:
[0112] S21. Provide a substrate and process the substrate.
[0113] In the embodiment of the present disclosure, the substrate may be a single crystal substrate or a composite substrate, and the size may be 2 to 8 inches.
[0114] Exemplarily, the substrate is a single crystal substrate with a size of 5 inches.
[0115] In the embodiment of the present disclosure, the substrate may be a Si substrate or a sapphire substrate.
[0116] Exemplarily, the substrate is a sapphire substrate.
[0117] In the disclosed embodiment, under pure H2 atmosphere, the temperature is controlled at 1000-1100°C and the cleaning time is 5-10 minutes.
[0118] Exemplarily, under pure H2 atmosphere conditions, the temperature is controlled at 1050°C and the cleaning time is 8 minutes.
[0119] S22, making a buffer layer on the substrate.
[0120] In the embodiment of the present disclosure, step S22 may include:
[0121] The buffer layer is produced by physical vapor deposition (PVD), metal-organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), hydride vapor phase epitaxy (HVPE), liquid phase epitaxy (LPE), atomic layer deposition (ALD) or pulsed laser deposition (PLD).
[0122] Exemplarily, the buffer layer is manufactured by MOCVD.
[0123] In the embodiment of the present disclosure, the growth temperature of the buffer layer may be 500-700°C.
[0124] Exemplarily, the growth temperature of the second buffer layer is 600°C.
[0125] In the embodiment of the present disclosure, the buffer layer may be an AlGaN buffer layer, and the thickness of the buffer layer may be 10 to 50 nm.
[0126] Exemplarily, the thickness of the buffer layer is 30 nm.
[0127] S23, manufacturing a surface treatment layer on the buffer layer, wherein the surface treatment layer is a MgN layer.
[0128] In the disclosed embodiment, the buffer layer is subjected to Mg ion surface treatment at a growth temperature of 800 to 1000° C. to obtain the surface treated layer.
[0129] The surface treatment layer made under the above conditions can make the first nucleation layer and the surface treatment layer form a Mg / MgN dense layer, spatially dividing the influence of the oxygen layer or nitrogen layer on the epitaxial layer (channel layer and barrier layer), and improving the leakage caused by ion diffusion.
[0130] Exemplarily, under the condition of a growth temperature of 900° C., the buffer layer is subjected to Mg ion surface treatment to obtain the surface treated layer.
[0131] In the embodiment of the present disclosure, the thickness of the surface treatment layer may be 1-10 nm.
[0132] In this implementation, a surface treatment layer of the above thickness is selected to be grown on the buffer layer, which can satisfy the aforementioned anti-diffusion function and will not cause the overall size of the transistor to be too large due to the layer being too thick.
[0133] Exemplarily, the thickness of the surface treatment layer is 5 nm.
[0134] S24, making a first nucleation layer on the surface treatment layer, the first nucleation layer being a Mg-doped GaN layer.
[0135] In the disclosed embodiment, under the condition of growth temperature of 1000-1100° C., a first nucleation layer with a thickness of 100-500 nm is grown.
[0136] Exemplarily, under the condition of a growth temperature of 1050° C., a first nucleation layer with a thickness of 300 nm is grown.
[0137] In this implementation, the first nucleation layer manufactured under the above conditions can form a Mg / MgN dense layer with the surface treatment layer, thereby reducing the risk of leakage and improving the stability of the transistor.
[0138] In the embodiment of the present disclosure, the doping concentration of Mg ions in the first nucleation layer can be 1×10 17 ~1×10 18 cm -3 .
[0139] In this implementation, the first nucleation layer with the above-mentioned doping concentration is selected, and Mg ions can be introduced to provide holes to compensate for excess electrons to form high resistance and reduce leakage, making the transistor more stable under long-term power operation conditions.
[0140] In the embodiment of the present disclosure, the doping concentration of Mg ions in the first nucleation layer gradually decreases along the direction from the surface treatment layer to the second nucleation layer, which can make the transition from Mg-doped GaN to GaN more natural.
[0141] For example, along the direction from the surface treatment layer to the second nucleation layer, the doping concentration of Mg ions in the first nucleation layer increases from 1×10 18 cm -3 Gradually reduced to 1×10 17 cm -3 .
[0142] In other examples, along the direction from the surface treatment layer to the second nucleation layer, the doping concentration of Mg ions in the first nucleation layer may gradually increase or remain constant, and the present disclosure does not limit this.
[0143] For example, the doping concentration of Mg ions is kept at 1×10 17 cm -3 constant.
[0144] In the embodiment of the present disclosure, the thickness of the first nucleation layer may be 100-500 nm.
[0145] In this implementation, the first nucleation layer of the above thickness is used to form a dense Mg / MgN layer with the surface treatment layer to reduce the risk of leakage, and the overall size of the transistor will not be too large due to the layer being too thick.
[0146] Exemplarily, the thickness of the first nucleation layer is 300 nm.
[0147] Figure 5 Schematic diagram of ion diffusion after adding the surface treatment layer and the first nucleation layer provided in the embodiment of the present disclosure. Figure 5 The transistor provided in the embodiment of the present disclosure adopts a surface treatment layer and a first nucleation layer. While preventing ion diffusion, Mg ions can be introduced to provide holes to compensate for excess electrons to form high resistance and reduce leakage, making the transistor more stable under long-term power working conditions.
[0148] S25, forming a second nucleation layer on the first nucleation layer, wherein the second nucleation layer is a GaN layer.
[0149] In the embodiment of the present disclosure, the growth temperature of the second nucleation layer may be 900-1100°C.
[0150] Exemplarily, the growth temperature of the second nucleation layer is 1000°C.
[0151] In the embodiment of the present disclosure, the thickness of the second nucleation layer may be 1-2 um.
[0152] S26, forming a channel layer on the second nucleation layer.
[0153] In the embodiment of the present disclosure, the channel layer may be a GaN channel layer, and the thickness of the channel layer may be 100 to 500 nm.
[0154] Exemplarily, the thickness of the channel layer is 300 nm.
[0155] S27. Fabricate a barrier layer on the channel layer.
[0156] In the embodiment of the present disclosure, the barrier layer may be an AlGaN barrier layer, and the thickness of the barrier layer may be 20-30 nm.
[0157] Exemplarily, the thickness of the barrier layer is 25 nm.
[0158] In the embodiment of the present disclosure, the molar amount of Al in the barrier layer is 0.2-0.3.
[0159] Exemplarily, the molar amount of Al in the barrier layer is 0.25.
[0160] S28. Fabricate a P-GaN layer on the barrier layer.
[0161] In one example, step S28 includes:
[0162] The first step is to make P-GaN thin film.
[0163] In the embodiment of the present disclosure, the thickness of the P-GaN film may be 1 to 5 nm.
[0164] Exemplarily, the thickness of the P-GaN film is 3 nm.
[0165] In the second step, the P-GaN film is patterned to obtain a P-GaN layer.
[0166] In the embodiment of the present disclosure, patterning the P-GaN film may include: forming a patterned mask layer on the surface of the P-GaN film; and etching the P-GaN film under the protection of the mask layer to form a P-GaN layer.
[0167] S29. Fabricate a passivation layer on the P-GaN layer.
[0168] In the embodiment of the present disclosure, the passivation layer may be a silicon oxide, silicon nitride, gallium nitride or aluminum nitride passivation layer.
[0169] Exemplarily, the passivation layer may be a silicon oxide passivation layer.
[0170] S30, etching the passivation layer to form a through hole.
[0171] In the embodiment of the present disclosure, a patterned mask layer is formed on the surface of the passivation layer; under the protection of the mask layer, a first through hole and a second through hole are made, the first through hole etches the passivation layer to form a through hole extending to the barrier layer. The second through hole passes through the passivation layer to form a through hole extending to the P-GaN layer.
[0172] S31, manufacturing a first electrode and a second electrode.
[0173] In the embodiment of the present disclosure, the first electrode and the second electrode are connected to the barrier layer through the first through hole.
[0174] In the embodiment of the present disclosure, one of the first electrode and the second electrode is a source electrode, and the other is a drain electrode.
[0175] S32. Make a control electrode.
[0176] The control electrode is connected to the P-GaN layer through the second through hole.
[0177] In the embodiment of the present disclosure, the control electrode is a gate.
[0178] After fabrication, the transistors are tested for resistance, capacitance, current, and voltage.
[0179] Figure 6 It is a schematic diagram of the leakage of transistors at different voltages provided by the relevant technology. Figure 7 Schematic diagram of the leakage of transistors under different voltages provided by the embodiment of the present disclosure. Figure 6 and Figure 7 , the horizontal axis is voltage, the unit is V, and the vertical axis is leakage current, the unit is A.
[0180] from Figure 6 It can be seen from the figure that the drain current (ID) and gate current (IGG) of the transistor provided by the related art have a leakage current greater than 1uA at 1400V. Figure 7 It can be seen that the drain current (ID) of the transistor provided in the disclosed embodiment is only 10nA at 1400V and does not break down. The transistor structure provided in the disclosed embodiment has a better breakdown voltage than the related art, a reduced gate leakage current is beneficial to device performance, and a better dynamic resistance performance.
[0181] The above description is only an optional embodiment of the present disclosure and is not intended to limit the present disclosure. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present disclosure shall be included in the protection scope of the present disclosure.
Claims
1. A transistor, characterized in that: The transistor comprises: a buffer layer (101), a surface treatment layer (102), a first nucleation layer (103), a second nucleation layer (104), a channel layer (105) and a barrier layer (106); The surface treatment layer (102) is located on the surface of the buffer layer (101); the first nucleation layer (103), the second nucleation layer (104), the channel layer (105) and the barrier layer (106) are sequentially stacked on the surface treatment layer (102); the surface treatment layer (102) is a MgN layer; the first nucleation layer (103) is a Mg-doped GaN nucleation layer; and the second nucleation layer (104) is a GaN nucleation layer.
2. The transistor according to claim 1, characterized in that The thickness of the surface treatment layer (102) is 1-10 nm.
3. The transistor according to claim 1 or 2, characterized in that: The doping concentration of Mg ions in the first nucleation layer (103) is 1×10 17 ~1×10 18 cm -3 .
4. The transistor according to claim 3, characterized in that Along the direction from the surface treatment layer (102) to the second nucleation layer (104), the doping concentration of Mg ions in the first nucleation layer (103) gradually decreases.
5. The transistor according to claim 3, characterized in that The thickness of the first nucleation layer (103) is 100-500 nm, and the thickness of the second nucleation layer (104) is 1-2 μm.
6. A method for preparing a transistor, characterized in that: The transistor preparation method comprises: Making a buffer layer; Making a surface treatment layer on the buffer layer, wherein the surface treatment layer is a MgN layer; Fabricating a first nucleation layer on the surface treatment layer, wherein the first nucleation layer is a Mg-doped GaN nucleation layer; Fabricating a second nucleation layer on the first nucleation layer, wherein the second nucleation layer is a GaN nucleation layer; forming a channel layer on the second nucleation layer; A barrier layer is formed on the channel layer.
7. The transistor manufacturing method according to claim 6, characterized in that: Producing a surface treatment layer on the buffer layer, comprising: Under the condition of a growth temperature of 800-1000° C., the buffer layer is subjected to Mg ion surface treatment to obtain the surface treatment layer.
8. The transistor manufacturing method according to claim 6, characterized in that: Producing a first nucleation layer on the surface treatment layer, comprising: Under the condition of a growth temperature of 1000-1100° C., a first nucleation layer with a thickness of 100-500 nm is grown.
9. The transistor manufacturing method according to claim 8, characterized in that: The doping concentration of Mg ions in the first nucleation layer is 1×10 17 ~1×10 18 cm -3 .
10. The transistor manufacturing method according to claim 9, characterized in that: Along the direction from the surface treatment layer to the second nucleation layer, the doping concentration of Mg ions in the first nucleation layer gradually decreases.