Multi-step and V-shaped groove gate gallium nitride P-channel field effect transistor and preparation method thereof

Abstract

The invention provides a multi-step and V-shaped groove gate gallium nitride P-channel field effect transistor and a preparation method thereof, and relates to the technical field of semiconductor devices. Comprising a substrate layer, a buffer layer, a barrier layer, a channel layer and a cap layer which are sequentially arranged from bottom to top, the groove extends downwards from the middle area of the upper surface of the cap layer and penetrates through the cap layer into the channel layer, and the shape of the groove is a multi-step groove, a V-shaped groove or an inverted trapezoidal groove; the source electrode is formed on the cap layer on one side of the groove; the drain electrode is formed on the cap layer on the other side of the groove; and the gate electrode is formed in the groove and is in contact with the channel layer. By adopting the multi-step groove gate, the V-shaped groove gate and the inverted trapezoidal groove gate, the electric field distribution between the gate electrode and the drain electrode can be optimized, the local high electric field is relieved, and the application range of the device in the high-voltage and high-power application field is widened; on the basis of realizing the enhanced P-channel field effect transistor, the output current is increased, and the performance and reliability of the P-channel field effect transistor in high-frequency and high-power application are improved.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor devices, and in particular to a multi-step and V-shaped groove gate gallium nitride P-channel field effect transistor and a preparation method thereof. Background Art

[0002] Gallium nitride (GaN) has the unique advantages of large bandgap, high electron drift velocity, high thermal conductivity, high temperature and high pressure resistance, which makes the integrated electronic devices made of GaN resistant to radiation and high temperature, and has the characteristics of high frequency, high power and high density. Integrated electronic devices made of GaN can be used to prepare radio frequency and power devices. Compared with GaN enhanced N-channel high-speed electron mobility transistor (HEMT), the research and development of GaN enhanced P-channel devices is relatively slow, which restricts the widespread application of all-GaN material complementary metal-oxide-semiconductor (CMOS) technology. The advantages of GaN devices such as high breakdown voltage, stronger radiation resistance and low switching loss are difficult to fully play.

[0003] In key areas such as power electronics and energy conversion, GaN materials have become key materials for solving device reliability issues in high-voltage, high-frequency, and high-power applications due to their excellent high breakdown voltage characteristics. High breakdown voltage can effectively prevent premature breakdown of devices during operation and extend their service life. However, due to the short gate-drain spacing of traditional gallium nitride P-channel field-effect transistors (PFETs), the peak electric field is concentrated in the area close to the gate when the device is operating at high voltage, increasing the risk of device breakdown. In addition, the enhanced device with a single dielectric groove gate structure has a deep groove depth, resulting in a large on-resistance, causing a large power loss when the device is on, and the increase in the device operating temperature affects its performance and reliability in high-frequency, high-power applications. Summary of the invention

[0004] The purpose of the embodiments of the present invention is to provide a step and V-groove gate gallium nitride P-channel field effect transistor and a preparation method thereof, which solves the problem that the peak electric field is concentrated in the area close to the gate, increasing the risk of device breakdown, and the increase in the device operating temperature affects its performance and reliability in high-frequency, high-power applications.

[0005] To solve the above technical problems, the embodiments of the present invention provide the following technical solutions:

[0006] A first aspect of the present invention provides a multi-step and V-shaped groove gate gallium nitride P-channel field effect transistor, comprising a substrate layer, a buffer layer, a barrier layer, a channel layer and a cap layer arranged in sequence from bottom to top;

[0007] A groove extending downward from the middle area of ​​the upper surface of the cap layer and penetrating the cap layer into the channel layer, wherein the shape of the groove is a multi-step groove, a V-shaped groove or an inverted trapezoidal groove;

[0008] A source electrode is formed on the cap layer at one side of the groove;

[0009] a drain electrode formed on the cap layer on the other side of the groove;

[0010] A gate electrode is formed in the groove and contacts the channel layer, wherein the level of the upper surface of the gate electrode is lower than the level of the upper surface of the channel layer.

[0011] In some modified embodiments of the first aspect of the present invention, the width of each step of the multi-step groove is the same, and the inclination angles of the V-shaped groove and the inverted trapezoidal groove are both greater than 0° and less than 90°.

[0012] In some modified implementations of the first aspect of the present invention, the material of the buffer layer is GaN material, and the thickness is 1 to 10 μm.

[0013] In some modified implementations of the first aspect of the present invention, the material of the barrier layer is AlGaN material, the Al component in the AlGaN material is 5% to 30%, and the thickness of the barrier layer is 5 to 30 nm.

[0014] In some modified embodiments of the first aspect of the present invention, the channel layer is a p-type GaN channel layer, the doping ions of the p-type GaN channel layer are Mg ions, and the doping concentration of Mg ions in the p-type GaN channel layer is 5×10 18 ~5×10 19 cm -3 , the thickness of the p-type GaN channel layer is 50nm~100nm.

[0015] In some modified embodiments of the first aspect of the present invention, the cap layer is a p-type heavily doped GaN channel layer, the doping ions of the p-type heavily doped GaN channel layer are Mg ions, and the doping concentration of Mg ions in the p-type heavily doped GaN channel layer is 1×10 19 ~1×10 20 cm -3 , thickness is 5nm~30nm.

[0016] In some modified implementations of the first aspect of the present invention, the materials of the source electrode and the drain electrode are both Ni / Au metal.

[0017] In some modified embodiments of the first aspect of the present invention, the material of the gate electrode is W / Au or Ti / Au metal.

[0018] A second aspect of the present invention provides a method for preparing a multi-step and V-groove gate gallium nitride P-channel field effect transistor, comprising:

[0019] Obtaining an epitaxial wafer, the epitaxial wafer comprising a substrate layer, a buffer layer, a barrier layer, a channel layer and a cap layer stacked in sequence from bottom to top;

[0020] Depositing metal on the upper surface of the cap layer to form a source electrode and a drain electrode, wherein the source electrode is located at an edge region on one side of the upper surface of the cap layer, and the drain electrode is located at an edge region on the other side of the upper surface of the cap layer;

[0021] Etching downward from the upper surface of the cap layer outside the source electrode and the drain electrode region to the upper surface of the channel layer;

[0022] Etching is performed multiple times downward from the upper surface of the channel layer to form a multi-step groove, and the width of each etching is the same;

[0023] A metal is deposited in the bottom of the multi-step groove to form a gate electrode.

[0024] In a third aspect of the present invention, a method for preparing a multi-step and V-shaped groove gate gallium nitride P-channel field effect transistor is provided, comprising:

[0025] Obtaining an epitaxial wafer, the epitaxial wafer comprising a substrate layer, a buffer layer, a barrier layer, a channel layer and a cap layer stacked in sequence from bottom to top;

[0026] Coating an SOG film on the upper surface of the cap layer to form a hard mask layer, and coating a photoresist layer on both side edge regions of the hard mask layer;

[0027] Removing part of the hard mask layer to form a hard mask layer with an inclination, and removing the photoresist layer, wherein the inclination angle of the hard mask layer with an inclination is greater than 0° and less than 90°;

[0028] Etching away a portion of the hard mask layer and the cap layer until it reaches the channel layer to form a V-shaped groove or an inverted trapezoidal groove;

[0029] Depositing metal on the upper surface of the cap layer to form a source electrode and a drain electrode, wherein the source electrode is located at an edge region on one side of the upper surface of the cap layer, and the drain electrode is located at an edge region on the other side of the upper surface of the cap layer;

[0030] Metal is deposited at the bottom of the V-shaped groove or the inverted trapezoidal groove to form a gate electrode.

[0031] Compared with the prior art, the present invention provides a multi-step and V-groove gate gallium nitride P-channel field effect transistor and a preparation method thereof, wherein the multi-step and V-groove gate gallium nitride P-channel field effect transistor comprises a substrate layer, a buffer layer, a barrier layer, a channel layer and a cap layer arranged in sequence from bottom to top; a groove extending downward from the middle area of ​​the upper surface of the cap layer and penetrating the cap layer into the channel layer, and the shape of the groove is a multi-step groove, a V-shaped groove or an inverted trapezoidal groove; a source electrode formed on the cap layer on one side of the groove; a drain electrode formed on the cap layer on the other side of the groove; a gate electrode formed in the groove and in contact with the channel layer, and a horizontal plane where the upper surface of the gate electrode is located is lower than a horizontal plane where the upper surface of the channel layer is located. In this way, the use of multi-step groove gate, V-shaped groove gate and inverted trapezoidal groove gate can optimize the electric field distribution between the gate and the drain, alleviate the local high electric field, and broaden the application of the device in high voltage and high power applications; through multi-step groove gate, V-shaped groove gate and inverted trapezoidal groove gate, on the basis of realizing enhanced P-channel field effect transistor, the output current is increased, the on-resistance is reduced, and the power loss of the P-channel field effect transistor in the on state is reduced, thereby improving the performance and reliability of the P-channel field effect transistor in high frequency and high power applications. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] By reading the detailed description below with reference to the accompanying drawings, the above and other objects, features and advantages of the exemplary embodiments of the present invention will become readily understood. In the accompanying drawings, several embodiments of the present invention are shown in an exemplary and non-limiting manner, and the same or corresponding reference numerals represent the same or corresponding parts, wherein:

[0033] Figure 1 The structure of a multi-step and V-groove gate GaN P-channel field effect transistor is schematically shown;

[0034] Figure 2 Schematic diagram of the preparation method of multi-step and V-groove gate GaN P-channel field effect transistor Figure 1 .

[0035] Figure 3 Schematic diagram showing the preparation process of multi-step and V-groove gate GaN P-channel field effect transistor Figure 1 ;

[0036] Figure 4 Schematic diagram of the preparation method of multi-step and V-groove gate GaN P-channel field effect transistor Figure 2 ;

[0037] Figure 5 Schematic diagram showing the preparation process of multi-step and V-groove gate GaN P-channel field effect transistor Figure 2 .

[0038] Description of Reference Numerals

[0039] 1. Substrate layer; 2. Buffer layer; 3. Barrier layer; 4. Channel layer; 5. Cap layer; 6. Groove; 61. Multi-step groove; 62. V-shaped groove; 63. Inverted trapezoidal groove; 7. Source electrode; 8. Drain electrode; 9. Gate electrode; 10. Hard mask layer; 11. Photoresist layer. DETAILED DESCRIPTION

[0040] The exemplary embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present invention are shown in the accompanying drawings, it should be understood that the present invention can be implemented in various forms and should not be limited by the embodiments described herein. On the contrary, these embodiments are provided in order to enable a more thorough understanding of the present invention and to fully convey the scope of the present invention to those skilled in the art.

[0041] It should be noted that, unless otherwise specified, the technical terms or scientific terms used in the present invention should have the common meanings understood by those skilled in the art to which the present invention belongs.

[0042] The present invention is further described in detail below with reference to specific embodiments, but the embodiments of the present invention are not limited thereto.

[0043] Embodiment 1:

[0044] Figure 1 The structure of a multi-step and V-groove gate GaN P-channel field effect transistor is schematically shown, wherein: Figure 1 (a) is a multi-step recessed gate GaN P-channel field effect transistor. Figure 1 (b) is a V-shaped groove gate GaN P-channel field effect transistor. Figure 1 (c) is a GaN P-channel field effect transistor with an inverted trapezoidal groove 63 gate. Specifically, the GaN P-channel field effect transistor with multiple steps and V-shaped grooves comprises: a substrate layer 1, a buffer layer 2, a barrier layer 3, a channel layer 4 and a cap layer 5 arranged in sequence from bottom to top;

[0045] The groove 6 extends downward from the middle area of ​​the upper surface of the cap layer 5 and penetrates the cap layer 5 to the channel layer 4. The shape of the groove is a multi-step groove 61, a V-shaped groove 62 or an inverted trapezoidal groove 63;

[0046] A source electrode 7 is formed on the cap layer 5 at one side of the groove 6;

[0047] A drain electrode 8 is formed on the cap layer 5 at the other side of the groove 6;

[0048] The gate electrode 9 is formed in the groove 6 and contacts the channel layer 4 . The level of the upper surface of the gate electrode 9 is lower than the level of the upper surface of the channel layer 4 .

[0049] Specifically, the structure of the epitaxial wafer is a structure in which a substrate layer 1, a buffer layer 2, a barrier layer 3, a channel layer 4 and a cap layer 5 are stacked in sequence, and a source electrode 7 and a drain electrode 8 are deposited on the cap layer 5, and the contact type is an ohmic contact. The cap layer 5 in the area without deposited metal and a portion of the channel layer 4 are etched away to form a groove, and the shape of the groove is a multi-step groove 61, a V-shaped groove 62 or an inverted trapezoidal groove 63; metal is deposited at the bottom of the channel layer 4 exposed after etching to form a gate electrode 9, and the contact type is a Schottky contact, so that an enhanced groove gate structure is generated, and the groove gate structure includes a multi-step groove gate and a gate electrode 9, or a V-shaped groove gate and a gate electrode 9, or an inverted trapezoidal groove gate and a gate electrode 9.

[0050] The multi-step groove gate formed by the multi-step groove and the gate electrode 9, the V-shaped groove gate formed by the V-shaped groove 62 and the gate electrode 9, and the inverted trapezoidal groove 63 gate formed by the inverted trapezoidal groove 63 and the gate electrode 9,

[0051] The multi-step groove gate has different manufacturing processes from the V-shaped groove gate and the inverted trapezoidal groove gate, and the V-shaped groove gate and the inverted trapezoidal groove gate have the same manufacturing process. The number of steps of the multi-step groove 61 can be changed according to demand, and the number of steps of the multi-step groove 61 is not specifically limited here.

[0052] The material of the substrate layer 1 is Si, Al2O3 or SiC.

[0053] As an optional implementation, the width of each step of the multi-step groove 61 is the same, and the inclination angles of the V-shaped groove 62 and the inverted trapezoidal groove 63 are both greater than 0° and less than 90°.

[0054] Specifically, the inclination angles of the V-shaped groove 62 and the inverted trapezoidal groove 63 can be changed according to requirements, as long as the inclination angles of the V-shaped groove 62 and the inverted trapezoidal groove 63 are greater than 0° and less than 90°.

[0055] As an optional implementation, the buffer layer 2 is made of GaN material and has a thickness of 1 to 10 μm.

[0056] As an optional implementation, the material of the barrier layer 3 is AlGaN material, the Al component in the AlGaN material is 5% to 30%, and the thickness of the barrier layer 3 is 5 to 30 nm.

[0057] As an optional embodiment, the channel layer 4 is a p-type GaN channel layer 4, the doping ions of the p-type GaN channel layer 4 are Mg ions, and the doping concentration of Mg ions in the p-type GaN channel layer 4 is 5×10 18 ~5×10 19 cm -3 , the thickness of the p-type GaN channel layer 4 is 50 nm to 100 nm.

[0058] As an optional embodiment, the cap layer 5 is a p-type heavily doped GaN channel layer 4, the doping ions of the p-type heavily doped GaN channel layer 4 are Mg ions, and the doping concentration of Mg ions in the p-type heavily doped GaN channel layer 4 is 1×10 19 ~1×10 20 cm -3 , thickness is 5nm~30nm.

[0059] As an optional implementation, the source electrode 7 and the drain electrode 8 are both made of Ni / Au metal.

[0060] Specifically, Ni metal has a higher work function and can form an ohmic contact with the surface of the cap layer 5, which can reduce the contact resistance between the metal and the semiconductor, reduce heat accumulation and power consumption, and Au metal has good stability and conductivity, preventing oxidation of the underlying Ni metal.

[0061] As an optional implementation, the material of the gate electrode 9 is W / Au or Ti / Au metal.

[0062] Specifically, the gate electrode 9 is a metal with a relatively low work function, such as W / Au or Ti / Au metal, to ensure Schottky contact with the channel layer 4, deplete the two-position hole gas at the heterojunction interface under the gate, and form an enhancement mode device.

[0063] In summary, the multi-step and V-groove gate GaN enhancement-type P-channel field effect transistor is a lateral structure. The multi-step and V-groove gate GaN enhancement-type P-channel field effect transistor effectively solves the problem of low breakdown voltage of traditional GaN enhancement-type P-channel field effect transistors due to the short distance between the gate and the drain and the high electric field offset to the gate, while avoiding the defects of small output current and large on-resistance of traditional single dielectric groove devices.

[0064] Based on the above Figure 1It can be seen from the implementation method that the multi-step and V-shaped groove gate gallium nitride P-channel field effect transistor of the embodiment of the present invention includes a substrate layer 1, a buffer layer 2, a barrier layer 3, a channel layer 4 and a cap layer 5 arranged in sequence from bottom to top; the groove extends downward from the middle area of ​​the upper surface of the cap layer 5 and penetrates the cap layer 5 to the channel layer 4, and the shape of the groove is a multi-step groove 61, a V-shaped groove or an inverted trapezoidal groove 63; the source electrode 7 is formed on the cap layer 5 on one side of the groove; the drain electrode 8 is formed on the cap layer 5 on the other side of the groove; the gate electrode 9 is formed in the groove and contacts with the channel layer 4, and the horizontal plane where the upper surface of the gate electrode 9 is located is lower than the horizontal plane where the upper surface of the channel layer 4 is located. In this way, the use of multi-step groove gate, V-shaped groove gate and inverted trapezoidal groove gate can optimize the electric field distribution between the gate and the drain, alleviate the local high electric field, and broaden the application of the device in high voltage and high power applications; through the multi-step groove gate, V-shaped groove gate and inverted trapezoidal groove gate, the output current is increased, the on-resistance is reduced, and the power loss of the P-channel field effect tube in the on state is reduced on the basis of realizing the enhanced P-channel field effect tube, thereby improving the performance and reliability of the P-channel field effect tube in high frequency and high power applications.

[0065] Embodiment 2:

[0066] Figure 2 The process diagram schematically shows the method for preparing a multi-step and V-groove gate GaN P-channel field effect transistor according to an embodiment of the present invention. Figure 1 , see Figure 2 As shown, the method for preparing the multi-step and V-shaped groove gate gallium nitride P-channel field effect transistor may include:

[0067] S201, obtaining an epitaxial wafer.

[0068] The epitaxial wafer includes a substrate layer 1, a buffer layer 2, a barrier layer 3, a channel layer 4 and a cap layer 5 which are stacked in sequence from bottom to top.

[0069] The epitaxial wafer can be obtained by epitaxial growth through metal-organic chemical vapor deposition (MOCVD). The material of the substrate layer 1 is Si, Al 2 O 3 Or SiC material.

[0070] Specifically, Figure 3 Schematic diagram showing the preparation process of multi-step and V-groove gate GaN P-channel field effect transistor Figure 1 ,in, Figure 3 (a) is the structure of the epitaxial wafer. The organic cleaning of the epitaxial wafer and the removal of the surface oxide layer are performed. The structure of the epitaxial wafer is shown in FIG. Figure 3(a). Cleaning of epitaxial wafers can reduce the interference of oxidation and contamination on the subsequent process of the device and the impact on the performance of the device. First, the organic cleaning of the epitaxial wafer is carried out. The epitaxial material is immersed in an acetone solution and ultrasonically cleaned for 5 minutes to remove organic pollutants on the surface of the material. Then, it is placed in an isopropanol solution and ultrasonically cleaned for 5 minutes to effectively remove the residual acetone on the surface. The epitaxial wafer is then placed in deionized water to rinse and remove the isopropanol residue attached to the surface of the material. Finally, the surface of the material is blown dry with high-purity nitrogen to ensure that there is no residual liquid on the epitaxial wafer. Then, the epitaxial wafer is placed in a BOE solution with a concentration of 1:7 for 30 seconds to remove the surface oxide layer of the epitaxial wafer, and then rinsed with a large amount of deionized water. Finally, the deionized water on the surface of the wafer is blown dry with high-purity nitrogen to complete the entire cleaning process of the epitaxial wafer.

[0071] S202 , depositing metal on the upper surface of the cap layer 5 to form a source electrode 7 and a drain electrode 8 .

[0072] The source electrode 7 is located at an edge region on one side of the upper surface of the cap layer 5 , and the drain electrode 8 is located at an edge region on the other side of the upper surface of the cap layer 5 .

[0073] Specifically, Figure 3 Schematic diagram showing the preparation process of multi-step and V-groove gate GaN P-channel field effect transistor Figure 1 ,in, Figure 3 (b) is a schematic diagram of forming the source electrode 7 and the drain electrode 8. The surface of the cap layer 5 is coated, baked, exposed and developed. The regions of the source electrode 7 and the drain electrode 8 are defined by the photolithography process. Then, the Ni / Au metal is sputtered on the surface of the developed epitaxial wafer by the magnetron sputtering process. The residual glue and the metal in the remaining area are then removed by a stripping liquid. The epitaxial wafer is annealed at 450°C for 5 minutes in a nitrogen atmosphere using a rapid thermal annealing process. This treatment can reduce the influence of the gold-semiconductor contact interface state, and the source electrode 7 and the drain electrode 8 form a good ohmic contact with the surface of the cap layer 5, reducing the metal-semiconductor contact resistance.

[0074] S203 , etching downward from the upper surface of the cap layer 5 outside the source electrode 7 and the drain electrode 8 region to the upper surface of the channel layer 4 .

[0075] Specifically, Figure 3 Schematic diagram showing the preparation process of multi-step and V-groove gate GaN P-channel field effect transistor Figure 1 ,in, Figure 3 (c) is a schematic diagram of the structure of the device after etching the cap layer 5. The source and drain electrode 8 region is etched to remove the cap layer 5 so that the channel layer 4 is completely exposed and then cleaned with a stripping solution to remove residual glue.

[0076] S204 , etching is performed from the upper surface of the channel layer 4 downward for multiple times to form a multi-step groove 61 , and the width of each etching is the same.

[0077] Specifically, Figure 3 Schematic diagram showing the preparation process of multi-step and V-groove gate GaN P-channel field effect transistor Figure 1 ,in, Figure 3 (d) is a schematic diagram of forming a multi-step groove 61. The channel layer 4 is etched using multiple photolithography processes and multiple ICP dry etching technologies. The etching width is shortened equidistantly according to the number of steps and the step length, and the etching depth is increased equidistantly according to the number of steps and the step height, forming a multi-step groove 61.

[0078] S205 , depositing metal at the bottom of the multi-step groove 61 to form a gate electrode 9 .

[0079] Specifically, Figure 3 Schematic diagram showing the preparation process of multi-step and V-groove gate GaN P-channel field effect transistor Figure 1 ,in, Figure 3 (e) is a schematic diagram of forming a gate electrode 9. First, the epitaxial wafer is subjected to gate groove annealing in a nitrogen atmosphere at 450°C for 5 minutes, and then preheated in a tetramethylammonium hydroxide (TMAH) solution at 80°C for 10 minutes to repair interface damage in the etched area. Then, a metal, which may be W or Ti metal, is sputtered on the bottom surface of the gate area of ​​the multi-step groove 61 using a magnetron sputtering process to form a gate electrode 9.

[0080] Embodiment three:

[0081] Based on the second embodiment Figure 3 In this embodiment, a method for preparing a multi-step and V-shaped groove gate gallium nitride P-channel field effect transistor is described by taking the preparation of a Si substrate layer 1, a 5μm GaN buffer layer 2, a 15nm AlGaN barrier layer 3, a 70nm GaN channel layer 4, and a 10nm GaN cap layer 5 as an example. The method for preparing a multi-step and V-shaped groove gate gallium nitride P-channel field effect transistor includes:

[0082] Step A1, obtaining an epitaxial wafer.

[0083] The epitaxial wafer includes a substrate layer 1, a buffer layer 2, a barrier layer 3, a channel layer 4 and a cap layer 5 which are stacked in sequence from bottom to top.

[0084] In the third embodiment, the epitaxial wafer may be obtained by MOCVD epitaxial growth. The material of the substrate layer 1 is Si.

[0085] Specifically, Figure 3Schematic diagram showing the preparation process of multi-step and V-groove gate GaN P-channel field effect transistor Figure 1 ,in, Figure 3 (a) is the structure of the epitaxial wafer. The organic cleaning of the epitaxial wafer and the removal of the surface oxide layer are performed. The structure of the epitaxial wafer is shown in FIG. Figure 3 (a). Cleaning of epitaxial wafers can reduce the interference of oxidation and contamination on the subsequent process of the device and the impact on the performance of the device. First, the organic cleaning of the epitaxial wafer is carried out. The epitaxial material is immersed in an acetone solution and ultrasonically cleaned for 5 minutes to remove organic pollutants on the surface of the material. Then, it is placed in an isopropanol solution and ultrasonically cleaned for 5 minutes to effectively remove the residual acetone on the surface. The epitaxial wafer is then placed in deionized water to rinse and remove the isopropanol residue attached to the surface of the material. Finally, the surface of the material is blown dry with high-purity nitrogen to ensure that there is no residual liquid on the epitaxial wafer. Then, the epitaxial wafer is placed in a BOE solution with a concentration of 1:7 for 30 seconds to remove the surface oxide layer of the epitaxial wafer, and then rinsed with a large amount of deionized water. Finally, the deionized water on the surface of the wafer is blown dry with high-purity nitrogen to complete the entire cleaning process of the epitaxial wafer.

[0086] Step A2: depositing metal on the upper surface of the cap layer 5 to form a source electrode 7 and a drain electrode 8.

[0087] The source electrode 7 is located at an edge region on one side of the upper surface of the cap layer 5 , and the drain electrode 8 is located at an edge region on the other side of the upper surface of the cap layer 5 .

[0088] Specifically, Figure 3 Schematic diagram showing the preparation process of multi-step and V-groove gate GaN P-channel field effect transistor Figure 1 ,in, Figure 3 (b) is a schematic diagram of forming the source electrode 7 and the drain electrode 8. The surface of the cap layer 5 is coated, baked, exposed, and developed. The regions of the source electrode 7 and the drain electrode 8 are defined by the photolithography process. Then, the Ni / Au metal is sputtered on the surface of the developed epitaxial wafer by the magnetron sputtering process. The residual glue and the metal in the remaining area are then removed by a stripping liquid. The epitaxial wafer is annealed at 450°C for 5 minutes in a nitrogen atmosphere using a rapid thermal annealing process. This treatment can reduce the influence of the gold-semiconductor contact interface state, and the source electrode 7 and the drain electrode 8 form a good ohmic contact with the surface of the cap layer 5, reducing the metal-semiconductor contact resistance.

[0089] Step A3: etching downward from the upper surface of the cap layer 5 outside the source electrode 7 and the drain electrode 8 region to the upper surface of the channel layer 4 .

[0090] Specifically, Figure 3 Schematic diagram showing the preparation process of multi-step and V-groove gate GaN P-channel field effect transistor Figure 1 ,in, Figure 3(c) is a schematic diagram of the device structure after etching the cap layer 5. The ICP dry etching technology is used to etch the non-source-drain electrode 8 area, and the cap layer 5 is etched away to completely expose the channel layer 4 to form a groove gate structure. The stripping solution is used to clean and remove the residual glue.

[0091] Step A4: etching is performed from the upper surface of the channel layer 4 downward for multiple times to form a multi-step groove 61, and the width of each etching is the same.

[0092] Specifically, Figure 3 Schematic diagram showing the preparation process of multi-step and V-groove gate GaN P-channel field effect transistor Figure 1 ,in, Figure 3 (d) is a schematic diagram of forming a multi-step groove 61. The channel layer 4 is etched using multiple photolithography processes and multiple ICP dry etching techniques. The etching width is shortened in accordance with the number of steps and the step length, and the etching depth is increased in accordance with the number of steps and the step height, thereby forming a multi-step groove 61 gate structure.

[0093] Step A5: deposit metal at the bottom of the multi-step groove 61 to form a gate electrode 9.

[0094] Specifically, Figure 3 Schematic diagram showing the preparation process of multi-step and V-groove gate GaN P-channel field effect transistor Figure 1 ,in, Figure 3 (e) is a schematic diagram of forming a gate electrode 9. First, the epitaxial wafer is placed in a nitrogen atmosphere at 450°C for 5 minutes for gate groove annealing, and then heated in a TMAH solution at 80°C for 10 minutes to repair interface damage in the etched area. Then, a magnetron sputtering process is used to sputter metal, which can be W or Ti metal, on the bottom surface of the gate area of ​​the multi-step groove 61 to form a gate electrode 9.

[0095] Embodiment 4:

[0096] Figure 4 Schematic diagram of the preparation method of multi-step and V-groove gate GaN P-channel field effect transistor Figure 2 , see Figure 4 As shown, the method for preparing the multi-step and V-shaped groove gate gallium nitride P-channel field effect transistor may include:

[0097] S401, obtaining an epitaxial wafer.

[0098] The epitaxial wafer includes a substrate layer 1, a buffer layer 2, a barrier layer 3, a channel layer 4 and a cap layer 5 which are stacked in sequence from bottom to top.

[0099] Specifically, the epitaxial wafer may be obtained by MOCVD epitaxial growth. The material of the substrate layer 1 is Si, Al2O3 or SiC material.

[0100] Specifically, Figure 5 Schematic diagram showing the preparation process of multi-step and V-groove gate GaN P-channel field effect transistor Figure 2 ,in, Figure 5 (a) is a schematic diagram of the structure of the epitaxial wafer. The organic cleaning of the epitaxial wafer and the removal of the surface oxide layer are performed. For the structure of the epitaxial wafer, please refer to Figure 5 (a). Cleaning of epitaxial wafers can reduce the interference of oxidation and contamination on the subsequent process of the device and the impact on the performance of the device. First, the organic cleaning of the epitaxial wafer is carried out. The epitaxial material is immersed in an acetone solution and ultrasonically cleaned for 5 minutes to remove organic pollutants on the surface of the material. Then, it is placed in an isopropanol solution and ultrasonically cleaned for 5 minutes to effectively remove the residual acetone on the surface. The epitaxial wafer is then placed in deionized water to rinse and remove the isopropanol residue attached to the surface of the material. Finally, the surface of the material is blown dry with high-purity nitrogen to ensure that there is no residual liquid on the epitaxial wafer. Then, the epitaxial wafer is placed in a BOE solution with a concentration of 1:7 for 30 seconds to remove the surface oxide layer of the epitaxial wafer, and then rinsed with a large amount of deionized water. Finally, the deionized water on the surface of the wafer is blown dry with high-purity nitrogen to complete the entire cleaning process of the epitaxial wafer.

[0101] S402 , coating an SOG film on the upper surface of the cap layer 5 to form a hard mask layer 10 , and coating a photoresist layer 11 on both side edge regions of the hard mask layer 10 .

[0102] Specifically, Figure 5 Schematic diagram showing the preparation process of multi-step and V-groove gate GaN P-channel field effect transistor Figure 2 ,in, Figure 5 (b) is a schematic diagram of the device after coating the photoresist layer 11. A silicon-on-glass bonding structure (SOG) solution is dropped on the center of the epitaxial wafer surface, and then the epitaxial wafer is quickly rotated to evenly coat the solution on the surface of the epitaxial wafer to form a uniform liquid film. The solvent is then soft-baked to remove the SOG film to make it semi-solid. The SOG film is further heated to completely solidify it to form a hard mask layer 10. Photoresist is then coated on the surface of the hard mask layer 10, and the coating is evenly spread, baked, exposed, and developed to form photoresist layers 11 on both sides.

[0103] S403 , removing a portion of the hard mask layer 10 to form a hard mask layer 10 with an inclination, and removing the photoresist layer 11 .

[0104] The inclination angle of the inclined hard mask layer 10 is greater than 0° and less than 90°.

[0105] Specifically, Figure 5 Schematic diagram showing the preparation process of multi-step and V-groove gate GaN P-channel field effect transistor Figure 2,in, Figure 5 (c) is a schematic diagram of the device after the photoresist layer 11 is removed. The hard mask layer 10 is etched with a diluted HF solution with a concentration of 2%. The gap between the hard mask layer 10 and the photoresist layer 11 causes the upper part of the hard mask layer 10 to be eroded faster than the lower part, forming a hard mask layer 10 with a slope. The photoresist layer 11 is then removed with a stripping solution.

[0106] S404 , etching away a portion of the hard mask layer 10 and the cap layer 5 until reaching the channel layer 4 , to form a V-shaped groove 62 or an inverted trapezoidal groove 63 .

[0107] Specifically, Figure 5 Schematic diagram showing the preparation process of multi-step and V-groove gate GaN P-channel field effect transistor Figure 2 ,in, Figure 5 (d) is a schematic diagram of forming an inverted trapezoidal groove 63, Figure 5 (e) is a schematic diagram of forming a V-shaped groove 62. ICP dry etching technology is used to etch away the hard mask layer 10 and the cap layer 5 in the non-source and drain electrode 8 area, and a portion of the channel layer 4 is etched to form a V-shaped groove 62 or an inverted trapezoidal groove 63; ideally, a V-shaped groove 62 is formed.

[0108] S405 , depositing metal on the upper surface of the cap layer 5 to form a source electrode 7 and a drain electrode 8 .

[0109] The source electrode 7 is located at an edge region on one side of the upper surface of the cap layer 5 , and the drain electrode 8 is located at an edge region on the other side of the upper surface of the cap layer 5 .

[0110] Specifically, Figure 5 Schematic diagram showing the preparation process of multi-step and V-groove gate GaN P-channel field effect transistor Figure 2 ,in, Figure 5 (f) is a schematic diagram of forming a source electrode 7 and a drain electrode 8 on the upper surface of the cap layer 5 of the inverted trapezoidal groove 63. The upper surface of the cap layer 5 of the inverted trapezoidal groove 63 or the upper surface of the cap layer 5 of the V-shaped groove 62 is subjected to photoresist coating, photoresist baking, exposure, and development. Ni / Au metal is then sputtered on the developed surface of the cap layer 5 using a magnetron sputtering process, and then the residual glue and metal in the remaining area are removed using a stripping solution. The epitaxial wafer is annealed at 450°C for 5 minutes in a nitrogen atmosphere using a rapid thermal annealing process.

[0111] S406 , depositing metal at the bottom of the V-shaped groove 62 or the inverted trapezoidal groove 63 to form a gate electrode 9 .

[0112] Specifically, Figure 5 Schematic diagram showing the preparation process of multi-step and V-groove gate GaN P-channel field effect transistor Figure 2 ,in, Figure 5(g) is a schematic diagram of forming a gate electrode 9 at the bottom of the inverted trapezoidal groove 63. Figure 5 (h) is a schematic diagram of forming a gate electrode 9 at the bottom of the V-shaped groove 62. The epitaxial wafer is placed in a nitrogen atmosphere at 450°C for 5 minutes to anneal the gate groove, and then heated in a TMAH solution at 80°C for 10 minutes to repair the interface damage in the etched area. Then, a metal, which may be W or Ti metal, is sputtered on the bottom surface of the V-shaped groove 62 or the inverted trapezoidal groove 63 by a magnetron sputtering process to form a gate electrode 9. Ideally, a V-shaped groove gate is formed.

[0113] Embodiment five:

[0114] Based on the fourth embodiment, Figure 5 In this embodiment 5, a method for preparing a multi-step and V-shaped groove gate gallium nitride P-channel field effect transistor is described by taking the preparation of a Si substrate layer 1, a 5μm GaN buffer layer 2, a 15nm AlGaN barrier layer 3, a 70nm GaN channel layer 4, and a 10nm GaN cap layer 5 as an example. The method for preparing a multi-step and V-shaped groove gate gallium nitride P-channel field effect transistor includes:

[0115] Step B1, obtaining an epitaxial wafer.

[0116] The epitaxial wafer includes a substrate layer 1, a buffer layer 2, a barrier layer 3, a channel layer 4 and a cap layer 5 which are stacked in sequence from bottom to top.

[0117] In the fifth embodiment, the epitaxial wafer may be obtained by MOCVD epitaxial growth. The material of the substrate layer 1 is Si.

[0118] Specifically, Figure 5 Schematic diagram showing the preparation process of multi-step and V-groove gate GaN P-channel field effect transistor Figure 2 ,in, Figure 5 (a) is a schematic diagram of the structure of the epitaxial wafer. The organic cleaning of the epitaxial wafer and the removal of the surface oxide layer are performed. For the structure of the epitaxial wafer, please refer to Figure 5 (a). Cleaning of epitaxial wafers can reduce the interference of oxidation and contamination on the subsequent process of the device and the impact on the performance of the device. First, the organic cleaning of the epitaxial wafer is carried out. The epitaxial material is immersed in an acetone solution and ultrasonically cleaned for 5 minutes to remove organic pollutants on the surface of the material. Then, it is placed in an isopropanol solution and ultrasonically cleaned for 5 minutes to effectively remove the residual acetone on the surface. The epitaxial wafer is then placed in deionized water to rinse and remove the isopropanol residue attached to the surface of the material. Finally, the surface of the material is blown dry with high-purity nitrogen to ensure that there is no residual liquid on the epitaxial wafer. Then, the epitaxial wafer is placed in a BOE solution with a concentration of 1:7 for 30 seconds to remove the surface oxide layer of the epitaxial wafer, and then rinsed with a large amount of deionized water. Finally, the deionized water on the surface of the wafer is blown dry with high-purity nitrogen to complete the entire cleaning process of the epitaxial wafer.

[0119] Step B2: coating an SOG film on the upper surface of the cap layer 5 to form a hard mask layer 10 , and coating a photoresist layer 11 on both side edge regions of the hard mask layer 10 .

[0120] Specifically, Figure 5 Schematic diagram showing the preparation process of multi-step and V-groove gate GaN P-channel field effect transistor Figure 2 ,in, Figure 5 (b) is a schematic diagram of the device after coating the photoresist layer 11. SOG solution is dropped on the center of the epitaxial wafer surface, and then the epitaxial wafer is quickly rotated to evenly coat the solution on the surface of the epitaxial wafer to form a uniform liquid film. The solvent is then soft-baked to remove the SOG film to make it semi-solid. The SOG film is further heated to completely solidify it to form a hard mask layer 10. Photoresist is then coated on the surface of the hard mask layer 10, and the coating is evenly applied, baked, exposed and developed to form photoresist layers 11 on both sides.

[0121] Step B3, removing part of the hard mask layer 10 to form a hard mask layer 10 with an inclination, and removing the photoresist layer 11.

[0122] The inclination angle of the inclined hard mask layer 10 is greater than 0° and less than 90°.

[0123] Specifically, Figure 5 Schematic diagram showing the preparation process of multi-step and V-groove gate GaN P-channel field effect transistor Figure 2 ,in, Figure 5 (c) is a schematic diagram of the device after the photoresist layer 11 is removed. The hard mask layer 10 is etched with a diluted HF solution with a concentration of 2%. The gap between the hard mask layer 10 and the photoresist layer 11 causes the upper part of the hard mask layer 10 to be eroded faster than the lower part, forming a hard mask layer 10 with a slope. The photoresist layer 11 is then removed with a stripping solution.

[0124] Step B4: etching away a portion of the hard mask layer 10 and the cap layer 5 until reaching the channel layer 4 to form a V-shaped groove 62 or an inverted trapezoidal groove 63 .

[0125] Specifically, Figure 5 Schematic diagram showing the preparation process of multi-step and V-groove gate GaN P-channel field effect transistor Figure 2 ,in, Figure 5 (d) is a schematic diagram of forming a V-shaped groove 62 or an inverted trapezoidal groove 63, wherein the ICP dry etching technology is used to etch away the hard mask layer 10 and the cap layer 5 in the non-source / drain electrode 8 area, and a portion of the channel layer 4 is etched to form a V-shaped groove 62; ideally, the gap in the middle of the photoresist layer 11 formed in step B2 can be small enough to form a complete V-shaped groove 62 by etching the hard mask layer 10, the cap layer 5 and the channel layer 4.

[0126] Step B5: depositing metal on the upper surface of the cap layer 5 to form a source electrode 7 and a drain electrode 8.

[0127] The source electrode 7 is located at an edge region on one side of the upper surface of the cap layer 5 , and the drain electrode 8 is located at an edge region on the other side of the upper surface of the cap layer 5 .

[0128] Specifically, Figure 5 Schematic diagram showing the preparation process of multi-step and V-groove gate GaN P-channel field effect transistor Figure 2 ,in, Figure 5 (e) is a schematic diagram of forming the source electrode 7 and the drain electrode 8. The surface of the cap layer 5 is subjected to photoresist coating, photoresist baking, exposure and development. The Ni / Au metal is then sputtered on the surface of the developed cap layer 5 by a magnetron sputtering process. The residual photoresist and the metal in the remaining area are then removed by a stripping solution. The epitaxial wafer is annealed at 450°C for 5 minutes in a nitrogen atmosphere using a rapid thermal annealing process.

[0129] Step B6: depositing metal at the bottom of the V-shaped groove 62 or the inverted trapezoidal groove 63 to form a gate electrode 9.

[0130] Specifically, Figure 5 Schematic diagram showing the preparation process of multi-step and V-groove gate GaN P-channel field effect transistor Figure 2 , among which, among which, Figure 5 (f) is a schematic diagram of forming a gate electrode 9 at the bottom of the V-shaped groove 62. Figure 5 (g) is a schematic diagram of forming a gate electrode 9 at the bottom of the inverted trapezoidal groove 63. The epitaxial wafer is placed in a nitrogen atmosphere at 450°C for 5 minutes to anneal the gate groove, and then heated in a TMAH solution at 80°C for 10 minutes to repair the interface damage in the etched area. Then, a metal, which may be W or Ti metal, is sputtered on the bottom surface of the V-shaped groove 62 or the inverted trapezoidal groove 63 by a magnetron sputtering process to form a gate electrode 9. Ideally, a V-shaped groove gate is formed.

[0131] It should be pointed out here that the description of the above embodiment of the method for preparing a multi-step and V-groove gate gallium nitride P-channel field effect transistor is similar to the description of the above embodiment of the multi-step and V-groove gate gallium nitride P-channel field effect transistor, and has similar beneficial effects as the embodiment of the multi-step and V-groove gate gallium nitride P-channel field effect transistor. For technical details not disclosed in the embodiment of the method for preparing a multi-step and V-groove gate gallium nitride P-channel field effect transistor of the embodiment of the present invention, please refer to the description of the embodiment of the multi-step and V-groove gate gallium nitride P-channel field effect transistor of the present invention for understanding.

[0132] The above are only specific embodiments of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art who is familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed by the present invention, which should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. A multi-step and V-groove gate GaN P-channel field effect transistor, characterized in that: It includes a substrate layer, a buffer layer, a barrier layer, a channel layer and a cap layer which are sequentially arranged from bottom to top; A groove extending downward from a middle area of ​​the upper surface of the cap layer and penetrating the cap layer into the channel layer, wherein the shape of the groove is a multi-step groove, a V-shaped groove or an inverted trapezoidal groove; a source electrode formed on the cap layer at one side of the groove; a drain electrode formed on the cap layer at the other side of the groove; A gate electrode is formed in the groove and contacts the channel layer, wherein the level of the upper surface of the gate electrode is lower than the level of the upper surface of the channel layer.

2. The multi-step and V-groove gate GaN P-channel field effect transistor according to claim 1, characterized in that: The width of each step of the multi-step groove is the same, and the inclination angles of the V-shaped groove and the inverted trapezoidal groove are both greater than 0° and less than 90°.

3. The multi-step and V-groove gate GaN P-channel field effect transistor according to claim 1, characterized in that: The buffer layer is made of GaN material and has a thickness of 1 to 10 μm.

4. The multi-step and V-groove gate GaN P-channel field effect transistor according to claim 1, characterized in that: The barrier layer is made of AlGaN material, the Al component of the AlGaN material is 5% to 30%, and the thickness of the barrier layer is 5 to 30 nm.

5. The multi-step and V-groove gate GaN P-channel field effect transistor according to claim 1, characterized in that: The channel layer is a p-type GaN channel layer, the doping ions of the p-type GaN channel layer are Mg ions, and the doping concentration of Mg ions in the p-type GaN channel layer is 5×10 18 ~5×10 19 cm -3 , the thickness of the p-type GaN channel layer is 50nm to 100nm.

6. The multi-step and V-groove gate GaN P-channel field effect transistor according to claim 1, characterized in that: The cap layer is a p-type heavily doped GaN channel layer, the doping ions of the p-type heavily doped GaN channel layer are Mg ions, and the doping concentration of Mg ions in the p-type heavily doped GaN channel layer is 1×10 19 ~1×10 20 cm -3 , thickness is 5nm~30nm.

7. The multi-step and V-groove gate GaN P-channel field effect transistor according to claim 1, characterized in that: The source electrode and the drain electrode are both made of Ni / Au metal.

8. The multi-step and V-groove gate GaN P-channel field effect transistor according to claim 1, characterized in that: The gate electrode is made of W / Au or Ti / Au metal.

9. A method for preparing a multi-step and V-groove gate gallium nitride P-channel field effect transistor, characterized in that: The multi-step and V-groove gate gallium nitride P-channel field effect transistor applicable to any one of claims 1 to 8 comprises: Obtaining an epitaxial wafer, wherein the epitaxial wafer includes a substrate layer, a buffer layer, a barrier layer, a channel layer and a cap layer stacked in sequence from bottom to top; Depositing metal on the upper surface of the cap layer to form a source electrode and a drain electrode, wherein the source electrode is located at an edge region on one side of the upper surface of the cap layer, and the drain electrode is located at an edge region on the other side of the upper surface of the cap layer; Etching downward from the upper surface of the cap layer outside the source electrode and the drain electrode region to the upper surface of the channel layer; Etching is performed multiple times downward from the upper surface of the channel layer to form a multi-step groove, and the width of each etching is the same; The metal is deposited in the bottom of the multi-step groove to form a gate electrode.

10. A method for preparing a multi-step and V-groove gate gallium nitride P-channel field effect transistor, characterized in that: The multi-step and V-groove gate gallium nitride P-channel field effect transistor applicable to any one of claims 1 to 8 comprises: Obtaining an epitaxial wafer, wherein the epitaxial wafer includes a substrate layer, a buffer layer, a barrier layer, a channel layer and a cap layer stacked in sequence from bottom to top; Coating a SOG film on the upper surface of the cap layer to form a hard mask layer, and coating a photoresist layer on both side edge regions of the hard mask layer; Removing part of the hard mask layer to form a hard mask layer with an inclination, and removing the photoresist layer, wherein the inclination angle of the hard mask layer with an inclination is greater than 0° and less than 90°; Etching away part of the hard mask layer and the cap layer until it reaches the channel layer to form a V-shaped groove or an inverted trapezoidal groove; Depositing metal on the upper surface of the cap layer to form a source electrode and a drain electrode, wherein the source electrode is located at an edge region on one side of the upper surface of the cap layer, and the drain electrode is located at an edge region on the other side of the upper surface of the cap layer; The metal is deposited at the bottom of the V-shaped groove or the inverted trapezoidal groove to form a gate electrode.

Images