Fin field effect transistor laterally diffused metal oxide semiconductor element

Abstract

The invention discloses a fin-type field effect transistor laterally diffused metal oxide semiconductor element. The fin-type field effect transistor laterally diffused metal oxide semiconductor element comprises a semiconductor substrate; the first well and the second well are arranged side by side and located in the semiconductor substrate; a semiconductor fin on the semiconductor substrate and extending in a first direction, the semiconductor fin including a first fin portion within the first well and a second fin portion within the second well; an additional semiconductor body in direct contact with the first fin portion and the second fin portion, the additional semiconductor body extending along the second direction; a source region located at the first fin portion; a drain region located at the second fin portion; a gate covering the semiconductor fin and extending in a second direction, the gate partially overlapping the first fin and partially overlapping the second fin, the additional semiconductor body being covered by the gate; and a single diffusion interruption structure embedded in the second fin portion and located between the gate and drain regions.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to an improved fin field effect transistor lateral diffused metal oxide semiconductor (FinFET LDMOS) element. Background Art

[0002] Fin field effect transistor (FinFET) devices have faster switching times and higher current density than planar complementary metal oxide semiconductor (CMOS) technology.

[0003] Bulk finFETs with a lateral double diffused MOS (LDMOS) structure are mainly used in RF power amplifiers and can provide a high breakdown voltage (e.g., between drain and source terminals). The high breakdown voltage is achieved, for example, by a charge carrier (e.g., electron) flow path through a depletion region.

[0004] Due to the significant advancement in IC technology for system-on-chip (SoC) architectures, FinFET-based LDMOS is essential for integrating high-voltage (HV) devices with low-voltage (LV) FinFET-based digital systems. Summary of the invention

[0005] The main purpose of the present invention is to provide an improved FinFET LDMOS device to solve the deficiencies or shortcomings of the prior art.

[0006] The present invention provides a FinFET The LDMOS element comprises: a semiconductor substrate of a first conductivity type; a first well of the first conductivity type, located in the semiconductor substrate; a second well of a second conductivity type, located in the semiconductor substrate and juxtaposed with the first well of the first conductivity type; a semiconductor fin, arranged on the semiconductor substrate and extending along a first direction, wherein the semiconductor fin comprises a first fin portion located in the first well of the first conductivity type and a second fin portion located in the second well of the second conductivity type; an additional semiconductor body, adjacent to the semiconductor fin and extending along a second direction orthogonal to the first direction, wherein the additional semiconductor body is in direct contact with the first fin portion and the second fin portion; a source region of the second conductivity type, located in the first fin portion; a drain region of the second conductivity type, located in the second fin portion; a gate, covering the semiconductor fin and extending along the second direction, wherein the gate partially overlaps with the first fin portion and partially overlaps with the second fin portion, wherein the additional semiconductor body is covered by the gate; and a single diffusion break (SDB) structure, embedded in the second fin portion and located between the gate and the drain region.

[0007] According to an embodiment of the present invention, the first fin portion includes a channel region between the source region and the SDB structure, wherein the channel region is disposed directly below the gate.

[0008] According to an embodiment of the present invention, the second fin portion includes a drift region in the second well of the second conductivity type located between the channel region and the SDB structure, wherein the gate partially overlaps with the drift region.

[0009] According to an embodiment of the present invention, the SDB structure includes a bottom insulating layer and a top dummy gate directly disposed on the bottom insulating layer, wherein the top dummy gate is spaced apart from the gate, wherein the top dummy gate extends along the second direction, wherein the bottom insulating layer includes silicon oxide, and wherein the top dummy gate and the gate are metal gates.

[0010] According to an embodiment of the present invention, the SDB structure is adjacent to the drain region.

[0011] According to an embodiment of the present invention, a top surface of the additional semiconductor body is lower than a top surface of the semiconductor fin.

[0012] According to an embodiment of the present invention, the FinFET LDMOS device further includes: a first epitaxial layer disposed on the source region; and a second epitaxial layer disposed on the drain region.

[0013] According to an embodiment of the present invention, the first epitaxial layer and the second epitaxial layer include SiP.

[0014] According to an embodiment of the present invention, the first conductivity type is P type and the second conductivity type is N type.

[0015] According to an embodiment of the present invention, the semiconductor substrate is a silicon substrate, the first well of the first conductivity type is a P-type well, the second well of the second conductivity type is an N-type well, and the source region of the second conductivity type is an N-type well. + doped region, the drain region of the second conductivity type is N + Doped region.

[0016] On the other hand, the present invention provides a FinFET LDMOS element, comprising: a semiconductor substrate of a first conductivity type; a first well of the first conductivity type, located in the semiconductor substrate; a second well of a second conductivity type, located in the semiconductor substrate and juxtaposed with the first well of the first conductivity type; a semiconductor fin, arranged on the semiconductor substrate and extending along a first direction, wherein the semiconductor fin comprises a first fin portion located in the first well of the first conductivity type and a second fin portion located in the second well of the second conductivity type; an additional semiconductor body, adjacent to the semiconductor fin and extending along a second direction orthogonal to the first direction, wherein the additional semiconductor body is in direct contact with the first fin portion; a source region of a second conductivity type, located in the first fin portion; a drain region of a second conductivity type, located in the second fin portion; a gate, covering the semiconductor fin and extending along the second direction, wherein the gate partially overlaps with the first fin portion and partially overlaps with the second fin portion, wherein the additional semiconductor body is covered by the gate; and a single diffusion break (SDB) structure, embedded in the second fin portion and located between the gate and the drain region.

[0017] According to an embodiment of the present invention, the first fin portion includes a channel region between the source region and the SDB structure, wherein the channel region is disposed directly below the gate.

[0018] According to an embodiment of the present invention, the second fin portion includes a drift region in the second well of the second conductivity type located between the channel region and the SDB structure, wherein the gate partially overlaps with the drift region.

[0019] According to an embodiment of the present invention, the SDB structure includes a bottom insulating layer and a top dummy gate directly disposed on the bottom insulating layer, wherein the top dummy gate is spaced apart from the gate, wherein the top dummy gate extends along the second direction, wherein the bottom insulating layer includes silicon oxide, and wherein the top dummy gate and the gate are metal gates.

[0020] According to an embodiment of the present invention, the SDB structure is adjacent to the drain region.

[0021] According to an embodiment of the present invention, a top surface of the additional semiconductor body is lower than a top surface of the semiconductor fin.

[0022] According to an embodiment of the present invention, the FinFET LDMOS device further includes: a first epitaxial layer disposed on the source region; and a second epitaxial layer disposed on the drain region.

[0023] According to an embodiment of the present invention, the first epitaxial layer and the second epitaxial layer include SiP.

[0024] According to an embodiment of the present invention, the first conductivity type is P type and the second conductivity type is N type.

[0025] According to an embodiment of the present invention, the semiconductor substrate is a silicon substrate, the first well of the first conductivity type is a P-type well, the second well of the second conductivity type is an N-type well, and the source region of the second conductivity type is an N-type well. + doped region, the drain region of the second conductivity type is N + Doped region. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 A three-dimensional perspective view of a FinFET LDMOS device according to an embodiment of the present invention;

[0027] Figure 2 FIG. 1 is a three-dimensional perspective view of a FinFET LDMOS device according to another embodiment of the present invention.

[0028] Explanation of symbols

[0029] 1.2 FinFET LDMOS components

[0030] 100 Semiconductor substrate

[0031] 101 The First Trap

[0032] 102 The Second Trap

[0033] 106 Additional semiconductor body

[0034] 108 Single diffusion interruption structure

[0035] 108i Bottom insulation layer

[0036] 108g Top dummy gate

[0037] CH Channel Area

[0038] ND Drift Zone

[0039] EP1 First epitaxial layer

[0040] EP2 Second epitaxial layer

[0041] F, F1-F3 semiconductor fins

[0042] FP1 First fin section

[0043] FP2 Second fin section

[0044] GE Gate

[0045] D1 First direction

[0046] D2 Second direction

[0047] D3 third direction

[0048] DR Drain Region

[0049] SR Source Region DETAILED DESCRIPTION

[0050] In the following, the details will be described with reference to the accompanying drawings, which also constitute part of the detailed description of the specification and are illustrated in a specific way that the embodiment can be implemented. The following embodiments have been described in sufficient detail to enable a person skilled in the art to implement them.

[0051] Of course, other embodiments may be adopted, or any structural, logical, and electrical changes may be made without departing from the embodiments described herein. Therefore, the following detailed description should not be considered as limiting, but rather, the embodiments included therein will be defined by the appended claims.

[0052] The present invention discloses an improved fin field effect transistor lateral diffused metal oxide semiconductor (FinFETLDMOS) device having an extra Si body (ESB) and a single diffusion break (SDB) structure, which can improve the performance of the high voltage device during high voltage operation.

[0053] See also Figure 1 , which is a three-dimensional perspective view of a FinFET LDMOS device according to an embodiment of the present invention. Figure 1 As shown, the FinFET LDMOS element 1 includes: a semiconductor substrate 100 of a first conductivity type, for example, a silicon substrate of a first conductivity type. According to an embodiment of the present invention, a plurality of semiconductor fins F are provided on the semiconductor substrate 100, for example, semiconductor fins F1-F3, extending along a first direction D1. It should be understood that the number of fins in the figure is only for illustration, and in other embodiments, there may be 4 or more fins. According to an embodiment of the present invention, the width of the semiconductor fin F in the second direction D2 is, for example, about 10 nm, but is not limited thereto. According to an embodiment of the present invention, the fin height of the semiconductor fin F in the third direction D3 is, for example, about 44 nm, but is not limited thereto.

[0054] According to an embodiment of the present invention, a trench insulation structure (not shown) may be provided between the plurality of semiconductor fins F for the purpose of element insulation. The above-mentioned trench insulation structure is a common structure in FinFET elements and is omitted in the figure for the sake of simplicity. According to an embodiment of the present invention, the plurality of semiconductor fins F protrude from the top surface of the trench insulation structure in the third direction D3.

[0055] According to an embodiment of the present invention, a first well 101 of a first conductivity type and a second well 102 of a second conductivity type are arranged in parallel in the semiconductor substrate 100. According to an embodiment of the present invention, the first conductivity type is, for example, a P type, and the second conductivity type is, for example, an N type. According to an embodiment of the present invention, for example, the semiconductor substrate 100 of the first conductivity type may be a P type silicon substrate, the first well 101 of the first conductivity type may be a P type well, and the second well 102 of the second conductivity type may be an N type well. According to an embodiment of the present invention, the first well 101 is directly adjacent to the second well 102.

[0056] According to the embodiment of the present invention, each semiconductor fin F includes a first fin portion FP1 located in a first conductive type first well 101 and a second fin portion FP2 located in a second conductive type second well 102. According to the embodiment of the present invention, the first fin portion FP1 and the second fin portion FP2 are directly adjacent to each other.

[0057] According to an embodiment of the present invention, the FinFET LDMOS element 1 further includes an extra semiconductor body (ESB) 106, which is located between the semiconductor fins F and adjacent to the semiconductor fins F. The strip-shaped extra semiconductor body 106 extends along a second direction D2 orthogonal to the first direction D1. According to an embodiment of the present invention, the extra semiconductor body 106 is in direct contact with the first fin portion FP1 and the second fin portion FP2. According to an embodiment of the present invention, the top surface of the extra semiconductor body 106 is lower than the top surface of the semiconductor fin F. When the element is turned on, the extra semiconductor body 106 can help collect extra charges and improve the performance of the element.

[0058] According to an embodiment of the present invention, the FinFET LDMOS element 1 further comprises a second conductivity type source region SR located in the first fin portion FP1 and a second conductivity type drain region DR located in the second fin portion FP2. According to an embodiment of the present invention, for example, the second conductivity type source region SR is N + doped region, the drain region DR of the second conductivity type is N + Doped region.

[0059] According to an embodiment of the present invention, the FinFET LDMOS element 1 further includes a gate GE, which covers the semiconductor fin F and extends along the second direction D2. According to an embodiment of the present invention, the gate GE partially overlaps with the first fin portion FP1 and partially overlaps with the second fin portion FP2. According to an embodiment of the present invention, the additional semiconductor body 106 is completely covered by the gate GE. In other words, when viewed from top to bottom, the gate GE completely overlaps with the additional semiconductor body 106.

[0060] According to an embodiment of the present invention, the FinFET LDMOS element 1 further includes a single diffusion break (SDB) structure 108 embedded in the second fin portion FP2. According to an embodiment of the present invention, the single diffusion break structure 108 is located between the gate GE and the drain region DR. According to an embodiment of the present invention, the single diffusion break structure 108 is adjacent to the drain region DR.

[0061] According to an embodiment of the present invention, the single diffusion interruption structure 108 includes a bottom insulating layer 108i and a top dummy gate 108g directly disposed on the bottom insulating layer 108i. According to an embodiment of the present invention, the distance from the top surface of the bottom insulating layer 108i of the single diffusion interruption structure 108 to the bottom thereof is, for example, about 100 nm, but is not limited thereto. According to an embodiment of the present invention, the top dummy gate 108g is spaced apart from the gate GE. According to an embodiment of the present invention, the top dummy gate 108g extends along the second direction D2. According to an embodiment of the present invention, the bottom insulating layer 108i includes, for example, silicon oxide. According to an embodiment of the present invention, the top dummy gate 108g and the gate GE are, for example, metal gates.

[0062] According to an embodiment of the present invention, the first fin portion FP1 includes a channel region CH located between the source region SR and the single diffusion interruption structure 108. According to an embodiment of the present invention, the channel region CH is directly disposed below the gate GE. According to an embodiment of the present invention, the second fin portion FP2 includes a drift region ND in the second well 102 of the second conductivity type located between the channel region CH and the single diffusion interruption structure 108. According to an embodiment of the present invention, the gate GE partially overlaps with the drift region ND.

[0063] According to an embodiment of the present invention, the FinFET LDMOS device 1 further comprises: a first epitaxial layer EP1 disposed on the source region SR. According to an embodiment of the present invention, the FinFET LDMOS device 1 further comprises: a second epitaxial layer EP2 disposed on the drain region DR. According to an embodiment of the present invention, for example, the first epitaxial layer EP1 and the second epitaxial layer EP2 comprise SiP epitaxial layers.

[0064] See also Figure 2 , which is a three-dimensional perspective view of a FinFET LDMOS device according to another embodiment of the present invention. Figure 2As shown, the FinFET LDMOS element 2 also includes: a semiconductor substrate 100 of the first conductivity type, for example, a silicon substrate of the first conductivity type. According to an embodiment of the present invention, a plurality of semiconductor fins F are arranged on the semiconductor substrate 100, for example, semiconductor fins F1-F3, extending along a first direction D1. According to an embodiment of the present invention, a trench insulation structure (not shown) can be arranged between the plurality of semiconductor fins F for the purpose of element insulation. The above-mentioned trench insulation structure is a common structure in FinFET elements and is omitted in the figure for simplicity of explanation. According to an embodiment of the present invention, a plurality of semiconductor fins F protrude from the top surface of the trench insulation structure toward a third direction D3.

[0065] According to an embodiment of the present invention, a first well 101 of a first conductivity type and a second well 102 of a second conductivity type are also arranged in parallel in the semiconductor substrate 100. According to an embodiment of the present invention, the first conductivity type is, for example, a P type, and the second conductivity type is, for example, an N type. According to an embodiment of the present invention, for example, the semiconductor substrate 100 of the first conductivity type may be a P type silicon substrate, the first well 101 of the first conductivity type may be a P type well, and the second well 102 of the second conductivity type may be an N type well. According to an embodiment of the present invention, the first well 101 is directly adjacent to the second well 102.

[0066] According to the embodiment of the present invention, each semiconductor fin F also includes a first fin portion FP1 located in a first conductive type first well 101 and a second fin portion FP2 located in a second conductive type second well 102. According to the embodiment of the present invention, the first fin portion FP1 and the second fin portion FP2 are directly adjacent to each other.

[0067] According to an embodiment of the present invention, the FinFET LDMOS element 2 further includes an additional semiconductor body (ESB) 106, which is located between the semiconductor fins F and adjacent to the semiconductor fins F. The strip-shaped additional semiconductor body 106 extends along a second direction D2 orthogonal to the first direction D1. According to an embodiment of the present invention, the additional semiconductor body 106 is only in direct contact with the first fin portion FP1, and is not in direct contact with the second fin portion FP2. According to an embodiment of the present invention, the top surface of the additional semiconductor body 106 is lower than the top surface of the semiconductor fin F.

[0068] According to an embodiment of the present invention, the FinFET LDMOS element 2 further includes a second conductivity type source region SR located in the first fin portion FP1 and a second conductivity type drain region DR located in the second fin portion FP2. According to an embodiment of the present invention, for example, the second conductivity type source region SR is N + doped region, the drain region DR of the second conductivity type is N + Doped region.

[0069] According to an embodiment of the present invention, the FinFET LDMOS element 2 further includes a gate GE, which covers the semiconductor fin F and extends along the second direction D2. According to an embodiment of the present invention, the gate GE partially overlaps with the first fin portion FP1 and partially overlaps with the second fin portion FP2. According to an embodiment of the present invention, the additional semiconductor body 106 is completely covered by the gate GE. In other words, when viewed from top to bottom, the gate GE completely overlaps with the additional semiconductor body 106.

[0070] According to an embodiment of the present invention, the FinFET LDMOS element 2 further includes a single diffusion interrupt (SDB) structure 108 embedded in the second fin portion FP2. According to an embodiment of the present invention, the single diffusion interrupt structure 108 is located between the gate GE and the drain region DR. According to an embodiment of the present invention, the single diffusion interrupt structure 108 is adjacent to the drain region DR.

[0071] According to an embodiment of the present invention, the single diffusion interruption structure 108 includes a bottom insulating layer 108i and a top dummy gate 108g directly disposed on the bottom insulating layer 108i. According to an embodiment of the present invention, the top dummy gate 108g is spaced apart from the gate GE. According to an embodiment of the present invention, the top dummy gate 108g extends along the second direction D2. According to an embodiment of the present invention, the bottom insulating layer 108i includes, for example, silicon oxide. According to an embodiment of the present invention, the top dummy gate 108g and the gate GE are, for example, metal gates.

[0072] According to an embodiment of the present invention, the first fin portion FP1 includes a channel region CH located between the source region SR and the single diffusion interruption structure 108. According to an embodiment of the present invention, the channel region CH is directly disposed below the gate GE. According to an embodiment of the present invention, the second fin portion FP2 includes a drift region ND in the second well 102 of the second conductivity type located between the channel region CH and the single diffusion interruption structure 108. According to an embodiment of the present invention, the gate GE partially overlaps with the drift region ND.

[0073] According to an embodiment of the present invention, the FinFET LDMOS device 2 further comprises: a first epitaxial layer EP1 disposed on the source region SR. According to an embodiment of the present invention, the FinFET LDMOS device 2 further comprises: a second epitaxial layer EP2 disposed on the drain region DR. According to an embodiment of the present invention, for example, the first epitaxial layer EP1 and the second epitaxial layer EP2 comprise SiP epitaxial layers.

[0074] The above descriptions are only preferred embodiments of the present invention. All equivalent changes and modifications made according to the claims of the present invention should fall within the scope of the present invention.

Claims

1. A fin field effect transistor laterally diffused metal oxide semiconductor device, comprising: A semiconductor substrate of a first conductivity type; A first well of a first conductivity type is located in the semiconductor substrate; A second well of the second conductivity type is located in the semiconductor substrate and is juxtaposed with the first well of the first conductivity type; The semiconductor fin is disposed on the semiconductor substrate and extends along a first direction, wherein: The semiconductor fin comprises a first fin portion located in a first well of the first conductivity type and a second fin portion located in a second well of the second conductivity type; an additional semiconductor body adjacent to the semiconductor fin and extending along a second direction orthogonal to the first direction, wherein the additional semiconductor body is in direct contact with the first fin portion and the second fin portion; A source region of the second conductivity type is located in the first fin portion; A drain region of the second conductivity type is located in the second fin portion; a gate covering the semiconductor fin and extending along the second direction, wherein the gate partially overlaps the first fin portion and partially overlaps the second fin portion, wherein the additional semiconductor body is covered by the gate; as well as A single diffusion interruption structure is embedded in the second fin portion and located between the gate and the drain region.

2. The finfield effect transistor lateral diffused metal oxide semiconductor device according to claim 1, wherein: The first fin portion includes a channel region between the source region and the single diffusion interruption structure, wherein the channel region is disposed directly below the gate.

3. The FinFET LDMOS device according to claim 2, wherein: The second fin portion includes a drift region in the second well of the second conductivity type between the channel region and the single diffusion interruption structure, wherein the gate partially overlaps the drift region.

4. The FinFET LDMOS device according to claim 1, wherein: The single diffusion interrupt structure includes a bottom insulating layer and a top dummy gate directly disposed on the bottom insulating layer, wherein the top dummy gate is spaced apart from the gate, wherein the top dummy gate extends along the second direction, wherein the bottom insulating layer includes silicon oxide, and wherein the top dummy gate and the gate are metal gates.

5. The FinFET LDMOS device according to claim 1, wherein: The single diffusion interrupt structure is adjacent to the drain region.

6. The FinFET LDMOS device according to claim 1, wherein: A top surface of the additional semiconductor body is lower than a top surface of the semiconductor fin.

7. The FinFET LDMOS device according to claim 1, wherein: Also includes: A first epitaxial layer is disposed on the source region; and The second epitaxial layer is disposed on the drain region.

8. The FinFET LDMOS device according to claim 7, wherein: The first epitaxial layer and the second epitaxial layer include SiP.

9. The FinFET LDMOS device according to claim 1, wherein: The first conductivity type is a P type and the second conductivity type is an N type.

10. The FinFET LDMOS device according to claim 1, wherein: The semiconductor substrate is a silicon substrate, the first well of the first conductivity type is a P-type well, the second well of the second conductivity type is an N-type well, and the source region of the second conductivity type is an N-type well. + doped region, the drain region of the second conductivity type is N + Doped region.

11. A fin field effect transistor lateral diffused metal oxide semiconductor device, comprising: A semiconductor substrate of a first conductivity type; A first well of a first conductivity type is located in the semiconductor substrate; A second well of the second conductivity type is located in the semiconductor substrate and is juxtaposed with the first well of the first conductivity type; The semiconductor fin is disposed on the semiconductor substrate and extends along a first direction, wherein: The semiconductor fin comprises a first fin portion located in a first well of the first conductivity type and a second fin portion located in a second well of the second conductivity type; an additional semiconductor body adjacent to the semiconductor fin and extending along a second direction orthogonal to the first direction, wherein the additional semiconductor body is in direct contact with the first fin portion; A source region of the second conductivity type is located in the first fin portion; A drain region of the second conductivity type is located in the second fin portion; a gate covering the semiconductor fin and extending along the second direction, wherein the gate partially overlaps the first fin portion and partially overlaps the second fin portion, wherein the additional semiconductor body is covered by the gate; as well as A single diffusion interruption structure is embedded in the second fin portion and located between the gate and the drain region.

12. The FinFET LDMOS device according to claim 11, wherein: The first fin portion includes a channel region between the source region and the single diffusion interruption structure, wherein the channel region is disposed directly below the gate.

13. The FinFET LDMOS device according to claim 12, wherein: The second fin portion includes a drift region in the second well of the second conductivity type between the channel region and the single diffusion interruption structure, wherein the gate partially overlaps the drift region.

14. The FinFET LDMOS device according to claim 11, wherein: The single diffusion interrupt structure includes a bottom insulating layer and a top dummy gate directly disposed on the bottom insulating layer, wherein the top dummy gate is spaced apart from the gate, wherein the top dummy gate extends along the second direction, wherein the bottom insulating layer includes silicon oxide, and wherein the top dummy gate and the gate are metal gates.

15. The FinFET LDMOS device according to claim 11, wherein: The single diffusion interrupt structure is adjacent to the drain region.

16. The FinFET LDMOS device according to claim 11, wherein: A top surface of the additional semiconductor body is lower than a top surface of the semiconductor fin.

17. The FinFET LDMOS device of claim 11, further comprising: A first epitaxial layer is disposed on the source region; and The second epitaxial layer is disposed on the drain region.

18. The FinFET LDMOS device according to claim 17, wherein: The first epitaxial layer and the second epitaxial layer include SiP.

19. The FinFET LDMOS device according to claim 11, wherein: The first conductivity type is a P type and the second conductivity type is an N type.

20. The FinFET LDMOS device according to claim 11, wherein: The semiconductor substrate is a silicon substrate, the first well of the first conductivity type is a P-type well, the second well of the second conductivity type is an N-type well, and the source region of the second conductivity type is an N-type well. + doped region, the drain region of the second conductivity type is N + Doped region.

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