Laterally diffused metal oxide semiconductor device and preparation method thereof

Abstract

The invention relates to a laterally diffused metal oxide semiconductor device and a preparation method thereof. The laterally diffused metal oxide semiconductor device comprises at least one cellular structure. The cellular structure comprises a substrate; the N-type first well region is arranged in the substrate; the first well region is internally provided with a first partition region, a partition region and a second partition region which are sequentially arranged along a first direction; a P-type first doped region and a P-type second doped region, the first doped region being located in the first subregion, and the second doped region being located in the second subregion; the P-type source region and the P-type drain region are arranged in the substrate and are respectively positioned on two sides of the first doped region along the second direction; the first direction is the width direction of the conductive channel, and the second direction is the length direction of the conductive channel. According to the invention, the rapid increase of the output current in the on state can be inhibited, thereby improving the stability of the output current of the device and improving the reliability of the device.

Description

Technical Field

[0001] The present application relates to the field of integrated circuit technology, and in particular to a laterally diffused metal oxide semiconductor device and a method for preparing the same. Background Art

[0002] With the continuous development of semiconductor technology, the application of lateral double-diffuse metal oxide semiconductor (LDMOS) devices is becoming more and more widespread.

[0003] As an indispensable and important component in high-low voltage compatible processes, P-channel LDMOS plays an important role in high-low voltage level conversion. In a kilovolt-level P-channel LDMOS, in order to achieve the maximum off-state breakdown voltage, the charge amount in the drift region and the charge amount in the substrate should be balanced. However, when the device is in the on state, the excess holes injected into the drift region seriously break the charge balance. Under high voltage, the output current increases rapidly with the increase of the applied voltage, resulting in the on-state breakdown voltage of the device being much lower than the off-state breakdown voltage, thereby reducing the reliability of the device. Summary of the invention

[0004] Based on this, it is necessary to provide a laterally diffused metal oxide semiconductor device and a method for preparing the same in order to address the above problems.

[0005] In order to achieve the above objectives, in a first aspect, the present application provides a laterally diffused metal oxide semiconductor device, comprising at least one cellular structure, wherein the cellular structure comprises:

[0006] substrate;

[0007] An N-type first well region is provided in the substrate; a first partition region, a partition region, and a second partition region are provided in the first well region and are arranged in sequence along a first direction;

[0008] A P-type first doping region and a P-type second doping region, wherein the first doping region is located in the first sub-area, and the second doping region is located in the second sub-area;

[0009] A P-type source region and a P-type drain region are arranged in the substrate; the source region is located on one side of the first doped region along the second direction, and the drain region is located on the other side of the first doped region along the second direction; the first direction is the width direction of the conductive channel, and the second direction is the length direction of the conductive channel.

[0010] In one embodiment, the size of the source region along the first direction is equal to the size of the first doped region along the first direction; the size of the drain region along the first direction is equal to the size of the first well region along the first direction.

[0011] In one embodiment, a ratio of a size of the source region along the first direction to a size of the first well region along the first direction is between 0.3 and 0.5.

[0012] In one embodiment, the first partition includes a first sub-partition and a second sub-partition arranged along the second direction, and the second sub-partition is located between the first sub-partition and the source area;

[0013] The doping concentration of the N-type impurities in the first sub-region is lower than the doping concentration of the N-type impurities in the second sub-region;

[0014] The doping concentration of the P-type impurities in the first sub-region is greater than the doping concentration of the P-type impurities in the second sub-region.

[0015] In one of the embodiments, a size of the first sub-partition along the second direction is greater than a size of the second sub-partition along the second direction.

[0016] In one embodiment, a ratio of a size of the first sub-region along the second direction to a size of the first region along the second direction is between 0.6 and 0.8;

[0017] And / or, a boundary of the first doped region in the first sub-region away from the substrate surface is non-planar.

[0018] In one embodiment, the second partition includes a third sub-partition and a fourth sub-partition arranged along the second direction, and the third sub-partition is located between the drain area and the fourth sub-partition;

[0019] The doping concentration of the N-type impurities in the third sub-region is lower than the doping concentration of the N-type impurities in the fourth sub-region;

[0020] The doping concentration of the P-type impurities in the third sub-region is greater than the doping concentration of the P-type impurities in the fourth sub-region.

[0021] In one embodiment, a size of the third sub-partition along the second direction is smaller than a size of the fourth sub-partition along the second direction.

[0022] In one embodiment, a ratio of a size of the third sub-region along the second direction to a size of the second sub-region along the second direction is between 0.2 and 0.4;

[0023] And / or, a boundary of a side of the second doping region in the third sub-region away from the substrate surface is non-planar.

[0024] In one embodiment, the cellular structure further comprises:

[0025] An N-type body region and a P-type second well region are respectively arranged in the substrate and are respectively located on both sides of the first doped region along the second direction; the source region is located in the body region, and the drain region is located in the second well region;

[0026] An N-type body lead-out region is provided in the body region;

[0027] The gate is disposed on the substrate and covers a portion of the body region.

[0028] In one embodiment, the laterally diffused metal oxide semiconductor device includes a plurality of the cell structures sequentially arranged along the first direction;

[0029] In two adjacent cellular structures, the first partitions of the two cellular structures are adjacent to each other, or the second partitions of the two cellular structures are adjacent to each other.

[0030] In one embodiment, the drain regions of the plurality of cellular structures are sequentially connected to form an integrated drain region;

[0031] The source regions of two adjacent cellular structures are connected to form an integrated source region, and the gate regions of two adjacent cellular structures are connected to form an integrated gate.

[0032] In one of the embodiments, the lateral diffused metal oxide semiconductor device further includes a connection structure, and the connection structure electrically connects two adjacent integrated gates.

[0033] In a second aspect, an embodiment of the present application provides a method for preparing a laterally diffused metal oxide semiconductor device, comprising:

[0034] providing a substrate;

[0035] An N-type first well region, a P-type first doped region and a P-type second doped region are formed in the substrate; a first partition, a partition region and a second partition arranged in sequence along a first direction are provided in the first well region, the first doped region is formed in the first partition, and the second doped region is formed in the second partition;

[0036] A P-type source region is formed in the substrate and on one side of the first doped region along the second direction; a P-type drain region is formed in the substrate and on the other side of the first doped region along the second direction; the first direction is the width direction of the conductive channel, and the second direction is the length direction of the conductive channel.

[0037] In one embodiment, the substrate has an implantation region and a non-implantation region adjacent to each other, the implantation region has a first region, a second region, and a third region sequentially arranged along the first direction, the first region has a first sub-region and a second sub-region arranged along the second direction, and the third region has a third sub-region and a fourth sub-region arranged along the second direction;

[0038] The step of forming an N-type first well region, a P-type first doped region and a P-type second doped region in the substrate; the first well region is provided with a first partition, a partition region and a second partition arranged in sequence along a first direction, forming the first doped region in the first partition, and forming the second doped region in the second partition, comprises:

[0039] A first patterned mask layer is formed on the substrate; the first patterned mask layer includes a mask portion and a plurality of first mask strips and a plurality of second mask strips, the mask portion covers the non-injection area, the plurality of first mask strips are arranged in the first sub-area at intervals along the second direction, and the plurality of second mask strips are arranged in the third sub-area at intervals along the second direction;

[0040] Implanting N-type impurities into the substrate to form the first well region;

[0041] removing the first patterned mask layer;

[0042] The first doped region and the second doped region are formed in the substrate.

[0043] The lateral diffused metal oxide semiconductor device and the preparation method thereof provided by the present application are provided by dividing the first well region into a first partition, a partition region and a second partition arranged in sequence along the width direction of the conductive channel, and setting a first doped region in the first partition, and setting a second doped region in the second partition. In this way, the first doped region is equivalent to the conductive region, and the second doped region is equivalent to the auxiliary depletion region. When the device is in the on state, the drain region, the conductive region and the source region form a conductive path, and the partition region can prevent the current from flowing from the conductive region into the auxiliary depletion region, and the charge balance state of the auxiliary depletion region will not change. Compared with the traditional device, the conductive region width of the device provided by the present application is reduced, so that the proportion of the charge balance state of the device after and before the conduction is reduced. Therefore, the rapid increase of the output current in the on state can be suppressed, thereby improving the stability of the output current of the device and improving the reliability of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] In order to more clearly illustrate the technical solutions in the embodiments or exemplary embodiments of the present application, the drawings required for use in the description of the embodiments or exemplary embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0045] Figure 1 A schematic diagram of the partial structure of a laterally diffused metal oxide semiconductor device provided in an embodiment of the present application.

[0046] Figure 2 for Figure 1 Schematic top view of the device shown.

[0047] Figure 3 for Figure 2 Schematic diagram of the cross-sectional structure of the device shown in section AA.

[0048] Figure 4 for Figure 2 Schematic diagram of the cross-sectional structure of the device shown in section BB.

[0049] Figure 5 for Figure 2 Schematic diagram of the cross-sectional structure of the device shown in the CC section.

[0050] Figure 6 A schematic diagram of the partial structure of another laterally diffused metal oxide semiconductor device provided in an embodiment of the present application.

[0051] Figure 7 A schematic diagram of the partial structure of another laterally diffused metal oxide semiconductor device provided in an embodiment of the present application.

[0052] Figure 8 1 is an output characteristic curve of a device in the related art and a device in the embodiment of the present application.

[0053] Fig. 9 A schematic flow chart of a method for preparing a laterally diffused metal oxide semiconductor device provided in an embodiment of the present application.

[0054] Fig.10 for Fig. 9 A schematic diagram of a process flow of S200 in the preparation method shown.

[0055] Figures 11A-11D Schematic diagram of the structure of the device structure at the AA section during the preparation method shown.

[0056] Figures 12A-12D Schematic diagram of the structure of the device structure at the BB section during the preparation method shown.

[0057] Figures 13A-13D Schematic diagram of the structure of the device structure at the BB section during the preparation method shown.

[0058] Description of reference numerals:

[0059] 1. Laterally diffused metal oxide semiconductor device; 10. Cell structure; 11. Substrate; 111. Base layer; 1111. Buried layer; 1112. Deep well region; 112. Epitaxial layer; 12. First well region; 121. First partition; 1211. First sub-partition; 1212. Second sub-partition; 122. Partition region; 123. Second partition; 1231. Third sub-partition; 1232. Fourth sub-partition; 131. First doped region; 132. Second doped region Region; 141, source region; 142, drain region; 151, second well region; 152, body region; 153, body lead region; 16, gate; 161, connection structure; 17, field oxide layer; 18, dielectric layer; 191, first conductive structure; 192, second conductive structure; 201, first patterned mask layer; 2011, mask portion; 2012, first mask strip; 2013, second mask strip; 202, sacrificial oxide layer; 203, second patterned mask layer. DETAILED DESCRIPTION

[0060] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. Embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0061] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0062] It should be understood that when an element or layer is referred to as being "on, adjacent to, connected to or coupled to other elements or layers, it may be directly on, adjacent to, connected to or coupled to other elements or layers, or there may be intervening elements or layers. On the contrary, when an element is referred to as being "directly on, directly adjacent to, directly connected to or directly coupled to other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types and / or parts, these elements, components, regions, layers, doping types and / or parts should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, doping type or part from another element, component, region, layer, doping type or part. Therefore, without departing from the teachings of the present application, the first element, component, region, layer, doping type or portion discussed below may be represented as a second element, component, region, layer or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

[0063] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as "under other elements" or "under it" or "under it" will be oriented as being "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0064] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" and the like specify the presence of stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. At the same time, in this specification, the term "and / or" includes any and all combinations of the relevant listed items.

[0065] Embodiments of the application are described herein with reference to cross-sectional views that are schematic diagrams of ideal embodiments (and intermediate structures) of the application, so that variations in the shapes shown due to, for example, manufacturing techniques and / or tolerances can be expected. Therefore, embodiments of the application should not be limited to the specific shapes of the zones shown herein, but rather include shape deviations due to, for example, manufacturing techniques. For example, an implanted region shown as a rectangle typically has rounded or curved features and / or an implant concentration gradient at its edges, rather than a binary change from an implanted region to a non-implanted region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is performed. Therefore, the regions shown in the figures are schematic in nature, their shapes do not represent the actual shape of the region of the device, and do not limit the scope of the application.

[0066] First, refer to Figure 1 , Figure 2 , Figure 3 , Figure 4 and Figure 5 As shown, an embodiment of the present application provides a laterally diffused metal oxide semiconductor device 1, including at least one cellular structure 10, the cellular structure 10 includes a substrate 11, an N-type first well region 12, a P-type first doping region 131, a P-type second doping region 132, a P-type source region 141 and a P-type drain region 142.

[0067] The first well region 12 is provided in the substrate 11, and the first well region 12 is provided with a first partition 121, a partition region 122, and a second partition 123 arranged in sequence along the first direction X, the first doping region 131 is located in the first partition 121, and the second doping region 132 is located in the second partition 123. Here, one side of the partition region 122 is adjacent to the first partition 121, and the other side is adjacent to the second partition 123.

[0068] Furthermore, the source region 141 and the drain region 142 are both disposed in the substrate 11, and the source region 141 is located on one side of the first doping region 131 along the second direction Y, and the drain region 142 is located on the other side of the first doping region 131 along the second direction Y. The first direction X is the width direction of the conductive channel, and the second direction Y is the length direction of the conductive channel.

[0069] The laterally diffused metal oxide semiconductor device 1 provided in the embodiment of the present application is provided by dividing the first well region 12 into a first partition 121, a partition region 122 and a second partition 123 arranged in sequence along the width direction of the conductive channel, and providing a first doping region 131 in the first partition 121, and providing a second doping region 132 in the second partition 123. In this way, the first doping region 131 is equivalent to the conductive region, and the second doping region 132 is equivalent to the auxiliary depletion region. When the device is in the on state, the drain region 142, the conductive region and the source region 141 form a conductive path, and the partition region 122 can prevent the current from flowing from the conductive region into the auxiliary depletion region, and the charge balance state of the auxiliary depletion region will not change. Compared with the traditional device, the conductive region width of the device provided in the embodiment of the present application is reduced, so that the proportion of the charge balance state of the device after and before the conduction is reduced. Therefore, the rapid increase of the output current in the on state can be suppressed, thereby improving the stability of the output current of the device and improving the reliability of the device.

[0070] In one embodiment, the substrate 11 includes a base layer 111 and an epitaxial layer 112 which are stacked, wherein the base layer 111 and the epitaxial layer 112 are both P-type. It should be noted that the material of the base layer 111 can be single crystal silicon, polycrystalline silicon, amorphous silicon, germanium silicon compound, silicon-on-insulator (SOI) or low temperature polysilicon (LTPS), etc., or other materials known to those skilled in the art, and the base layer 111 can provide a supporting foundation for the structural layer on the base layer 111.

[0071] In one embodiment, the size of the source region 141 along the first direction X is equal to the size of the first doping region 131 along the first direction X. The size of the drain region 142 along the first direction X is equal to the size of the first well region 12 along the first direction X.

[0072] In an example, the size of the source region 141 along the first direction X is the width of the source region 141 , the size of the first doping region 131 along the first direction X is the width of the first doping region 131 , the size of the drain region 142 along the first direction X is the width of the drain region 142 , and the size of the first well region 12 along the first direction X is the width of the first well region 12 .

[0073] Thus, by reducing the width of the source region 141 , the hole injection efficiency of the source region 141 at the same voltage can be reduced, which is beneficial to suppressing the rapid increase of the output current in the on state, thereby improving the stability of the device output current and improving the reliability of the device.

[0074] In one embodiment, the ratio of the size of the source region 141 along the first direction X to the size of the first well region 12 along the first direction X is between 0.3 and 0.5, that is, the ratio of the size of the first doped region 131 (or the first sub-region 121) along the first direction X to the size of the first well region 12 along the first direction X is between 0.3 and 0.5.

[0075] Exemplarily, the ratio of the dimension of the source region 141 along the first direction X to the dimension of the first well region 12 along the first direction X may be 0.3, 0.35, 0.4, 0.45, 0.48 or 0.5.

[0076] The above arrangement can make the effective conductive channel width account for 30%-50% of the width of the entire cell structure 10, that is, compared with traditional devices, the conductive channel width is reduced, which is beneficial to suppress the rapid increase of the output current in the on state, thereby improving the stability of the device output current and improving the reliability of the device.

[0077] It can be understood that the ratio of the sum of the dimensions of the partition region 122 and the second doping region 132 (or the second sub-region 123) along the first direction X to the dimension of the first well region 12 along the first direction X is between 0.5 and 0.7. That is, the ratio of the sum of the dimensions of the partition region 122 and the second doping region 132 (or the second sub-region 123) along the width direction of the conductive channel to the dimension of the first well region 12 along the width direction of the conductive channel is between 0.5 and 0.7.

[0078] In one embodiment, the dimension of the first well region 12 in a cell structure 10 along the width direction of the conductive channel is equal to the dimension of the cell structure 10 along the width direction of the conductive channel. Exemplarily, the dimension of the cell structure 10 along the width direction of the conductive channel is the width of the cell structure 10.

[0079] In one embodiment, referring to Figure 2 As shown, the first partition 121 includes a first sub-partition 1211 and a second sub-partition 1212 arranged along the second direction Y, the second sub-partition 1212 is located between the first sub-partition 1211 and the source region 141, and the first sub-partition 1211 is located between the drain region 142 and the second sub-partition 1212. The doping concentration of the N-type impurity in the first sub-partition 1211 is less than the doping concentration of the N-type impurity in the second sub-partition 1212. The doping concentration of the P-type impurity in the first sub-partition 1211 is greater than the doping concentration of the P-type impurity in the second sub-partition 1212.

[0080] The above configuration can increase the doping concentration of the P-type impurities in the first doping region 131 , which is beneficial to preventing the device from breaking down prematurely when in the on state, thereby improving the reliability of the device.

[0081] In one embodiment, the size of the first sub-partition 1211 along the second direction Y is greater than the size of the second sub-partition 1212 along the second direction Y. In one example, the size of the first sub-partition 1211 along the second direction Y is the length of the first sub-partition 1211 , and the size of the second sub-partition 1212 along the second direction Y is the length of the second sub-partition 1212 .

[0082] The above setting is equivalent to making the first sub-partition 1211 in the first partition 121 account for a larger proportion, which is beneficial to further increase the doping concentration of P-type impurities in the first sub-partition 1211, and further helps to prevent the device from breaking down prematurely in the turned-on state, thereby improving the reliability of the device.

[0083] In one embodiment, the ratio of the size of the first sub-region 1211 along the second direction Y to the size of the first region 121 along the second direction Y is between 0.6 and 0.8. For example, the ratio of the size of the first sub-region 1211 along the second direction Y to the size of the first region 121 along the second direction Y may be 0.6, 0.65, 0.72, 0.76 or 0.8.

[0084] In one embodiment, a ratio of a size of the first sub-region 1211 along the length direction of the conductive channel to a size of the first doped region 131 along the length direction of the conductive channel is between 0.6 and 0.8.

[0085] The above setting can make the doping concentration of P-type impurities in the first partition 121 within a reasonable range. On the one hand, it can prevent the device from breaking down prematurely in the on state, which is beneficial to improving the reliability of the device. On the other hand, it can avoid the doping concentration of N-type impurities in the first partition 121 being too low, thereby causing the performance of the device to deteriorate.

[0086] In one embodiment, referring to Figure 3 As shown, the boundary of one side of the first doped region 131 in the first sub-region 1211 away from the surface of the substrate 11 is a non-plane. In one example, the bottom surface of the first doped region 131 in the first sub-region 1211 is a non-plane. Exemplarily, the non-plane can be a regular wavy surface, an irregular wavy surface, a serrated surface, a crenel-shaped surface, etc.

[0087] It should be noted that, in the embodiment of the present application, the N-type impurities are injected into the first sub-division 1211 in segments, so that the doping concentration of the N-type impurities in the first sub-division 1211 is lower than the doping concentration of the N-type impurities in the second sub-division 1212, thereby making the doping concentration of the P-type impurities in the first sub-division 1211 higher than the doping concentration of the P-type impurities in the second sub-division 1212. Furthermore, the segmented injection process is adopted to make the bottom surface of the first doping region 131 in the first sub-division 1211 non-planar, and at the same time, the segmented injection process is adopted to achieve the control of the output current of the device in the on state without introducing additional complex processes.

[0088] In one embodiment, referring to Figure 2 As shown, the second sub-region 123 includes a third sub-region 1231 and a fourth sub-region 1232 arranged along the second direction Y, the third sub-region 1231 is located between the drain region 142 and the fourth sub-region 1232, and the fourth sub-region 1232 is located between the source region 141 and the third sub-region 1231. The doping concentration of the N-type impurity in the third sub-region 1231 is less than the doping concentration of the N-type impurity in the fourth sub-region 1232. The doping concentration of the P-type impurity in the third sub-region 1231 is greater than the doping concentration of the P-type impurity in the fourth sub-region 1232.

[0089] The above configuration can increase the doping concentration of the P-type impurities in the second doping region 132 , which is beneficial to preventing the device from breaking down prematurely when in the on state, thereby improving the reliability of the device.

[0090] In one embodiment, the size of the third sub-partition 1231 along the second direction Y is smaller than the size of the fourth sub-partition 1232 along the second direction Y. In one example, the size of the third sub-partition 1231 along the second direction Y is the length of the third sub-partition 1231 , and the size of the fourth sub-partition 1232 along the second direction Y is the length of the fourth sub-partition 1232 .

[0091] The above-mentioned setting is equivalent to making the proportion of the third sub-partition 1231 in the second partition 123 larger, so that the N-type doping concentration of the second partition 123 is greater than the N-type doping concentration of the first partition 121. Since the first partition 121 injects holes in the turned-on state, the depletion area of ​​the first doping region 131 is reduced. Therefore, by increasing the concentration of N-type impurities in the second partition 123 to assist the depletion of the first doping region 131, the degree of destruction of the charge balance of the first partition 121 is reduced, and the rapid increase of the output current in the turned-on state is suppressed, thereby improving the stability of the device output current and improving the reliability of the device.

[0092] In one embodiment, the ratio of the size of the third sub-region 1231 along the second direction Y to the size of the second region 123 along the second direction Y is between 0.2 and 0.4. For example, the ratio of the size of the third sub-region 1231 along the second direction Y to the size of the second region 123 along the second direction Y can be 0.2, 0.25, 0.29, 0.32, 0.35, 0.38 or 0.4.

[0093] In one embodiment, a ratio of a size of the third sub-region 1231 along the length direction of the conductive channel to a size of the second doped region 132 along the length direction of the conductive channel is between 0.2 and 0.4.

[0094] The above setting can make the doping concentration of P-type impurities in the second doping region 132 within a reasonable range. On the one hand, it can assist the depletion of the first doping region 131 and reduce the degree of damage to the charge balance of the first partition 121. On the other hand, it can avoid the doping concentration of N-type impurities in the second partition 123 being too low, thereby causing the performance of the device to deteriorate.

[0095] In one embodiment, referring to Figure 5 As shown, the boundary of one side of the second doping region 132 in the third sub-region 1231 away from the surface of the substrate 11 is a non-plane. In one example, the bottom surface of the first doping region 131 in the third sub-region 1231 is a non-plane. Exemplarily, the non-plane can be a regular wavy surface, an irregular wavy surface, a serrated surface, a crenel-shaped surface, etc.

[0096] It should be noted that, in the embodiment of the present application, the N-type impurities are injected into the third sub-region 1231 in segments, so that the doping concentration of the N-type impurities in the third sub-region 1231 is lower than the doping concentration of the N-type impurities in the fourth sub-region 1232, thereby making the doping concentration of the P-type impurities in the third sub-region 1231 higher than the doping concentration of the P-type impurities in the fourth sub-region 1232. Further, the segmented injection process is adopted to make the bottom surface of the first doping region 131 in the third sub-region 1231 non-planar, and at the same time, the segmented injection process is adopted to achieve the control of the output current of the device in the on state without introducing additional complex processes.

[0097] In one embodiment, referring to Figure 1 , Figure 2 , Figure 3 , Figure 4 and Figure 5As shown, the cell structure 10 also includes an N-type body region 152, a P-type body lead region 153, a P-type second well region 151 and a gate 16. The body region 152 and the second well region 151 are respectively arranged in the substrate 11, and are respectively located on both sides of the first doping region 131 along the second direction Y. The source region 141 and the body lead region 153 are located in the body region 152, and the drain region 142 is located in the second well region 151. The gate 16 is arranged on the substrate 11 and covers part of the body region 152, and the area covered by the gate 16 is a conductive channel. Further, an N-type deep well region 1112 and a P-type buried layer 1111 are arranged in the base layer 111.

[0098] In one example, the dimension of the gate 16 along the first direction X is equal to the dimension of the source region 141 along the first direction X. In one example, the width of the gate 16 is equal to the width of the source region 141. In this way, the ratio of the width of the gate 16 to the width of the cell structure 10 can be equal to the ratio of the width of the first doping region 131 to the width of the cell structure 10, thereby reducing the width of the conductive channel, which is beneficial to suppressing the rapid increase of the output current in the on state, thereby improving the stability of the device output current and improving the reliability of the device.

[0099] In one embodiment, referring to Figure 6 As shown, the lateral diffused metal oxide semiconductor device 1 includes a plurality of cellular structures 10 sequentially arranged along a first direction X. In two adjacent cellular structures 10, the first partitions 121 of the two cellular structures 10 are adjacent, or the second partitions 123 of the two cellular structures 10 are adjacent.

[0100] In one example, Figure 6 Taking the orientation in as an example, from bottom to top, the first partition 121 of the first cellular structure 10 is adjacent to the first partition 121 of the second cellular structure 10, the second partition 123 of the second cellular structure 10 is adjacent to the second partition 123 of the third cellular structure 10, the first partition 121 of the third cellular structure 10 is adjacent to the first partition 121 of the fourth cellular structure 10... and so on.

[0101] The above arrangement is conducive to increasing the arrangement density of the cellular structure 10 per unit area of ​​the device, thereby improving the device performance.

[0102] In one embodiment, referring to Figure 7 As shown, the drain regions 142 of the plurality of cell structures 10 are sequentially connected to form an integrated drain region 142. The source regions 141 of two adjacent cell structures 10 are connected to form an integrated source region 141, and the gates 16 of two adjacent cell structures 10 are connected to form an integrated gate 16.

[0103] The above arrangement is conducive to increasing the arrangement density of the cellular structure 10 per unit area of ​​the device, thereby improving the device performance.

[0104] In one embodiment, the LDMOS device 1 further includes a connection structure 161 , and the connection structure 161 electrically connects two adjacent integrated gates 16 .

[0105] In one embodiment, referring to Figure 1 and Figure 3 As shown, the lateral diffused metal oxide semiconductor device 1 further includes a field oxide layer 17, a dielectric layer 18, a first conductive structure 191 and a second conductive structure 192. The field oxide layer 17 at least covers the first well region 12, and the dielectric layer 18 covers the field oxide layer 17, the gate 16 and the exposed surface of the substrate 11. The first conductive structure 191 penetrates the dielectric layer 18 and is electrically connected to the drain region 142, and the second conductive structure 192 penetrates the dielectric layer 18 and is electrically connected to the source region 141. Further, the second conductive structure 192 is also electrically connected to the body lead-out region 153. In one example, the first conductive structure 191 is a drain, and the second conductive structure 192 is a source.

[0106] Reference Figure 8 As shown, the applicant has tested the performance of devices in the related art and the devices in the embodiments of the present application. It can be seen from the figure that the devices in the embodiments of the present application can better suppress the upward warping of the output characteristic curve under high voltage, thereby improving the stability of the output current.

[0107] Second, refer to Fig. 9 As shown, the embodiment of the present application provides a method for preparing a laterally diffused metal oxide semiconductor device, which specifically includes the following steps:

[0108] S100: Provide a substrate 11. Exemplarily, the substrate 11 includes a base layer 111 and an epitaxial layer 112 which are stacked, wherein both the base layer 111 and the epitaxial layer 112 are of P type.

[0109] S200: forming an N-type first well region 12, a P-type first doping region 131, and a P-type second doping region 132 in the substrate 11. The first well region 12 is provided with a first sub-region 121, a partition region 122, and a second sub-region 123 arranged in sequence along the first direction X, a first doping region 131 is formed in the first sub-region 121, and a second doping region 132 is formed in the second sub-region 123.

[0110] S300: forming a P-type source region 141 in the substrate 11 and on one side of the first doping region 131 along the second direction Y; forming a P-type drain region 142 in the substrate 11 and on the other side of the first doping region 131 along the second direction Y. The first direction X is the width direction of the conductive channel, and the second direction Y is the length direction of the conductive channel.

[0111] The method for preparing a lateral diffused metal oxide semiconductor device provided in the embodiment of the present application is to divide the first well region 12 into a first partition 121, a partition region 122 and a second partition 123 arranged in sequence along the width direction of the conductive channel, and to set a first doping region 131 in the first partition 121, and to set a second doping region 132 in the second partition 123. In this way, the first doping region 131 is equivalent to the conductive region, and the second doping region 132 is equivalent to the auxiliary depletion region. When the device is in the on state, the drain region 142, the conductive region and the source region 141 form a conductive path, and the partition region 122 can prevent the current from flowing from the conductive region to the auxiliary depletion region, and the charge balance state of the auxiliary depletion region will not change. Compared with the traditional device, the conductive region width of the device provided in the embodiment of the present application is reduced, so that the proportion of the charge balance state of the device after and before the conduction is reduced. Therefore, the rapid increase of the output current in the on state can be suppressed, thereby improving the stability of the device output current and improving the reliability of the device.

[0112] In one embodiment, the substrate 11 has adjacent implantation regions (not shown in the figure) and non-implantation regions (not shown in the figure), the implantation regions have a first region (not shown in the figure), a second region (not shown in the figure) and a third region (not shown in the figure) arranged in sequence along a first direction X, the first region has a first sub-region (not shown in the figure) and a second sub-region (not shown in the figure) arranged along a second direction Y, and the third region has a third sub-region (not shown in the figure) and a fourth sub-region (not shown in the figure) arranged along the second direction Y.

[0113] Here, it should be noted that the injection region refers to the region on the substrate 11 where the first well region 12 needs to be formed, and the non-injection region refers to the region on the substrate 11 where the first well region 12 is not formed. The first region is the region on the substrate 11 corresponding to the first partition 121, the second region is the region on the substrate 11 corresponding to the partition region 122, the third region is the region on the substrate 11 corresponding to the second partition 123, the first sub-region is the region on the substrate 11 corresponding to the first sub-region 1211, the second sub-region is the region on the substrate 11 corresponding to the second sub-region 1212, the third sub-region is the region on the substrate 11 corresponding to the third sub-region 1231, and the fourth sub-region is the region on the substrate 11 corresponding to the fourth sub-region 1232.

[0114] In one example, S200 specifically includes the following steps:

[0115] S210: forming a first patterned mask layer 201 on the substrate 11. The structure after the first patterned mask layer 201 is formed is as follows Fig.11A , Fig. 12A and Fig.13A As shown, the first patterned mask layer 201 includes a mask portion 2011 and a plurality of first mask strips 2012 and a plurality of second mask strips 2013, the mask portion 2011 covers the non-implantation region, the plurality of first mask strips 2012 are arranged at intervals in the first sub-region along the second direction Y, and the plurality of second mask strips 2013 are arranged at intervals in the third sub-region along the second direction Y. Exemplarily, the first patterned mask layer 201 is a photoresist.

[0116] In this way, it is equivalent to covering the first sub-region and the third sub-region in sections, which facilitates the subsequent process to perform segmented implantation on the first sub-region and the third sub-region.

[0117] S220: N-type impurities are implanted into the substrate 11 to form a first well region 12. Exemplarily, the N-type impurities are implanted using an ion implantation process.

[0118] Specifically, refer to Fig.11A As shown, part of the first sub-region is covered by the first mask strip 2012, and therefore, the region covered by the first mask strip 2012 is not implanted with N-type impurities, so that the doping concentration of the N-type impurities in the first sub-region is less than the doping concentration of the N-type impurities in the second sub-region, and thus the doping concentration of the P-type impurities in the first sub-region can be greater than the doping concentration of the P-type impurities in the second sub-region. The third sub-region is the same as the first sub-region, and will not be described in detail here.

[0119] S230: removing the first patterned mask layer 201. The structure after the first patterned mask layer 201 is removed is as follows Fig. 11B , Fig. 12B and Fig. 13B In one example, after the first patterned mask layer 201 is removed, a sacrificial oxide layer 202 is formed on the surface of the substrate 11 .

[0120] S240 : forming a first doping region 131 and a second doping region 132 in the substrate 11 .

[0121] In one embodiment, referring to Fig. 11B , Fig. 11C , Fig. 12B , Fig. 12C , Fig. 13B and Fig. 13C As shown, S240 specifically includes the following steps:

[0122] S241: Perform the first P-type impurity implantation into the substrate 11.

[0123] S242 : removing the sacrificial oxide layer 202 .

[0124] S243 : implanting N-type impurities into the substrate 11 to form a body region 152 .

[0125] S244 : forming a second patterned mask layer 203 on the substrate 11 .

[0126] S245: implanting P-type impurities into the substrate 11 for the second time.

[0127] S246: Annealing the substrate 11.

[0128] It should be noted that since ion implantation will damage the substrate 11, the mobility and life of the electron-hole pairs will be greatly reduced. In addition, most of the implanted ions are not in the lattice position in a substitutional form. In order to activate the ions and restore the original mobility, the substrate 11 must be annealed at an appropriate temperature. Annealing can repair lattice defects and move impurity atoms to lattice points to activate impurities. Generally, it takes about 450-550°C to repair lattice defects and 900-1000°C to activate impurities. The activation of impurities is related to time and temperature. The longer the time and the higher the temperature, the more fully the impurities are activated. Commonly used annealing methods for the substrate 11 include high-temperature thermal annealing and rapid thermal annealing (RTA). In one example, a high-temperature thermal annealing process can be used for annealing. Specifically, a high-temperature furnace is used to heat the silicon wafer to 800-1000°C and maintain it for 20-40 minutes. In another example, a rapid thermal annealing process may be used for annealing. Compared with a high temperature thermal annealing process, the rapid thermal annealing process has a shorter annealing time, can avoid diffusion of doped ions caused by long-term high temperature, and reduce instantaneous enhanced diffusion of doped ions.

[0129] The structure after annealing is as follows Fig.11D , Fig.12D and Fig.13D shown.

[0130] In one embodiment, S300 includes the following steps:

[0131] S400 : forming a field oxide layer 17 on the substrate 11 .

[0132] S500 : forming a gate 16 on the substrate 11 .

[0133] S600 : forming a source region 141 , a drain region 142 and a body lead-out region 153 in the substrate 11 .

[0134] S700: A dielectric layer 18, a first conductive structure 191, and a second conductive structure 192 are formed on the substrate 11. The first conductive structure 191 penetrates the dielectric layer 18 and is electrically connected to the drain region 142, and the second conductive structure 192 penetrates the dielectric layer 18 and is electrically connected to the source region 141. Furthermore, the second conductive structure 192 is also electrically connected to the body lead-out region 153. In one example, the first conductive structure 191 is a drain, and the second conductive structure 192 is a source.

[0135] It should be understood that, in the embodiments of the present application, although the various steps in the flowchart of the accompanying drawings are displayed in sequence according to the indication of the arrows, these steps are not necessarily executed in sequence in the order indicated by the arrows. Unless there is a clear description in this article, the execution of these steps is not strictly limited in order, and these steps can be executed in other orders. Moreover, at least a portion of the steps in the accompanying drawings may include multiple steps or multiple stages, and these steps or stages are not necessarily executed at the same time, but can be executed at different times, and the execution order of these steps or stages is not necessarily to be carried out in sequence, but can be executed in turn or alternately with other steps or at least a portion of the steps or stages in other steps.

[0136] In the description of this specification, the description with reference to the terms "some embodiments", "other embodiments", "ideal embodiments", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.

[0137] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features of the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0138] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be construed as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent application shall be subject to the attached claims.

Claims

1. A laterally diffused metal oxide semiconductor device, characterized in that: The invention comprises at least one cellular structure, wherein the cellular structure comprises: substrate; An N-type first well region is provided in the substrate; a first partition region, a partition region, and a second partition region are provided in the first well region and are arranged in sequence along a first direction; A P-type first doping region and a P-type second doping region, wherein the first doping region is located in the first sub-area, and the second doping region is located in the second sub-area; A P-type source region and a P-type drain region are arranged in the substrate; the source region is located on one side of the first doped region along the second direction, and the drain region is located on the other side of the first doped region along the second direction; the first direction is the width direction of the conductive channel, and the second direction is the length direction of the conductive channel.

2. The laterally diffused metal oxide semiconductor device according to claim 1, characterized in that: The size of the source region along the first direction is equal to the size of the first doped region along the first direction; the size of the drain region along the first direction is equal to the size of the first well region along the first direction.

3. The laterally diffused metal oxide semiconductor device according to claim 2, characterized in that: The ratio of the size of the source region along the first direction to the size of the first well region along the first direction is between 0.3 and 0.

5.

4. The laterally diffused metal oxide semiconductor device according to claim 1, characterized in that: The first partition includes a first sub-partition and a second sub-partition arranged along the second direction, and the second sub-partition is located between the first sub-partition and the source area; The doping concentration of the N-type impurities in the first sub-region is lower than the doping concentration of the N-type impurities in the second sub-region; The doping concentration of the P-type impurities in the first sub-region is greater than the doping concentration of the P-type impurities in the second sub-region.

5. The laterally diffused metal oxide semiconductor device according to claim 4, characterized in that: A size of the first sub-partition along the second direction is greater than a size of the second sub-partition along the second direction.

6. The laterally diffused metal oxide semiconductor device according to claim 4, characterized in that: A ratio of a size of the first sub-region along the second direction to a size of the first region along the second direction is between 0.6 and 0.8; And / or, a boundary of the first doped region in the first sub-region away from the substrate surface is non-planar.

7. The laterally diffused metal oxide semiconductor device according to claim 1, characterized in that: The second partition includes a third sub-partition and a fourth sub-partition arranged along the second direction, and the third sub-partition is located between the drain area and the fourth sub-partition; The doping concentration of the N-type impurities in the third sub-region is lower than the doping concentration of the N-type impurities in the fourth sub-region; The doping concentration of the P-type impurities in the third sub-region is greater than the doping concentration of the P-type impurities in the fourth sub-region.

8. The laterally diffused metal oxide semiconductor device according to claim 7, characterized in that: A size of the third sub-partition along the second direction is smaller than a size of the fourth sub-partition along the second direction.

9. The laterally diffused metal oxide semiconductor device according to claim 8, characterized in that: A ratio of a size of the third sub-region along the second direction to a size of the second sub-region along the second direction is between 0.2 and 0.4; And / or, a boundary of the second doped region in the third sub-region away from the substrate surface is non-planar.

10. The laterally diffused metal oxide semiconductor device according to any one of claims 1 to 9, characterized in that: The cellular structure also includes: An N-type body region and a P-type second well region are respectively arranged in the substrate and are respectively located on both sides of the first doped region along the second direction; the source region is located in the body region, and the drain region is located in the second well region; An N-type body lead-out region is provided in the body region; The gate is disposed on the substrate and covers a portion of the body region.

11. The laterally diffused metal oxide semiconductor device according to claim 10, characterized in that: The laterally diffused metal oxide semiconductor device comprises a plurality of the cell structures sequentially arranged along the first direction; In two adjacent cellular structures, the first partitions of the two cellular structures are adjacent to each other, or the second partitions of the two cellular structures are adjacent to each other.

12. The laterally diffused metal oxide semiconductor device according to claim 11, characterized in that: The drain regions of the plurality of cellular structures are sequentially connected to form an integrated drain region; The source regions of two adjacent cellular structures are connected to form an integrated source region, and the gate regions of two adjacent cellular structures are connected to form an integrated gate.

13. The laterally diffused metal oxide semiconductor device according to claim 12, characterized in that: The lateral diffused metal oxide semiconductor device further includes a connection structure, which electrically connects two adjacent integrated gates.

14. A method for preparing a laterally diffused metal oxide semiconductor device, characterized in that: include: providing a substrate; Forming an N-type first well region, a P-type first doping region and a P-type second doping region in the substrate; A first partition, a partition region, and a second partition arranged in sequence along a first direction are provided in the first well region, the first doping region is formed in the first partition, and the second doping region is formed in the second partition; A P-type source region is formed in the substrate and on one side of the first doped region along the second direction; a P-type drain region is formed in the substrate and on the other side of the first doped region along the second direction; the first direction is the width direction of the conductive channel, and the second direction is the length direction of the conductive channel.

15. The method for preparing a laterally diffused metal oxide semiconductor device according to claim 14, characterized in that: The substrate comprises an implantation region and a non-implantation region adjacent to each other, the implantation region comprises a first region, a second region and a third region sequentially arranged along the first direction, the first region comprises a first sub-region and a second sub-region arranged along the second direction, and the third region comprises a third sub-region and a fourth sub-region arranged along the second direction; The steps of forming an N-type first well region, a P-type first doped region and a P-type second doped region in the substrate; providing a first partition, a partition region and a second partition arranged in sequence along a first direction in the first well region, forming the first doped region in the first partition, and forming the second doped region in the second partition include: A first patterned mask layer is formed on the substrate; the first patterned mask layer includes a mask portion and a plurality of first mask strips and a plurality of second mask strips, the mask portion covers the non-injection area, the plurality of first mask strips are arranged in the first sub-area at intervals along the second direction, and the plurality of second mask strips are arranged in the third sub-area at intervals along the second direction; Implanting N-type impurities into the substrate to form the first well region; removing the first patterned mask layer; The first doped region and the second doped region are formed in the substrate.

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