Laterally diffused metal oxide semiconductor device

Abstract

The invention relates to a laterally diffused metal oxide semiconductor device, which comprises a substrate; the body region and the drift region are arranged in the substrate along a first direction; a drain region is arranged in the drift region, and a source region is arranged in the body region; the first direction is perpendicular to the thickness direction of the substrate; the first dielectric layer is arranged on the substrate and at least covers part of the body region and part of the drift region; the first field plate is arranged on the side, away from the substrate, of the first dielectric layer, the orthographic projection of the first field plate on the substrate is located between the body region and the drain region, and part of the drift region is covered with the first field plate; the first high-K dielectric layer is arranged on the side, away from the substrate, of the first dielectric layer and connected with the end, close to the drain region, of the first field plate, and the orthographic projection of the first high-K dielectric layer on the substrate covers part of the drift region. According to the laterally diffused metal oxide semiconductor device provided by the invention, on one hand, the withstand voltage of the device can be improved, and on-resistance can be smaller under the same breakdown voltage on the other hand.

Description

Technical Field

[0001] The present application relates to the technical field of integrated circuits, and in particular to a laterally diffused metal oxide semiconductor device. Background Art

[0002] With the continuous development of semiconductor technology, the application of lateral double-diffuse metal oxide semiconductor (LDMOS) devices is becoming more and more widespread.

[0003] The key to LDMOS devices is to achieve high voltage and low on-resistance. In order to improve the withstand voltage, it is necessary to increase the length of the drift region and reduce the concentration of the drift region. However, the on-resistance of the device also increases. In order to improve the withstand voltage of the device and alleviate the contradictory relationship between withstand voltage and on-resistance, field plate technology is introduced as an effective means. Field plate technology is a junction termination technology that can weaken the peak electric field at the PN junction interface. The field plate makes the electric field line part of the donor impurities in the drift region pointing to the acceptor impurities in the P-type body region point from the donor impurities to the field plate, which expands the width of the PN junction depletion region, increases the curvature radius of the depletion region, and alleviates the electric field strength on the device surface. However, the surface electric field strength of the drift region at the edge of the field plate is large, which restricts the improvement of the breakdown voltage of LDMOS devices by field plate technology. Summary of the invention

[0004] Based on this, it is necessary to provide a laterally diffused metal oxide semiconductor device to address the above problems.

[0005] In order to achieve the above objectives, in a first aspect, an embodiment of the present application provides a laterally diffused metal oxide semiconductor device, comprising:

[0006] substrate;

[0007] The body region and the drift region are arranged in the substrate along a first direction; a drain region is provided in the drift region, and a source region is provided in the body region; the first direction is perpendicular to the thickness direction of the substrate;

[0008] A first dielectric layer is disposed on the substrate and covers at least a portion of the body region and a portion of the drift region;

[0009] A first field plate is disposed on a side of the first dielectric layer away from the substrate, wherein an orthographic projection of the first field plate on the substrate is located between the body region and the drain region and covers a portion of the drift region;

[0010] The first high-K dielectric layer is disposed on a side of the first dielectric layer away from the substrate and connected to an end of the first field plate close to the drain region. The orthographic projection of the first high-K dielectric layer on the substrate covers a portion of the drift region.

[0011] The laterally diffused metal oxide semiconductor device provided in the embodiment of the present application can adjust the electric flux distribution on the surface of the drift region by setting a first high-K dielectric layer connected to the first field plate on the side of the first dielectric layer away from the substrate, thereby weakening the high peak electric field on the surface of the drift region below the first field plate close to the drain region. On the one hand, the device's withstand voltage can be improved, and on the other hand, a smaller on-resistance can be achieved under the same breakdown voltage.

[0012] In one embodiment, the laterally diffused metal oxide semiconductor device further comprises:

[0013] A first doped region, disposed in the substrate; a portion of the first doped region is located between the body region and the drift region;

[0014] A gate is arranged on a side of the first dielectric layer away from the substrate, and the orthographic projection of the gate on the substrate covers part of the body region and part of the first doped region; one end of the first field plate is connected to one end of the gate close to the drain region, and the other end of the first field plate extends in a direction close to the drain region.

[0015] In one embodiment, the gate and the first field plate are an integrated structure.

[0016] In one embodiment, the first field plate includes an inclined portion and a flat portion, the inclined portion connects the flat portion and the gate; the distance between the flat portion and the substrate is greater than the distance between the gate and the substrate;

[0017] A surface of the first high-K dielectric layer close to the substrate is flush with a surface of the flat portion close to the substrate, and / or a surface of the first high-K dielectric layer away from the substrate is flush with a surface of the flat portion away from the substrate.

[0018] In one of the embodiments, the laterally diffused metal oxide semiconductor device further comprises a first conductive structure electrically connected to the drain region, and an orthographic projection of the first conductive structure on the substrate covers at least a portion of the drain region;

[0019] One end of the first high-K dielectric layer close to the drain region is connected to the first conductive structure.

[0020] In one embodiment, the laterally diffused metal oxide semiconductor device further comprises:

[0021] a second dielectric layer, disposed on a side of the first field plate away from the substrate, and a side of the first high-K dielectric layer away from the substrate;

[0022] A second field plate is arranged on a side of the second dielectric layer away from the substrate; the orthographic projection of the second field plate on the substrate covers the body region, the substrate between the body region and the drift region, and a portion of the drift region;

[0023] The second high-K dielectric layer is disposed on a side of the second dielectric layer away from the substrate and connected to an end of the second field plate close to the drain region. The orthographic projection of the second high-K dielectric layer on the substrate covers a portion of the drift region.

[0024] In one of the embodiments, the laterally diffused metal oxide semiconductor device further comprises a third field plate disposed on a side of the second dielectric layer away from the substrate, and an orthographic projection of the third field plate on the substrate covers the drain region and a portion of the drift region;

[0025] The second high-K dielectric layer is also connected to an end of the third field plate close to the source region.

[0026] In one embodiment, a surface of the second high-K dielectric layer close to the substrate, a surface of the second field plate close to the substrate, and a surface of the third field plate close to the substrate are flush;

[0027] And / or, a surface of the second high-K dielectric layer away from the substrate, a surface of the second field plate away from the substrate, and a surface of the third field plate away from the substrate are flush.

[0028] In one embodiment, the dielectric constant of the first high-K dielectric layer is between 21 and 200;

[0029] And / or, the dielectric constant of the second high-K dielectric layer is between 21-200.

[0030] In a second aspect, an embodiment of the present application provides a laterally diffused metal oxide semiconductor device, comprising:

[0031] substrate;

[0032] The body region and the drift region are arranged in the substrate along a first direction; a drain region is provided in the drift region, and a source region is provided in the body region; the first direction is perpendicular to the thickness direction of the substrate;

[0033] A gate, disposed on the substrate, wherein an orthographic projection of the gate on the substrate covers a portion of the body region;

[0034] A second dielectric layer is provided on a side of the gate away from the substrate;

[0035] A second field plate is disposed on a side of the second dielectric layer away from the substrate; an orthographic projection of the second field plate on the substrate covers the body region and a portion of the drift region;

[0036] The second high-K dielectric layer is disposed on a side of the second dielectric layer away from the substrate and connected to an end of the second field plate close to the drain region. The orthographic projection of the second high-K dielectric layer on the substrate covers a portion of the drift region.

[0037] In one of the embodiments, the laterally diffused metal oxide semiconductor device further comprises a third field plate disposed on a side of the second dielectric layer away from the substrate, and an orthographic projection of the third field plate on the substrate covers the drain region and a portion of the drift region;

[0038] The second high-K dielectric layer is also connected to an end of the third field plate close to the source region.

[0039] In one embodiment, a surface of the second high-K dielectric layer close to the substrate, a surface of the second field plate close to the substrate, and a surface of the third field plate close to the substrate are flush;

[0040] And / or, a surface of the second high-K dielectric layer away from the substrate, a surface of the second field plate away from the substrate, and a surface of the third field plate away from the substrate are flush.

[0041] The laterally diffused metal oxide semiconductor device provided in the embodiment of the present application can adjust the electric flux distribution on the surface of the drift region by setting a second high-K dielectric layer connected to the second field plate on the side of the second dielectric layer away from the substrate, thereby weakening the high peak electric field on the surface of the drift region below the second field plate close to the drain region. On the one hand, the device's withstand voltage can be improved, and on the other hand, a smaller on-resistance can be achieved under the same breakdown voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] In order to more clearly illustrate the technical solutions in the embodiments or exemplary embodiments of the present application, the drawings required for use in the description of the embodiments or exemplary embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0043] Figure 1 A schematic diagram of the cross-sectional structure of a laterally diffused metal oxide semiconductor device provided in an embodiment of the present application.

[0044] Figure 2 for Figure 1 Schematic top view of the device shown.

[0045] Figure 3 3 is a comparison diagram of the electric field intensity distribution on the drift region surface of a conventional device and a device in an embodiment of the present application.

[0046] Figure 4 It is a comparison diagram of the breakdown characteristic curves of the traditional device and the device in the embodiment of the present application.

[0047] Figure 5 4 is a comparison diagram of output characteristic curves of a traditional device and a device in an embodiment of the present application.

[0048] Figure 6 A schematic diagram of the cross-sectional structure of another laterally diffused metal oxide semiconductor device provided in an embodiment of the present application.

[0049] Description of reference numerals:

[0050] 1. Laterally diffused metal oxide semiconductor device; 11. base; 111. substrate; 112. buried layer; 113. top silicon layer; 1131. body region; 1132. drift region; 1133. drain region; 1134. source region; 1135. first doped region; 1136. body lead-out region; 121. first dielectric layer; 122. second dielectric layer; 13. first field plate; 131. inclined portion; 132. flat portion; 141. first high-K dielectric layer; 142. second high-K dielectric layer; 15. gate; 161. first conductive structure; 162. second conductive structure; 171. second field plate; 172. third field plate. DETAILED DESCRIPTION

[0051] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. Embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0052] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0053] It should be understood that when an element or layer is referred to as being "on, adjacent to, connected to or coupled to other elements or layers, it may be directly on, adjacent to, connected to or coupled to other elements or layers, or there may be intervening elements or layers. On the contrary, when an element is referred to as being "directly on, directly adjacent to, directly connected to or directly coupled to other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types and / or parts, these elements, components, regions, layers, doping types and / or parts should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, doping type or part from another element, component, region, layer, doping type or part. Therefore, without departing from the teachings of the present application, the first element, component, region, layer, doping type or portion discussed below may be represented as a second element, component, region, layer or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

[0054] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as "under other elements" or "under it" or "under it" will be oriented as being "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0055] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" and the like specify the presence of stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. At the same time, in this specification, the term "and / or" includes any and all combinations of the relevant listed items.

[0056] Embodiments of the application are described herein with reference to cross-sectional views that are schematic diagrams of ideal embodiments (and intermediate structures) of the application, so that variations in the shapes shown due to, for example, manufacturing techniques and / or tolerances can be expected. Therefore, embodiments of the application should not be limited to the specific shapes of the zones shown herein, but rather include shape deviations due to, for example, manufacturing techniques. For example, an implanted region shown as a rectangle typically has rounded or curved features and / or an implant concentration gradient at its edges, rather than a binary change from an implanted region to a non-implanted region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is performed. Therefore, the regions shown in the figures are schematic in nature, their shapes do not represent the actual shape of the region of the device, and do not limit the scope of the application.

[0057] First, refer to Figure 1 and Figure 2 As shown, an embodiment of the present application provides a laterally diffused metal oxide semiconductor device 1, wherein the laterally diffused metal oxide semiconductor device 1 takes an N-type laterally diffused metal oxide semiconductor device 1 as an example, wherein the first doping type is P-type and the second doping type is N-type. In other embodiments, the laterally diffused metal oxide semiconductor device 1 may also be a P-type laterally diffused metal oxide semiconductor device 1, wherein the first doping type is N-type and the second doping type is P-type.

[0058] Specifically, the LDMOS device 1 includes a substrate 11 , a body region 1131 , a drift region 1132 , a source region 1134 , a drain region 1133 , a first dielectric layer 121 , a first field plate 13 and a first high-K dielectric layer 141 .

[0059] The body region 1131 and the drift region 1132 are arranged in the substrate 11 along the first direction X. In one example, the body region 1131 and the drift region 1132 are arranged adjacent to each other along the first direction X. In another example, the body region 1131 and the drift region 1132 are arranged at intervals along the first direction X. The drain region 1133 is arranged in the drift region 1132, and the source region 1134 is arranged in the body region 1131. The first dielectric layer 121 is arranged on the substrate 11 and at least covers a portion of the body region 1131 and a portion of the drift region 1132. The first field plate 13 is arranged on a side of the first dielectric layer 121 away from the substrate 11, and the orthographic projection of the first field plate 13 on the substrate 11 is located between the body region 1131 and the drain region 1133, and a portion of the orthographic projection covers a portion of the drift region 1132. The first high-K dielectric layer 141 is disposed on a side of the first dielectric layer 121 away from the substrate 11 and connected to an end of the first field plate 13 close to the drain region 1133. The orthographic projection of the first high-K dielectric layer 141 on the substrate 11 covers a portion of the drift region 1132. The first direction X is perpendicular to the thickness direction of the substrate 11.

[0060] Here, it should be noted that the “orthographic projection” in the embodiment of the present application refers to the projection along the thickness direction of the substrate 11. The body region 1131 in the embodiment of the present application is of the first doping type, and the drift region 1132, the drain region 1133 and the source region 1134 are of the second doping type.

[0061] The laterally diffused metal oxide semiconductor device 1 provided in the embodiment of the present application can adjust the electric flux distribution on the surface of the drift region 1132 by setting a first high-K dielectric layer 141 connected to the first field plate 13 on the side of the first dielectric layer 121 away from the substrate 11, thereby weakening the high peak electric field on the surface of the drift region 1132 below the end of the first field plate 13 close to the drain region 1133. On the one hand, the device's withstand voltage can be improved, and on the other hand, a smaller on-resistance can be achieved under the same breakdown voltage.

[0062] In one embodiment, the base 11 includes a stacked substrate 111 , a buried layer 112 , and a top silicon layer 113 . The body region 1131 , the drift region 1132 , the source region 1134 , and the drain region 1133 are all disposed in the top silicon layer 113 .

[0063] In one example, the materials of the substrate 111 and the top silicon layer 113 may be single crystal silicon, polycrystalline silicon, amorphous silicon, germanium silicon compound or low temperature polysilicon (LTPS), or other materials known to those skilled in the art.

[0064] In one example, the material of the buried layer 112 may be silicon dioxide, silicon nitride or silicon oxyfluoride. In another example, the material of the buried layer 112 may also be other dielectric materials with a dielectric constant smaller than that of silicon dioxide.

[0065] In one embodiment, the lateral diffused metal oxide semiconductor device 1 further includes a first doped region 1135 and a gate 15. The first doped region 1135 is disposed in the substrate 11, and further, the first doped region 1135 is disposed in the top silicon layer 113. Part of the first doped region 1135 is located between the body region 1131 and the drift region 1132, and the first doped region 1135 is of the second doping type. The gate 15 is disposed on the side of the first dielectric layer 121 away from the substrate 11, and the orthographic projection of the gate 15 on the substrate 11 covers part of the body region 1131 and part of the first doped region 1135. One end of the first field plate 13 is connected to one end of the gate 15 close to the drain region 1133, and the other end of the first field plate 13 extends in a direction close to the drain region 1133. In this way, the first field plate 13 can better expand the width of the depletion region, increase the curvature radius of the depletion region, alleviate the boundary electric field strength, and improve the device's ability to resist breakdown.

[0066] Furthermore, the gate 15 and the first field plate 13 are an integrated structure. In this way, the gate 15 and the first field plate 13 can be manufactured simultaneously in the same process, thereby reducing the difficulty of manufacturing the device.

[0067] In one embodiment, the conductive structure constitutes the gate 15 and the first field plate 13 , wherein the conductive structure located above the body region 1131 is the gate 15 , and the conductive structure located above the first doped region 1135 and the drift region 1132 is the first field plate 13 .

[0068] In one embodiment, the gate 15 includes a gate conductive layer, the material of the gate conductive layer is polysilicon, the material of the first field plate 13 is also polysilicon, and the first field plate 13 and the gate conductive layer are an integrated structure.

[0069] Furthermore, the gate 15 may further include a gate oxide layer. The gate oxide layer is made of silicon dioxide. The gate oxide layer is disposed on a side of the gate conductive layer close to the substrate 11 .

[0070] In one embodiment, the first field plate 13 includes an inclined portion 131 and a flat portion 132, wherein the inclined portion 131 connects the flat portion 132 and the gate 15. The distance between the flat portion 132 and the substrate 11 is greater than the distance between the gate 15 and the substrate 11.

[0071] In one example, the surface of the first high-K dielectric layer 141 close to the substrate 11 is flush with the surface of the flat portion 132 close to the substrate 11 , that is, the surface of the first high-K dielectric layer 141 close to the substrate 11 and the surface of the flat portion 132 close to the substrate 11 are located on the same plane.

[0072] Furthermore, the surface of the first high-K dielectric layer 141 away from the substrate 11 is flush with the surface of the flat portion 132 away from the substrate 11 , that is, the surface of the first high-K dielectric layer 141 away from the substrate 11 and the surface of the flat portion 132 away from the substrate 11 are located on the same plane.

[0073] The above setting can better adjust the electric flux distribution on the surface of the drift region 1132, and further weaken the high peak electric field on the surface of the drift region 1132 below one end of the first field plate 13 close to the drain region 1133. On the one hand, it can improve the device's withstand voltage, and on the other hand, it can achieve a smaller on-resistance at the same breakdown voltage.

[0074] In one embodiment, the lateral diffused metal oxide semiconductor device 1 further includes a first conductive structure 161 electrically connected to the drain region 1133, and the orthographic projection of the first conductive structure 161 on the substrate 11 covers at least a portion of the drain region 1133. Exemplarily, the first conductive structure 161 is a drain. One end of the first high-K dielectric layer 141 close to the drain region 1133 is connected to the first conductive structure 161.

[0075] In this way, the positive projection range of the first high-K dielectric layer 141 on the substrate 11 can be increased, thereby maximizing the coverage of the drift region 1132, so that the first high-K dielectric layer 141 can better regulate the electric flux distribution on the surface of the drift region 1132, and further weaken the high peak electric field on the surface of the drift region 1132 below the end of the first field plate 13 close to the drain region 1133. On the one hand, the device's withstand voltage can be improved, and on the other hand, a smaller on-resistance can be achieved under the same breakdown voltage.

[0076] In one embodiment, the lateral diffused metal oxide semiconductor device 1 further includes a second dielectric layer 122, a second field plate 171 and a second high-K dielectric layer 142, wherein the second dielectric layer 122 is disposed on a side of the first field plate 13 away from the substrate 11, and on a side of the first high-K dielectric layer 141 away from the substrate 11. The second field plate 171 is disposed on a side of the second dielectric layer 122 away from the substrate 11. The orthographic projection of the second field plate 171 on the substrate 11 covers the body region 1131, the substrate 11 between the body region 1131 and the drift region 1132, and a portion of the drift region 1132. The second high-K dielectric layer 142 is disposed on a side of the second dielectric layer 122 away from the substrate 11, and is connected to an end of the second field plate 171 close to the drain region 1133, and the orthographic projection of the second high-K dielectric layer 142 on the substrate 11 covers a portion of the drift region 1132.

[0077] In this way, on the one hand, by setting a double-layer field plate, the width of the depletion region can be better expanded, the curvature radius of the depletion region can be increased, the boundary electric field strength can be alleviated, and the device's ability to resist breakdown can be improved; on the other hand, by setting a double-layer high-K dielectric layer, the high peak electric field on the surface of the drift region 1132 below the end of the first field plate 13 and the second field plate 171 close to the drain region 1133 can be further weakened, which can not only improve the device's withstand voltage, but also achieve a smaller on-resistance at the same breakdown voltage.

[0078] In one embodiment, the LDMOS device 1 further includes a third field plate 172 disposed on a side of the second dielectric layer 122 away from the substrate 11, and an orthographic projection of the third field plate 172 on the substrate 11 covers the drain region 1133 and a portion of the drift region 1132. The second high-K dielectric layer 142 is also connected to an end of the third field plate 172 close to the source region 1134.

[0079] In this way, on the one hand, the width of the depletion region can be better expanded, the curvature radius of the depletion region can be increased, the boundary electric field strength can be alleviated, and the device's ability to resist breakdown can be improved; on the other hand, the positive projection range of the second high-K dielectric layer 142 on the substrate 11 can be larger, thereby maximizing the coverage of the drift region 1132, thereby better regulating the electric flux distribution on the surface of the drift region 1132, and further weakening the high peak electric field on the surface of the drift region 1132 below the end of the second field plate 171 and the third field plate 172 close to the drain region 1133. On the one hand, the device's withstand voltage can be improved, and on the other hand, a smaller on-resistance can be achieved under the same breakdown voltage.

[0080] In one example, the third field plate 172 is disposed on a side of the first conductive structure 161 away from the substrate 11, and is connected to the first conductive structure 161. Exemplarily, the material of the third field plate 172 may be metal.

[0081] In one embodiment, the LDMOS device 1 further includes a second conductive structure 162 and a body lead-out region 1136, wherein the body lead-out region 1136 is disposed in the body region 1131 and is of the second doping type. Exemplarily, the second conductive structure 162 may be a source.

[0082] In one example, the second conductive structure 162 is electrically connected to the source region 1134. In another example, the second conductive structure 162 is also electrically connected to the body tie-out region 1136.

[0083] Further, the second field plate 171 is disposed on a side of the second conductive structure 162 away from the substrate 11, and is connected to the second conductive structure 162. Exemplarily, the material of the second field plate 171 may be metal.

[0084] In one embodiment, the surface of the second high-K dielectric layer 142 close to the substrate 11, the surface of the second field plate 171 close to the substrate 11, and the surface of the third field plate 172 close to the substrate 11 are flush, that is, the surface of the second high-K dielectric layer 142 close to the substrate 11, the surface of the second field plate 171 close to the substrate 11, and the surface of the third field plate 172 close to the substrate 11 are located on the same plane.

[0085] Furthermore, the surface of the second high-K dielectric layer 142 away from the substrate 11, the surface of the second field plate 171 away from the substrate 11, and the surface of the third field plate 172 away from the substrate 11 are flush, that is, the surface of the second high-K dielectric layer 142 away from the substrate 11, the surface of the second field plate 171 away from the substrate 11, and the surface of the third field plate 172 away from the substrate 11 are located on the same plane.

[0086] The above setting can better adjust the electric flux distribution on the surface of the drift region 1132, and further weaken the high peak electric field on the surface of the drift region 1132 below the end of the second field plate 171 close to the drain region 1133. On the one hand, it can improve the device's withstand voltage, and on the other hand, it can achieve a smaller on-resistance at the same breakdown voltage.

[0087] In one embodiment, the dielectric constant of the first high-K dielectric layer 141 is between 21 and 200. For example, the dielectric constant of the first high-K dielectric layer 141 may be 21, 30, 50, 70, 90, 110, 130, 150, 180, 190 or 200.

[0088] In one embodiment, the critical breakdown field strength of the first high-K dielectric layer 141 is greater than 30 V / μm.

[0089] In one embodiment, the material of the first high-K dielectric layer 141 may include any one of HfO 2 , TiO 2 , HfZrO, HfSiNO, Ta 2 O 5 , ZrO 2 , ZrSiO 2 , Al 2 O 3 , SrTiO 3 and BaSrTiO.

[0090] In one embodiment, the dielectric constant of the second high-K dielectric layer 142 is between 21 and 200. For example, the dielectric constant of the second high-K dielectric layer 142 may be 21, 30, 50, 70, 90, 110, 130, 150, 180, 190, or 200.

[0091] In one embodiment, the critical breakdown field strength of the second high-K dielectric layer 142 is greater than 30 V / μm.

[0092] In one embodiment, the material of the second high-K dielectric layer 142 may include any one of HfO 2 , TiO 2 , HfZrO, HfSiNO, Ta 2 O 5 , ZrO 2 , ZrSiO 2 , Al 2 O 3 , SrTiO 3 and BaSrTiO.

[0093] It should be noted that, refer to Figure 3 As shown, the applicant compares the electric field intensity distribution on the surface of the drift region 1132 of the conventional device and the device in the embodiment of the present application. It can be seen from the figure that the electric field peak value on the surface of the drift region 1132 of the device in the embodiment of the present application is lower than the electric field peak value on the surface of the drift region 1132 of the conventional device. Figure 4 and Figure 5 As shown, when the breakdown voltage of the traditional device and the device in the embodiment of the present application is the same, the linear region current of the device in the embodiment of the present application is larger and a smaller on-resistance can be achieved.

[0094] In one embodiment, the present application also provides a method for preparing a laterally diffused metal oxide semiconductor device 1, which can be used to prepare the above-mentioned laterally diffused metal oxide semiconductor device 1, and specifically comprises the following steps:

[0095] S10: providing a substrate 11. Illustratively, after providing the substrate 11, the substrate 11 may be pre-cleaned.

[0096] S20: forming a first doping region 1135 in the substrate 11. For example, the first doping region 1135 may be formed by an ion implantation process.

[0097] S30: forming a first dielectric layer 121 on the substrate 11. Exemplarily, the material of the first dielectric layer 121 may be silicon dioxide.

[0098] S40 : forming a gate 15 and a first field plate 13 on the first dielectric layer 121 .

[0099] S50: forming a body region 1131 in the substrate 11. For example, the body region 1131 may be formed by an ion implantation process.

[0100] S60: forming a drain region 1133, a source region 1134 and a body lead-out region 1136 in the substrate 11. Exemplarily, the drain region 1133, the source region 1134 and the body lead-out region 1136 may be formed by an ion implantation process.

[0101] S70 : forming a first high-K dielectric layer 141 on the first dielectric layer 121 .

[0102] S80 : forming a second dielectric layer 122 on the substrate 11 , wherein the second dielectric layer 122 covers the first high-K dielectric layer 141 , the first field plate 13 and the gate 15 .

[0103] S90: etching the second dielectric layer 122 to form an etched groove, and filling the etched groove to form a first conductive structure 161 and a second conductive structure 162. The first conductive structure 161 is electrically connected to the drain region 1133, and the second conductive structure 162 is electrically connected to the source region 1134.

[0104] S100 : forming a second high-K dielectric layer 142 on the second dielectric layer 122 .

[0105] S110 : forming a second field plate 171 and a third field plate 172 on the second dielectric layer 122 .

[0106] Second, refer to Figure 6As shown, an embodiment of the present application provides a laterally diffused metal oxide semiconductor device 1, wherein the laterally diffused metal oxide semiconductor device 1 takes an N-type laterally diffused metal oxide semiconductor device 1 as an example, wherein the first doping type is P-type and the second doping type is N-type. In other embodiments, the laterally diffused metal oxide semiconductor device 1 may also be a P-type laterally diffused metal oxide semiconductor device 1, wherein the first doping type is N-type and the second doping type is P-type.

[0107] Specifically, the LDMOS device 1 includes a substrate 11 , a body region 1131 , a drift region 1132 , a source region 1134 , a drain region 1133 , a gate 15 , a second dielectric layer 122 , a second field plate 171 and a second high-K dielectric layer 142 .

[0108] The body region 1131 and the drift region 1132 are arranged in the substrate 11 along the first direction X. The drain region 1133 is arranged in the drift region 1132, and the source region 1134 is arranged in the body region 1131. The gate 15 is arranged on the substrate 11, and the orthographic projection of the gate 15 on the substrate 11 covers part of the body region 1131. The second dielectric layer 122 is arranged on the side of the gate 15 away from the substrate 11. The second field plate 171 is arranged on the side of the second dielectric layer 122 away from the substrate 11. The orthographic projection of the second field plate 171 on the substrate 11 covers the body region 1131 and part of the drift region 1132. The second high-K dielectric layer 142 is arranged on the side of the second dielectric layer 122 away from the substrate 11, and is connected to one end of the second field plate 171 close to the drain region 1133, and the orthographic projection of the second high-K dielectric layer 142 on the substrate 11 covers part of the drift region 1132. The first direction X is perpendicular to the thickness direction of the substrate 11.

[0109] Here, it should be noted that the “orthographic projection” in the embodiment of the present application refers to the projection along the thickness direction of the substrate 11. The body region 1131 in the embodiment of the present application is of the first doping type, and the drift region 1132, the drain region 1133 and the source region 1134 are of the second doping type.

[0110] The laterally diffused metal oxide semiconductor device 1 provided in the embodiment of the present application can adjust the electric flux distribution on the surface of the drift region 1132 by setting a second high-K dielectric layer 142 connected to the second field plate 171 on the side of the second dielectric layer 122 away from the substrate 11, thereby weakening the high peak electric field on the surface of the drift region 1132 below the end of the second field plate 171 close to the drain region 1133. On the one hand, the device's withstand voltage can be improved, and on the other hand, a smaller on-resistance can be achieved under the same breakdown voltage.

[0111] In one embodiment, the LDMOS device 1 further includes a first doped region 1135 of the second doping type, the first doped region 1135 is disposed in the substrate 11 , and a portion of the first doped region 1135 is located between the body region 1131 and the drift region 1132 .

[0112] In one embodiment, the base 11 includes a stacked substrate 111 , a buried layer 112 , and a top silicon layer 113 . The body region 1131 , the first doped region 1135 , the drift region 1132 , the source region 1134 , and the drain region 1133 are all disposed in the top silicon layer 113 .

[0113] In one example, the materials of the substrate 111 and the top silicon layer 113 may be single crystal silicon, polycrystalline silicon, amorphous silicon, germanium silicon compound or low temperature polysilicon (LTPS), or other materials known to those skilled in the art.

[0114] In one example, the material of the buried layer 112 may be silicon dioxide, silicon nitride or silicon oxyfluoride. In another example, the material of the buried layer 112 may also be other dielectric materials with a dielectric constant smaller than that of silicon dioxide.

[0115] In one embodiment, the LDMOS device 1 further includes a third field plate 172 disposed on a side of the second dielectric layer 122 away from the substrate 11, and an orthographic projection of the third field plate 172 on the substrate 11 covers the drain region 1133 and a portion of the drift region 1132. The second high-K dielectric layer 142 is also connected to an end of the third field plate 172 close to the source region 1134.

[0116] In this way, on the one hand, the width of the depletion region can be better expanded, the curvature radius of the depletion region can be increased, the boundary electric field strength can be alleviated, and the device's ability to resist breakdown can be improved; on the other hand, the positive projection range of the second high-K dielectric layer 142 on the substrate 11 can be larger, thereby maximizing the coverage of the drift region 1132, thereby better regulating the electric flux distribution on the surface of the drift region 1132, and further weakening the high peak electric field on the surface of the drift region 1132 below the end of the second field plate 171 close to the drain region 1133. On the one hand, the device's withstand voltage can be improved, and on the other hand, a smaller on-resistance can be achieved under the same breakdown voltage.

[0117] In one example, the material of the second field plate 171 and the third field plate 172 includes metal.

[0118] In one embodiment, the surface of the second high-K dielectric layer 142 close to the substrate 11, the surface of the second field plate 171 close to the substrate 11, and the surface of the third field plate 172 close to the substrate 11 are flush, that is, the surface of the second high-K dielectric layer 142 close to the substrate 11, the surface of the second field plate 171 close to the substrate 11, and the surface of the third field plate 172 close to the substrate 11 are located on the same plane.

[0119] Furthermore, the surface of the second high-K dielectric layer 142 away from the substrate 11, the surface of the second field plate 171 away from the substrate 11, and the surface of the third field plate 172 away from the substrate 11 are flush, that is, the surface of the second high-K dielectric layer 142 away from the substrate 11, the surface of the second field plate 171 away from the substrate 11, and the surface of the third field plate 172 away from the substrate 11 are located on the same plane.

[0120] The above setting can better adjust the electric flux distribution on the surface of the drift region 1132, and further weaken the high peak electric field on the surface of the drift region 1132 below the end of the second field plate 171 close to the drain region 1133. On the one hand, it can improve the device's withstand voltage, and on the other hand, it can achieve a smaller on-resistance at the same breakdown voltage.

[0121] In one embodiment, the dielectric constant of the second high-K dielectric layer 142 is between 21 and 200. For example, the dielectric constant of the second high-K dielectric layer 142 may be 21, 30, 50, 70, 90, 110, 130, 150, 180, 190, or 200.

[0122] In one embodiment, the critical breakdown field strength of the second high-K dielectric layer 142 is greater than 30 V / μm.

[0123] In one embodiment, the material of the second high-K dielectric layer 142 may include any one of HfO 2 , TiO 2 , HfZrO, HfSiNO, Ta 2 O 5 , ZrO 2 , ZrSiO 2 , Al 2 O 3 , SrTiO 3 and BaSrTiO.

[0124] In one embodiment, the lateral diffused metal oxide semiconductor device 1 further includes a first dielectric layer 121, a first conductive structure 161, a second conductive structure 162 and a body lead-out region 1136, wherein the first dielectric layer 121 is disposed between the gate 15 and the substrate 11, the first conductive structure 161 is electrically connected to the drain region 1133, and the second conductive structure 162 is electrically connected to the source region 1134. In one example, the second conductive structure 162 is also electrically connected to the body lead-out region 1136.

[0125] Furthermore, the second field plate 171 is disposed on a side of the second conductive structure 162 away from the substrate 11 and connected to the second conductive structure 162 , and the third field plate 172 is disposed on a side of the first conductive structure 161 away from the substrate 11 and connected to the first conductive structure 161 .

[0126] In one embodiment, the present application also provides a method for preparing a laterally diffused metal oxide semiconductor device 1, which can be used to prepare the above-mentioned laterally diffused metal oxide semiconductor device 1, and specifically comprises the following steps:

[0127] S10: providing a substrate 11. Illustratively, after providing the substrate 11, the substrate 11 may be pre-cleaned.

[0128] S20: forming a first doping region 1135 in the substrate 11. For example, the first doping region 1135 may be formed by an ion implantation process.

[0129] S30: forming a first dielectric layer 121 on the substrate 11. Exemplarily, the material of the first dielectric layer 121 may be silicon dioxide.

[0130] S40 : forming a gate 15 on the first dielectric layer 121 .

[0131] S50: forming a body region 1131 in the substrate 11. For example, the body region 1131 may be formed by an ion implantation process.

[0132] S60: forming a drain region 1133, a source region 1134 and a body lead-out region 1136 in the substrate 11. Exemplarily, the drain region 1133, the source region 1134 and the body lead-out region 1136 may be formed by an ion implantation process.

[0133] S70 : forming a second dielectric layer 122 on the substrate 11 , wherein the second dielectric layer 122 covers the first dielectric layer 121 and the gate 15 .

[0134] S80: Etching the second dielectric layer 122 to form etching grooves, and filling the etching grooves to form the first conductive structure 161 and the second conductive structure 162. The first conductive structure 161 is electrically connected to the drain region 1133, and the second conductive structure 162 is electrically connected to the source region 1134 and the body lead region 1136.

[0135] S90 : forming a second high-K dielectric layer 142 on the second dielectric layer 122 .

[0136] S100 : forming a second field plate 171 and a third field plate 172 on the second dielectric layer 122 .

[0137] In the description of this specification, the description with reference to the terms "some embodiments", "other embodiments", "ideal embodiments", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.

[0138] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features of the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0139] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be construed as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent application shall be subject to the attached claims.

Claims

1. A laterally diffused metal oxide semiconductor device, characterized in that: include: substrate; A body region and a drift region are arranged in the substrate along a first direction; a drain region is provided in the drift region, and a source region is provided in the body region; The first direction is perpendicular to the thickness direction of the substrate; A first dielectric layer is disposed on the substrate and covers at least a portion of the body region and a portion of the drift region; A first field plate is disposed on a side of the first dielectric layer away from the substrate, wherein an orthographic projection of the first field plate on the substrate is located between the body region and the drain region and covers a portion of the drift region; The first high-K dielectric layer is disposed on a side of the first dielectric layer away from the substrate and connected to an end of the first field plate close to the drain region. The orthographic projection of the first high-K dielectric layer on the substrate covers a portion of the drift region.

2. The laterally diffused metal oxide semiconductor device according to claim 1, characterized in that: The laterally diffused metal oxide semiconductor device further comprises: A first doped region, disposed in the substrate; a portion of the first doped region is located between the body region and the drift region; A gate is arranged on a side of the first dielectric layer away from the substrate, and the orthographic projection of the gate on the substrate covers part of the body region and part of the first doped region; one end of the first field plate is connected to one end of the gate close to the drain region, and the other end of the first field plate extends toward the direction close to the drain region.

3. The laterally diffused metal oxide semiconductor device according to claim 2, characterized in that: The gate and the first field plate are an integrated structure.

4. The laterally diffused metal oxide semiconductor device according to claim 2, characterized in that: The first field plate includes an inclined portion and a flat portion, wherein the inclined portion connects the flat portion and the gate; the distance between the flat portion and the substrate is greater than the distance between the gate and the substrate; A surface of the first high-K dielectric layer close to the substrate is flush with a surface of the flat portion close to the substrate, and / or a surface of the first high-K dielectric layer away from the substrate is flush with a surface of the flat portion away from the substrate.

5. The laterally diffused metal oxide semiconductor device according to claim 1, characterized in that: The laterally diffused metal oxide semiconductor device further comprises a first conductive structure electrically connected to the drain region, wherein an orthographic projection of the first conductive structure on the substrate covers at least a portion of the drain region; One end of the first high-K dielectric layer close to the drain region is connected to the first conductive structure.

6. The laterally diffused metal oxide semiconductor device according to any one of claims 1 to 5, characterized in that: The laterally diffused metal oxide semiconductor device further comprises: a second dielectric layer, disposed on a side of the first field plate away from the substrate, and a side of the first high-K dielectric layer away from the substrate; A second field plate is arranged on a side of the second dielectric layer away from the substrate; the orthographic projection of the second field plate on the substrate covers the body region, the substrate between the body region and the drift region, and a portion of the drift region; The second high-K dielectric layer is disposed on a side of the second dielectric layer away from the substrate and connected to an end of the second field plate close to the drain region. The orthographic projection of the second high-K dielectric layer on the substrate covers a portion of the drift region.

7. The laterally diffused metal oxide semiconductor device according to claim 6, characterized in that: The laterally diffused metal oxide semiconductor device further comprises a third field plate disposed on a side of the second dielectric layer away from the substrate, wherein an orthographic projection of the third field plate on the substrate covers the drain region and a portion of the drift region; The second high-K dielectric layer is also connected to an end of the third field plate close to the source region.

8. The laterally diffused metal oxide semiconductor device according to claim 7, characterized in that: The surface of the second high-K dielectric layer close to the substrate, the surface of the second field plate close to the substrate, and the surface of the third field plate close to the substrate are flush; And / or, a surface of the second high-K dielectric layer away from the substrate, a surface of the second field plate away from the substrate, and a surface of the third field plate away from the substrate are flush.

9. The laterally diffused metal oxide semiconductor device according to claim 6, characterized in that: The dielectric constant of the first high-K dielectric layer is between 21 and 200; And / or, the dielectric constant of the second high-K dielectric layer is between 21-200.

10. A laterally diffused metal oxide semiconductor device, characterized in that: include: substrate; A body region and a drift region are arranged in the substrate along a first direction; a drain region is provided in the drift region, and a source region is provided in the body region; The first direction is perpendicular to the thickness direction of the substrate; A gate, disposed on the substrate, wherein an orthographic projection of the gate on the substrate covers a portion of the body region; A second dielectric layer is provided on a side of the gate away from the substrate; A second field plate is disposed on a side of the second dielectric layer away from the substrate; The orthographic projection of the second field plate on the substrate covers the body region and a portion of the drift region; The second high-K dielectric layer is disposed on a side of the second dielectric layer away from the substrate and connected to an end of the second field plate close to the drain region. The orthographic projection of the second high-K dielectric layer on the substrate covers a portion of the drift region.

11. The laterally diffused metal oxide semiconductor device according to claim 10, characterized in that: The laterally diffused metal oxide semiconductor device further comprises a third field plate disposed on a side of the second dielectric layer away from the substrate, wherein an orthographic projection of the third field plate on the substrate covers the drain region and a portion of the drift region; The second high-K dielectric layer is also connected to an end of the third field plate close to the source region.

12. The laterally diffused metal oxide semiconductor device according to claim 11, characterized in that: The surface of the second high-K dielectric layer close to the substrate, the surface of the second field plate close to the substrate, and the surface of the third field plate close to the substrate are flush; And / or, a surface of the second high-K dielectric layer away from the substrate, a surface of the second field plate away from the substrate, and a surface of the third field plate away from the substrate are flush.

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