Semiconductor device and preparation method thereof

Abstract

The invention relates to a semiconductor device and a preparation method thereof, the semiconductor device comprises a well region, a drift region, a drain region and a source region in a substrate, the drift region is located in the well region, the drain region is located in the drift region, and the outer side wall of the drain region comprises two first side walls distributed along a second direction and two second side walls distributed along a first direction; the source region is located in the well region on one side of the first side wall; the shallow trench isolation structure is partially located in the drift region, surrounds the first side wall and the second side wall of the drain region, and further extends to the inner side wall of the well region along the second direction; the size between the first side wall, close to the source region, of the drain region and the outer side wall, close to the source region, of the shallow trench isolation structure in the first direction is a target width, and the size between the second side wall of the drain region and the inner side wall of the drift region in the second direction is a target length; the ratio of the target width to the target length is within a target range, and the target range is associated with a target withstand voltage value of the semiconductor device. The withstand voltage of the semiconductor device is improved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor device and a method for preparing the same. Background Art

[0002] DEMOS devices (Drain Extension MOS) are high-voltage devices. The more common DEMOS devices are lateral double-diffused MOSFETs (LDMOS). DEMOS devices have many advantages, such as better thermal stability and frequency stability, higher gain and durability, lower feedback capacitance and thermal resistance, as well as constant input impedance and simpler bias circuits.

[0003] In order to increase the breakdown voltage (Breakdown Voltage, BV) or the source-drain breakdown voltage (Breakdown VoltageDrain-to-Source, BVdss), a shallow trench isolation structure is usually provided in a DEMOS device. However, the breakdown voltage or source-drain breakdown voltage of the existing DEMOS device with a shallow trench isolation structure still needs to be improved. Summary of the invention

[0004] Based on this, the present application provides a semiconductor structure and a method for manufacturing the same, so as to improve the withstand voltage or source-drain breakdown voltage of a semiconductor device, especially a DEMOS device.

[0005] In a first aspect, an embodiment of the present application provides a semiconductor device, including:

[0006] A substrate, a shallow trench isolation structure and a gate structure; the substrate includes a well region, a drift region, a drain region and a source region, the drift region is located in the well region, the drain region is located in the drift region, and the outer sidewall of the drain region includes two first sidewalls distributed along the second direction and two second sidewalls distributed along the first direction, the first direction and the second direction are both parallel to the top surface of the substrate, and the first direction intersects with the second direction;

[0007] The source region is located in a well region on one side of the first side wall;

[0008] The shallow trench isolation structure is partially located in the drift region and surrounds the first side wall and the second side wall of the drain region, wherein the shallow trench isolation structure located outside the second side wall also extends along the second direction to the inner side wall of the well region;

[0009] The gate structure crosses and covers a portion of the well region, the drift region and the shallow trench isolation structure along the first direction;

[0010] Among them, the dimension along the first direction between the first side wall of the drain region close to the source region and the outer side wall of the shallow trench isolation structure close to the source region is a target width, and the dimension along the second direction between the second side wall of the drain region and the inner side wall of the drift region is a target length; the ratio of the target width to the target length is within a target range, and the target range is associated with a target withstand voltage value of the semiconductor device.

[0011] In some embodiments of the present application, the target range is 0.9-1.3.

[0012] In some embodiments of the present application, the target range is associated with the target withstand voltage value of the semiconductor device and includes: when the ratio of the target width to the target length is within the target range, the position of the superimposed breakdown voltage moves from the first position of the drift region to the second position of the drift region, and the target withstand voltage value at the second position is greater than the target withstand voltage value at the first position; the superimposed breakdown voltage is the superposition of the lateral breakdown voltage along the first direction between the source region and the drain region and the longitudinal breakdown voltage along the second direction between the drain region and the substrate.

[0013] In some embodiments of the present application, the target withstand voltage range of the semiconductor device is 30V-60V, the target width range is 1.4 microns-1.9 microns, and the target length range is 1.4 microns-1.9 microns.

[0014] In some embodiments of the present application, an outer sidewall of the shallow trench isolation structure outside the first sidewall does not contact an inner sidewall of the drift region in the first direction.

[0015] In some embodiments of the present application, the depth of the shallow trench isolation structure is greater than the depth of the drain region and less than the depth of the drift region.

[0016] In some embodiments of the present application, the inner sidewall of the drift region includes four inner corners, and the cross-section of the inner corners in a direction parallel to the top surface of the substrate is in an arc shape.

[0017] In some embodiments of the present application, the doping type of the drift region is opposite to the doping type of the well region, the doping type of the drain region is the same as the doping type of the drift region, and the doping type of the source region is opposite to the doping type of the well region.

[0018] In some embodiments of the present application, the doping type of the well region is P type, and the doping types of the drift region, the drain region and the source region are N type; or, the doping type of the well region is N type, and the doping types of the drift region, the drain region and the source region are P type.

[0019] In a second aspect, an embodiment of the present application further provides a method for preparing a semiconductor device, comprising:

[0020] Providing a substrate, wherein a well region is formed in the substrate;

[0021] forming a drift region in the well region, wherein the doping type of the drift region is opposite to the doping type of the well region;

[0022] forming a drain region in the drift region, wherein the doping type of the drain region is the same as the doping type of the drift region, and the outer sidewall of the drain region comprises two first sidewalls distributed along a second direction and two second sidewalls distributed along the first direction, wherein the first direction and the second direction are both parallel to the top surface of the substrate, and the first direction intersects with the second direction;

[0023] forming a source region in a well region on one side of the first sidewall of the drain region, wherein the doping type of the source region is opposite to the doping type of the well region;

[0024] A shallow trench isolation structure is formed in the drift region, which surrounds a first sidewall and a second sidewall of the drain region, wherein the shallow trench isolation structure outside the second sidewall also extends along the second direction to the inner sidewall of the well region; wherein a dimension along the first direction between a first sidewall of the drain region close to the source region and an outer sidewall of the shallow trench isolation structure close to the source region is a target width, and a dimension along the second direction between a second sidewall of the drain region and an inner sidewall of the drift region is a target length; a ratio of the target width to the target length is within a target range, and the target range is associated with a target withstand voltage value of the semiconductor device;

[0025] A gate structure is formed along the first direction, spanning and covering a portion of the well region, the drift region and the shallow trench isolation structure.

[0026] The embodiments of the present application may or at least have the following advantages:

[0027] In the embodiment of the present application, a semiconductor device and a method for forming the same, the semiconductor device comprises a substrate, the substrate comprises a well region, a drift region, a drain region and a source region, the drift region is located in the well region, the drain region is located in the drift region, the outer sidewall of the drain region comprises two first sidewalls distributed along a second direction and two second sidewalls distributed along a first direction, the first direction and the second direction are both parallel to the top surface of the substrate, and the first direction intersects with the second direction; the source region is located in the well region on one side of the first sidewall; a shallow trench isolation structure, the shallow trench isolation structure is partially located in the drift region and surrounds the first sidewall and the second sidewall of the drain region, wherein the shallow trench isolation structure located on the outer side of the second side wall also extends along the second direction to the inner side wall of the well region; the gate structure spans and covers part of the well region, the drift region and the shallow trench isolation structure along the first direction; wherein the dimension along the first direction between the first side wall of the drain region close to the source region and the outer side wall of the shallow trench isolation structure close to the source region is a target width, and the dimension along the second direction between the second side wall of the drain region and the inner side wall of the drift region is a target length; the ratio of the target width to the target length is within a target range, and the target range is associated with a target withstand voltage value of the semiconductor device. The semiconductor device of the present application not only optimizes the lateral breakdown voltage between the source region and the drain region along the first direction, but also optimizes the longitudinal breakdown voltage between the drain region and the substrate along the second direction by making the shallow trench isolation structure in the drift region satisfy the ratio of the target width to the target length, so that the position of the superimposed breakdown voltage of the lateral breakdown voltage and the longitudinal breakdown voltage is moved from the inner corner of the drift region that is easily broken down to the inner side wall of the drift region that is not easily broken down and is parallel to the second side wall, thereby improving the target withstand voltage value (withstand voltage (BV) or source-drain breakdown voltage (BVdss)) of the semiconductor device.

[0028] The details of one or more embodiments of the present application are set forth in the following drawings and description. Other features, objects, and advantages of the present application will become apparent from the description, drawings, and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0030] Figure 1 A schematic diagram of a semiconductor device structure provided by the prior art;

[0031] Figure 2A schematic diagram of a top view structure of a semiconductor device provided in some embodiments of the present application;

[0032] Figure 3 for Figure 2 A schematic diagram of a structure in which the semiconductor device does not have a gate structure;

[0033] Figure 4 for Figure 2 A schematic diagram of a cross-sectional structure of a semiconductor device obtained along a cutting line AB;

[0034] Figure 5 for Figure 2 A schematic diagram of a cross-sectional structure of a semiconductor device obtained along a cutting line CD direction;

[0035] Figure 6 Schematic diagram of simulation structure of semiconductor devices at different target widths provided by some embodiments of the present application. DETAILED DESCRIPTION

[0036] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. Embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0037] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0038] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers, doping types and / or parts, these elements, components, regions, layers, doping types and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or part from another element, component, region, layer, doping type or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer, doping type or part discussed below can be represented as a second element, component, region, layer or part.

[0039] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as "under other elements" or "under it" or "under it" will be oriented as being "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0040] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" and the like specify the presence of stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. At the same time, in this specification, the term "and / or" includes any and all combinations of the relevant listed items.

[0041] The structure of the embodiments of the present invention should not be limited to the specific shapes shown in the drawings of the specification, but includes shape deviations due to, for example, manufacturing technology.

[0042] It can be understood that in the drawings of the present application, some adjacent film layers with the same processed film material are drawn to be connected to make them close to the actual structure.

[0043] DEMOS devices can increase the distance from the drain region to the source region by increasing or deepening the size of the shallow trench isolation structure (STI), thereby allocating more of the large voltage from the drain region, thereby improving the withstand voltage (BV) or source-drain breakdown voltage (BVdss). Figure 1The structure diagram of the existing DEMOS device with shallow trench isolation structure is shown in FIG. 1 , wherein the DEMOS device comprises: a first substrate 101; a first well region 102 located in the first substrate 101, wherein the doping type of the first well region 102 may be P-type; a first drift region 103 located in the first well region 102, wherein the doping type of the first drift region 103 is N-type; a first shallow trench isolation structure 106 located in the first drift region 103; a first drain region 104 located in the first drift region 103 on one side of the first shallow trench isolation structure 106, wherein the doping type of the first drain region 104 is N-type; and a first source region 105 located in the first well region 102 on the side of the first shallow trench isolation structure 106 away from the first drain region 104. The existing DEMOS device only considers the lateral breakdown voltage between the first drain region 104 and the first source region 105 (lateral breakdown voltage, for example, is Figure 1 In the actual process, it is found that the breakdown point of the DEMOS device is not just a simple one-dimensional electric field from the first drain region 104 to the first source region 105 (such as Figure 1 The lateral breakdown voltage BVDS in the X-axis direction is caused by the existing method that only enhancing the lateral breakdown voltage between the first drain region 104 and the first source region 105 sometimes cannot improve the withstand voltage (BV) or source-drain breakdown voltage (BVdss) of the DEMOS device. At this time, the superposition effect of the multi-dimensional field must be considered. For details, please continue to refer to Figure 1 In practice, the DEMOS device will also have a longitudinal breakdown voltage BVDB (for example, longitudinal breakdown voltage BVDB) between the first drain region 104 and the first substrate 101. Figure 1 In the Y-axis direction), the superposition of the longitudinal breakdown voltage BVDB and the lateral breakdown voltage BVDS will result in a superimposed breakdown voltage VE, and the superimposed breakdown voltage VE will be close to the position of the first inner corner 10 of the first drift region 103, making the first inner corner 10 of the first drift region 103 easy to become a breakdown point or easy to be broken down, thereby limiting the withstand voltage (BV) or source-drain breakdown voltage (BVdss) of the DEMOS device.

[0044] To this end, an embodiment of the present application provides a semiconductor device and a method for preparing the same. The semiconductor device not only optimizes the lateral breakdown voltage between the source region and the drain region along the first direction, but also optimizes the longitudinal breakdown voltage between the drain region and the substrate along the second direction by making the shallow trench isolation structure in the drift region satisfy the ratio of the target width to the target length, so that the position of the superimposed breakdown voltage of the lateral breakdown voltage and the longitudinal breakdown voltage is moved from the inner corner of the drift region that is easily broken down to the inner side wall of the drift region that is not easily broken down and is parallel to the first side wall, thereby improving the target withstand voltage value (withstand voltage (BV) or source-drain breakdown voltage (BVdss)) of the semiconductor device.

[0045] An embodiment of the present application first provides a semiconductor device. Figure 2 A schematic diagram of a top view structure of a semiconductor device provided in some embodiments of the present application; Figure 3 for Figure 2 A schematic diagram of a structure in which the semiconductor device does not have a gate structure; Figure 4 for Figure 2 A schematic diagram of a cross-sectional structure of a semiconductor device obtained along a cutting line AB; Figure 5 for Figure 2 Schematic diagram of the cross-sectional structure of the semiconductor device obtained along the cutting line CD direction.

[0046] refer to Figure 2-Figure 5 , the semiconductor device comprising:

[0047] Substrate 201, shallow trench isolation structure 205 and gate structure 207;

[0048] The substrate 201 includes a well region 202, a drift region 203, a drain region 204 and a source region 206. The drift region 203 is located in the well region 202, the drain region 204 is located in the drift region 203, and the outer sidewall of the drain region 204 includes two first sidewalls 11 distributed along the second direction (refer to Figure 3 ) and two second side walls 12 distributed along the first direction (reference Figure 3 ), the first direction and the second direction are both parallel to the top surface of the substrate 201, and the first direction intersects with the second direction;

[0049] The source region 206 is located in the well region 202 on one side of the first sidewall 11;

[0050] The shallow trench isolation structure 205 is partially located in the drift region 203 and surrounds the first side wall 11 and the second side wall 12 of the drain region 204, wherein the shallow trench isolation structure 205 located outside the second side wall 12 also extends along the second direction to the inner side wall of the well region 202;

[0051] The gate structure 207 crosses and covers a portion of the well region 202 , the drift region 203 and the shallow trench isolation structure 205 along the first direction;

[0052] Among them, the dimension along the first direction between the first side wall 11 of the drain region 204 close to the source region 206 and the outer side wall of the shallow trench isolation structure 205 close to the source region 206 is a target width D1, and the dimension along the second direction between the second side wall 12 of the drain region 204 and the inner side wall of the drift region 203 is a target length D2; the ratio of the target width D1 to the target length D2 is within a target range, and the target range is associated with the target withstand voltage value of the semiconductor device.

[0053] Specifically, the semiconductor device is a power device, the power device includes a DEMOS device, and the DEMOS device includes an LDMOS device.

[0054] The substrate 201 may include a relative top surface and a back surface. The material of the substrate 201 may include silicon (Si), germanium (Ge), or silicon germanium (GeSi), silicon carbide (SiC); it may also be silicon on insulator (SOI), germanium on insulator (GOI); or it may also include other materials, such as III-V group compounds such as gallium arsenide.

[0055] The substrate 201 has a well region 202, and the well region 202 is doped with impurity ions. The doping type of the well region 202 varies according to the type of the semiconductor device. In some embodiments, when the type of the semiconductor device is N-type, the doping type of the well region 202 is P-type, that is, the well region 202 is doped with P-type impurity ions, and the P-type impurity ions include one or more of boron ions, gallium ions, or indium ions. In other embodiments, when the type of the semiconductor device is P-type, the doping type of the well region 202 is N-type, that is, the well region 202 is doped with N-type impurity ions, and the N-type impurity ions include one or more of phosphorus ions, arsenic ions, or antimony ions. In some embodiments, the well region 202 can be formed by injecting P-type impurity ions or N-type impurity ions into the substrate 201.

[0056] The drift region 203 is located in the well region 202. The depth of the drift region 203 may be less than, equal to, or greater than the depth of the well region 202. The doping type of the drift region 203 is opposite to the doping type of the well region 202. In some embodiments, when the doping type of the well region 202 is P-type, the doping type of the drift region 203 is N-type. In other embodiments, when the doping type of the well region 202 is N-type, the doping type of the drift region 203 is P-type. In some embodiments, the drift region 203 may be formed by implanting P-type impurity ions or N-type impurity ions into the substrate 201.

[0057] The drain region 204 is located in the drift region 203, the depth of the drain region 204 is less than the depth of the drift region 203, the doping type of the drain region 204 is the same as the doping type of the drift region 203, and the concentration of impurity ions doped in the drain region 204 is greater than the concentration of impurity ions doped in the drift region 203. In some embodiments, when the doping type of the drift region 203 is N-type, the doping type of the drain region 204 is N-type. In other embodiments, when the doping type of the drift region 203 is P-type, the doping type of the drain region 204 is P-type. In some embodiments, the drain region 204 can be formed by implanting P-type impurity ions or N-type impurity ions into the substrate 201.

[0058] The drain region 204 is in a cubic shape. Specifically, the drain region 204 may include an opposite top surface and a bottom surface, and four outer side walls located between the top surface and the bottom surface. The four outer side walls include two first side walls 11 distributed along the second direction (refer to Figure 3 ) and two second side walls 12 distributed along the first direction (reference Figure 3 ), the first direction and the second direction are both parallel to the top surface of the substrate 201, and the first direction intersects with the second direction. In some embodiments, the two first side walls 11 may be parallel to each other, the two second side walls 12 may also be parallel to each other, and the first direction and the second direction are perpendicular to each other. In a specific example, the first direction is Figure 2-Figure 5 The X-axis direction is shown in Figure 2-Figure 5 The Y-axis direction shown in .

[0059] The source region 206 is located in the well region 202 on one side of the first sidewall 11, the doping type of the source region 206 is opposite to that of the well region 202 and is the same as that of the drain region 204, and the depth of the source region 206 is less than the depth of the well region 202, and the concentration of impurity ions doped in the source region 206 is greater than the concentration of impurity ions doped in the well region 202. In some embodiments, when the doping type of the well region 202 is P-type, the doping type of the source region 206 is N-type. In other embodiments, when the doping type of the well region 202 is N-type, the doping type of the source region 206 is P-type. In some embodiments, the source region 206 can be formed by implanting P-type impurity ions or N-type impurity ions in the substrate 201.

[0060] The shallow trench isolation structure 205 is partially located in the drift region 203 and partially located in the well region 202. The outer wall of the shallow trench isolation structure 205 outside the first side wall does not contact the inner wall of the drift region 203 in the first direction. The depth of the shallow trench isolation structure 205 is greater than the depth of the drain region 204 and less than the depth of the drift region 203. Specifically, the shallow trench isolation structure 205 is partially located in the drift region 203 and surrounds the first side wall 11 and the second side wall 12 of the drain region 204, and the shallow trench isolation structure 205 located outside the second side wall 12 also extends along the second direction to the inner wall of the well region 202; and the The ratio of the target width D1 to the target length D2 is within the target range, the target range is associated with the target withstand voltage value of the semiconductor device, the target width D1 is the dimension between the first side wall 11 of the drain region 204 close to the source region 206 and the outer side wall of the shallow trench isolation structure 205 close to the source region 206 along the first direction, the target length D2 is the dimension between the second side wall 12 of the drain region 204 and the inner side wall of the drift region 203 along the second direction, and the target range is associated with the target withstand voltage value of the semiconductor device including: when the ratio of the target width D1 to the target length D2 is within the target range, the position VE of the superimposed breakdown voltage (reference Figure 3 ) moves from a first position of the drift region 203 to a second position of the drift region 203, wherein the target withstand voltage value of the second position is greater than the target withstand voltage value of the first position; the superimposed breakdown voltage VE is a lateral breakdown voltage BVDS along a first direction between the source region 206 and the drain region 204 (reference Figure 3 ), and the longitudinal breakdown voltage BVDB between the drain region 204 and the substrate 201 along the second direction (reference Figure 3 In one example, the first position is an inner corner 13 (reference Figure 3 ), the second position is the inner sidewall of the drift region 203 which is not easily broken down and is parallel to the second sidewall 12, and the angle between the superimposed breakdown voltage VE and the longitudinal breakdown voltage BVDB at the second position is smaller than the angle between the superimposed breakdown voltage VE and the longitudinal breakdown voltage BVDB at the first position. The present application enables the shallow trench isolation structure 205 in the drift region 203 to meet the ratio of the target width D1 to the target length D2, which not only optimizes the lateral breakdown voltage BVDS along the first direction between the source region 206 and the drain region 204 (reference Figure 3 , Breakdown Voltage Drain to Source, BVDS), and optimizes the longitudinal breakdown voltage BVDB along the second direction between the drain region 204 and the substrate 201 (reference Figure 3 , Breakdown Voltage Bulk to Drain, BVDB), so that the position of the superimposed breakdown voltage VE of the lateral breakdown voltage BVDS and the longitudinal breakdown voltage BVDB is moved from the inner corner 13 of the drift region 203 which is easily broken down to the inner side wall of the drift region 203 which is not easily broken down and is parallel to the second side wall 12, thereby improving the target withstand voltage value (withstand voltage (BV) or source-drain breakdown voltage (BVdss)) of the semiconductor device.

[0061] The target withstand voltage value is greater than the withstand voltage value of the existing semiconductor device. The target withstand voltage value is generally 5V-10V greater than the withstand voltage value of the existing semiconductor device (the existing semiconductor device can be, for example, a semiconductor device before the shallow trench isolation structure is improved). For example, when the withstand voltage value of the existing semiconductor device is 45V, the withstand voltage value of the semiconductor device can be increased by 5V-10V by adopting the improvement method described above in the present application, that is, the withstand voltage value of the improved semiconductor device is 45V-55V, and the target withstand voltage value is 45V-55V.

[0062] In some embodiments, the ratio of the target width D1 to the target length D2 is within a target range, and the target range may be 0.9-1.3. Furthermore, the target range may be 1. In a specific embodiment, the ratio of the target width D1 to the target length D2 may be 0.9, 1.0, 1.1, 1.2, or 1.3. When the ratio of the target width D1 to the target length D2 is within the aforementioned specific range, the lateral breakdown voltage BVDS (reference value) along the first direction between the source region 206 and the drain region 204 is further optimized. Figure 3 , Breakdown Voltage Drain to Source, BVDS), and further optimizes the longitudinal breakdown voltage BVDB along the second direction between the drain region 204 and the substrate 201 (reference Figure 3 , Breakdown Voltage Bulk to Drain, BVDB), so that the position of the superimposed breakdown voltage VE of the lateral breakdown voltage BVDS and the longitudinal breakdown voltage BVDB is moved to a greater extent from the inner corner 13 of the drift region 203 which is easily broken down to the inner side wall of the drift region 203 which is not easily broken down and is parallel to the second side wall 12, thereby further improving the target withstand voltage value (withstand voltage (BV) or source-drain breakdown voltage (BVdss)); and preventing the target withstand voltage value (withstand voltage (BV) or source-drain breakdown voltage (BVdss)) from decreasing instead of increasing due to the ratio of the target width D1 to the target length D2 being too large or too small, for details, please refer to Figure 6 , Figure 6The target length D2 is 1.5 microns, and the target width D1 changes, and the corresponding target withstand voltage value is simulated. The horizontal axis represents the target width D1, and the vertical axis represents the target withstand voltage value. Figure 6 It can be seen that when the target width D1 is in the range of 1.4 microns to 1.9 microns, that is, the ratio of the target width D1 to the target length D2 is in the target range of 0.9-1.3, the target withstand voltage value can maintain a higher value (47V-51V), and when the ratio of the target width D1 to the target length D2 is less than 0.9 (the target width D1 is less than 1.4 microns, and the target length D2 is 1.5 microns) or greater than 1.3 (the target width D1 is greater than 1.9 microns, and the target length D2 is 1.5 microns), the target withstand voltage value will decrease instead of increase (will decrease).

[0063] In a specific embodiment, the target withstand voltage range of the semiconductor device is 30V-60V, for example, it can be 30V, 35V, 40V, 45V, 50V, 50V, 60V, the target width D1 range is 1.4 microns-1.9 microns, for example, it can be 1.4 microns, 1.5 microns, 1.6 microns, 1.7 microns, 1.8 microns, 1.9 microns, the target length D2 range is 1.4 microns-1.9 microns, for example, it can be 1.4 microns, 1.5 microns, 1.6 microns, 1.7 microns, 1.8 microns, 1.9 microns, and the ratio of the target width D1 to the target length D2 is within the target range of 0.9-1.3.

[0064] In some embodiments, the inner sidewall of the drift region 203 includes four inner corners 13 (refer to Figure 3 ), the cross section of the inner corner 13 in the direction parallel to the top surface of the substrate 201 is in an arc shape. When the inner corner 13 is in an arc shape, it is useful to reduce tip discharge, making the inner corner 13 less likely to be broken down. By cooperating with the shallow trench isolation structure 205 with the aforementioned specific structure and the specific target width D1 and target length D2 ratio, the target withstand voltage value (withstand voltage (BV) or source-drain breakdown voltage (BVdss)) of the semiconductor device can be further improved.

[0065] The gate structure 207 spans and covers a portion of the well region 202 , the drift region 203 and the shallow trench isolation structure 205 along the first direction. The source region 206 and the drain region 204 are respectively located on two sides of the gate structure 207 along the first direction.

[0066] In some embodiments, the gate structure 207 includes a gate dielectric layer and a gate electrode located on the upper dielectric layer. In a specific example, the material of the gate dielectric layer is silicon oxide, and the material of the gate electrode is polysilicon. In another specific example, the material of the gate dielectric layer is a high-K dielectric material, and the K dielectric material includes HfO 2 、Al2 O 3 、ZrO 2 , one or more of HfSiO, HfSiON, HfTaO and HfZrO, the material of the gate electrode includes metal, and the metal includes one or more of W, Al, Cu, Ti, Ta, Co, TaN, NiSi, CoSi, TiN, TiAl and TaSiN.

[0067] The present application also provides a method for preparing a semiconductor device, comprising:

[0068] A substrate 201 is provided, wherein a well region 202 is formed in the substrate 201. In a specific example, a first ion implantation is performed on the substrate 201 to form the well region 202. Before the first ion implantation is performed, a mask layer may be formed correspondingly on a portion of the top surface of the substrate 201 where no implantation is required;

[0069] A drift region 203 is formed in the well region 202. The doping type of the drift region 203 is opposite to that of the well region 202. In a specific example, a second ion implantation is performed on the substrate 201 to form the drift region 203. Before the second ion implantation is performed, a mask layer may be formed on a portion of the top surface of the substrate 201 where no implantation is required.

[0070] A drain region 204 is formed in the drift region 203, wherein the doping type of the drain region 204 is the same as the doping type of the drift region 203, and the outer sidewall of the drain region 204 includes two first sidewalls distributed along the second direction and two second sidewalls distributed along the first direction, wherein the first direction and the second direction are both parallel to the top surface of the substrate 201, and the first direction intersects with the second direction;

[0071] A source region 206 is formed in the well region 202 on one side of the first sidewall of the drain region 204. The doping type of the source region 206 is opposite to that of the well region 202. In a specific example, a third ion implantation is performed on the substrate 201 to form the source region 206 and the drain region 204. Before the third ion implantation is performed, a mask layer may be formed on a portion of the top surface of the substrate 201 where no implantation is required.

[0072] A shallow trench isolation structure 205 is formed in the drift region 203, which surrounds the first sidewall and the second sidewall of the drain region 204, wherein the shallow trench isolation structure 205 outside the second sidewall also extends along the second direction to the inner sidewall of the well region 202; wherein the dimension along the first direction between the first sidewall 11 of the drain region 204 close to the source region 206 and the outer sidewall of the shallow trench isolation structure 205 close to the source region 206 is a target width D1, and the dimension along the second direction between the second sidewall 12 of the drain region 204 and the inner sidewall of the drift region 203 is a target length D2; the ratio of the target width D1 to the target length D2 is within a target range, and the target range is associated with a target withstand voltage value of the semiconductor device. In a specific example, the formation process of the shallow trench isolation structure 205 may include: forming a trench in the substrate 201; filling the trench with isolation material, and planarizing the filled isolation material, and forming the shallow trench isolation structure 205 in the trench;

[0073] A gate structure 207 is formed along the first direction to cross and cover a portion of the well region 202 , the drift region 203 , and the shallow trench isolation structure 205 .

[0074] In the description of this specification, the description with reference to the terms "some embodiments", "other embodiments", "ideal embodiments", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.

[0075] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features of the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0076] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be construed as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent application shall be subject to the attached claims.

Claims

1. A semiconductor device, characterized in that: include: Substrate, shallow trench isolation structure and gate structure; The substrate includes a well region, a drift region, a drain region and a source region, the drift region is located in the well region, the drain region is located in the drift region, and the outer sidewall of the drain region includes two first sidewalls distributed along the second direction and two second sidewalls distributed along the first direction, the first direction and the second direction are both parallel to the top surface of the substrate, and the first direction intersects with the second direction; The source region is located in a well region on one side of the first side wall; The shallow trench isolation structure is partially located in the drift region and surrounds the first side wall and the second side wall of the drain region, wherein the shallow trench isolation structure located outside the second side wall also extends along the second direction to the inner side wall of the well region; The gate structure crosses and covers a portion of the well region, the drift region and the shallow trench isolation structure along the first direction; Among them, the dimension along the first direction between the first side wall of the drain region close to the source region and the outer side wall of the shallow trench isolation structure close to the source region is a target width, and the dimension along the second direction between the second side wall of the drain region and the inner side wall of the drift region is a target length; the ratio of the target width to the target length is within a target range, and the target range is associated with a target withstand voltage value of the semiconductor device.

2. The semiconductor device according to claim 1, wherein: The target range is 0.9-1.

3.

3. The semiconductor device according to claim 1, wherein: The target range is associated with the target withstand voltage value of the semiconductor device and includes: when the ratio of the target width to the target length is within the target range, the position of the superimposed breakdown voltage moves from the first position of the drift region to the second position of the drift region, and the target withstand voltage value at the second position is greater than the target withstand voltage value at the first position; the superimposed breakdown voltage is the superposition of the lateral breakdown voltage along the first direction between the source region and the drain region and the longitudinal breakdown voltage along the second direction between the drain region and the substrate.

4. The semiconductor device according to claim 1 or 2, characterized in that: The target withstand voltage range of the semiconductor device is 30V-60V, the target width range is 1.4 microns-1.9 microns, and the target length range is 1.4 microns-1.9 microns.

5. The semiconductor device according to claim 1, wherein: An outer sidewall of the shallow trench isolation structure outside the first sidewall does not contact the inner sidewall of the drift region in the first direction.

6. The semiconductor device according to claim 1 or 5, characterized in that: The depth of the shallow trench isolation structure is greater than the depth of the drain region and less than the depth of the drift region.

7. The semiconductor device according to claim 1 or 2, characterized in that: The inner side wall of the drift region includes four inner corners, and the cross-section of the inner corners in a direction parallel to the top surface of the substrate is in an arc shape.

8. The semiconductor device according to claim 1, wherein: The doping type of the drift region is opposite to that of the well region, the doping type of the drain region is the same as that of the drift region, and the doping type of the source region is opposite to that of the well region.

9. The semiconductor device according to claim 8, characterized in that The doping type of the well region is P type, and the doping types of the drift region, the drain region and the source region are N type; or, the doping type of the well region is N type, and the doping types of the drift region, the drain region and the source region are P type.

10. A method for preparing a semiconductor device, characterized in that: include: Providing a substrate, wherein a well region is formed in the substrate; forming a drift region in the well region, wherein the doping type of the drift region is opposite to the doping type of the well region; forming a drain region in the drift region, wherein the doping type of the drain region is the same as the doping type of the drift region, and the outer sidewall of the drain region comprises two first sidewalls distributed along a second direction and two second sidewalls distributed along the first direction, wherein the first direction and the second direction are both parallel to the top surface of the substrate, and the first direction intersects with the second direction; forming a source region in a well region on one side of the first sidewall of the drain region, wherein the doping type of the source region is opposite to the doping type of the well region; A shallow trench isolation structure is formed in the drift region, which surrounds a first sidewall and a second sidewall of the drain region, wherein the shallow trench isolation structure outside the second sidewall also extends along the second direction to the inner sidewall of the well region; wherein a dimension along the first direction between a first sidewall of the drain region close to the source region and an outer sidewall of the shallow trench isolation structure close to the source region is a target width, and a dimension along the second direction between a second sidewall of the drain region and an inner sidewall of the drift region is a target length; a ratio of the target width to the target length is within a target range, and the target range is associated with a target withstand voltage value of the semiconductor device; A gate structure is formed along the first direction, spanning and covering a portion of the well region, the drift region and the shallow trench isolation structure.

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