Integrated SBD silicon carbide MOSFET cellular structure and preparation method thereof

Abstract

The invention relates to the technical field of semiconductors, in particular to an SBD-integrated silicon carbide MOSFET cellular structure and a preparation method, by additionally arranging a Schottky metal layer and optimizing the SBD-integrated silicon carbide MOSFET cellular structure according to the additionally arranged Schottky metal layer, an SBD can be integrated in the silicon carbide MOSFET cellular structure without increasing the cellular size, and therefore the SBD-integrated silicon carbide MOSFET cellular structure can be obtained. And the channel density of the chip is higher and the on resistance is smaller under the same chip area, so that the conduction loss is reduced, and the conduction efficiency of the chip is improved under the condition of ensuring that the follow current voltage is smaller.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to an integrated SBD silicon carbide MOSFET cell structure and a preparation method thereof. Background Art

[0002] The silicon carbide MOSFET body diode is a metal-oxide-semiconductor field-effect transistor based on silicon carbide material. It has the advantages of high switching frequency, high conversion efficiency, high power density and low cooling requirements. It is mainly used in bridge circuits to provide a freewheeling channel for the inductor current that cannot change suddenly when the switching device is disconnected, so that the inductor current can gradually decrease, avoiding excessively high voltage spikes in the circuit that damage the switching devices and other components in the circuit.

[0003] However, since the bandgap of SiC (3.26eV) is much higher than the bandgap of silicon (1.12eV), the turn-on voltage of SiC MOSFET body diode (about 2.3V) is much higher than the turn-on voltage of silicon-based MOSFET body diode (about 0.7V), which requires a larger conduction voltage drop during the freewheeling process of SiC MOSFET body diode, resulting in a longer start time of freewheeling, reduced stability, and greater power loss, reducing system efficiency. At present, in order to reduce this conduction voltage drop, it is usually chosen to construct a trench in the SiC MOSFET cell. The bottom of the trench is a typical planar gate SiC MOSFET structure, and a Schottky barrier diode (SBD) is constructed on the upper surface of the boss, such as Figure 1 As shown, a Schottky barrier is formed, allowing electrons to cross with relatively low energy. However, this integrated SBD method will increase the width of the SiC MOSFET cell, so that when the chip area is constant, the number of integrated SBD SiC MOSFET cells that can be accommodated is reduced, resulting in a decrease in the channel density of the chip and an increase in the on-resistance of the chip, thereby increasing the conduction loss of the chip and reducing the conduction efficiency of the chip. Summary of the invention

[0004] The purpose of the present invention is to provide an integrated SBD silicon carbide MOSFET cell structure and a preparation method in view of the corresponding deficiencies in the prior art. By adding a Schottky metal layer and optimizing the integrated SBD silicon carbide MOSFET cell structure based on the added Schottky metal layer, SBD can be integrated in the silicon carbide MOSFET cell structure without increasing the cell size.

[0005] The objective of the present invention is achieved by adopting the following scheme: A method for preparing a planar integrated SBD silicon carbide MOSFET cell structure comprises the following steps: 1) Reduce the size of the gate vertically to expose the sidewall between the drift region and the gate; 2) disposing a second Schottky metal layer on the exposed side wall between the drift region and the gate, and connecting the second Schottky metal layer to the first Schottky metal layer; 3) reducing the lateral size of the first Schottky metal layer; 4) A second p+ type region is provided below the right end of the first Schottky metal layer.

[0006] Preferably, a longitudinal reduction threshold is provided for longitudinally reducing the size of the gate, and the value range of the longitudinal reduction threshold is 40% to 50%.

[0007] Preferably, a lateral reduction threshold is provided to reduce the lateral size of the first Schottky metal layer, and the value range of the lateral reduction threshold is 30% to 40%.

[0008] Preferably, the second Schottky metal layer is disposed on the exposed side wall between the drift region and the gate by metal sputtering.

[0009] Preferably, the second p+ type region is disposed below the right end of the first Schottky metal layer by aluminum ion implantation.

[0010] The planar integrated SBD silicon carbide MOSFET cell structure obtained by the above preparation method includes a drain, a substrate, a drift region, a p-body type region, a first p+ type region, an n+ type region, an ohmic metal layer, a gate, and an oxide layer stacked from bottom to top, characterized in that a second Schottky metal layer is provided on the exposed side wall between the drift region and the gate, and the second Schottky metal layer is connected to the first Schottky metal layer.

[0011] Preferably, a second P+ type region is provided below the right end of the first Schottky metal.

[0012] A method for preparing a trench integrated SBD silicon carbide MOSFET cell structure comprises the following steps: 1) On the left side of the bottom of the dummy gate, a Schottky metal layer is formed by metal sputtering; 2) On the right side of the bottom of the dummy gate, an oxide layer is formed by dry oxygen growth; 3) Using an oxide layer to separate the Schottky metal layer from the sidewall portion of the Ohmic metal layer.

[0013] The trench-type integrated SBD silicon carbide MOSFET cell structure obtained by the above-mentioned preparation method includes a drain, an n+ type substrate, an n- type drift region, a P-type region, an ohmic metal layer, an n+ type region, a gate, and a first oxide layer stacked from bottom to top, and is characterized in that a Schottky metal layer is provided at the dummy gate trench, and the Schottky metal layer is separated from the ohmic metal layer by a second oxide layer.

[0014] The beneficial effects of the present invention are as follows: ① The present invention sets a lateral reduction threshold and a longitudinal reduction threshold, thereby reducing the lateral size of the Schottky contact and the size of the planar integrated SBD silicon carbide MOSFET cell structure while ensuring that the planar integrated SBD silicon carbide MOSFET cell structure has the original function, so that the chip channel density is higher and the on-resistance is smaller under the same chip area, thereby reducing the conduction loss and improving the conduction efficiency of the chip while ensuring that the freewheeling voltage is small; ② The present invention increases the on-current capability of the integrated SBD, reduces the freewheeling loss under high current conditions, and improves the withstand voltage capability of the integrated SBD structure by adding an additional p+ region below the second Schottky metal layer of the planar integrated SBD silicon carbide MOSFET cell structure; ③ The present invention realizes SBD structure integration without increasing the cell size by adding a Schottky metal layer at the dummy gate trench of the trench-type integrated SBD silicon carbide MOSFET cell structure, and isolates the Schottky contact and the ohmic contact through the oxide layer, so that the chip channel density is higher and the on-resistance is smaller under the same chip area, thereby reducing the conduction loss and improving the conduction efficiency of the chip while ensuring a small freewheeling voltage.

[0015] Bridge circuit: A rectifying circuit consisting of four diodes connected in a "bridge" structure. Its function is to convert the alternating current output by the AC transformer circuit into unidirectional pulsating direct current.

[0016] SBD: refers to Schottky Barrier Diode. SBD integration refers to the formation of Schottky barrier diodes and other electronic components (such as silicon carbide MOSFET, etc.) on the same wafer through a series of process steps such as doping, etching, deposition, etc. during the semiconductor manufacturing process.

[0017] Bandgap width: refers to the width of a band gap (in electron volts (ev)). The energy of electrons in solids cannot be continuously measured, but rather is a number of discontinuous energy bands. To conduct electricity, there must be free electrons or holes. The energy band where free electrons exist is called the conduction band (which can conduct electricity), and the energy band where free holes exist is called the valence band (which can also conduct electricity). For bound electrons to become free electrons or holes, they must obtain enough energy to jump from the valence band to the conduction band. The minimum value of this energy is the bandgap width.

[0018] Freewheeling: refers to providing a low impedance path in the circuit through a freewheeling diode, allowing the current to continue to flow when the switch element is turned off, thereby preventing current mutations and the generation of reverse voltage. The freewheeling diode is usually connected in parallel at both ends of components such as inductors or relays. When these components are powered off, the freewheeling diode will turn on, allowing the current to continue to flow through it, thereby protecting other components in the circuit from damage.

[0019] On-state voltage drop: refers to the voltage drop across an electronic device (such as a diode, transistor, MOSFET, etc.) when it is in the on state. From an energy perspective, this is the voltage corresponding to the energy consumed by the physical properties of the device when current passes through the device.

[0020] SiC MOSFET cell structure: A cell is composed of source, drain, gate, semiconductor layer (such as p-body, n-drift and other regions), and multiple such cells can be combined to form a complete SiC MOSFET device.

[0021] Chip channel: refers to the area between the source and drain in a semiconductor device. It is a channel for current flow, and its characteristics have a crucial impact on the performance of the chip. The channel in the present invention refers to the path for electrons or holes to conduct between the source and drain. Channel density refers to the number of channels per unit area in SiC MOSFET. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 It is a schematic diagram of the cell structure of the conventional integrated SBD silicon carbide MOSFET of the present invention; Figure 2 Schematic diagram of the planar and trench integrated SBD silicon carbide MOSFET cell structure of the present invention, Figure 2 a is a plane type, Figure 2 b is groove type; Figure 3 Schematic diagram of the optimization process of the planar integrated SBD silicon carbide MOSFET cell in Example 1; Figure 4 Schematic diagram of the structure of the planar integrated SBD silicon carbide MOSFET cell in this embodiment 1. DETAILED DESCRIPTION

[0023] like Figures 1 to 4 As shown, an integrated SBD silicon carbide MOSFET cell structure and a preparation method include the following steps: A method for preparing a planar integrated SBD silicon carbide MOSFET cell structure comprises the following steps: 1) The size of the gate 8 is reduced longitudinally to expose the side wall between the drift region 3 and the gate 8; 2) a second Schottky metal layer 9 is provided on the exposed side wall 23 between the drift region 3 and the gate 8, and the second Schottky metal layer 9 is connected to the first Schottky metal layer 10; 3) reducing the lateral size of the first Schottky metal layer 10; 4) A second p + -type region 11 is provided below the right end of the first Schottky metal layer 10 .

[0024] In the present invention, a longitudinal reduction threshold is provided for longitudinally reducing the size of the gate 8, and the value range of the longitudinal reduction threshold is 40% to 50%; a lateral reduction threshold is provided for reducing the lateral size of the first Schottky metal layer 10, and the value range of the lateral reduction threshold is 30% to 40%.

[0025] In the present invention, the second Schottky metal layer 9 is disposed on the exposed side wall 23 between the drift region 3 and the gate 8 by metal sputtering; the second p+ type region 11 is disposed below the right end of the first Schottky metal layer 10 by aluminum ion implantation.

[0026] The planar integrated SBD silicon carbide MOSFET cell structure obtained by the above preparation method is as follows: Figure 2 As shown in a, it includes a drain 1, a substrate 2, a drift region 3, a p-body type region 4, a first p+ type region 5, an n+ type region 6, an ohmic metal layer 7, a gate 8, and an oxide layer 22 stacked from bottom to top, characterized in that a second Schottky metal layer 9 is provided on the exposed side wall 23 between the drift region 3 and the gate 8, and the second Schottky metal layer 9 is connected to the first Schottky metal layer 10.

[0027] In the present invention, a second P+ type region 11 is provided below the right end of the first Schottky metal layer 10 .

[0028] A method for preparing a trench integrated SBD silicon carbide MOSFET cell structure comprises the following steps: 1) On the left side of the bottom of the dummy gate, a Schottky metal layer 16 is formed by metal sputtering; 2) On the right side of the bottom of the dummy gate, an oxide layer 17 is formed by dry oxygen growth; 3) The Schottky metal layer 16 is partially separated from the sidewall of the ohmic metal layer 18 by using the oxide layer 17 .

[0029] The trench-type integrated SBD silicon carbide MOSFET cell structure obtained by the above-mentioned preparation method is as follows: Figure 2As shown in b, it includes a drain 12, an n+ type substrate 13, an n- type drift region 14, a P type region 15, an ohmic metal layer 18, an n+ type region 19, a gate 20, and a first oxide layer 21 stacked from bottom to top, and is characterized in that a Schottky metal layer 16 is provided at the dummy gate trench, and the Schottky metal layer 16 is separated from the ohmic metal layer 18 by a second oxide layer 17.

[0030] According to the above method, embodiments 1 and 2 are performed to construct a planar integrated SBD silicon carbide MOSFET cell and a trench integrated SBD silicon carbide MOSFET cell: Example 1 (Planar Integrated SBD Silicon Carbide MOSFET Cell): 1) In Figure 1 On the basis of the conventional integrated SBD silicon carbide MOSFET cell shown, the size of the gate 8 is reduced vertically, so that the side wall between the drift region 3 and the gate 8 is exposed; 2) a second Schottky metal layer 9 is provided on the exposed side wall 23 between the drift region 3 and the gate 8 by metal sputtering, and the second Schottky metal layer 9 is connected to the first Schottky metal layer 10; In this embodiment, Figure 4 As shown, an oxide layer A is provided on the side wall between the drift region 3 and the gate 8. When forming the second Schottky metal layer 9, A is dug out, and the second Schottky metal layer 9 is formed by metal sputtering.

[0031] 3) reducing the lateral size of the first Schottky metal layer 10; 4) A second p+ type region 11 is provided below the right end of the first Schottky metal layer 10 by aluminum ion implantation.

[0032] In this embodiment, a longitudinal reduction threshold is provided for longitudinally reducing the size of the gate 8, and the value range of the longitudinal reduction threshold is 40% to 50% (i.e., the top of the gate is reduced by 0.8 to 1.2 μm); a lateral reduction threshold is provided for reducing the lateral size of the first Schottky metal layer 10, and the value range of the lateral reduction threshold is 30% to 40%. The longitudinal reduction threshold and the lateral reduction threshold are determined through multiple calibration experiments and are empirical values.

[0033] In this embodiment, the planar integrated SBD silicon carbide MOSFET cell structure includes a drain 1, a substrate 2, a drift region 3, a p-body type region 4, a first p+ type region 5, an n+ type region 6, an ohmic metal layer 7, a gate 8, and an oxide layer 22 stacked from bottom to top, and a second Schottky metal layer 9 is provided on the exposed side wall 23 between the drift region 3 and the gate 8, and the second Schottky metal layer 9 is connected to the first Schottky metal layer 10.

[0034] In this embodiment, a second P+ type region 11 is provided below the right end of the first Schottky metal 10 .

[0035] In this embodiment, the planar integrated SBD silicon carbide MOSFET cell has two different source contacts, one is an ohmic contact source S1 for conducting MOS current, and the other is a Schottky contact source S2 for forming a Schottky junction. When the cell is turned on; ① Forward conduction: A forward voltage is applied between the gate 8 and the ohmic contact source S1 to form a channel. The current flows in from the drain 1, flows through the drift region 3 and the channel into the highly doped n+ region 6, and finally flows out from the ohmic contact source S1. The ohmic contact source S1, the gate 8, the drain 1, the first p+ region 5 of the doped region, the n+ region 6, the p-body region 4, the drift region 3 and the substrate 2 form a typical MOSFET cell structure.

[0036] ② Reverse freewheeling: When a reverse voltage is applied between the gate 8 and the Schottky contact source S2, the channel is closed, and the current flows from the Schottky contact source S2, flows into the drift region 3 through the Schottky junction formed between the S2 metal electrode and the semiconductor, and finally flows out from the drain 1. The Schottky contact source S2, the drift region 3, the substrate 2, and the drain 1 together form the SBD structure.

[0037] Among them, compared with the original silicon carbide MOSFET body diode, the turn-on voltage of the silicon carbide SBD is lower, only about 1.1V, which reduces the freewheeling conduction voltage drop of the silicon carbide MOSFET and improves the system efficiency.

[0038] Embodiment 2 (Trench-type integrated SBD silicon carbide MOSFET cell): A method for preparing a trench integrated SBD silicon carbide MOSFET cell structure comprises the following steps: 1) On the left side of the bottom of the dummy gate, a Schottky metal layer 16 is formed by metal sputtering; 2) On the right side of the bottom of the dummy gate, an oxide layer 17 is formed by dry oxygen growth; 3) The Schottky metal layer 16 is partially separated from the sidewall of the ohmic metal layer 18 by using the oxide layer 17 .

[0039] In this embodiment, the trench-type integrated SBD silicon carbide MOSFET cell includes a drain 12, an n+ type substrate 13, an n- type drift region 14, a P-type region 15, an ohmic metal layer 18, an n+ type region 19, a gate 20, and a first oxide layer 21 stacked from bottom to top; a Schottky metal layer 16 is provided at the dummy gate trench, and the Schottky metal layer 16 is separated from the ohmic metal layer 18 by a second oxide layer 17.

[0040] In this embodiment, the trench-type integrated SBD silicon carbide MOSFET cell adopts a double trench structure, one trench is used to form a gate 20 of the channel, and the other process adopts Schottky contact to form a Schottky junction, so as to integrate SBD in the silicon carbide MOSFET cell. The Schottky metal layer 16 is located at the bottom of the dummy gate (trench) to form a Schottky contact source.

[0041] In this embodiment, the trench integrated SBD silicon carbide MOSFET cell has two different source contacts, one is an ohmic contact source S1 for conducting MOS current, and the other is a Schottky contact source S2 formed by Schottky metallization at the bottom of the dummy gate. The ohmic contact source S1 is located on the side wall of the dummy gate and the top of the n+ type region 19, and the Schottky contact source S2 is located at the bottom of the dummy gate. When the cell is turned on: ① MOSFET forward conduction: A forward voltage is applied between the gate 20 and the ohmic contact source S1 to form a channel, and the current flows in from the drain 12, flows into the n+ type region 19 through the channel formed by the side wall of the gate 20, and finally flows out from the ohmic contact source S1. The ohmic contact source S1, the gate 20, the doped region n+ type region 19, the P type region 15, the n- type drift region 14, the n+ type substrate 13 and the drain 12 constitute a typical MOSFET cell structure.

[0042] ② MOSFET reverse freewheeling: A reverse voltage is applied between the gate 20 and the Schottky contact source S2, and the channel is closed. The current flows in from the Schottky contact source S2, flows into the n-type drift region 14 through the Schottky junction, and finally flows out from the drain 12. The Schottky contact source S2, the n-type drift region 14, the n+ type substrate 13 and the drain 12 together form an SBD structure. Compared with the original body diode, this structure reduces the conduction voltage drop of the MOSFET reverse freewheeling and reduces the reverse freewheeling loss.

[0043] In this embodiment, a trench-type cell structure is adopted, and the SBD structure integration is realized without increasing the cell size without affecting the original MOS structure, so that the chip channel density is higher and the on-resistance is smaller under the same chip area, thereby reducing the conduction loss, and improving the conduction efficiency of the chip while ensuring that the freewheeling voltage is small. In addition, the ohmic contact of the P-type region 15 improves the on-current capability of the integrated SBD, reduces the freewheeling loss under high current conditions, and improves the voltage resistance of the integrated SBD structure.

[0044] Experiments have shown that by adding a Schottky metal layer to the traditional integrated SBD silicon carbide MOSFET cell structure, embodiments 1 and 2 can make the chip channel density higher and the on-resistance smaller under the same chip area, thereby reducing the conduction loss and improving the conduction efficiency of the chip while ensuring a small freewheeling voltage.

[0045] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modification made to the present invention by those skilled in the art without departing from the spirit of the present invention shall fall within the protection scope of the present invention.

Claims

1. A method for preparing a planar integrated SBD silicon carbide MOSFET cell structure, characterized in that: The following steps are involved: 1) reducing the size of the gate (8) in the longitudinal direction so that the side wall between the drift region (3) and the gate (8) is exposed; 2) providing a second Schottky metal layer (9) on the exposed side wall (23) between the drift region (3) and the gate (8), and connecting the second Schottky metal layer (9) to the first Schottky metal layer (10); 3) reducing the lateral size of the first Schottky metal layer (10); 4) A second p+ type region (11) is provided below the right end of the first Schottky metal layer (10).

2. The preparation method according to claim 1, characterized in that: A longitudinal reduction threshold is provided for longitudinally reducing the size of the grid (8), and the value range of the longitudinal reduction threshold is 40% to 50%.

3. The preparation method according to claim 1, characterized in that: A lateral reduction threshold is provided for reducing the lateral size of the first Schottky metal layer (10), and the value range of the lateral reduction threshold is 30% to 40%.

4. The preparation method according to claim 1, characterized in that: The second Schottky metal layer (9) is disposed on the exposed side wall (23) between the drift region (3) and the gate (8) by means of metal sputtering.

5. The preparation method according to claim 1, characterized in that: The second p+ type region (11) is arranged below the right end of the first Schottky metal layer (10) by means of aluminum ion implantation.

6. A planar integrated SBD silicon carbide MOSFET cell structure obtained by the preparation method according to claim 1, comprising a drain (1), a substrate (2), a drift region (3), a p-body type region (4), a first p+ type region (5), an n+ type region (6), an ohmic metal layer (7), a gate (8), and an oxide layer (22) stacked from bottom to top, characterized in that: A second Schottky metal layer (9) is provided on the exposed side wall (23) between the drift region (3) and the gate (8), and the second Schottky metal layer (9) is connected to the first Schottky metal layer (10).

7. The planar integrated SBD silicon carbide MOSFET cell structure according to claim 6, characterized in that: A second P+ type region (11) is provided below the right end of the first Schottky metal (10).

8. A method for preparing a trench integrated SBD silicon carbide MOSFET cell structure, characterized in that: The following steps are involved: 1) forming a Schottky metal layer (16) on the left side of the bottom of the dummy gate by metal sputtering; 2) forming an oxide layer (17) on the right side of the bottom of the dummy gate by dry oxygen growth; 3) Using an oxide layer (17) to separate the Schottky metal layer (16) from the side wall portion of the Ohmic metal layer (18).

9. A trench integrated SBD silicon carbide MOSFET cell structure obtained by the preparation method according to claim 8, comprising a drain (12), an n+ type substrate (13), an n- type drift region (14), a P type region (15), an ohmic metal layer (18), an n+ type region (19), a gate (20), and a first oxide layer (21) stacked from bottom to top, characterized in that: A Schottky metal layer (16) is provided at the dummy gate trench, and the Schottky metal layer (16) is separated from the ohmic metal layer (18) by a second oxide layer (17).

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