Transistor and preparation method thereof, array substrate, display panel and display device

Abstract

The invention provides a transistor and a preparation method thereof, an array substrate, a display panel and a display device. The transistor comprises a substrate; the active layer is located on one side of the substrate, the active layer comprises a crystalline oxide, the crystalline oxide comprises a first crystalline phase, and the area occupied by the first crystalline phase in the crystalline oxide per unit area is larger than or equal to 0.4 and smaller than or equal to 1. According to the technical scheme, the field effect mobility of the transistor can be improved.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a transistor and a method for manufacturing the same, an array substrate, a display panel, and a display device. Background Art

[0002] Field effect mobility is one of the important parameters to measure the performance of field effect transistors. It is used to characterize the mobility of charge carriers in semiconductors under the action of an electric field. Generally speaking, the higher the field effect mobility, the better the performance of the transistor. Crystalline oxides are an important semiconductor material. They are widely used in the manufacture of field effect transistors because of their good optical and electrical properties. However, the field effect mobility of crystalline oxides still needs to be further improved. Summary of the invention

[0003] In order to solve the above problems, the embodiments of the present application provide a transistor and a method for manufacturing the same, an array substrate, a display panel, and a display device.

[0004] In a first aspect, an embodiment of the present application provides a transistor, comprising: a substrate; an active layer, located on one side of the substrate, the active layer comprising a crystalline oxide, the crystalline oxide comprising a first crystalline phase, and an area occupied by the first crystalline phase per unit area of ​​the crystalline oxide is greater than or equal to 0.4 and less than or equal to 1.

[0005] In combination with the first aspect, the area occupied by the first crystalline phase per unit area of ​​the crystalline oxide is greater than or equal to 0.8 and less than or equal to 1; preferably, the first crystalline phase includes a 111 crystalline phase; preferably, the crystalline oxide also includes a second crystalline phase and a third crystalline phase, the second crystalline phase includes a 001 crystalline phase, and the third crystalline phase includes a 101 crystalline phase; preferably, in the crystalline oxide per unit area, the area occupied by the first crystal direction is greater than the area occupied by the third crystalline phase, and the area occupied by the third crystalline phase is greater than the area occupied by the second crystalline phase; preferably, the area occupied by the second crystalline phase per unit area of ​​the crystalline oxide is greater than or equal to 0 and less than or equal to 0.003; preferably, the area occupied by the second crystalline phase per unit area of ​​the crystalline oxide is greater than or equal to 0 and less than or equal to 0.002; preferably, the crystalline oxide includes indium gallium oxide; preferably, the ratio of the amount of indium and gallium in the indium gallium oxide is greater than 1.

[0006] In combination with the first aspect, the field effect mobility of the transistor is greater than or equal to 20 cm 2 / Vs; preferably, the field effect mobility of the transistor is positively correlated with the area occupied by the first crystalline phase in the crystalline oxide per unit area.

[0007] In combination with the first aspect, the transistor further comprises: a source-drain electrode layer located on the side of the active layer facing away from the substrate, the source-drain electrode layer comprising a source electrode and a drain electrode, the source electrode and the drain electrode being electrically connected to the active layer respectively; preferably, a first insulating layer is provided between the source-drain electrode layer and the active layer, the first insulating layer being provided with a plurality of first openings, the source electrode and the drain electrode being electrically connected to the active layer respectively through the first openings; preferably, the transistor further comprises a buffer layer, the buffer layer being located between the substrate and the active layer; preferably, the transistor further comprises a first gate electrode, being located on the side of the active layer close to the substrate; a second insulating layer is provided between the first gate electrode and the active layer; or, preferably, the transistor further comprises a second gate electrode, being located on the side of the active layer facing away from the substrate, a third insulating layer is provided between the second gate electrode and the active layer The transistor further comprises a first gate and a second gate, the first gate is located on a side of the active layer close to the substrate, the second gate is located on a side of the active layer away from the substrate, a second insulating layer is arranged between the first gate and the active layer, and a third insulating layer is arranged between the second gate and the active layer; the third insulating layer is provided with a plurality of second openings, the orthographic projections of the second openings on the substrate at least partially overlap with the orthographic projections of the first openings on the substrate, and the source and the drain are electrically connected to the active layer through the first opening and the second opening. Alternatively, preferably, the transistor further comprises a first gate and a second gate, the first gate is located on a side of the active layer close to the substrate, the second gate is located on a side of the active layer away from the substrate, a second insulating layer is arranged between the first gate and the active layer, and a third insulating layer is arranged between the second gate and the active layer; the third insulating layer is provided with a plurality of second openings, the orthographic projections of the second openings on the substrate at least partially overlap with the orthographic projections of the first openings on the substrate, and the source and the drain are electrically connected to the active layer through the first opening and the second opening.

[0008] In a second aspect, an embodiment of the present application also provides a method for preparing a transistor, comprising: preparing an active layer on a substrate, wherein the active layer comprises a crystalline oxide, the crystalline oxide comprises a first crystalline phase, and an area occupied by the first crystalline phase per unit area of ​​the crystalline oxide is greater than or equal to 0.4 and less than or equal to 1.

[0009] In combination with the second aspect, an active layer is prepared on a substrate, including: preparing an active layer on the substrate using a magnetron sputtering process, wherein the sputtering power of the magnetron sputtering process is 2.5 to 12.5 kW, and the gas atmosphere of the magnetron sputtering process includes a mixture of argon and oxygen, wherein the volume proportion of oxygen is 10% to 20%; preferably, the sputtering power is 2.5 to 7.5 kW.

[0010] In combination with the second aspect, after preparing the active layer, the method further includes: preparing a first insulating layer on the side of the active layer facing away from the substrate; patterning the first insulating layer to form a plurality of first openings, wherein the plurality of first openings expose a portion of the active layer; forming a first metal layer on the side of the first insulating layer facing away from the substrate, patterning the first metal layer to obtain a source-drain electrode layer, wherein the source-drain electrode layer includes a source electrode and a drain electrode, and the source electrode and the drain electrode are electrically connected to the active layer through the first openings; preferably, before preparing the active layer, the method further includes: forming a second metal layer on the substrate, patterning the second metal layer to obtain a first gate electrode; forming a second insulating layer on the side of the first gate electrode facing away from the substrate; or, after preparing the active layer, the method further includes: The method comprises: forming a third insulating layer on the side of the active layer facing away from the substrate; forming a third metal layer on the side of the third insulating layer facing away from the substrate, and patterning the third metal layer to obtain a second gate; or, before preparing the active layer, the method further comprises: forming a second metal layer on the substrate, and patterning the second metal layer to obtain a first gate; forming a second insulating layer on the side of the first gate facing away from the substrate; after preparing the active layer, the method further comprises: forming a third insulating layer on the side of the active layer facing away from the substrate; forming a third metal layer on the side of the third insulating layer facing away from the substrate, and patterning the third metal layer to obtain a second gate; preferably, before preparing the active layer, the method further comprises: forming a buffer layer on the substrate.

[0011] In a third aspect, an embodiment of the present application further provides an array substrate, comprising the above-mentioned transistor, or comprising a transistor prepared according to the above-mentioned method.

[0012] In a fourth aspect, an embodiment of the present application further provides a display panel, comprising the above-mentioned array substrate.

[0013] In a fifth aspect, an embodiment of the present application further provides a display device, comprising the above-mentioned display panel.

[0014] Through the above technical solution, the area occupied by the first crystal phase in the unit area of ​​the crystalline oxide is greater than or equal to 0.4, so that the crystalline oxide tends to crystallize in a single grain orientation, which can improve the field effect mobility of the transistor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 It is a schematic diagram of the structure of a transistor provided in one embodiment of the present application.

[0016] Figure 2 It is a schematic diagram of the structure of a transistor provided in yet another embodiment of the present application.

[0017] Figure 3 It is a schematic diagram of the structure of a transistor provided in yet another embodiment of the present application.

[0018] Figure 4It is a schematic diagram of the process of a transistor manufacturing method provided in one embodiment of the present application.

[0019] Figure 5a This is the crystal orientation imaging image of sample 1.

[0020] Figure 5b This is the crystal orientation imaging image of sample 2.

[0021] Figure 5c This is the crystal orientation imaging image of sample 3.

[0022] Figure 6 It is a transfer characteristic curve graph of sample 1 to sample 3.

[0023] Figure 7 It is a schematic flow chart of a method for preparing a transistor provided in yet another embodiment of the present application.

[0024] Figure 8 It is a schematic flow chart of a method for preparing a transistor provided in yet another embodiment of the present application.

[0025] Fig. 9 It is a schematic flow chart of a method for preparing a transistor provided in yet another embodiment of the present application.

[0026] Fig.10 It is a schematic diagram of the structure of a display device provided in one embodiment of the present application. DETAILED DESCRIPTION

[0027] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0028] Generally speaking, the larger the grain size of the crystalline oxide, the better the crystallization performance, the higher the field effect mobility, which is conducive to the output of large current. However, the oxide film forming process in the prior art is complicated and the grain size is not easy to control. For example, it can be considered to introduce hydrogen during film formation to increase the grain size after annealing, but it will cause the threshold voltage of the transistor device to shift in the negative direction and deviate from its normal design value. The inventor has found that the field effect mobility of the transistor is not positively correlated with the grain size, and the field effect mobility of the transistor is more closely related to the grain orientation of the crystalline oxide. Based on this discovery, the inventor further studied and proposed this application.

[0029] In a first aspect, an embodiment of the present application provides a transistor, comprising: a substrate; an active layer, located on one side of the substrate, the active layer comprising a crystalline oxide, the crystalline oxide comprising a first crystalline phase, and the area occupied by the first crystalline phase per unit area of ​​the crystalline oxide is greater than or equal to 0.4 and less than or equal to 1. In an embodiment of the present application, the area occupied by the first crystalline phase per unit area of ​​the crystalline oxide is greater than or equal to 0.4, so that the crystalline oxide tends to crystallize in a single grain orientation, which can improve the field effect mobility of the transistor device.

[0030] Figure 1 is a schematic diagram of the structure of a transistor provided in one embodiment of the present application. Figure 1 As shown, the transistor includes a substrate 10 and an active layer 240 .

[0031] Optionally, the substrate 10 includes a rigid substrate, such as glass, or a flexible substrate, such as polyimide.

[0032] In the embodiment of the present application, the active layer 240 is located on one side of the substrate 10. The active layer 240 includes a crystalline oxide, the crystalline oxide includes a first crystalline phase, and the area occupied by the first crystalline phase per unit area of ​​the crystalline oxide (i.e., the area ratio of the first crystalline phase) is greater than or equal to 0.4 and less than or equal to 1. Optionally, the area occupied by the first crystalline phase per unit area of ​​the crystalline oxide is greater than or equal to 0.8 and less than or equal to 1. Exemplarily, the area occupied by the first crystalline phase per unit area of ​​the crystalline oxide is 0.4, 0.5, 0.6, 0.7, 0.8, 0.9, 1. In the embodiment of the present application, the first crystalline phase includes a 111 crystalline phase.

[0033] In the embodiment of the present application, the crystalline oxide also includes a second crystalline phase and a third crystalline phase, the second crystalline phase includes a 001 crystalline phase, and the third crystalline phase includes a 101 crystalline phase. The second crystalline phase and the third crystalline phase belong to heterogeneous phases in the crystalline oxide. Therefore, in the crystalline oxide per unit area, the smaller the area occupied by the second crystalline phase and the third crystalline phase, the more conducive it is for the crystalline oxide to tend to single grain orientation crystallization. Optionally, in the crystalline oxide per unit area, the area occupied by the first crystalline phase is greater than the area occupied by the third crystalline phase (i.e., the area ratio of the third crystalline phase), and the area occupied by the third crystalline phase is greater than the area occupied by the second crystalline phase (i.e., the area ratio of the second crystalline phase). Optionally, the area occupied by the second crystalline phase in the crystalline oxide per unit area (i.e., the area ratio of the second crystalline phase) is greater than or equal to 0 and less than or equal to 0.003. Optionally, the area occupied by the second crystalline phase in the crystalline oxide per unit area is greater than or equal to 0 and less than or equal to 0.002. For example, the area occupied by the second crystalline phase per unit area of ​​the crystalline oxide is 0, 0.001, 0.002, or 0.003. In the embodiment of the present application, the crystalline oxide includes indium gallium oxide, and the ratio of the number of indium atoms to gallium atoms in the indium gallium oxide is greater than 1. Specifically, the number of indium atoms in the indium gallium oxide is greater than the number of gallium atoms, that is, the indium gallium oxide has a high indium-to-gallium ratio.

[0034] Continue to refer Figure 1 The transistor further includes a source-drain layer 260 located on the side of the active layer 240 away from the substrate 10, the source-drain layer 260 includes a source 261 and a drain 262, the source 261 and the drain 262 are respectively electrically connected to the active layer 240. A first insulating layer 250 is provided between the source-drain layer 260 and the active layer 240, the first insulating layer 250 is provided with a plurality of first openings 251, the source 261 and the drain 262 are respectively electrically connected to the active layer 240 through the first openings 251. Optionally, the first insulating layer 250 includes an interlayer dielectric layer.

[0035] In the embodiment of the present application, the transistor includes a first gate 230, which is located on the side of the active layer 240 close to the substrate 10. A second insulating layer 220 is provided between the first gate 230 and the active layer 240. Optionally, the second insulating layer 220 includes a gate insulating layer. That is, in the embodiment of the present application, the transistor is a transistor of a bottom gate structure. Optionally, the thickness of the second insulating layer 220 is greater than or equal to 800A and less than or equal to 4000A. Exemplarily, the thickness of the second insulating layer 220 is 800A, 100A, 1500A, 2000A, 2500A, 3000A, 3500A, 4000A.

[0036] Optionally, the transistor further includes a buffer layer 210 , and the buffer layer 210 is located between the substrate 10 and the active layer 240 .

[0037] In the embodiment of the present application, the field effect mobility of the transistor is greater than or equal to 20 cm 2 / Vs. For example, the field effect mobility of the transistor is 20cm 2 / Vs, 30cm 2 / Vs, 40cm 2 / Vs, 50cm 2 / Vs, 60cm 2 / Vs, 70cm 2 / Vs, 80cm 2 / Vs, 90cm 2 / Vs. In the embodiment of the present application, the field effect mobility of the transistor is positively correlated with the area occupied by the first crystalline phase in the crystalline oxide per unit area. That is, the larger the area occupied by the first crystalline phase in the crystalline oxide per unit area, the higher the field effect mobility of the transistor. By limiting the area occupied by the first crystalline phase in the crystalline oxide per unit area, the crystalline oxide tends to crystallize in a single grain orientation, optimizing the area occupied by the first crystalline phase, and thus improving the field effect mobility of the transistor.

[0038] Figure 2 It is a schematic diagram of the structure of a transistor provided in yet another embodiment of the present application. Figure 2 The transistor shown with Figure 1 The difference of the transistor shown is that the transistor is a transistor of a top gate structure. Specifically, the transistor includes a second gate 280, which is located on the side of the active layer 240 away from the substrate 10. A third insulating layer 270 is arranged between the second gate 280 and the active layer 240. Optionally, the third insulating layer 270 includes a gate insulating layer. The third insulating layer 270 is provided with a plurality of second openings 271, and the orthographic projection of the second openings 271 on the substrate 10 overlaps at least partially with the orthographic projection of the first openings 251 on the substrate 10. The source 261 and the drain 262 are electrically connected to the active layer 240 through the first opening 251 and the second opening 271. Optionally, the thickness of the third insulating layer 270 is greater than or equal to 800A and less than or equal to 4000A. Exemplarily, the thickness of the third insulating layer 270 is 800A, 100A, 1500A, 2000A, 2500A, 3000A, 3500A, or 4000A.

[0039] Figure 3 It is a schematic diagram of the structure of a transistor provided in yet another embodiment of the present application. Figure 3 The transistor shown with Figure 1The difference of the transistor shown is that the transistor is a transistor of a dual-gate structure. Specifically, the transistor includes a first gate 230 and a second gate 280, the first gate 230 is located on the side of the active layer 240 close to the substrate 10, and the second gate 280 is located on the side of the active layer 240 away from the substrate 10. A second insulating layer 220 is arranged between the first gate 230 and the active layer 240, and a third insulating layer 270 is arranged between the second gate 280 and the active layer 240. The third insulating layer 270 is provided with a plurality of second openings 271, and the orthographic projection of the second opening 271 on the substrate 10 overlaps at least partially with the orthographic projection of the first opening 251 on the substrate 10, and the source 261 and the drain 262 are electrically connected to the active layer 240 through the first opening 251 and the second opening 271.

[0040] In a second aspect, an embodiment of the present application provides a method for preparing a transistor, comprising: preparing an active layer on a substrate, wherein the active layer comprises a crystalline oxide, the crystalline oxide comprises a first crystalline phase, and the area occupied by the first crystalline phase per unit area of ​​the crystalline oxide is greater than or equal to 0.4 and less than or equal to 1. In an embodiment of the present application, the area occupied by the first crystalline phase per unit area of ​​the crystalline oxide is greater than or equal to 0.4, so that the crystalline oxide tends to crystallize in a single grain orientation, which can improve the field effect mobility of the transistor device.

[0041] Figure 4 FIG. 1 is a flow chart of a transistor manufacturing method provided by an embodiment of the present application. Figure 4 As shown, the method includes the following steps.

[0042] Step S410, preparing an active layer on a substrate.

[0043] In an embodiment of the present application, the active layer includes a crystalline oxide, and the crystalline oxide includes a first crystalline phase. The area occupied by the first crystalline phase per unit area of ​​the crystalline oxide is greater than or equal to 0.4 and less than or equal to 1. In an embodiment of the present application, the area occupied by the first crystalline phase per unit area of ​​the crystalline oxide is greater than or equal to 0.4, which can make the crystalline oxide tend to crystallize in a single grain orientation, thereby improving the field effect mobility of the transistor device.

[0044] In an embodiment of the present application, an active layer is prepared on a substrate, comprising: preparing an active layer on a substrate using a magnetron sputtering process. The sputtering power of the magnetron sputtering process is 2.5 to 12.5 Kw. Optionally, the sputtering power is 2.5 to 7.5 Kw. Exemplarily, the sputtering power is 2.5 Kw, 5 Kw, 7.5 Kw, 10 Kw, and 12.5 Kw. The gas atmosphere of the magnetron sputtering process includes a mixed gas of argon and oxygen. Among them, the volume proportion of oxygen is 10% to 20%. Exemplarily, the volume proportion of oxygen is 10%, 12%, 14%, 16%, 18%, and 20%. In an embodiment of the present application, by regulating the sputtering power of magnetron sputtering and the volume proportion of oxygen (i.e., the oxygen partial pressure), the crystalline oxide can be controlled to tend to single grain orientation crystallization, increase the area proportion of the first crystal phase, and thereby increase the field effect mobility of the device. In addition, in the embodiments of the present application, there is no need to introduce hydrogen, which can simplify the preparation process and will not affect the performance of the transistor device (for example, the threshold voltage remains at a normal value).

[0045] The following is an explanation using samples 1 to 3.

[0046] Sample 1, Sample 2, and Sample 3 are the same indium gallium oxide. The sputtering power of the magnetron sputtering process of Sample 1 is a specific value between 2.5 and 7.5 Kw, for example, 5 Kw. The volume proportion of oxygen in the gas atmosphere of Sample 1 is a specific value between 10% and 20%, for example, 15%. The sputtering power of the magnetron sputtering process of Sample 2 is a specific value between 7.5 and 12.5 Kw, for example, 10 Kw. The volume proportion of oxygen in the gas atmosphere of Sample 2 is a specific value between 10% and 20%, for example, 15%. The sputtering power of the magnetron sputtering process of Sample 3 is a specific value between 2.5 and 7.5 Kw, for example, 5 Kw. The volume proportion of oxygen in the gas atmosphere of Sample 3 is 0 to 10%, for example, 5%.

[0047] Sample 1, sample 2 and sample 3 were formed under their respective magnetron sputtering conditions. After the film was formed, the electron backscatter diffraction (EBSD) was used to test and the following results were obtained: Figure 5a , 5b The crystal orientation imaging images (Orientation Imaging Microscopy, OIM) of samples 1 to 3 are shown in Table 1 by analyzing the orientation imaging images.

[0048] Table 1 Area proportion of each crystal phase in sample 1, sample 2 and sample 3

[0049]

[0050] As shown in Table 1, the area ratio of the first crystal phase of sample 1 and sample 2 is greater than 0.4, the area ratio of the first crystal phase is relatively high, and the area ratio of the second crystal phase and the third crystal phase is relatively low, tending to single grain orientation crystallization. The area ratio of the first crystal phase of sample 3 is only 21.9%, which is less than 0.4, and the area ratio of the third crystal phase in sample 3 is relatively high, that is, the area ratio of the impurity phase is relatively high. Samples 1, 2, and 3 are prepared as follows Figure 3 The dual-gate structure transistor shown in the figure is prepared by referring to the present application Fig. 9 . The performance of the transistor is tested and the following results are obtained: Figure 6 The transfer characteristic curve is shown. Figure 6 The transfer characteristic curve in FIG shows the relationship between the gate voltage and the channel current. The field effect mobility of the transistor is calculated based on the data in the transfer characteristic curve and formula (1):

[0051]

[0052] Among them, I D is the channel current, V GS is the gate voltage, L is the length of the device, W is the width of the device, Cox is the capacitance per unit area, the value of L / W is 1, Cox depends on the thickness of the gate insulating layer (e.g., the second insulating layer and / or the third insulating layer), and the thickness of the gate insulating layer in samples 1 to 3 is 1200A. When the formula takes the maximum value, it is the field effect mobility. The field effect mobility and threshold voltage of samples 1, 2 and 3 are shown in Table 2.

[0053] Table 2 Field effect mobility and threshold voltage of sample 1, sample 2 and sample 3

[0054]

[0055]

[0056] It can be seen from Table 2 that samples 1 and 2 have better field effect mobility, and the field effect mobility of sample 3 is lower. That is, when the crystalline oxide tends to crystallize in a single grain orientation, the field effect mobility of the crystalline oxide meets the device requirements, and the larger the area proportion of the first crystal phase, the greater the field effect mobility.

[0057] Figure 7 FIG. 1 is a flow chart of a method for manufacturing a transistor provided by another embodiment of the present application. Figure 7 As shown, the method includes the following steps.

[0058] Step S710: forming a second metal layer on the substrate, and patterning the second metal layer to obtain a first gate.

[0059] Step S720: forming a second insulating layer on a side of the first gate facing away from the substrate.

[0060] Optionally, the second insulating layer includes a gate insulating layer.

[0061] Step S730: preparing an active layer on the side of the second insulating layer facing away from the substrate.

[0062] Optionally, according to Figure 4 The active layer was prepared by the method in .

[0063] Step S740: forming a first insulating layer on the side of the active layer facing away from the substrate, and patterning the first insulating layer to form a plurality of first openings.

[0064] Optionally, the first insulating layer includes an interlayer dielectric layer.

[0065] Step S750: forming a first metal layer on the side of the first insulating layer facing away from the substrate, and patterning the first metal layer to obtain a source and drain layer.

[0066] In the embodiment of the present application, the source-drain electrode layer includes a source electrode and a drain electrode, and the source electrode and the drain electrode are electrically connected to the active layer through the first opening, so as to obtain Figure 1 The bottom-gate transistor is shown.

[0067] Figure 8 FIG. 1 is a flow chart of a transistor manufacturing method provided by another embodiment of the present application. Figure 8 As shown, the method includes the following steps.

[0068] Step S810, forming an active layer on a substrate.

[0069] Optionally, according to Figure 4 The active layer was prepared by the method in .

[0070] Step S820: forming a third insulating layer on the side of the active layer facing away from the substrate.

[0071] Optionally, the third insulating layer includes a gate insulating layer.

[0072] Step S830: forming a third metal layer on a side of the third insulating layer facing away from the substrate, and patterning the third metal layer to obtain a second gate.

[0073] Step S840, forming a first insulating layer on the side of the second gate facing away from the substrate, patterning the first insulating layer and the third insulating layer, forming a first opening on the first insulating layer, and forming a second opening on the third insulating layer.

[0074] Optionally, the first insulating layer includes an interlayer dielectric layer.

[0075] Step S850: forming a first metal layer on the side of the first insulating layer facing away from the substrate, and patterning the first metal layer to obtain a source and drain layer.

[0076] In the embodiment of the present application, the source-drain electrode layer includes a source electrode and a drain electrode, and the source electrode and the drain electrode are electrically connected to the active layer through the first opening and the second opening, so as to obtain Figure 2 A transistor with a top-gate structure is shown.

[0077] Fig. 9 FIG. 1 is a flow chart of a transistor manufacturing method provided by another embodiment of the present application. Fig. 9 As shown, the method includes the following steps.

[0078] Step S910: forming a second metal layer on the substrate, and patterning the second metal layer to obtain a first gate.

[0079] Step S920: forming a second insulating layer on a side of the first gate facing away from the substrate.

[0080] Optionally, the second insulating layer includes a gate insulating layer.

[0081] Step S930: preparing an active layer on the side of the second insulating layer facing away from the substrate.

[0082] Optionally, according to Figure 4 The active layer was prepared by the method in .

[0083] Step S940: forming a third insulating layer on the side of the active layer facing away from the substrate.

[0084] Optionally, the third insulating layer includes a gate insulating layer.

[0085] Step S950: forming a third metal layer on a side of the third insulating layer facing away from the substrate, and patterning the third metal layer to obtain a second gate.

[0086] Step S960, forming a first insulating layer on the side of the second gate facing away from the substrate, patterning the first insulating layer and the third insulating layer, forming a first opening on the first insulating layer, and forming a second opening on the third insulating layer.

[0087] Optionally, the first insulating layer includes an interlayer dielectric layer.

[0088] Step S970: forming a first metal layer on the side of the first insulating layer facing away from the substrate, and patterning the first metal layer to obtain a source and drain layer.

[0089] In the embodiment of the present application, the source-drain electrode layer includes a source electrode and a drain electrode, and the source electrode and the drain electrode are electrically connected to the active layer through the first opening and the second opening, so as to obtain Figure 3 The transistor with a dual gate structure is shown.

[0090] In a third aspect, an embodiment of the present application further provides an array substrate, comprising the above-mentioned transistor.

[0091] In a fourth aspect, an embodiment of the present application further provides a display panel, comprising the above-mentioned array substrate.

[0092] In a fifth aspect, an embodiment of the present application provides a display device, which includes the display panel in the above embodiment.

[0093] Fig.10 is a schematic diagram of the structure of a display device provided by an embodiment of the present application. Fig.10 As shown, the display device 1000 is a product with an image display function. For example, the display device 1000 can be used to display static images, such as pictures or photos. The display device 1000 can also be used to display dynamic images, such as videos.

[0094] The display device 1000 may be a laptop computer, a mobile phone, a handheld or portable computer, a camera, a camcorder, a vehicle-mounted smart central control screen, a calculator, a smart watch, a GPS navigator, an electronic photo, an electronic billboard or sign, a projector, etc.

[0095] The display device 1000 includes the above-mentioned display panel, which may be an organic light emitting diode display panel or a quantum dot electroluminescent display panel.

[0096] In addition, the display device 1000 may also have functions such as taking photos, recording videos, fingerprint recognition, and face recognition. Accordingly, the display device 1000 also includes at least one functional module for implementing the above functions, such as an under-screen camera, an under-screen fingerprint recognition sensor, and the like.

[0097] The basic principles of the present application are described above in conjunction with specific embodiments. However, it should be noted that the advantages, strengths, effects, etc. mentioned in the present application are only examples and not limitations, and it cannot be considered that these advantages, strengths, effects, etc. are required by each embodiment of the present application. In addition, the specific details disclosed above are only for the purpose of illustration and ease of understanding, not for limitation, and the above details do not limit the present application to being implemented by adopting the above specific details.

[0098] The block diagrams of the devices, apparatuses, equipment, and systems involved in this application are only illustrative examples and are not intended to require or imply that they must be connected, arranged, and configured in the manner shown in the block diagram. As will be appreciated by those skilled in the art, these devices, apparatuses, equipment, and systems can be connected, arranged, and configured in any manner. Words such as "including", "comprising", "having", etc. are open words, referring to "including but not limited to", and can be used interchangeably with them. The words "or" and "and" used here refer to the words "and / or" and can be used interchangeably with them, unless the context clearly indicates otherwise. The words "such as" used here refer to the phrase "such as but not limited to", and can be used interchangeably with them.

[0099] It should also be noted that in the apparatus, device and method of the present application, each component or each step can be decomposed and / or recombined. Such decomposition and / or recombination should be regarded as equivalent solutions of the present application.

[0100] The above description of the disclosed aspects is provided to enable any person skilled in the art to make or use the present application. Various modifications to these aspects will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other aspects without departing from the scope of the present application. Therefore, the present application is not intended to be limited to the aspects shown herein, but rather to the widest scope consistent with the principles and novel features disclosed herein.

[0101] The above description has been given for the purpose of illustration and description. In addition, this description is not intended to limit the embodiments of the present application to the forms disclosed herein. Although multiple example aspects and embodiments have been discussed above, those skilled in the art will recognize certain variations, modifications, changes, additions and sub-combinations thereof.

[0102] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A transistor, characterized in that: include: substrate; An active layer is located on one side of the substrate, the active layer includes a crystalline oxide, the crystalline oxide includes a first crystalline phase, and an area occupied by the first crystalline phase in a unit area of ​​the crystalline oxide is greater than or equal to 0.4 and less than or equal to 1.

2. The transistor according to claim 1, characterized in that The area occupied by the first crystal phase in the crystalline oxide per unit area is greater than or equal to 0.8 and less than or equal to 1; Preferably, the first crystal phase includes 111 crystal phase; Preferably, the crystalline oxide further comprises a second crystal phase and a third crystal phase, the second crystal phase comprises a 001 crystal phase, and the third crystal phase comprises a 101 crystal phase; Preferably, in the crystalline oxide per unit area, the area occupied by the first crystal phase is larger than the area occupied by the third crystal phase, and the area occupied by the third crystal phase is larger than the area occupied by the second crystal phase; Preferably, the area occupied by the second crystal phase in the crystalline oxide per unit area is greater than or equal to 0 and less than or equal to 0.003; Preferably, the area occupied by the second crystal phase in the crystalline oxide per unit area is greater than or equal to 0 and less than or equal to 0.002; Preferably, the crystalline oxide comprises indium gallium oxide; Preferably, the ratio of the number of indium atoms to that of gallium atoms in the indium gallium oxide is greater than 1.

3. The transistor according to claim 1, characterized in that The field effect mobility of the transistor is greater than or equal to 20 cm 2 / Vs; Preferably, the field effect mobility of the transistor is positively correlated with the area occupied by the first crystal phase per unit area of ​​the crystalline oxide.

4. The transistor according to claim 1, characterized in that Also includes: a source-drain electrode layer located on a side of the active layer away from the substrate, the source-drain electrode layer comprising a source electrode and a drain electrode, the source electrode and the drain electrode being electrically connected to the active layer respectively; Preferably, a first insulating layer is provided between the source-drain electrode layer and the active layer, the first insulating layer is provided with a plurality of first openings, and the source electrode and the drain electrode are electrically connected to the active layer through the first openings respectively; Preferably, the transistor further comprises a buffer layer, wherein the buffer layer is located between the substrate and the active layer; Preferably, the transistor further comprises a first gate located on a side of the active layer close to the substrate; a second insulating layer is provided between the first gate and the active layer; or, Preferably, the transistor further comprises a second gate, which is located on a side of the active layer away from the substrate, a third insulating layer is provided between the second gate and the active layer, the third insulating layer is provided with a plurality of second openings, an orthographic projection of the second openings on the substrate at least partially overlaps with an orthographic projection of the first openings on the substrate, and the source and the drain are electrically connected to the active layer through the first openings and the second openings; or, Preferably, the transistor further includes a first gate and a second gate, the first gate is located on a side of the active layer close to the substrate, the second gate is located on a side of the active layer away from the substrate, a second insulating layer is arranged between the first gate and the active layer, and a third insulating layer is arranged between the second gate and the active layer; the third insulating layer is provided with a plurality of second openings, the orthographic projections of the second openings on the substrate at least partially overlap with the orthographic projections of the first openings on the substrate, and the source and the drain are electrically connected to the active layer through the first openings and the second openings.

5. A method for preparing a transistor, characterized in that: include: An active layer is prepared on a substrate, wherein the active layer includes a crystalline oxide, the crystalline oxide includes a first crystalline phase, and an area occupied by the first crystalline phase per unit area of ​​the crystalline oxide is greater than or equal to 0.4 and less than or equal to 1.

6. The transistor manufacturing method according to claim 5, characterized in that: The step of preparing an active layer on a substrate comprises: An active layer is prepared on a substrate by a magnetron sputtering process, wherein the sputtering power of the magnetron sputtering process is 2.5 to 12.5 kW, and the gas atmosphere of the magnetron sputtering process includes a mixed gas of argon and oxygen, wherein the volume proportion of oxygen is 10% to 20%; Preferably, the sputtering power is 2.5-7.5Kw.

7. The transistor manufacturing method according to claim 5, characterized in that: After preparing the active layer, the method further comprises: Prepare a first insulating layer on the side of the active layer facing away from the substrate; Performing patterning on the first insulating layer to form a plurality of first openings, wherein the plurality of first openings expose a portion of the active layer; forming a first metal layer on a side of the first insulating layer away from the substrate, and patterning the first metal layer to obtain a source-drain electrode layer, wherein the source-drain electrode layer includes a source electrode and a drain electrode, and the source electrode and the drain electrode are electrically connected to the active layer through the first opening; Preferably, before preparing the active layer, the method further comprises: forming a second metal layer on the substrate, patterning the second metal layer to obtain a first gate; forming a second insulating layer on the side of the first gate away from the substrate; or, after preparing the active layer, the method further comprises: forming a third insulating layer on the side of the active layer away from the substrate; forming a third metal layer on the side of the third insulating layer away from the substrate, patterning the third metal layer to obtain a second gate; or, before preparing the active layer, the method further comprises: forming a second metal layer on the substrate, patterning the second metal layer to obtain a first gate; forming a second insulating layer on the side of the first gate away from the substrate; after preparing the active layer, the method further comprises: forming a third insulating layer on the side of the active layer away from the substrate; forming a third metal layer on the side of the third insulating layer away from the substrate, patterning the third metal layer to obtain a second gate; Preferably, before preparing the active layer, the method further comprises: forming a buffer layer on the substrate.

8. An array substrate, characterized in that: A transistor comprising any one of claims 1 to 4, or a transistor prepared according to the method according to any one of claims 5 to 7.

9. A display panel, characterized in that: Comprising the array substrate as claimed in claim 8.

10. A display device, characterized in that: Comprising the display panel as claimed in claim 9.

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