Semiconductor device and display panel

Abstract

The invention provides a semiconductor device and a display panel, a semiconductor material of an active layer in the semiconductor device is doped with at least one of a tantalum element, a terbium element and a praseodymium element, and the semiconductor material comprises a metal oxide semiconductor material; a specific content of tantalum element is doped in the semiconductor material, the tantalum element is n-type doping, the effective mass of electrons is small, and the electron cloud overlapping degree can be increased due to a 5s spherical electron orbit, so that the mobility can be increased; the semiconductor material is doped with at least one of a specific content of terbium element and praseodymium element, and the terbium element and the praseodymium element can generate an acceptor trap state at the bottom of a conduction band, so that photoelectrons are captured, a photon-generated carrier recombination center can be effectively formed, and the light stability is improved.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a semiconductor device and a display panel. Background Art

[0002] In recent years, as a result of the development of liquid crystal technology, electroluminescence and related technologies, flat panel displays have been commercialized. They are driven by active matrix circuits including field effect thin film semiconductor devices that use amorphous silicon-based thin films as active layers formed on glass substrates. The performance of thin film semiconductor devices depends mainly on the properties of the active layer.

[0003] Amorphous silicon-based thin film semiconductor devices include thin film semiconductor devices including active layers formed of amorphous silicon or thin film semiconductor devices including active layers formed of polycrystalline silicon. Amorphous silicon thin film semiconductor devices have a problem in that the charge mobility is approximately 0.5 cm 2 / (V·s) or so, so it is difficult to increase the operating speed of the display device. The problem with polycrystalline silicon thin film semiconductor devices is that, since crystallization, impurity doping and activation processes are required, the manufacturing process is more complicated and the manufacturing cost is higher than that of amorphous silicon thin film semiconductor devices. In addition, the problem with polycrystalline silicon thin film semiconductor devices is that, since it is difficult to ensure the uniformity of the polycrystalline silicon layer, when the polycrystalline silicon layer is used as an active layer of a large-scale display device, the image quality is reduced.

[0004] In order to realize the next generation of high-performance / high-resolution / large-size display devices, thin-film semiconductor devices with excellent performance are required. For this purpose, oxide semiconductor films, such as Indium Gallium Zinc Oxide (IGZO) films, have been developed and studied as active layers of thin-film semiconductor devices. However, the mobility and light stability of traditional oxide thin-film semiconductor devices need to be improved. Summary of the invention

[0005] The present application provides a semiconductor device and a display panel to improve the mobility and light stability of an oxide thin film semiconductor device.

[0006] To solve the above problems, the technical solutions provided by this application are as follows:

[0007] The embodiment of the present application provides a semiconductor device, which includes an active layer, wherein the semiconductor material of the active layer is doped with tantalum, and at least one of terbium and praseodymium;

[0008] Wherein, the semiconductor material includes metal oxide semiconductor material.

[0009] In the semiconductor device provided in the embodiment of the present application, the atomic percentage of tantalum element in the semiconductor material is greater than or equal to 10% and less than or equal to 40%, the atomic percentage of terbium element is less than or equal to 10%, and / or the atomic percentage of praseodymium element is less than or equal to 10%.

[0010] In the semiconductor device provided in the embodiment of the present application, the semiconductor material further includes indium element, and the atomic percentage of the indium element is greater than or equal to 60% and less than or equal to 90%.

[0011] In the semiconductor device provided in the embodiment of the present application, the tantalum element doped in the semiconductor material has a valence of +5.

[0012] In the semiconductor device provided in the embodiment of the present application, the semiconductor device further comprises a gate electrode, and a source electrode and a drain electrode connected to the active layer, and the semiconductor device is configured such that when the gate electrode does not apply a gate voltage, the current between the source electrode and the drain electrode is less than 10 -5 A.

[0013] In the semiconductor device provided in the embodiment of the present application, the metal oxide semiconductor material includes a crystalline structure and / or an amorphous structure.

[0014] In the semiconductor device provided in the embodiment of the present application, the metal oxide semiconductor material includes indium oxide.

[0015] In the semiconductor device provided in the embodiment of the present application, the mobility of the active layer increases with the increase of the carrier concentration in the active layer.

[0016] In the semiconductor device provided in the embodiment of the present application, the carrier concentration in the active layer is greater than or equal to 10 19 cm -3 and less than 10 20 cm -3 .

[0017] In the semiconductor device provided in the embodiment of the present application, the band gap width of the active layer is greater than or equal to 3.0 eV and less than or equal to 3.8 eV.

[0018] An embodiment of the present application further provides a display panel, which includes the semiconductor device described in one of the aforementioned embodiments.

[0019] The beneficial effects of the present application are as follows: in the semiconductor device and display panel provided by the present application, the semiconductor material of the active layer in the semiconductor device is doped with tantalum, and at least one of terbium and praseodymium, and the semiconductor material includes a metal oxide semiconductor material; by doping the semiconductor material with a specific content of tantalum, the tantalum element is n-type doped, the electron effective mass is small, and the 5s spherical electron orbit can increase the degree of electron cloud overlap, thereby increasing the mobility; by doping the semiconductor material with a specific content of at least one of terbium and praseodymium, the terbium and praseodymium elements will generate acceptor-type trap states at the bottom of the conduction band, thereby capturing photoelectrons, thereby effectively forming a photogenerated carrier recombination center and improving photostability; and, by doping the semiconductor material with a specific content of tantalum and terbium, the heterostructure in the semiconductor material can be increased, and the semiconductor material can be transformed from a polycrystalline state to an amorphous state to adapt to the preparation of large-generation line oxide semiconductor devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the technical solutions in the embodiments or the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0021] Figure 1 A schematic diagram of a cross-sectional structure of a semiconductor device provided in an embodiment of the present application.

[0022] Figure 2 Another schematic diagram of the cross-sectional structure of a semiconductor device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0023] The following descriptions of the embodiments are with reference to the attached diagrams to illustrate specific embodiments that the present application can be implemented in. The directional terms mentioned in the present application, such as [up], [down], [front], [back], [left], [right], [inside], [outside], [side], etc., are only with reference to the directions of the attached drawings. Therefore, the directional terms used are used to illustrate and understand the present application, rather than to limit the present application. In the figures, units with similar structures are represented by the same reference numerals. In the accompanying drawings, the thickness of some layers and regions is exaggerated for clear understanding and ease of description. That is, the size and thickness of each component shown in the drawings are arbitrarily shown, but the present application is not limited to this.

[0024] Please refer to Figure 1 and Figure 2 , Figure 1 A schematic cross-sectional structure diagram of a semiconductor device provided in an embodiment of the present application, Figure 2Another cross-sectional structural diagram of a semiconductor device provided in an embodiment of the present application. The semiconductor device 10 includes an active layer 11, a gate electrode 12, a source electrode 13, a drain electrode 14, and a gate insulating layer 15 located between the active layer 11 and the gate electrode 12. Figure 1 and Figure 2 The difference between the semiconductor device 10 is that, Figure 1 The semiconductor device 10 in the embodiment adopts a top gate structure, that is, the gate electrode 12 is located above the active layer 11, and Figure 2 The semiconductor device 10 in the embodiment adopts a bottom gate structure, that is, the gate electrode 12 is located below the active layer 11. However, the structure of the semiconductor device 10 of the present application is not limited thereto. Figure 1 and Figure 2 The structure of the semiconductor device 10 is only for illustration.

[0025] The embodiments of this application are Figure 2 The structure of the semiconductor device 10 is described as an example. Figure 2 , the semiconductor device 10 is disposed on a substrate 20. The substrate 20 may be a glass substrate, or any of various substrates used in a general semiconductor device process, such as a plastic substrate or a silicon substrate. The substrate 20 may be an inorganic substrate or an organic substrate, and may be transparent, opaque, or translucent.

[0026] The gate electrode 12 of the semiconductor device 10 is disposed on the substrate 20. The gate electrode 12 may be formed of a general electrode material (e.g., a metal, an alloy, a conductive metal oxide, a conductive metal nitride, etc.). For example, the gate electrode 12 may be formed of a metal such as titanium (Ti), platinum (Pt), ruthenium (Ru), gold (Au), silver (Ag), molybdenum (Mo), aluminum (Al), tungsten (W), copper (Cu), neodymium (Nd), chromium (Cr), tantalum (Ta), or an alloy including the metal, or a conductive oxide such as indium zinc oxide (IZO), aluminum zinc oxide (AZO), indium tantalum oxide (ITO), gallium zinc oxide (GZO) or zinc tantalum oxide (ZTO) or a compound including a conductive oxide. The gate electrode 12 may have a single-layer structure or a multi-layer structure.

[0027] The gate insulating layer 15 covers the gate electrode 12 and the substrate 20. The gate insulating layer 15 may include a silicon oxide (SiOx) layer, a silicon oxynitride (SiOxNy) layer, or a silicon nitride (SiNx) layer, or may include another material layer such as a high-k material (e.g., HfO) having a dielectric constant higher than that of the silicon nitride layer. 2 or Al 2 O 3) layer. The gate insulating layer 15 may have a structure in which at least two layers among a silicon oxide layer, a silicon oxynitride layer, a silicon nitride layer and a high-k material layer are stacked. For example, the gate insulating layer 15 may have a structure in which a silicon nitride layer and a silicon oxide layer are stacked. In this case, the silicon nitride layer and the silicon oxide layer may be sequentially disposed on the gate electrode 12. Although Figure 2 Although not shown in the figure, a predetermined lower layer may be provided on the substrate 20, and the gate electrode 12 and the gate insulating layer 15 covering the gate electrode 12 may be provided on the lower layer. The lower layer may be an insulating layer, such as an oxide layer. The oxide layer may be, for example, a silicon oxide layer. However, the material of the lower layer may be varied in various ways.

[0028] The active layer 11 is disposed on a side of the gate insulating layer 15 away from the gate electrode 12. The active layer 11 may be disposed above the gate electrode 12 to face the gate electrode 12. The width of the active layer 11 may be greater than the width of the gate electrode 12. However, in some cases, the width of the active layer 11 may be similar to or less than the width of the gate electrode 12.

[0029] The source electrode 13 and the drain electrode 14 are located on a side of the active layer 11 away from the gate electrode 12. Optionally, the source electrode 13 and the drain electrode 14 are located on the active layer 11 and directly contact the active layer 11. The active layer 11 includes a channel portion and a source contact portion and a drain contact portion located on both sides of the channel portion, and the channel portion connects the source contact portion and the drain contact portion. The source electrode 13 is connected to the source contact portion, and the drain electrode 14 is connected to the drain contact portion. The gate electrode 12 is at least arranged corresponding to the channel portion.

[0030] The source electrode 13 and the drain electrode 14 may each have a single-layer structure or a multi-layer structure. The materials of the source electrode 13 and the drain electrode 14 may be the same as or similar to the material of the gate electrode 12. The source electrode 13 and the drain electrode 14 may each be formed of the same material as the gate electrode 12, or may be formed of a material different from the gate electrode 12. For example, each of the source electrode 13 and / or the drain electrode 14 may be formed of a metal such as Ti, Pt, Ru, Au, Ag, Mo, Al, W, Cu, Nd, Cr, Ta, or an alloy including the metal, or a conductive oxide such as IZO, AZO, ITO, GZO or ZTO, or a compound including a conductive oxide.

[0031] A passivation layer 21 is provided on one side of the source electrode 13 and the drain electrode 14 away from the active layer 11. The passivation layer 21 may be a silicon oxide layer, a silicon oxynitride layer, a silicon nitride layer or an organic layer, or may have a structure in which at least two of a silicon oxide layer, a silicon oxynitride layer, a silicon nitride layer and an organic layer are stacked. For example, the passivation layer 21 may have a single-layer structure formed of silicon oxide or silicon nitride, or a multilayer structure including a silicon oxide layer and a silicon nitride layer disposed on the silicon oxide layer. In addition, the passivation layer 21 may have a multilayer structure including two or more layers. In this case, the passivation layer 21 may include a silicon oxide layer, a silicon oxynitride layer and a silicon nitride layer stacked in sequence.

[0032] The material of the active layer 11 includes a semiconductor material, for example, the semiconductor material includes a metal oxide semiconductor material such as indium oxide, and the metal oxide semiconductor material includes a crystalline structure and / or an amorphous structure. The active layer 11 can be formed by using, for example, physical vapor deposition (PVD) such as sputtering to form a semiconductor material. Sputtering can be reactive sputtering. In addition, sputtering can be co-sputtering using multiple targets. When forming a semiconductor material by using co-sputtering, nitrogen (N 2 ) or oxygen (O 2 ) as a reaction gas, in addition, argon (Ar) can also be used. Nitrogen can be a source of nitrogen, and oxygen can be a source of oxygen. Argon can serve as a carrier gas. In addition, argon can improve deposition efficiency by generating plasma. The flow rate of nitrogen can range from about 20sccm to about 200sccm, and the flow rate of oxygen can range from about 1sccm to about 15sccm. The flow rate of argon can range from about 1sccm to about 100sccm. The supply of nitrogen can be greater than the supply of oxygen. For example, the supply of nitrogen can be 10 times or more, or 50 times or more, of the supply of oxygen.

[0033] In some embodiments, the semiconductor material of the active layer 11 is doped with at least one of tantalum (Ta), terbium (Tb) and praseodymium (Pr). That is, in some embodiments, the semiconductor material of the active layer 11 is doped with tantalum and terbium; in other embodiments, the semiconductor material of the active layer 11 is doped with tantalum and praseodymium; in other embodiments, the semiconductor material of the active layer 11 is doped with tantalum, terbium and praseodymium.

[0034] Among them, the atomic percentage of tantalum element in the semiconductor material is greater than or equal to 10% and less than or equal to 40%, that is, the content of tantalum element in the semiconductor material of the active layer 11 is 10at%≤Ta at%≤40at%, for example, the content of tantalum element is 10at%, 12at%, 15at%, 17at%, 19at%, 20at%, 22at%, 23at%, 26at%, 28at%, 30at%, 33at%, 36at%, 38at%, 40at%, etc.

[0035] It should be noted that at% means atomic percentage.

[0036] The atomic percentage of terbium in the semiconductor material is less than or equal to 10%, and / or the atomic percentage of praseodymium is less than or equal to 10%. In the embodiment of the present application, the semiconductor material includes terbium as an example. Among them, the atomic percentage of terbium in the semiconductor material is less than or equal to 10%, that is, the content of terbium in the semiconductor material of the active layer 11 is 0at%<Tb at%≤10at%, for example, the content of terbium is 0.1at%, 0.5at%, 1at%, 1.5at%, 1.8at%, 2at%, 2.6at%, 2.9at%, 3at%, 3.3at%, 3.6at%, 4at%, 4.3at%, 4.6at%, 5at%, 5.5at%, 6at%, 6.5at%, 7at%, 7.5at%, 8at%, 8.5at%, 9at%, 9.5at%, 10at%, etc.

[0037] In this way, by doping the semiconductor material of the active layer 11 with a specific content of tantalum, the tantalum element is n-type doped, the electron effective mass is small, and the 5s spherical electron orbit can increase the degree of electron cloud overlap, thereby increasing the mobility; by doping the semiconductor material with a specific content of at least one of terbium and praseodymium, the terbium and praseodymium elements will generate acceptor-type trap states at the bottom of the conduction band, thereby capturing photoelectrons, thereby effectively forming photogenerated carrier recombination centers and improving photostability; moreover, by doping the semiconductor material with a specific content of tantalum and terbium elements, the heterostructure in the semiconductor material can be increased, and the semiconductor material can be transformed from a polycrystalline state to an amorphous state to adapt to the preparation of large-generation line oxide semiconductor devices; in addition, by doping the semiconductor material with a specific content of tantalum and at least one of terbium and praseodymium elements, the tantalum, terbium, and praseodymium elements will combine with oxygen to form compounds to reduce oxygen vacancies in the semiconductor material, thereby reducing the oxygen defect density.

[0038] In some embodiments, the semiconductor material further includes indium, and the atomic percentage of indium (In) is greater than or equal to 60% and less than or equal to 90%. That is, the content of indium in the semiconductor material of the active layer 11 is 60at%≤Tb at%≤90at%, for example, the content of indium is 60at%, 63at%, 65at%, 67at%, 70%, 72at%, 75at%, 78at%, 80at%, 83at%, 87at%, 89at%, 90at%, etc.

[0039] In some embodiments, the tantalum element doped in the semiconductor material has a valence of +5. Ta has a valence of +5, which can passivate the attraction of negatively charged centers, such as O, compared to In capturing 3 electrons. 2- OH - In addition, the tantalum element has a valence of +5 and can form n-type doping. Ta replaces In, and two more free electrons become n-type carriers, such as Ta+In 3+ → 5+ +2e - +In. Ta is n-type doped, the effective mass of electrons is small, and the 5s spherical electron orbit can increase the overlap of electron clouds and increase mobility.

[0040] In some embodiments, the mobility of the active layer 11 increases with the increase of the carrier concentration in the active layer 11. For example, in the present application, the carrier concentration of the active layer 11 is greater than or equal to 10 19 cm -3 and less than 10 20 cm -3 The band gap of the active layer 11 is greater than or equal to 3.0 eV and less than or equal to 3.8 eV.

[0041] In some embodiments, the present application can improve the mobility and photostability while reducing the off-state circuit of the semiconductor device 10 by doping tantalum, terbium and praseodymium in the semiconductor material of the active layer 11. For example, the semiconductor device is configured such that the current between the source electrode 13 and the drain electrode 14 is less than 10 when the gate voltage is not applied to the gate electrode 12. -5 A.

[0042] Based on the same inventive concept, an embodiment of the present application further provides a display panel, the display panel comprising the semiconductor device 10 described in one of the aforementioned embodiments. The display panel comprises a liquid crystal display panel, a light-emitting diode (LED) display panel, a micro light-emitting diode (Micro-LED) display panel or a sub-millimeter light-emitting diode (Mini-LED) display panel.

[0043] According to the above embodiments, it can be seen that:

[0044] In a semiconductor device and a display panel provided by the present application, the semiconductor material of the active layer in the semiconductor device is doped with tantalum and at least one of terbium and praseodymium, the atomic percentage of tantalum is greater than or equal to 10% and less than or equal to 40%, the atomic percentage of terbium is less than or equal to 10%, and / or the atomic percentage of praseodymium is less than or equal to 10%; by doping the semiconductor material with a specific content of tantalum, the tantalum is n-type doped, the electron effective mass is small, and the 5s spherical electron orbit can increase the degree of electron cloud overlap, thereby increasing the mobility; by doping the semiconductor material with a specific content of at least one of terbium and praseodymium, the terbium and praseodymium will generate acceptor-type trap states at the bottom of the conduction band, thereby capturing photoelectrons, thereby effectively forming a photogenerated carrier recombination center and improving photostability; and, by doping the semiconductor material with tantalum and terbium, the heterostructure in the semiconductor material can be increased, and the semiconductor material can be transformed from a polycrystalline state to an amorphous state to adapt to the preparation of large-generation line oxide semiconductor devices.

[0045] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0046] The embodiments of the present application are introduced in detail above. Specific examples are used in this article to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the technical solution and core idea of ​​the present application. Ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or replace some of the technical features therein with equivalents; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A semiconductor device, characterized in that: An active layer is included, wherein the semiconductor material of the active layer is doped with tantalum, terbium and praseodymium; Wherein, the semiconductor material includes metal oxide semiconductor material.

2. The semiconductor device according to claim 1, wherein: The atomic percentage of tantalum in the semiconductor material is greater than or equal to 10% and less than or equal to 40%, the atomic percentage of terbium is less than or equal to 10%, and / or the atomic percentage of praseodymium is less than or equal to 10%.

3. The semiconductor device according to claim 2, characterized in that The semiconductor material also includes indium element, and the atomic percentage of the indium element is greater than or equal to 60% and less than or equal to 90%.

4. The semiconductor device according to claim 1, wherein: The tantalum element doped in the semiconductor material has a valence of +5.

5. The semiconductor device according to claim 1, wherein: The semiconductor device further comprises a gate electrode, and a source electrode and a drain electrode connected to the active layer. The semiconductor device is configured such that when the gate electrode does not apply a gate voltage, a current between the source electrode and the drain electrode is less than 10 -5 A.

6. The semiconductor device according to claim 1, wherein: The metal oxide semiconductor material includes a crystalline structure and / or an amorphous structure.

7. The semiconductor device according to claim 6, characterized in that The metal oxide semiconductor material includes indium oxide.

8. The semiconductor device according to any one of claims 1 to 7, characterized in that The mobility of the active layer increases with the increase of the carrier concentration in the active layer.

9. The semiconductor device according to claim 8, characterized in that The carrier concentration in the active layer is greater than or equal to 10 19 cm -3 and less than 10 20 cm -3 .

10. The semiconductor device according to claim 8, characterized in that The bandgap width of the active layer is greater than or equal to 3.0 eV and less than or equal to 3.8 eV.

11. A display panel, characterized in that: A semiconductor device comprising the semiconductor device as claimed in any one of claims 1 to 10.

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