Semiconductor device

Abstract

The purpose of the present invention is to improve the short-circuit tolerance of a semiconductor device having a carrier storage layer. This semiconductor device is provided with: an emitter layer (4) and a contact layer (11) provided on a surface layer section of a base layer (3); a carrier storage layer (2) provided between the base layer (3) and the drift layer (1); and a trench in which the gate electrode (5b) is embedded and which reaches a position deeper than the carrier storage layer (2). The contact layer (11) is deeper than the emitter layer (4). The impurity concentration of the carrier storage layer (2) is 1.4 E16 / cm3 or less at least in a portion adjacent to the trench.

Description

Technical Field

[0001] The present invention relates to semiconductor devices. Background Art

[0002] For example, in order to reduce inverter losses, the conduction loss and switching loss of IGBT (Insulated Gate Bipolar Transistor) are sought to be reduced. Since current flows through the IGBT in the vertical direction, it is effective to reduce the resistance of the drift layer that maintains the withstand voltage, and research has been conducted on optimizing the cell structure so that carriers can be easily accumulated when conducting. As a result, for example, the following patent document 1 proposes an IGBT that connects a P-type base layer to an N-type base layer. - An N-type layer with a higher impurity concentration than the drift layer is provided between the N-type drift layers to enhance the carrier accumulation effect. This N-type layer is called a carrier accumulation layer (CS layer).

[0003] Patent Document 1: Japanese Patent Application Publication No. 2020-107707

[0004] When a carrier accumulation layer is provided in the IGBT as described in Patent Document 1, the effect of reducing the collector-emitter saturation voltage Vce(sat) can be obtained, but on the other hand, the problem of reduced short-circuit tolerance arises. Short-circuit tolerance is the length of time from when a load is short-circuited until the power device is destroyed, and is one of the electrical characteristics required of the IGBT. Even when the load is in a short-circuit state due to a malfunction, for example, a large current flows through the IGBT, and the gate voltage rises due to the displacement current, it is required to withstand several microseconds without being destroyed. Summary of the invention

[0005] The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to improve the short-circuit resistance of a semiconductor device having a carrier accumulation layer.

[0006] The semiconductor device of the present invention comprises: a semiconductor substrate having a first conductive type drift layer formed thereon; a second conductive type base layer provided on a surface portion of a first main surface side of the semiconductor substrate; a first conductive type emitter layer selectively provided on a surface portion of the base layer, having an impurity concentration higher than that of the drift layer; a second conductive type contact layer selectively provided on a surface portion of the base layer, having an impurity concentration higher than that of the base layer; a first conductive type carrier storage layer provided between the base layer and the drift layer, having an impurity concentration higher than that of the drift layer; The drift layer is high; a groove is arranged on the first main surface side of the semiconductor substrate and reaches a position deeper than the carrier storage layer; a gate insulating film is arranged on the inner surface of the groove; a gate electrode is arranged on the gate insulating film and buried in the groove; and a collector layer of the second conductivity type is arranged on the surface portion of the second main surface side of the semiconductor substrate, the depth of the contact layer is deeper than the emitter layer, and the impurity concentration of the carrier storage layer is less than or equal to 1.4E16 / cm at least in the portion adjacent to the groove. 3 .

[0007] Effects of the Invention

[0008] According to the present invention, the short-circuit resistance of a semiconductor device having a carrier accumulation layer is improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 It is a top view of the semiconductor device according to the first embodiment.

[0010] Figure 2 This is a cross-sectional view of the IGBT according to the first embodiment.

[0011] Figure 3 This is a diagram showing the relationship between the impurity concentration of the carrier storage layer and the collector-emitter saturation voltage.

[0012] Figure 4 This is a diagram showing the relationship between the impurity concentration of the carrier accumulation layer and the gate voltage immediately before the destruction of the IGBT in the short-circuit state.

[0013] Figure 5 This is a manufacturing process diagram of the IGBT according to the first embodiment.

[0014] Figure 6 This is a manufacturing process diagram of the IGBT according to the first embodiment.

[0015] Figure 7 This is a manufacturing process diagram of the IGBT according to the first embodiment.

[0016] Figure 8 This is a manufacturing process diagram of the IGBT according to the first embodiment.

[0017] Fig. 9 This is a manufacturing process diagram of the IGBT according to the first embodiment.

[0018] Fig.10 This is a manufacturing process diagram of the IGBT according to the first embodiment.

[0019] Fig.11 This is a manufacturing process diagram of the IGBT according to the first embodiment.

[0020] Fig.12 This is a manufacturing process diagram of the IGBT according to the first embodiment.

[0021] Fig.13 This is a manufacturing process diagram of the IGBT according to the first embodiment.

[0022] Fig.14 This is a manufacturing process diagram of the IGBT according to the first embodiment.

[0023] Fig.15 This is a manufacturing process diagram of the IGBT according to the first embodiment.

[0024] Fig.16 It is a cross-sectional view of an RC-IGBT according to a modification of the first embodiment.

[0025] Fig.17 It is a cross-sectional view of an RC-IGBT according to a modification of the first embodiment.

[0026] Fig.18 It is a cross-sectional view of an IGBT according to a modification of the first embodiment.

[0027] Fig.19 It is a cross-sectional view of an IGBT according to the second embodiment.

[0028] Fig. 20 It is a cross-sectional view of an RC-IGBT according to a modification of the second embodiment.

[0029] Fig.21 It is a cross-sectional view of an IGBT according to the third embodiment.

[0030] Fig. 22 It is a cross-sectional view of an RC-IGBT according to a modification of the third embodiment. DETAILED DESCRIPTION

[0031] In the following embodiments, the first conductivity type is set to N type and the second conductivity type is set to P type. However, the first conductivity type may be set to P type and the second conductivity type may be set to N type. In addition, N type with relatively high impurity concentration is referred to as “N +", the N-type with relatively low impurity concentration is recorded as "N - ", the P type with relatively high impurity concentration is recorded as "P + ", the P type with relatively low impurity concentration is recorded as "P - "Here, the level of impurity concentration in each region is determined by the peak concentration. That is, a region with a high (or low) impurity concentration refers to a region with a high (or low) peak impurity concentration.

[0032] <Implementation Method 1>

[0033] Figure 1 It is a top view of the semiconductor device according to Embodiment 1. In Embodiment 1, the semiconductor device includes a trench gate IGBT as a semiconductor element.

[0034] like Figure 1 As shown, the semiconductor device according to the first embodiment includes: a cell region 31 in which the cell of the IGBT is arranged; a gate pad region 32 in which the gate pad of the IGBT is arranged; a gate wiring region 33 in which the gate wiring connecting the gate electrode of the IGBT to the gate pad is arranged; and a terminal region 34 provided outside the cell region 31, the gate pad region 32, and the gate wiring region 33. The emitter pad of the IGBT is arranged on the cell region 31. A withstand voltage holding structure such as FLR (Field Limiting Ring) and VLD (Variation of Lateral Doping) is appropriately provided in the terminal region 34 according to the withstand voltage design required for the semiconductor device.

[0035] Figure 2 is a cross-sectional view showing the structure of the IGBT according to the first embodiment. Figure 2 yes Figure 1 A cross-sectional view of a portion of the cell region 31 is shown.

[0036] like Figure 2 As shown in FIG. 1 , the IGBT according to the first embodiment is formed using a semiconductor substrate 40 on which an N-type drift layer 1 is formed. Next, the surface ( Figure 2 The upper surface of the semiconductor substrate 40 is referred to as the "first main surface", and the back surface of the semiconductor substrate 40 ( Figure 2 The lower surface of the substrate is called the “second main surface”.

[0037] A P-type base layer 3 is provided on the surface layer portion of the first main surface side of the semiconductor substrate 40. N-type base layers 3 having an impurity concentration higher than that of the drift layer 1 are selectively provided on the surface layer portion of the base layer 3. + The emitter layer 4 of the type and the P +An N-type contact layer 11 is provided below the base layer 3 , that is, between the base layer 3 and the drift layer 1 .

[0038] A groove is formed on the first main surface of the semiconductor substrate 40, and the groove penetrates the emitter layer 4, the base layer 3, and the carrier storage layer 2 to reach the drift layer 1. That is, the groove reaches a position deeper than the carrier storage layer 2. A gate insulating film 5a is formed on the inner surface of the groove. In addition, a gate electrode 5b is formed on the gate insulating film 5a so as to be buried in the groove. The groove is formed deeper than the carrier storage layer 2, thereby stabilizing the withstand voltage between the collector and the emitter.

[0039] An interlayer insulating film 6 is provided on the first main surface of the semiconductor substrate 40 so as to cover the gate electrode 5b, and an emitter electrode 7 is provided on the interlayer insulating film 6. A contact hole reaching the emitter layer 4 and the contact layer 11 is formed in the interlayer insulating film 6, and the emitter electrode 7 is connected to the emitter layer 4 and the contact layer 11 through the contact hole.

[0040] An N-type buffer layer 8 (hereinafter referred to as "phosphorus buffer layer 8") in which phosphorus is injected as an impurity is provided on the surface portion of the second main surface side of the semiconductor substrate 40, and a P-type collector layer 9 is provided on the surface portion of the phosphorus buffer layer 8. That is, the phosphorus buffer layer 8 is provided between the drift layer 1 and the collector layer 9. In addition, a collector electrode 10 connected to the collector layer 9 is provided on the second main surface of the semiconductor substrate 40.

[0041] The peak concentration of impurities in the base layer 3 is set to about 8.0E16 / cm 3 ~5.0E17 / cm 3 , so that the gate threshold voltage Vth when current starts to flow from the collector to the emitter is about 6V.

[0042] Figure 3 This is a graph showing the relationship between the impurity concentration of the carrier storage layer 2 and the collector-emitter saturation voltage Vce(sat) of the IGBT. If the impurity concentration of the carrier storage layer 2 is increased, a potential barrier is formed between the drift layer 1 and the carrier storage layer 2, and the accumulation effect of holes from the second main surface of the semiconductor substrate 40 is improved, so that the resistance of the drift layer 1 is reduced. Therefore, if Figure 3 As shown, Vce(sat) can be reduced by increasing the concentration of the carrier accumulation layer 2. However, if the concentration of the carrier accumulation layer 2 is simply increased, the channel length becomes shorter, so the current flowing during a short circuit becomes larger, and the short circuit tolerance may be reduced.

[0043] Figure 4: is a graph showing the relationship between the impurity concentration of the carrier accumulation layer 2 and the gate voltage Vge when the IGBT in the short-circuit state is about to be destroyed (hereinafter referred to as "gate voltage when about to be destroyed"). Figure 4 The data used here are actual values ​​obtained by increasing the gate voltage while keeping the time constant when the IGBT is short-circuited. A high gate voltage just before destruction means a high short-circuit withstand capability.

[0044] from Figure 4 It can also be seen that if the impurity concentration of the carrier storage layer 2 is increased, the short-circuit resistance decreases. However, it can be seen that as long as the impurity concentration of the carrier storage layer 2 is less than or equal to 1.4E16 / cm 3 , it is possible to have a short-circuit withstand capability equal to or higher than that of an IGBT without a carrier storage layer 2 (i.e., when the impurity concentration of the carrier storage layer 2 is 0). Here, in this embodiment, the impurity concentration of the carrier storage layer 2 is set to be less than or equal to 1.4E16 / cm in at least the portion adjacent to the trench, i.e., the portion directly below the channel region where the channel is formed. 3 .

[0045] Here, the impurity concentration in the carrier storage layer 2 is less than or equal to 1.4E16 / cm 3 The diffusion potential V at the PN junction between the carrier storage layer 2 and the base layer 3 is bi It is obtained by the following formula (1).

[0046] [Formula 1]

[0047]

[0048] In formula (1), q is the elementary charge, k is B is the Boltzmann constant, T is the temperature, N A is the acceptor density, N D is the donor density, n i is the intrinsic carrier density. As can be seen from formula (1), if the impurity concentration of the carrier accumulation layer 2 increases, the diffusion potential increases, and even if the temperature inside the semiconductor device rises during a short-circuit operation, it is difficult for the PN junction to disappear, so the short-circuit tolerance is improved. Figure 4 In the curve diagram, the impurity concentration in the carrier accumulation layer 2 is 0.7E16 / cm 3 On the other hand, when the impurity concentration of the carrier storage layer 2 exceeds 0.7E16 / cm 3In the range of , the reduction in short-circuit withstand due to the shortening of the channel length becomes significant, so the gate voltage at the time of destruction tends to decrease as the impurity concentration of the carrier storage layer 2 is increased. However, as long as the impurity concentration of the carrier storage layer 2 is suppressed to less than or equal to 1.4E16 / cm 3 , it is possible to suppress the decrease in short-circuit withstand capability due to the shortening of the channel length, thereby ensuring a short-circuit withstand capability that is equal to or higher than that of an IGBT without the carrier accumulation layer 2.

[0049] In addition, in this embodiment, the contact layer 11 is formed deeper than the emitter layer 4. As a result, the resistance of the hole current path from the second main surface of the semiconductor substrate 40 becomes smaller, and it is expected that the short-circuit resistance will be improved. In addition, the voltage drop is suppressed and the latching action of the parasitic transistor of the IGBT is prevented.

[0050] Here, referring to Figure 5 to Figure 15 The manufacturing method of the IGBT involved in the first embodiment is described while referring to the process diagram.

[0051] First, Figure 5 As shown, an N-type semiconductor substrate 40 is prepared to become the drift layer 1. The resistivity of the semiconductor substrate 40 is usually set to be greater than or equal to 20Ω·cm and less than or equal to 100Ω·cm as a vehicle-mounted product. The material of the semiconductor substrate 40 can be silicon or a wide bandgap semiconductor such as silicon carbide (SiC). Compared with previous semiconductor devices using silicon, semiconductor devices formed using wide bandgap semiconductors have excellent operation under high voltage, large current, and high temperature. As wide bandgap semiconductors, in addition to silicon carbide, there are gallium nitride (GaN)-based materials, diamond, etc.

[0052] Next, a P-type impurity region having a withstand voltage maintaining structure is formed in a region to be the termination region 34 by performing a heat treatment at a high temperature for a long time so as to surround the cell region 31 .

[0053] Then, impurities are implanted into the first main surface of the semiconductor substrate 40 by selective ion implantation using photolithography technology, so that Figure 6 as well as Figure 7 As shown, a carrier storage layer 2 and a base layer 3 are formed on the surface portion of the first main surface side of the semiconductor substrate 40. At this time, in order to form the carrier storage layer 2 at a position deeper than the base layer 3, it is effective to inject phosphorus with a high energy of MeV in the ion implantation for forming the carrier storage layer 2 and perform high-temperature driving after the phosphorus is implanted.

[0054] Next, selective ion implantation of phosphorus and arsenic is performed to Figure 8 As shown, the emitter layer 4 is selectively formed on the surface portion of the base layer 3 .

[0055] Then, a trench penetrating the emitter layer 4, the base layer 3, and the carrier storage layer 2 is formed on the first main surface of the semiconductor substrate 40 by selective dry etching using photolithography. Fig. 9 As shown, a gate insulating film 5 a is formed on the inner surface of the trench by thermal oxidation or CVD, and polysilicon is buried in the trench by CVD to form a gate electrode 5 b.

[0056] Then, by selective ion implantation, such as Fig.10 As shown, the contact layer 11 is selectively formed on the surface of the base layer 3. In order to make the contact layer 11 deeper than the emitter layer 4, it is effective to implant boron at high energy and perform high-temperature heat treatment. Alternatively, the emitter layer 4 may be formed after the trench is formed.

[0057] Next, if Fig.11 As shown, the interlayer insulating film 6 is formed by forming a TEOS oxide film, a BPTEOS oxide film (TEOS oxide film containing B and P as impurities), etc., and a contact hole reaching the emitter layer 4 and the contact layer 11 is formed in the interlayer insulating film 6 by selective etching. In the case of forming the contact hole by dry etching, in order to prevent the interlayer insulating film 6 from remaining at the bottom of the contact hole, the etching time may be set so that the first main surface of the semiconductor substrate 40 is slightly overetched. However, if the overetching becomes excessive, the emitter layer 4 disappears and causes a decrease in the current carrying capacity, so the depth of the overetching of the first main surface of the semiconductor substrate 40 is preferably shallower than the depth of the emitter layer 4. That is, the position of the bottom of the emitter electrode 7 connected to the emitter layer 4 through the contact hole is preferably shallower than the bottom of the emitter layer 4.

[0058] Next, Al, AlSi, AlCu, and Cu metals are formed into films by sputtering and evaporation, so that Fig.12 As shown, an emitter electrode 7 is formed on the interlayer insulating film 6. At this time, the emitter electrode 7 is connected to the emitter layer 4 and the contact layer 11 through a contact hole formed in the interlayer insulating film 6. Furthermore, a protective film composed of a glass coating or polyimide may be formed on the emitter electrode 7 as needed.

[0059] Then, by grinding the second main surface side of the semiconductor substrate 40, Fig.13 The semiconductor substrate 40 is thinned as shown. Then, as Fig.14As shown, by performing ion implantation of impurities on the second main surface of the semiconductor substrate 40, a phosphorus buffer layer 8 and a collector layer 9 are formed on the surface layer of the second main surface side of the semiconductor substrate 40. At this time, in order to form the phosphorus buffer layer 8 at a position deeper than the collector layer 9, the ion implantation for forming the phosphorus buffer layer 8 is performed at a high energy of several hundred keV to several MeV. Then, the impurities implanted into the semiconductor substrate 40 are activated by laser annealing and furnace annealing.

[0060] Finally, a metal film is formed on the second main surface of the semiconductor substrate 40 by sputtering or evaporation, so that Fig.15 The collector electrode 10 is formed as shown. The collector electrode 10 may be a laminated structure composed of a plurality of laminated films such as ASi, Ti, Ni, Au, and Ag in consideration of obtaining a highly ohmic contact with silicon and solder bonding.

[0061] [Modifications]

[0062] In the first embodiment, the semiconductor element formed in the cell region 31 is an IGBT, but the semiconductor device may be an RC-IGBT (Reverse Conducting IGBT) composed of an IGBT and a diode connected in reverse parallel thereto.

[0063] Fig.16 FIG. 4 is a cross-sectional view of an RC-IGBT as a modified example of the first embodiment. Fig.16 As shown in FIG. 1 , the RC-IGBT includes an IGBT region 21 that functions as an IGBT and a diode region 22 that functions as a diode. The structure of the IGBT region 21 is similar to that of the Figure 2 The IGBT shown has the same construction.

[0064] On the other hand, in the diode region 22, a P-type anode layer 12 is formed on the carrier storage layer 2, that is, on the surface of the first main surface side of the semiconductor substrate 40. Furthermore, a P-type anode layer 12 having a higher impurity concentration than the anode layer 12 is formed on the surface of the anode layer 12. + The anode layer 12 and the contact layer 13 are both P-type regions, so they can also be collectively referred to as "anode layers".

[0065] In addition, an N-type cathode layer 14 is formed on the surface layer portion on the second main surface side of the semiconductor substrate 40. In addition, the carrier storage layer 2 does not need to be provided in the diode region 22.

[0066] In diode region 22, emitter electrode 7 is connected to anode layer 12 and contact layer 13 through a contact hole formed in interlayer insulating film 6, and collector electrode 10 is connected to cathode layer 14. Thus, the diode in diode region 22 and the IGBT in IGBT region 21 are connected in antiparallel.

[0067] exist Fig.16 In the RC-IGBT of FIG. 1 , in order to stabilize the breakdown voltage, the same trench as that of the IGBT region 21 is formed in the diode region 22. However, the potential of the electrode formed in the trench of the IGBT region 21 is set to the emitter potential of the IGBT.

[0068] The anode layer 12 of the diode region 22 is formed deeper than the base layer 3 of the IGBT region 21 relative to the first main surface of the semiconductor substrate 40. For an IGBT having a carrier storage layer 2 below the base layer 3, the electric field becomes high at the bottom of the trench during on-off operation and short-circuit operation, generating dynamic avalanche. At this time, if the anode layer 12 is deeper than the base layer 3, it becomes easier for carriers to escape to the diode side, which can prevent carriers from concentrating on the IGBT side and causing element destruction.

[0069] In addition, if Fig.17 As shown, the interlayer insulating film 6 may not be formed in the diode region 22, but the entire upper surface of the diode region 22 may be in contact with the emitter electrode 7. This makes it easier for carriers to escape, which is effective in improving breakdown resistance.

[0070] The impurity concentration of the anode layer 12 may be lower than that of the base layer 3. This can ensure short-circuit resistance and reduce the recovery loss of the diode.

[0071] In addition, if Fig.18 As shown, an N-type buffer layer 15 (hereinafter referred to as "proton buffer layer 15") injected with protons as impurities may be provided between the drift layer 1 and the phosphorus buffer layer 8. This suppresses the supply of holes from the second main surface of the semiconductor substrate 40 during short-circuit operation, makes it easier to produce an imbalance in the concentration of electrons and holes, and suppresses the increase in the electric field on the first main surface side, which is effective in improving short-circuit tolerance. The proton buffer layer 15 can be formed by injecting protons after polishing the second main surface side of the semiconductor substrate 40 and converting the protons into donors by heat treatment at about 400°C.

[0072] Fig.18 Although an example in which the proton buffer layer 15 is provided in the IGBT is shown, the proton buffer layer 15 can also be applied to the RC-IGBT.

[0073] <Implementation Method 2>

[0074] Fig.19 2 is a cross-sectional view showing the structure of an IGBT according to Embodiment 2. Fig.19As shown, in the second embodiment, the carrier storage layer 2 adjacent to the trench is only partially provided near the trench where the gate electrode 5b is buried, that is, directly below the trench region where the trench is formed. The carrier storage layer 2 is not formed in the region other than the trench vicinity. The drift layer 1 or the trench is interposed between adjacent carrier storage layers 2. In order to ensure the short-circuit tolerance of the IGBT, the impurity concentration of the carrier storage layer 2 is set to be less than or equal to 1.4E16 / cm at least in the portion adjacent to the trench. 3 .

[0075] According to the second embodiment, Vce(sat) of the IGBT is increased compared to the first embodiment, but the turn-off loss Eoff is reduced, so that an IGBT suitable for high-speed operation is obtained.

[0076] [Modifications]

[0077] like Fig. 20 As shown, the local carrier accumulation layer 2 shown in the second embodiment can also be applied to RC-IGBT. Fig. 20 In the structure of the IGBT region 21, Fig.19 The structure of the diode region 22 is the same as that of the IGBT. Fig.16 The diode region 22 is the same.

[0078] <Implementation Method 3>

[0079] Fig.21 2 is a cross-sectional view showing the structure of an IGBT according to Embodiment 3. Fig.21 As shown, in Embodiment 3, the carrier storage layer 2 is composed of a first carrier storage layer 2a and a second carrier storage layer 2b, the first carrier storage layer 2a is arranged near the trench in which the gate electrode 5b is buried, that is, just below the channel region, and the second carrier storage layer 2b is arranged in the region between the first carrier storage layers 2a. The impurity concentration of the first carrier storage layer 2a is set to be less than or equal to 1.4E16 / cm 3 , thereby ensuring the short-circuit tolerance of the IGBT. The impurity concentration of the second carrier storage layer 2b is set to a value higher than that of the drift layer 1, thereby reducing the Vce(sat) of the IGBT. The impurity concentration of the second carrier storage layer 2b can be higher or lower than that of the first carrier storage layer 2a.

[0080] [Modifications]

[0081] like Fig. 22 As shown, the carrier storage layer 2 composed of the first carrier storage layer 2a and the second carrier storage layer 2b shown in Embodiment 3 can also be applied to RC-IGBT. Fig. 22 In the structure of the IGBT region 21, Fig.21 The structure of the diode region 22 is the same as that of the IGBT. Fig.16 The diode region 22 is the same.

[0082] In addition, each embodiment can be freely combined, and each embodiment can be appropriately modified or omitted.

[0083] <Appendix>

[0084] Hereinafter, various aspects of the present invention are summarized as appendices.

[0085] (Appendix 1)

[0086] A semiconductor device comprising:

[0087] A semiconductor substrate having a first conductivity type drift layer formed thereon;

[0088] a second conductive type base layer provided on a surface portion of the semiconductor substrate on the first main surface side;

[0089] an emitter layer of the first conductivity type, which is selectively provided on the surface portion of the base layer and has a higher impurity concentration than the drift layer;

[0090] a second conductive type contact layer, which is selectively provided on the surface portion of the base layer and has a higher impurity concentration than the base layer;

[0091] a first conductive type carrier storage layer disposed between the base layer and the drift layer and having a higher impurity concentration than the drift layer;

[0092] a groove provided on the first main surface side of the semiconductor substrate and reaching a position deeper than the carrier accumulation layer;

[0093] a gate insulating film disposed on an inner surface of the trench;

[0094] a gate electrode disposed on the gate insulating film and embedded in the trench; and

[0095] a collector layer of a second conductivity type provided on a surface portion of the semiconductor substrate on the second main surface side,

[0096] The contact layer is deeper than the emitter layer,

[0097] The impurity concentration of the carrier accumulation layer is less than or equal to 1.4E16 / cm at least in the portion adjacent to the trench. 3 .

[0098] (Appendix 2)

[0099] The semiconductor device according to Appendix 1, wherein:

[0100] The carrier accumulation layer is locally formed near the trench.

[0101] (Appendix 3)

[0102] The semiconductor device according to Appendix 1, wherein:

[0103] The carrier accumulation layer comprises:

[0104] The first carrier accumulation layer is arranged near the groove and has an impurity concentration less than or equal to 1.4E16 / cm 3 ;as well as

[0105] The second carrier storage layer is disposed between the first carrier storage layers and has an impurity concentration higher than that of the drift layer.

[0106] (Appendix 4)

[0107] A semiconductor device according to any one of Appendix 1 to Appendix 3, wherein:

[0108] The position of the bottom of the emitter electrode connected to the emitter layer is shallower than the bottom of the emitter layer.

[0109] (Appendix 5)

[0110] A semiconductor device according to any one of Appendix 1 to Appendix 4, wherein:

[0111] It also has a diode region that functions as a diode.

[0112] The diode region has:

[0113] the drift layer;

[0114] an anode layer of a second conductivity type provided on a surface portion of the semiconductor substrate on the first main surface side; and

[0115] a first conductive type cathode layer provided on a surface layer portion of the semiconductor substrate on the second main surface side,

[0116] The anode layer is formed deeper than the base layer with respect to the first main surface of the semiconductor substrate.

[0117] (Appendix 6)

[0118] A semiconductor device according to any one of Appendix 1 to Appendix 4, wherein:

[0119] It also has a diode region that functions as a diode.

[0120] The diode region has:

[0121] the drift layer;

[0122] an anode layer of a second conductivity type provided on a surface portion of the semiconductor substrate on the first main surface side; and

[0123] a first conductive type cathode layer provided on a surface layer portion of the semiconductor substrate on the second main surface side,

[0124] The anode layer has a lower impurity concentration than the base layer.

[0125] (Appendix 7)

[0126] A semiconductor device according to any one of Appendix 1 to Appendix 6, wherein:

[0127] A first conductivity type buffer layer into which protons are implanted as impurities is provided between the drift layer and the collector layer.

[0128] (Appendix 8)

[0129] A semiconductor device according to any one of Appendix 1 to Appendix 7, wherein:

[0130] The resistivity of the drift layer is greater than or equal to 20 Ω·cm and less than or equal to 100 Ω·cm.

[0131] Description of the label

[0132] 1 drift layer, 2 carrier storage layer, 2a first carrier storage layer, 2b second carrier storage layer, 3 base layer, 4 emitter layer, 5a gate insulating film, 5b gate electrode, 6 interlayer insulating film, 7 emitter electrode, 8 phosphorus buffer layer, 9 collector layer, 10 collector electrode, 11 contact layer, 12 anode layer, 13 contact layer, 14 cathode layer, 15 proton buffer layer, 21 IGBT region, 22 diode region, 31 cell region, 32 gate pad region, 33 gate wiring region, 34 terminal region, 40 semiconductor substrate.

Claims

1. A semiconductor device comprising: A semiconductor substrate having a first conductivity type drift layer formed thereon; a second conductive type base layer provided on a surface portion of the semiconductor substrate on the first main surface side; an emitter layer of the first conductivity type, which is selectively provided on the surface portion of the base layer and has a higher impurity concentration than the drift layer; a second conductive type contact layer, which is selectively provided on the surface portion of the base layer and has a higher impurity concentration than the base layer; a first conductive type carrier storage layer disposed between the base layer and the drift layer and having a higher impurity concentration than the drift layer; a groove provided on the first main surface side of the semiconductor substrate and reaching a position deeper than the carrier accumulation layer; a gate insulating film disposed on an inner surface of the trench; A gate electrode, which is disposed on the gate insulating film and buried in the trench; as well as a collector layer of a second conductivity type provided on a surface portion of the semiconductor substrate on the second main surface side, The contact layer is deeper than the emitter layer, The impurity concentration of the carrier accumulation layer is less than or equal to 1.4E16 / cm at least in the portion adjacent to the trench. 3 .

2. The semiconductor device according to claim 1, wherein The carrier accumulation layer is locally formed near the trench.

3. The semiconductor device according to claim 1, wherein The carrier accumulation layer comprises: The first carrier accumulation layer is arranged near the groove and has an impurity concentration less than or equal to 1.4E16 / cm 3 ; as well as The second carrier storage layer is disposed between the first carrier storage layers and has an impurity concentration higher than that of the drift layer.

4. The semiconductor device according to any one of claims 1 to 3, wherein: The position of the bottom of the emitter electrode connected to the emitter layer is shallower than the bottom of the emitter layer.

5. The semiconductor device according to any one of claims 1 to 4, wherein: It also has a diode region that functions as a diode. The diode region has: the drift layer; a second conductivity type anode layer provided on a surface portion of the semiconductor substrate on the first main surface side; as well as a first conductive type cathode layer provided on a surface layer portion of the semiconductor substrate on the second main surface side, The anode layer is formed deeper than the base layer with respect to the first main surface of the semiconductor substrate.

6. The semiconductor device according to any one of claims 1 to 4, wherein: It also has a diode region that functions as a diode. The diode region has: the drift layer; a second conductivity type anode layer provided on a surface portion of the semiconductor substrate on the first main surface side; as well as a first conductive type cathode layer provided on a surface layer portion of the semiconductor substrate on the second main surface side, The anode layer has a lower impurity concentration than the base layer.

7. The semiconductor device according to any one of claims 1 to 6, wherein: A first conductivity type buffer layer into which protons are implanted as impurities is provided between the drift layer and the collector layer.

8. The semiconductor device according to any one of claims 1 to 7, wherein: The resistivity of the drift layer is greater than or equal to 20 Ω·cm and less than or equal to 100 Ω·cm.

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