Semiconductor device and manufacturing method thereof

Abstract

The invention provides a semiconductor device and a manufacturing method thereof, before a high-voltage gate oxide layer is formed, a top central area of a device isolation structure is etched to form a first groove, a patterned barrier layer is formed to cover the inner surface of the first groove, and in the process of forming the high-voltage gate oxide layer through thermal oxidation, the patterned barrier layer is formed to cover the inner surface of the first groove. The barrier layer on the side wall of the first groove is equivalent to additional two barrier layers in the transverse direction, so that transverse diffusion of O2 in the growth process of the high-voltage gate oxide layer can be better blocked, the beak problem is solved, and a series of adverse problems caused by the beak can be avoided. The method can be compatible with the current high-voltage gate oxide manufacturing process, does not need to add a special manufacturing process, does not need to implant other unnecessary ions, is simple and effective, does not challenge the process limit of the high-voltage gate oxide manufacturing process, and is safer and more reliable. Furthermore, the tail end of one side of the grid electrode extends into the first groove, so that process windows of a grid electrode metal silicide and a grid electrode contact hole can be increased.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit manufacturing, and in particular to a semiconductor device and a manufacturing method thereof. Background Art

[0002] With the continuous miniaturization of semiconductor components and the requirements of specific application scenarios, current product designs often require high-voltage devices and non-high-voltage devices (such as low-voltage devices and standard-voltage devices) to be designed on the same substrate. High-voltage devices are devices that can withstand higher voltages while ensuring that the gate is not broken down under high-voltage operation. Generally, the thickness of the high-voltage gate oxide layer of high-voltage devices is two orders of magnitude higher than the gate oxide layer thickness of 1.1 / 2.5V non-high-voltage devices, usually in In devices of smaller size, in order to achieve higher isolation requirements, shallow trench isolation (STI) structures are often located on both sides of the high-voltage gate oxide layer in the structure of high-voltage devices. Since the thickness of the high-voltage gate oxide layer is thick and the process time is long, in the process of forming the high-voltage gate oxide layer by thermal oxidation, it is inevitable that oxygen molecules will diffuse laterally through the STI on both sides of the high-voltage gate oxide layer during the thermal oxidation process, and form a bird's beak structure in the active area where the STI is far away from both sides of the high-voltage gate oxide layer. Summary of the invention

[0003] The object of the present invention is to provide a semiconductor device and a manufacturing method thereof, which can improve the bird's beak problem in the process of forming a high-voltage gate oxide layer.

[0004] To achieve the above object, the present invention provides a method for manufacturing a semiconductor device, which comprises the following steps:

[0005] providing a substrate, forming a device isolation structure in the substrate, the device isolation structure defining a high voltage region in the substrate;

[0006] Etching a top central area of ​​the device isolation structure to form a first groove;

[0007] forming a patterned barrier layer, wherein the patterned barrier layer exposes the base of the high-voltage region and masks the remaining region including the inner surface of the first groove;

[0008] Under the mask of the patterned barrier layer, a high-voltage gate oxide layer is formed on the surface of the substrate in the high-voltage region by thermal oxidation, and the bottom of the high-voltage gate oxide layer is higher than the bottom of the first groove.

[0009] Optionally, the step of forming a device isolation structure in the substrate includes:

[0010] forming a pad oxide layer and a hard mask layer on the surface of the substrate, and etching the hard mask layer by photolithography and etching processes to form a patterned hard mask layer;

[0011] Using the patterned hard mask layer as a mask, etching the pad oxide layer and the substrate to form a shallow trench in the substrate;

[0012] Depositing an insulating dielectric material to fill the shallow trench;

[0013] The top of the insulating dielectric material is planarized to the top surface of the patterned hard mask layer, and the patterned hard mask layer is removed to form the device isolation structure with a top higher than the top of the substrate.

[0014] Optionally, the step of forming the patterned barrier layer comprises:

[0015] Depositing a barrier layer on the surface of the device isolation structure and the substrate, wherein the barrier layer also covers the inner surface of the first groove;

[0016] The barrier layer on the high-voltage region is removed by photolithography and etching processes, and at the same time, the top of one side of the device isolation structure adjacent to the high-voltage region is etched open to form the patterned barrier layer, and a second groove exposing the top side wall of the substrate of the high-voltage region is formed at the top of one side of the device isolation structure adjacent to the high-voltage region, and the second groove is shallower than the first groove.

[0017] Optionally, before or after forming the device isolation structure in the substrate, a pad oxide layer is also formed on the substrate; after removing the barrier layer on the high-voltage area by photolithography and etching processes, the pad oxide layer on the substrate surface of the high-voltage area is also wet-etched to expose the substrate surface of the high-voltage area.

[0018] Optionally, the patterned barrier layer further exposes the top of one side of the device isolation structure adjacent to the high voltage region, and after forming the patterned barrier layer and before forming a high voltage gate oxide layer on the substrate surface of the high voltage region by thermal oxidation, the method further includes:

[0019] Under the mask of the patterned barrier layer, a portion of the substrate in the high-voltage region is consumed by thermal oxidation to form a sacrificial oxide layer;

[0020] The sacrificial oxide layer is removed by wet etching, and at the same time, the top side of the device isolation structure close to the high voltage region is etched open to lower the top of the substrate in the high voltage region, and at the same time, a second groove is formed on the top side of the device isolation structure close to the high voltage region to expose the top side wall of the substrate in the high voltage region, and the bottom of the second groove is shallower than the bottom of the first groove.

[0021] Optionally, the manufacturing method has at least one of the following limiting conditions (1) to (3): (1) the width of the first groove accounts for 40% to 70% of the width of the device isolation structure in which it is located; (2) the width of the second groove is at least 10% to 20% greater than the width of the device isolation structure in which it is located; (3) the first groove is located in the left and right center of the device isolation structure, and the depth of the first groove in the device isolation structure accounts for less than 20% to 30% of the total depth of the device isolation structure in which it is located.

[0022] Optionally, the manufacturing method, after forming the high-voltage gate oxide layer, further comprises:

[0023] removing the patterned barrier layer;

[0024] Polysilicon is deposited and excess polysilicon is removed by etching to form a gate that at least covers the high-voltage gate oxide layer.

[0025] Optionally, one end of the gate is formed in the first groove.

[0026] Based on the same inventive concept, the present invention also provides a semiconductor device, comprising:

[0027] substrate;

[0028] a device isolation structure formed in the substrate and defining a high voltage region in the substrate, wherein a first groove is formed in a top central region of the device isolation structure;

[0029] A high-voltage gate oxide layer is formed on the surface of the substrate in the high-voltage region, and the bottom of the high-voltage gate oxide layer is higher than the bottom of the first groove.

[0030] Optionally, a second groove is formed on the top of one side of the device isolation structure adjacent to the high voltage region, the second groove exposes the side wall of the high voltage gate oxide layer, and the second groove is shallower than the first groove.

[0031] Optionally, the semiconductor device has at least one of the following restrictions (1) to (3): (1) the width of the first groove accounts for 40% to 70% of the width of the device isolation structure in which it is located; (2) the width of the second groove is at least 10% to 20% greater than the width of the device isolation structure in which it is located; (3) the first groove is located in the left and right center of the device isolation structure, and the depth of the first groove in the device isolation structure accounts for less than 20% to 30% of the total depth of the device isolation structure in which it is located.

[0032] Optionally, the semiconductor device further comprises a gate, the gate covers the high-voltage gate oxide layer and one end of the gate is formed in the first groove.

[0033] Compared with the prior art, the technical solution of the present invention has at least one of the following beneficial effects:

[0034] 1. Before forming the high-voltage gate oxide layer, the top central area of ​​the device isolation structure is first etched to form a first groove, and a patterned barrier layer is further formed to cover the inner surface of the first groove. In the process of forming the high-voltage gate oxide layer by thermal oxidation, two barrier layers are added in the lateral direction, so that the lateral diffusion of O2 in the growth process of the high-voltage gate oxide layer can be better blocked, and the bird's beak problem can be improved, thereby avoiding a series of problems such as the inability to form metal silicide on the active area due to the bird's beak, the inability to connect the contact hole CT (not shown) formed on the active area to the metal silicide, the high resistance state of the formed contact hole CT and the high RC delay, the high power consumption of the high-voltage device and even the inability to work normally.

[0035] 2. It is compatible with the current high-voltage gate oxide process, without adding any special process and without the need to implant other unnecessary ions. It is simple and effective, will not challenge the process limits of the high-voltage gate oxide process, and is safer and more reliable.

[0036] 3. One end of the gate extends into the first groove, which can increase the process window of the gate metal silicide salicide and the gate contact hole, and the gate end formed in the first groove is relatively flat, which is conducive to the growth of metal silicide on the gate in this area, and further facilitates the connection between the contact plug on the gate and the metal silicide. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Those skilled in the art will appreciate that the accompanying drawings are provided for a better understanding of the present invention and do not constitute any limitation on the scope of the present invention.

[0038] Figure 1 It is a schematic diagram of the cross-sectional structure of a bird's beak problem in an existing high-voltage device.

[0039] Figure 2 The present invention is a flowchart of a method for manufacturing a semiconductor device according to a specific embodiment of the present invention.

[0040] Figure 3 It is a schematic diagram of the cross-sectional structure of a device in a method for manufacturing a semiconductor device according to a specific embodiment of the present invention. DETAILED DESCRIPTION

[0041] In the following description, a large number of specific details are given in order to provide a more thorough understanding of the present invention. However, it is obvious to those skilled in the art that the present invention can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present invention, some technical features known in the art are not described. It should be understood that the present invention can be implemented in different forms and should not be interpreted as being limited to the embodiments proposed here. On the contrary, providing these embodiments will make the disclosure thorough and complete, and the scope of the present invention will be fully conveyed to those skilled in the art. The same reference numerals represent the same elements from beginning to end. It should be understood that when an element is referred to as "connected to", "coupled" other elements, it can be directly connected to other elements, or there can be intervening elements. On the contrary, when an element is referred to as "directly connected to" other elements, there is no intervening element. When used here, the singular forms of "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates another way. It should also be understood that the term "comprising" is used to identify the presence of features, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, steps, operations, elements, components and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0042] The inventor of this application has found that Figure 1 In the process of forming the high voltage gate oxide layer HVGOX by thermal oxidation in the furnace tube, in addition to the vertical growth of the gate oxide layer GOX, there will also be lateral diffusion of O2, which will lead to bird's beak (such as Figure 1The presence of bird's beaks can easily lead to the following problems: (1) the silicon oxide on the surface of the active area AA used as the source and drain area of ​​the high-voltage device is abnormally thick, affecting the implementation of subsequent processes; (2) when the lateral length of these bird's beaks is long, it is easy for them to pass through the top surface of the adjacent active area from one side of an STI structure and connect with another STI structure, thereby preventing the subsequent formation of metal silicide (not shown) on the active area; (3) even if the bird's beaks formed on the top surfaces of the active areas between adjacent STIs do not form a connection, they may invade the active area if the bird's beaks are too large. The area of ​​the active area where salicide should be formed is occupied, resulting in the inability to form a salicide with normal morphology on the active area; (4) the subsequent amount of etching solution such as HF acid needs to be increased to wet remove the bird's beak; (5) due to the presence of the bird's beak on the active area, the contact hole CT (not shown) subsequently formed on the active area cannot be connected to the metal silicide (for example, when the window for wet removal of the bird's beak is insufficient); (6) due to the presence of the bird's beak on the active area, the metal silicide is insufficiently formed, which in turn causes the formed contact hole CT to be in a high resistance state and a high RC delay, resulting in high power consumption of the high-voltage device and even failure to work normally.

[0043] Therefore, it is urgent to improve or reduce the bird's beak problem of high-voltage devices.

[0044] At present, in order to solve the above problems, the growth rate of the high-voltage gate oxide layer HVGOX is generally adjusted by adjusting the furnace thermal oxidation process parameters (such as increasing the process temperature), or by implanting other ions to change the surface structure of the substrate SUB to adjust the growth rate of the high-voltage gate oxide layer HVGOX and the bird's beak. These methods have the following disadvantages: first, they will challenge the furnace process limit and change the morphology (thermal profile) of the high-voltage gate oxide layer HVGOX; second, increasing ion implantation will have a negative effect on device performance.

[0045] Based on this, the present invention provides a semiconductor device and a manufacturing method thereof, wherein a first groove is etched in the top center of a formed device isolation structure, and the coverage position of the barrier layer is improved through the first groove, thereby increasing the device isolation structure's barrier capability to the lateral diffusion of O2, improving the bird's beak problem, and avoiding other adverse problems caused by the bird's beak.

[0046] The technical solution proposed by the present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer according to the following description. It should be noted that the accompanying drawings are all in a very simplified form and are not in precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0047] Please refer to Figure 2An embodiment of the present invention provides a method for manufacturing a semiconductor device, which comprises the following steps:

[0048] S1, providing a substrate, forming a device isolation structure in the substrate, wherein the device isolation structure defines a high voltage region in the substrate;

[0049] S2, etching a top central area of ​​the device isolation structure to form a first groove;

[0050] S3, forming a patterned barrier layer, wherein the patterned barrier layer exposes the base of the high-voltage region and masks the remaining region including the inner surface of the first groove;

[0051] S4, under the mask of the patterned barrier layer, forming a high-voltage gate oxide layer on the surface of the substrate in the high-voltage region by thermal oxidation, and the bottom of the high-voltage gate oxide layer is higher than the bottom of the first groove.

[0052] In step S1, refer to Figure 3 In (A), first, the provided substrate 100 can be any suitable semiconductor substrate material, such as pure silicon, silicon germanium (SiGe), silicon carbide (SiC) or silicon on insulator (SOI), etc.; then, a device isolation structure 101 is formed in the substrate 100, and the device isolation structure can be a shallow trench isolation structure STI or a local field oxygen isolation structure.

[0053] Optionally, a plurality of device isolation structures 101 are formed in the substrate 100 to define corresponding device active regions, including a high voltage region AA1 of a high voltage gate oxide layer to be formed into a high voltage device and an active region AA2 other than the high voltage region AA1, wherein the active region AA2 includes an active region of a source and drain region to be formed into a high voltage device. In addition, the line width of the device isolation structure 101 where the first groove needs to be formed later is greater than that of other device isolation structures 101 to ensure a process window for manufacturing the first groove.

[0054] Please refer to Figure 3 In (A), taking a shallow trench isolation structure as an example, the specific steps of forming a device isolation structure 101 in the substrate 100 include:

[0055] (1) A pad oxide layer (PAD OX) 102 is formed on the substrate 100 by any suitable process such as thermal oxidation, atomic layer deposition or plasma enhanced chemical vapor deposition, and a hard mask layer such as silicon nitride is further deposited on the pad oxide layer by chemical vapor deposition, and the hard mask layer is etched by photolithography and etching processes to form a patterned hard mask layer (not shown) for defining a shallow trench formation area. The pad oxide layer 102 can serve as a stress buffer layer when depositing the hard mask layer and the subsequent barrier layer, and can also serve as a stop layer in the subsequent process of removing the hard mask layer and the barrier layer.

[0056] (2) Using the patterned hard mask layer as a mask, the pad oxide layer 102 and the substrate 100 are etched to form a shallow trench (not shown) in the substrate 100 .

[0057] (3) A linear oxide layer (not shown) is formed on the inner surface of the shallow trench by thermal oxidation, atomic layer deposition or plasma enhanced chemical vapor deposition, and an insulating dielectric material (not shown) is further deposited by a chemical vapor deposition process to fill the shallow trench.

[0058] (4) The top of the insulating dielectric material is flattened to the top surface of the patterned hard mask layer through a chemical mechanical polishing process, thereby removing excess insulating dielectric material, thereby forming a shallow trench isolation structure STI filled in the shallow trench and serving as a device isolation structure 101, and defining a high-voltage area AA (i.e., an active area of ​​the high-voltage device) in the substrate 100.

[0059] (5) The patterned hard mask layer is removed by a wet etching process, so that the top of the formed device isolation structure 101 is higher than the top of the substrate. At this time, the top of the device isolation structure 101 is flat. As an example, the top surface of the device isolation structure 101 is about 1 / 3 of a inch higher than the top surface of the substrate 100. The thickness of the liner oxide layer 102 covering the top surface of the substrate 100 such as the high voltage area is

[0060] Optionally, before etching the substrate 100 to form a shallow trench for manufacturing the device isolation structure 101, or after forming the device isolation structure 101, P-type ions such as boron are implanted into the substrate 100 to form a P-well region (not shown), or N-type ions such as arsenic or phosphorus are implanted to form an N-well region (not shown).

[0061] In step S2, first, refer to Figure 3In (A), a photoresist is coated on the top of the pad oxide layer 102 and the device isolation structure 101, and a photolithography process such as exposure and development is performed to form a patterned photoresist layer 103, and the patterned photoresist layer 103 defines a central area of ​​the top of the device isolation structure 101 adjacent to the high-voltage area AA1 where the first groove is to be formed; then, please refer to Figure 3 In (B), the patterned photoresist layer 103 is used as a mask to etch the central area of ​​the top of the device isolation structure 101 adjacent to the high voltage area AA1 to form a first groove 101a whose bottom surface is lower than the top surface of the substrate 100.

[0062] Optionally, the first groove 101a is located at the left and right center of the device isolation structure 101 adjacent to the high voltage area AA1, and the depth of the first groove 101a in the device isolation structure 101 adjacent to the high voltage area AA1 accounts for less than 20% to 30% of the total depth (i.e., the total thickness in the longitudinal direction) of the device isolation structure 101. Thus, the first groove is centrally arranged and has a shallow depth, which is used to ensure that after a barrier layer is subsequently formed in the device isolation structure 101, the device isolation structure 101 with the first groove 101a can still provide an effective isolation effect, and the addition of the barrier layer and the groove will not generate unexpected stress on the active area below and around the device isolation structure 101, thereby not having a negative effect on the mobility of carriers in the active area.

[0063] As an example, the thickness of the central area of ​​the top of the device isolation structure 101 adjacent to the high-voltage region AA1 that is etched away is That is, the depth of the first groove 101 is

[0064]

[0065] Afterwards, please refer to Figure 3 In (C), the patterned photoresist layer 103 is removed by dry stripping or wet stripping. In step S3, please refer to Figure 3 In (E) and (F), any suitable process steps may be used to form a patterned barrier layer 104a, wherein the patterned barrier layer 104a exposes the substrate 100 in the high-voltage region and masks the remaining region including the inner surface (including the sidewalls and the bottom surface) of the first groove 101a.

[0066] As an example, the step of forming the patterned barrier layer 104a includes:

[0067] First, please refer to Figure 3In (D), a barrier material such as silicon nitride or silicon oxynitride is deposited on the surface of the liner oxide layer 102 and the device isolation structure 101 (including the inner surface of the first groove 101a and the top surface of the device isolation structure 101 around the top of the first groove 101a) by any suitable process such as furnace tube deposition or chemical vapor deposition to form a barrier layer 104. As an example, the barrier layer 104 is relatively thin and conformally covers the inner surface of the first groove 101a and the surface of other regions. Its deposition will not generate unexpected stress on the substrate active region below and around the device isolation structure 101 having the first groove 101a, and will not have a negative effect on the mobility of carriers in the active region.

[0068] Next, please refer to Figure 3 In (E), a series of photolithography processes such as photoresist coating, exposure and development are performed to form a patterned photoresist layer 105. The patterned photoresist layer 105 defines a region of the barrier layer that needs to be retained in a subsequent high-voltage gate oxide layer formation process.

[0069] Then, the patterned photoresist layer 105 is used as a mask to etch and remove the blocking layer 104 in the area exposed by the patterned photoresist layer 105, thereby forming a patterned blocking layer 104a.

[0070] Afterwards, please refer to Figure 3 In (F), the patterned photoresist layer 105 is removed by a dry stripping process or a wet stripping process.

[0071] Among them, the patterned barrier layer 104a covers the surface of the area that needs to be masked in the subsequent high-voltage gate oxide layer formation process. The surfaces of these areas include the surrounding side walls and the bottom surface of the first groove 101a, the top surface of the device isolation structure 101 around the first groove 101a, and the top surface of the substrate outside the high-voltage area AA1 (for example, the top surface of the substrate of the active area AA2). On the one hand, it can protect these areas in the subsequent high-voltage gate oxide layer formation process. On the other hand, because the patterned barrier layer 104a has a greater barrier ability to oxygen than the silicon dioxide film layer, in the subsequent process of forming the high-voltage area gate oxide layer, it can prevent the amount of oxygen passing through the device isolation structure 101 from the high-voltage area AA1, and then in the subsequent process of forming the high-voltage area gate oxide layer, it can reduce the bird's beak problem caused by the oxygen passing through the device isolation structure 101 area oxidizing the corresponding active area AA2 surface layer.

[0072] Optionally, in the above example, the formed patterned photoresist layer 105 also exposes the top side of the substrate 100 of the device isolation structure 101 having the first groove 101a adjacent to the high voltage region AA1 (i.e., the top corner region of the device isolation structure 101 adjacent to the high voltage region AA1), and after etching the barrier layer 104 using the patterned photoresist layer 105 as a mask, and before or after removing the patterned photoresist layer 105, a further wet etching or dry etching process is further performed to etch and remove the pad oxide layer 102 in the region exposed by the patterned photoresist layer 105, and a certain amount of over-etching can be performed when etching the pad oxide layer 102, thereby etching and opening the top side of the substrate 100 of the device isolation structure 101 adjacent to the high voltage region AA1, and forming the second groove 101b. At this time, the patterned barrier layer 104a exposes the inner surface of the second groove 101b on the top side of the substrate 100 of the device isolation structure 101 adjacent to the high voltage region AA1. The second groove 101b is a corner notch of the device isolation structure 101 with the first groove 101a, and one side of the second groove 101b exposes the top side wall of the substrate 100 of the high-voltage area AA1. The purpose of exposing the top side wall of the high-voltage area AA1 is to better round the top corner of the substrate 100 of the high-voltage area AA1, so as to facilitate the formation of a high-voltage gate oxide layer with uniform edge thickness in the later stage. The bottom depth of the second groove 101b is shallower than the bottom depth of the first groove 101a, and the bottom depth of the second groove 101b is deeper than the top surface of the substrate 100 of the high-voltage area AA1. The bottom of the second groove 101b is kept lower than that of the first groove 101a to ensure the blocking ability of the remaining barrier layer 104a in the first groove 101a to the oxygen that laterally penetrates the device isolation structure 101, and to reduce the bird's beak effect generated on the active area AA2 during the formation of the high-voltage gate oxide layer as much as possible. The second groove 101b is also used to subsequently form a high-voltage gate oxide layer in a self-aligned manner. During the formation of the high-voltage gate oxide layer, sufficient space is prepared for the edge of the formed high-voltage gate oxide layer to reduce excessive squeezing of the edge of the in-situ generated high-voltage gate oxide layer.

[0073] Optionally, in the above example, the formed patterned photoresist layer 105 also exposes the top side of the substrate 100 of the device isolation structure 101 adjacent to the high-voltage area AA1 (i.e., the top corner area of ​​the device isolation structure 101 adjacent to the high-voltage area AA1). After etching the barrier layer 104 using the patterned photoresist layer 105 as a mask, and before or after removing the patterned photoresist layer 105, the pad oxide layer 102 in the area exposed by the patterned photoresist layer 105 is further etched and removed by a wet etching or dry etching process to expose the top surface of the substrate 100 of the high-voltage area AA1. After removing the patterned photoresist layer 105 and exposing the top surface of the substrate 100 in the high-voltage area AA1, thermal oxidation is performed under the mask of the patterned barrier layer 104a. The thermal oxidation can be achieved by a furnace tube oxidation process. During the thermal oxidation process, since the surface of the substrate 101 in the high-voltage area AA1 is exposed, oxygen molecules directly contact and react with the substrate 100 in this area and consume the substrate 100 downward to form a sacrificial oxide layer of a desired thickness (not shown); then, any suitable HF acid solution, SPM (a mixture of H2SO4, H2O2, and H2O) or SC1 (a mixture of NH4OH, H2O2, and H2O) can be selected. The etching liquid is used to wet-etch and remove the sacrificial oxide layer. In this process, since the etching selectivity ratio of the portion of the device isolation structure 101 exposed by the patterned barrier layer 104a to the sacrificial oxide layer 103 is not high, the etching liquid will also etch the top and sidewall of the device isolation structure 101 exposed by the patterned barrier layer 104a. After removing the sacrificial oxide layer, the top of the substrate 100 of the high-voltage area AA1 is lowered to the required height. At this time, the top of the device isolation structure 101 close to the high-voltage area AA1 is etched open to form a second groove 101b, and in this process, the exposed top corner of the substrate 100 of the high-voltage area AA1 can be rounded. The second groove 101b is a notch on one side of the top of the device isolation structure 101, and one side of it exposes the top sidewall of the substrate 100 of the high-voltage area. The bottom depth of the second groove 101b is shallower than the bottom depth of the first groove 101a, and the bottom depth of the second groove 101b is deeper than the top surface of the substrate 100 of the high-voltage area AA1. The second groove 101 b is used to form a high voltage gate oxide layer in a self-aligned manner later.

[0074] It should be understood that the width of the first groove 101a and the width of the second groove 101b can be reasonably set according to the device performance design requirements. The width of the first groove 101a is preferably greater than the width of the second groove 101b. As an example, the width of the first groove 101a accounts for 40% to 70% of the overall width of the top of the device isolation structure 101 where it is located, thereby providing a sufficiently large process window for the formation of the first groove 101a and the deposition coverage of the barrier layer 104 in the first groove 101a, and ensuring that the isolation effect of the top of the device isolation structure 101 after the formation of the first groove 101a and the second groove 101b is not affected, and ensuring that the gate contact hole CT on the subsequent gate 107 can be formed normally. As another example, the width of the second groove 101b is at least 10% to 20% greater than the overall width of the top of the device isolation structure 101 where it is located (for example, the width of the second groove 101b is between 10% and 20% of the overall width of the top of the device isolation structure 101 where it is located, or exceeds 20% of the overall width of the top of the device isolation structure 101 where it is located), thereby providing a sufficiently large self-alignment process window for the formation of the high-voltage gate oxide layer 106 and preparing sufficient space for the edge of the formed high-voltage gate oxide layer. Because the remaining barrier layer 104a is a certain distance away from the bottom and side walls of the device isolation structure 101, the adverse stress effects that the remaining barrier layer 104a may have on the substrate can be completely ignored, thereby simplifying the process and reducing the cost.

[0075] In step S4, please refer to Figure 3 In (F) and (G), a corresponding thermal oxidation process recipe (gate oxide recipe) is set according to the thickness requirement of the high-voltage gate oxide layer of the high-voltage device. According to the process recipe, the surface of the substrate 100 exposed in the high-voltage area AA1 is thermally oxidized under the masking effect of the patterned barrier layer 104a, and the high-voltage gate oxide layer 106 required for the high-voltage area AA1 is self-alignedly grown. It should be understood that during the thermal oxidation process, oxygen molecules O2 diffuse in the vertical direction to achieve the growth of the high-voltage gate oxide layer 106, but in the horizontal direction, due to the blocking effect of two layers of barriers provided by the patterned barrier layer 104a covering the side wall of the first groove 101a of the device isolation structure 101, O2 can be effectively prevented from laterally passing through the top of the device isolation structure 101, thereby causing the top of the active area AA2 (i.e., the active area outside the side of the device isolation structure 101 away from the high-voltage area) to be oxidized and form a bird's beak. This can avoid the problems caused by the presence of the bird's beak when metal silicide and contact holes are subsequently formed on the top surface of the active area AA2 (i.e., the active area outside the side of the device isolation structure 101 away from the high-voltage area).

[0076] It should be understood that, in some embodiments of the present invention, even if the first groove 101a is shallower than the second groove 101b, it can provide a corresponding barrier to the lateral diffusion of O2 when the high-voltage gate oxide layer 106 is formed by thermal oxidation, thereby reducing the formation of a bird's beak. However, preferably, the bottom depth of the first groove 101a is deep enough and can be deeper than the bottom depth of the second groove 101b, so that the bottom depth D2 of the high-voltage gate oxide layer 106 formed by thermal oxidation is less than the bottom depth D1 of the first groove 101a, thereby providing sufficient barrier to the lateral diffusion of O2 when the high-voltage gate oxide layer 106 is formed by thermal oxidation, thereby preventing the formation of a bird's beak.

[0077] In step S5, please refer to Figure 3 In (G) and (H), after the required high-voltage gate oxide layer 106 is formed, the patterned barrier layer 104a and the pad oxide layer 102 can be removed by any suitable process such as wet etching, and polysilicon can be deposited and gate lithography and etching can be performed to form a gate 107 on the high-voltage gate oxide layer 106.

[0078] Optionally, the gate 107 extends continuously from the high-voltage gate oxide layer 106 to the inner surface of the second groove 101b and the inner surface of the first groove 101a. One end of the gate 107 can stay in the first groove 101a, and it can be connected to the side wall of the first groove 101a away from the high-voltage area AA1, or it can be not connected. One end of the gate 107 stays in the first groove 101a, which is conducive to providing a larger process window when the gate metal silicide and the gate contact hole are subsequently formed on the gate 107 and improving the reliability of the gate contact hole. Preferably, the bottom surface of the first groove 101a is relatively flat, so that the end of the gate 107 formed in the first groove 101a is relatively flat, which is conducive to the growth of metal silicide on the end of the gate, and further conducive to the connection between the contact plug on the gate and the metal silicide.

[0079] In summary, the manufacturing method of the semiconductor device of the present embodiment forms a first groove on the top center of the device isolation structure (such as STI) formed near the high voltage region before forming the high voltage gate oxide layer, and retains a barrier layer in the first groove, thereby improving the barrier layer position in the high voltage gate oxide layer growth process relative to the prior art, increasing the barrier ability of the device isolation structure and the barrier layer to the lateral diffusion of O2 in the high voltage gate oxide layer growth process, thereby improving the bird's beak problem, and avoiding a series of problems such as the inability to form metal silicide on the active region due to the bird's beak, and the inability of the contact hole CT (not shown) formed on the active region to be connected to the metal silicide, the high resistance state of the formed contact hole CT and the high RC delay, and the high power consumption of the high voltage device or even the inability to work normally. In addition, the present solution mainly adds the formation process of the first groove (including photolithography and etching) relative to the prior art, is compatible with the current high voltage gate oxide process, does not add special processes, does not need to implant other unnecessary ions, is simple and controllable, does not challenge the process limit of the high voltage gate oxide process, and is safer and more reliable. In addition, one end of the gate extends into the first groove, which can increase the process window of gate metal silicide and gate contact hole.

[0080] It should be understood that in the above embodiment, the first groove 101a is formed at the left-right center of the device isolation structure 101, but the technical solution of the present invention is not limited thereto. If the process allows and the mechanical strength and isolation effect of the device isolation structure 101 can be guaranteed, the first groove 101a can also be formed at a position deviating from the center to the left or right of the device isolation structure 101. Based on the same inventive concept, please refer to Figure 3 (H), an embodiment of the present invention further provides a semiconductor device, which can be formed by the manufacturing method of the semiconductor device of the present invention, the semiconductor device comprises a substrate 100, a device isolation structure 101 and a high-voltage gate oxide layer 106, wherein the device isolation structure 101 is formed in the substrate 100 and defines a high-voltage area AA1 in the substrate 100, and a first groove 101a is formed in the top central area of ​​the device isolation structure 101; the high-voltage gate oxide layer 106 is formed on the surface of the substrate 100 in the high-voltage area AA1 and the bottom of the high-voltage gate oxide layer 106 is higher than the bottom of the first groove 101a, and the bottom depth of the first groove 101a is sufficient, so as to provide sufficient barrier to the lateral diffusion of O2 when the high-voltage gate oxide layer 106 is formed by thermal oxidation, thereby preventing the formation of a bird's beak.

[0081] Optionally, a second groove 101b is further formed on the top of one side of the device isolation structure 101 adjacent to the high voltage region AA1, the second groove 101b exposes the sidewall of the high voltage gate oxide layer 106, and the bottom of the second groove 101b is shallower than (i.e., higher than) the bottom of the first groove 101a. The bottom of the high voltage gate oxide layer 106 is higher than (i.e., shallower than) the bottom of the first groove 101a.

[0082] Optionally, the width of the first groove 101a accounts for 40% to 70% of the width of the device isolation structure 101 in which it is located. Optionally, the width of the second groove 101b exceeds at least 10% to 20% of the width of the device isolation structure 101 in which it is located. Optionally, the first groove 101a is located at the left and right center of the device isolation structure 101 adjacent to the high-voltage area AA1, and the depth of the first groove 101a in the device isolation structure 101 accounts for less than 20% to 30% of the total depth of the device isolation structure 101 in which it is located.

[0083] Optionally, the semiconductor device further comprises a gate 107 , which covers the high voltage gate oxide layer 106 and has one end formed in the first groove 101 a , thereby increasing the process window of the gate metal silicide and the gate contact hole.

[0084] It should be understood that the semiconductor device of this embodiment does not only include the above-mentioned film layers and structures, but may also include any other suitable structures, such as metal silicide formed on the substrate surface in the high-voltage area, metal silicide and gate contact holes formed on the gate surface, etc., which will not be described in detail here.

[0085] In summary, the semiconductor device of the present invention has a first groove formed in the top center of the device isolation structure. The first groove is used to block the lateral diffusion of O2 molecules during the process of forming a high-voltage gate oxide layer by thermal oxidation to avoid the formation of a bird's beak. The performance and reliability of the semiconductor device of the present invention are improved.

[0086] The above description is only a description of the preferred embodiment of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the technical solution of the present invention.

Claims

1. A method for manufacturing a semiconductor device, characterized in that: include: providing a substrate, forming a device isolation structure in the substrate, the device isolation structure defining a high voltage region in the substrate; Etching a top central area of ​​the device isolation structure to form a first groove; forming a patterned barrier layer, wherein the patterned barrier layer exposes the base of the high-voltage region and masks the remaining region including the inner surface of the first groove; Under the mask of the patterned barrier layer, a high-voltage gate oxide layer is formed on the surface of the substrate in the high-voltage region by thermal oxidation, and the bottom of the high-voltage gate oxide layer is higher than the bottom of the first groove.

2. The manufacturing method according to claim 1, characterized in that The step of forming a device isolation structure in the substrate comprises: forming a pad oxide layer and a hard mask layer on the surface of the substrate, and etching the hard mask layer by photolithography and etching processes to form a patterned hard mask layer; Using the patterned hard mask layer as a mask, etching the pad oxide layer and the substrate to form a shallow trench in the substrate; Depositing an insulating dielectric material to fill the shallow trench; The top of the insulating dielectric material is planarized to the top surface of the patterned hard mask layer, and the patterned hard mask layer is removed to form the device isolation structure with a top higher than the top of the substrate.

3. The manufacturing method according to claim 1, characterized in that: The steps of forming the patterned barrier layer include: Depositing a barrier layer on the surface of the device isolation structure and the substrate, wherein the barrier layer also covers the inner surface of the first groove; The barrier layer on the high-voltage region is removed by photolithography and etching processes, and at the same time, the top of one side of the device isolation structure adjacent to the high-voltage region is etched open to form the patterned barrier layer, and a second groove exposing the top side wall of the substrate of the high-voltage region is formed at the top of one side of the device isolation structure adjacent to the high-voltage region, and the second groove is shallower than the first groove.

4. The manufacturing method according to claim 3, characterized in that: Before or after forming the device isolation structure in the substrate, a pad oxide layer is also formed on the substrate; after removing the barrier layer on the high-voltage area by photolithography and etching processes, the pad oxide layer on the substrate surface of the high-voltage area is also wet-etched to expose the substrate surface of the high-voltage area.

5. The manufacturing method according to claim 1, characterized in that: The patterned barrier layer also exposes the top of one side of the device isolation structure adjacent to the high voltage region. After forming the patterned barrier layer and before forming a high voltage gate oxide layer on the substrate surface of the high voltage region by thermal oxidation, the method further includes: Under the mask of the patterned barrier layer, a portion of the substrate in the high-voltage region is consumed by thermal oxidation to form a sacrificial oxide layer; The sacrificial oxide layer is removed by wet etching, and at the same time, the top side of the device isolation structure close to the high voltage region is etched open to lower the top of the substrate in the high voltage region, and at the same time, a second groove is formed on the top side of the device isolation structure close to the high voltage region to expose the top side wall of the substrate in the high voltage region, and the second groove is shallower than the first groove.

6. The manufacturing method according to claim 4 or 5, characterized in that: The invention has at least one of the following restrictions (1) to (3): (1) the width of the first groove accounts for 40% to 70% of the width of the device isolation structure in which the first groove is located; (2) the width of the second groove exceeds the width of the device isolation structure in which the second groove is located by at least 10% to 20%; (3) The first groove is located at the left and right center of the device isolation structure, and the depth of the first groove in the device isolation structure accounts for less than 20% to 30% of the total depth of the device isolation structure.

7. The manufacturing method according to any one of claims 1 to 5, characterized in that: After forming the high voltage gate oxide layer, the method further comprises: removing the patterned barrier layer; Polysilicon is deposited and excess polysilicon is removed by etching to form a gate that at least covers the high-voltage gate oxide layer.

8. The manufacturing method according to claim 7, characterized in that: One end of the gate is formed in the first groove.

9. A semiconductor device, characterized in that: include: substrate; a device isolation structure formed in the substrate and defining a high voltage region in the substrate, wherein a first groove is formed in a top central region of the device isolation structure; A high-voltage gate oxide layer is formed on the surface of the substrate in the high-voltage region, and the bottom of the high-voltage gate oxide layer is higher than the bottom of the first groove.

10. The semiconductor device according to claim 9, wherein: A second groove is formed on the top of one side of the device isolation structure adjacent to the high voltage region. The second groove exposes the side wall of the high voltage gate oxide layer, and the bottom of the second groove is shallower than the bottom of the first groove.

11. The semiconductor device according to claim 10, wherein: The invention has at least one of the following restrictions (1) to (3): (1) the width of the first groove accounts for 40% to 70% of the width of the device isolation structure in which the first groove is located; (2) the width of the second groove exceeds the width of the device isolation structure in which the second groove is located by at least 10% to 20%; (3) The first groove is located at the left and right center of the device isolation structure, and the depth of the first groove in the device isolation structure accounts for less than 20% to 30% of the total depth of the device isolation structure.

12. The semiconductor device according to claim 9, wherein It also includes a gate, which covers the high-voltage gate oxide layer and has one end formed in the first groove.

Images