Semiconductor device and electronic system including the same

Abstract

A semiconductor device and an electronic system including the same are provided. The semiconductor device includes a semiconductor substrate and a first transistor disposed on the semiconductor substrate. The first transistor includes an insulating structure disposed on the semiconductor substrate, a channel region disposed on the insulating structure and including a first semiconductor layer and extending in a direction crossing the semiconductor substrate, a first source region and a first drain region electrically connected to the channel region, a first gate insulating layer disposed on the channel region, and a second gate insulating layer disposed on the first gate insulating layer. And a first gate electrode disposed on the first gate insulating layer. A first region, which is one of the first source region and the first drain region, and a second region, which is the other of the first source region and the first drain region, include different materials or have different crystal structures.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to a semiconductor device and an electronic system including the semiconductor device. Background Art

[0002] Small but multifunctional semiconductor devices can be used in various electronic industries. With the progress of the electronic industry, research on improving the performance and integration of semiconductor devices continues. For example, by reducing the distance between multiple circuit elements included in the semiconductor device, the integration of the semiconductor device can be improved. Summary of the invention

[0003] Embodiments of the present disclosure provide a semiconductor device capable of improving performance and integration, and an electronic system including the semiconductor device.

[0004] A semiconductor device according to an embodiment includes a semiconductor substrate and a first transistor disposed on the semiconductor substrate. The first transistor includes an insulating structure disposed on the semiconductor substrate, a channel region disposed on the insulating structure and including a first semiconductor layer and extending in a direction intersecting the semiconductor substrate, a first source region and a first drain region electrically connected to the channel region, a first gate insulating layer disposed on the channel region, and a first gate electrode disposed on the first gate insulating layer. The first region as one of the source region and the drain region and the second region as the other of the first source region and the first drain region include different materials or have different crystal structures.

[0005] A semiconductor device according to an embodiment includes a semiconductor substrate and a plurality of transistors, the plurality of transistors being arranged on the semiconductor substrate and including a first transistor and a second transistor having different structures. The first transistor includes an insulating structure arranged on the semiconductor substrate, a channel region arranged on the insulating structure and including a first semiconductor layer and extending in a direction inclined or perpendicular to the semiconductor substrate, a source region and a drain region electrically connected to the channel region, a gate insulating layer arranged on the channel region, and a gate electrode arranged on the gate insulating layer. One of the source region and the drain region includes a partial portion of the semiconductor substrate.

[0006] An electronic system according to an embodiment includes a main substrate, a semiconductor device disposed on the main substrate, and a controller electrically connected to the semiconductor device on the main substrate.

[0007] According to an embodiment, the high voltage transistor has a vertical structure (eg, a vertical channel structure), which can improve integration. In addition, the second region as one of the source region and the drain region of the high voltage transistor includes a partial portion of the semiconductor substrate, which can improve the performance of the high voltage transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 is a partial cross-sectional view schematically showing a semiconductor device according to an embodiment.

[0009] Figure 2 It is shown Figure 1 An enlarged cross-sectional view of an example of a channel structure included in a semiconductor device is shown.

[0010] Figure 3 It is schematically shown Figure 1 A partial cross-sectional view of a circuit region included in the semiconductor device shown.

[0011] Figure 4 It is schematically shown Figure 1 A cross-sectional view of a partial portion of a circuit region included in the semiconductor device shown.

[0012] Figure 5 It is schematically shown Figure 3 A plan view of a first transistor and a second transistor included in the circuit area shown.

[0013] Figure 6 , Figure 7 , Figure 8 , Fig. 9 , Fig.10 , Fig.11 and Fig.12 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment.

[0014] Fig.13 is an enlarged plan view showing a partial portion of a semiconductor device according to an embodiment.

[0015] Fig.14 is an enlarged plan view showing a partial portion of a semiconductor device according to an embodiment.

[0016] Fig.15 is a cross-sectional view schematically showing a semiconductor device according to an embodiment.

[0017] Fig.16 is a view schematically illustrating an electronic system including a semiconductor device according to an embodiment.

[0018] Fig.17 is a perspective view schematically showing an electronic system including a semiconductor device according to an embodiment.

[0019] Fig.18 is a cross-sectional view schematically showing a semiconductor package according to an embodiment.

[0020] Fig.19is a cross-sectional view schematically showing a semiconductor package according to an embodiment. DETAILED DESCRIPTION

[0021] The embodiments of the present disclosure will be described more fully below with reference to the accompanying drawings so that those skilled in the art to which the present disclosure belongs can easily practice the present disclosure. The present disclosure can be implemented in various different forms and is not necessarily limited to the embodiments provided herein.

[0022] Parts irrelevant to the description are omitted to clearly describe the present disclosure, and the same or similar components are denoted by the same reference numerals throughout the specification.

[0023] It should be understood that when a component such as a layer, film, region, or substrate is referred to as being "on" another component, it can be directly on the other component or intervening components may also be present. In contrast, when a component is referred to as being "directly on" another component, there are no intervening components. Furthermore, when a component is referred to as being "on" or "above" a reference component, the component may be positioned above or below the reference component and is not necessarily "on" or "above" the reference component in an opposite direction of gravity.

[0024] In addition, unless explicitly described to the contrary, the word “comprise” and variations such as “comprising” or “including”, will be understood to imply the inclusion of stated elements but not the exclusion of any other elements.

[0025] In addition, throughout the specification, the phrases "on a plane", "in a plane", "on a plan view" or "in a plan view" may indicate a situation where a part is viewed from above or from the top, and the phrases "on a section" or "in a section" may indicate when a section taken in a vertical direction is viewed from the side.

[0026] It should be understood that the terms "first", "second", "third", etc. are used herein to distinguish one element from another element, and the elements are not limited by these terms. Therefore, the "first" element in an embodiment may be described as the "second" element in another embodiment.

[0027] It should be understood that descriptions of features or aspects within each embodiment should typically be considered as available for other similar features or aspects in other embodiments, unless the context clearly dictates otherwise.

[0028] As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0029] In the following, reference Figures 1 to 12 , a semiconductor device and a method for manufacturing the same according to an embodiment will be described in detail.

[0030] Figure 1 is a partial cross-sectional view schematically showing a semiconductor device 10 according to an embodiment. Figure 2 It is shown Figure 1 FIG. 1 is an enlarged cross-sectional view of an example of a channel structure CH included in the semiconductor device 10 shown. For a clear understanding, Figure 1 The coordinates are mainly based on the unit area 100, and Figure 1 The figure shows the Figure 5 1 is a cross-sectional view of the circuit area 200 taken along line AA′, regardless of the coordinates.

[0031] Reference Figure 1 and Figure 2 According to the embodiment, the semiconductor device 10 may include a cell region 100 including a memory cell structure and a circuit region 200 including a peripheral circuit structure for controlling the operation of the memory cell structure. For example, the circuit region 200 and the cell region 100 may correspond to Fig.16 The electronic system 1000 shown in FIG. 1 includes a first structure 1100F and a second structure 1100S of a semiconductor device 1100. In some embodiments, the circuit region 200 and the unit region 100 may include Fig.18 The semiconductor chip 2200 is shown with a first structure 3100 and a second structure 3200 .

[0032] Here, the circuit region 200 may include a peripheral circuit structure on a first substrate 210, and the cell region 100 may include a gate stack structure 120 and a channel structure CH as a memory cell structure on a second substrate 110. The circuit region 200 may include a first wiring portion 230, and the cell region 100 may include a second wiring portion 180 electrically connected to the memory cell structure.

[0033] In an embodiment, the cell region 100 may be disposed on the circuit region 200. Therefore, the region corresponding to the circuit region 200 does not need to be fixed separately from the cell region 100. Therefore, the area of ​​the semiconductor device 10 can be reduced. However, the embodiment is not necessarily limited thereto and may be modified. For example, the circuit region 200 may be disposed next to the cell region 100.

[0034] The cell region 100 may include a cell array region 102 and a connection region 104. A gate stack structure 120 and a channel structure CH may be disposed on a second substrate 110 in the cell array region 102. A structure that connects the gate stack structure 120 and / or the channel structure CH in the cell array region 102 to the circuit region 200 or an external circuit may be in the cell array region 102 and / or the connection region 104.

[0035] In an embodiment, the second substrate 110 may include a semiconductor layer including a semiconductor material. For example, the second substrate 110 may be a semiconductor substrate including or formed of a semiconductor material, or may be a semiconductor substrate in which a semiconductor layer is disposed on a base substrate. For example, the second substrate 110 may include silicon, germanium, silicon germanium, silicon on insulator, germanium on insulator, etc., or may be formed of silicon, germanium, silicon germanium, silicon on insulator, germanium on insulator, etc. Here, the semiconductor layer included in the second substrate 110 may be doped with a p-type dopant or an n-type dopant. For example, the p-type dopant may include boron (B), gallium (Ga), etc., and the n-type dopant may include phosphorus (P), arsenic (As), etc. However, the embodiment is not necessarily limited to the material of the second substrate 110, the dopant of the conductivity type doped to the semiconductor layer, etc.

[0036] In the cell array region 102, a gate stack structure 120 and a channel structure CH may be positioned. The gate stack structure 120 may include a cell insulating layer 132 and a gate line 130 alternately stacked on a first surface (e.g., a front surface or an upper surface) of a second substrate 110. The channel structure CH may extend in a direction (Z-axis direction in the figure) intersecting the second substrate 110 while penetrating the gate stack structure 120. For example, the channel structure CH may be disposed perpendicular to the cell insulating layer 132 and the gate line 130.

[0037] In an embodiment, a first horizontal conductive layer 112 and / or a second horizontal conductive layer 114 may be provided between the second substrate 110 and the gate stack structure 120 in the cell array region 102. For example, the horizontal conductive layers 112 and 114 may be sequentially disposed on the second substrate 110 and below the gate stack structure 120. The first horizontal conductive layer 112 and the second horizontal conductive layer 114 may electrically connect (e.g., directly connect) the channel structure CH and the second substrate 110. The first horizontal conductive layer 112 may serve as a partial portion of a common source line of the semiconductor device 10. For example, the first horizontal conductive layer 112 may serve as a common source line together with the second substrate 110.

[0038] The first horizontal conductive layer 112 and the second horizontal conductive layer 114 may include a semiconductor material (e.g., polysilicon). For example, the first horizontal conductive layer 112 may include a polysilicon layer containing a dopant. Embodiments are not necessarily limited thereto. The second horizontal conductive layer 114 may include a material different from that of the first horizontal conductive layer 112 (e.g., an insulating material), or the second horizontal conductive layer 114 may not be provided.

[0039] The gate stack structure 120 in which unit insulating layers 132 and gate lines 130 are alternately stacked may be disposed on the second substrate 110 (eg, on the first horizontal conductive layer 112 and the second horizontal conductive layer 114 disposed on the second substrate 110 ).

[0040] The gate line 130 may include any of a variety of conductive materials. For example, the gate line 130 may include a metal material (such as tungsten (W), copper (Cu), aluminum (Al), etc.), polysilicon, a metal nitride (for example, titanium nitride (TiN), tantalum nitride (TaN), etc.), or a combination thereof. Figure 2 As shown in the enlarged view of , a local portion of the barrier layer 156 (e.g., the first barrier layer 156a) including an insulating material may be disposed outside the gate line 130. The cell insulating layer 132 may include any of various insulating materials such as, for example, silicon oxide, silicon nitride, silicon oxynitride, a low dielectric constant material having a lower dielectric constant than silicon oxide, or a combination thereof.

[0041] In an implementation, a channel structure CH may be provided. The channel structure CH may penetrate the gate stack structure 120 and extend in a direction crossing the second substrate 110 (eg, a direction perpendicular to the second substrate 110 or the Z axis).

[0042] The channel structure CH may include a channel layer 140 and a gate dielectric layer 150 disposed on the channel layer 140 between the gate line 130 and the channel layer 140. The channel structure CH may further include a core insulating layer 142 inside the channel layer 140. In some embodiments, the core insulating layer 142 may not be provided. The channel structure CH may further include a channel pad 144 disposed on the channel layer 140 and / or the gate dielectric layer 150. The gate dielectric layer 150 disposed between the gate line 130 and the channel layer 140 may include a tunneling layer 152, a charge storage layer 154, and a blocking layer 156 sequentially disposed on the channel layer 140. For example, the tunneling layer 152 may be disposed closer to the channel layer 140 than the charge storage layer 154 and the blocking layer 156.

[0043] Each channel structure CH forms a memory cell string, and when viewed in a plan view, a plurality of channel structures CH may be spaced apart from each other, forming rows and columns at the same time. For example, in a plan view, a plurality of channel structures CH may be arranged to form various shapes such as a lattice shape or a zigzag shape. The channel structure CH may have a column shape. For example, in a cross-sectional view, the channel structure CH may have an inclined side surface so that the width of the channel structure CH decreases as the channel structure CH extends closer to the second substrate 110 according to the aspect ratio. However, the embodiment is not necessarily limited thereto, and various modifications may be made to the arrangement, structure, shape, etc. of the channel structure CH.

[0044] The channel layer 140 may include a semiconductor material (eg, polysilicon). The core insulating layer 142 may include any of various insulating materials such as, for example, silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof.

[0045] The tunneling layer 152 may include an insulating material (e.g., silicon oxide, silicon oxynitride, etc.) capable of tunneling charges. The charge storage layer 154 may be used as a data storage area, and the charge storage layer 154 may include polysilicon, silicon nitride, etc. The blocking layer 156 may include an insulating material capable of preventing undesired charges from flowing into the gate line 130. The blocking layer 156 may include, for example, silicon oxide, silicon nitride, silicon oxynitride, a high dielectric constant material having a higher dielectric constant than silicon oxide, or a combination thereof. In an embodiment, the blocking layer 156 may include a first blocking layer 156a and a second blocking layer 156b, the first blocking layer 156a including a portion extending horizontally along the gate line 130, and the second blocking layer 156b extending vertically between the first blocking layer 156a and the charge storage layer 154. For example, the first blocking layer 156a may contact the gate line 130, and the second blocking layer 156b may not contact the gate line 130.

[0046] Materials, stack structures, etc. of the channel layer 140 , the core insulating layer 142 , and the gate dielectric layer 150 may be variously modified, and the embodiments are not necessarily limited thereto.

[0047] The channel pad 144 may cover the upper surface of the core insulating layer 142 and may be electrically connected to the channel layer 140. The channel pad 144 may include a conductive material (eg, polysilicon doped with a dopant), but embodiments are not necessarily limited thereto.

[0048] In an embodiment, the gate stack structure 120 may include a plurality of gate stack structures 120a and 120b stacked sequentially. The number of stacked gate lines 130 may increase, and thus the number of memory cells may increase. Figure 1 In the embodiment, the gate stack structure 120 includes a first gate stack structure 120a and a second gate stack structure 120b as an example. In some embodiments, the gate stack structure 120 may include one gate stack structure or three or more gate stack structures.

[0049] When a plurality of gate stack structures 120a and 120b are provided as described above, the channel structure CH may include a plurality of channel structures CH1 and CH2 that penetrate the plurality of gate stack structures 120a and 120b, respectively, and are electrically connected to each other. In a cross-sectional view, each of the plurality of channel structures CH1 and CH2 may have an inclined side surface such that a width of each of the plurality of channel structures CH1 and CH2 decreases according to an aspect ratio as each of the plurality of channel structures CH1 and CH2 extends closer to the second substrate 110. A curved portion due to a difference in width of the plurality of channel structures CH1 and CH2 may be provided at a connecting portion of the plurality of channel structures CH1 and CH2. In some embodiments, the plurality of channel structures CH1 and CH2 may have an inclined side surface that extends continuously without a curved portion. Figure 2 , it is shown as an example that the gate dielectric layer 150, the channel layer 140, and the core insulating layer 142 of the plurality of channel structures CH1 and CH2 are continuously extended to have an integral structure. In some embodiments, the gate dielectric layer 150, the channel layer 140, and the core insulating layer 142 of the plurality of channel structures CH1 and CH2 may be formed separately and electrically connected to each other. In some embodiments, a separate channel pad 144 may be additionally provided at the connection portion of the plurality of channel structures CH1 and CH2. Therefore, the embodiments are not necessarily limited to the shapes of the plurality of channel structures CH1, CH2.

[0050] In an embodiment, the gate stack structure 120 may be divided into a plurality of parts in a plan view by a separation structure 146 that extends in a direction intersecting the second substrate 110 (e.g., in a direction perpendicular to the second substrate 110 or the Z-axis) and penetrates the gate stack structure 120. An upper separation region 148 may be disposed at an upper portion of the gate stack structure 120. In a plan view, the separation structure 146 and / or the upper separation region 148 may extend in a first direction (Y-axis direction) and be spaced apart from each other at a predetermined interval in a second direction (X-axis direction) transverse to the first direction.

[0051] The separation structure 146 and / or the upper separation region 148 may be filled with any of various insulating materials such as, for example, silicon oxide, silicon nitride, or silicon oxynitride. However, the embodiment is not necessarily limited thereto, and various modifications may be made to the structure, shape, material, etc. of the separation structure 146 or the upper separation region 148.

[0052] The connection region 104 and the second wiring portion 180 may connect the gate stack structure 120 and the channel structure CH in the cell array region 102 to the circuit region 200 or an external circuit. The connection region 104 may be at the periphery of the cell array region 102, and a partial portion of the second wiring portion 180 may be in the connection region 104.

[0053] The second wiring portion 180 may include a member that electrically connects the gate line 130, the channel structure CH, the horizontal conductive layers 112 and 114, and / or the second substrate 110 to the circuit region 200 or an external circuit. For example, the second wiring portion 180 may include a bit line 182, a gate contact portion 184, a source contact portion, a through plug 188, a contact via 180a, and a connection wiring 190, the contact via 180a being connected to each of the bit line 182, the gate contact portion 184, the source contact portion, and / or the through plug 188, and the connection wiring 190 connecting the bit line 182, the gate contact portion 184, the source contact portion, the through plug 188, and the contact via 180a.

[0054] The bit line 182 may extend in a second direction (X-axis direction) crossing the first direction in which the gate line 130 extends. The bit line 182 may be electrically connected to the channel structure CH (eg, the channel pad 144) through a contact via 180a (eg, a bit line contact via) penetrating the cell insulating layer 132.

[0055] In the connection region 104, a plurality of gate contact portions 184 may penetrate the cell insulating layer 132 and be electrically connected to a plurality of gate lines 130 extending to the connection region 104, respectively. In the drawings, it is shown as an example that the plurality of gate lines 130 have a stepped shape in one direction or in multiple directions in the connection region 104, but the embodiment is not necessarily limited thereto. In the connection region 104, the source contact portion may penetrate the cell insulating layer 132 and be electrically connected to the horizontal conductive layers 112 and 114 and / or the second substrate 110. The through plug 188 may penetrate the gate stack structure 120 or may be outside the gate stack structure 120 and electrically connected to the first wiring portion 230 of the circuit region 200.

[0056] exist Figure 1 , it is shown as an example that each of the gate contact portion 184, the source contact portion and / or the through plug 188 has an inclined side surface, so that in the cross-sectional view, the width of each of the gate contact portion 184, the source contact portion and / or the through plug 188 decreases as each of the gate contact portion 184, the source contact portion and / or the through plug 188 moves toward the second substrate 110 due to the aspect ratio, and a curved portion is provided at a boundary portion of the plurality of gate stack structures 120a and 120b. However, the embodiment is not necessarily limited to this. For example, in some embodiments, the source contact portion and / or the through plug 188 may not include a curved portion at a boundary portion of the plurality of gate stack structures 120a and 120b.

[0057] exist Figure 1, it is shown as an example that the connection wiring 190 is a single layer on the same plane as the bit line 182, and the second insulating layer 192 is a single layer on the same plane as the bit line 182 and the connection wiring 190. However, this is not necessarily limited to this. For example, the connection wiring 190 may include a plurality of wiring layers, and may further include a contact path and be connected to the bit line 182, the gate contact portion 184, the source contact portion, and / or the through plug 188.

[0058] The bit line 182 , the gate line 130 , the horizontal conductive layers 112 and 114 , and / or the second substrate 110 connected to the channel structure CH may be electrically connected to the circuit element 220 of the circuit region 200 through the second wiring portion 180 and the first wiring portion 230 .

[0059] The circuit region 200 may include a first substrate 210 , a circuit element 220 on the first substrate 210 , and a first wiring portion 230 .

[0060] The first substrate 210 may be a semiconductor substrate including a semiconductor material. For example, the first substrate 210 may be a semiconductor substrate including or formed of a semiconductor material, or may be a semiconductor substrate in which a semiconductor layer is disposed on a base substrate. For example, the first substrate 210 may include single crystal or polycrystalline silicon, epitaxial silicon, germanium, silicon germanium, silicon on insulator (SOI), germanium on insulator (GOI), etc.

[0061] The circuit elements 220 on the first substrate 210 may include circuit elements that control the operation of the memory cell structures in the cell region 100. For example, the circuit elements 220 may include a decoder circuit 1110 (see Fig.16 )、Page buffer 1120 (refer to Fig.16 )、Logic circuit 1130 (refer to Fig.16 ) and other peripheral circuit structures.

[0062] The circuit element 220 may include a plurality of transistors 260 and 270. In an embodiment, the plurality of transistors 260 and 270 may include a first transistor 260 and a second transistor 270, which will be described in more detail later. The circuit element 220 may include not only active elements such as the first transistor 260 and the second transistor 270, but also passive elements such as capacitors, resistors, inductors, etc.

[0063] The first wiring portion 230 on the first substrate 210 may be electrically connected to the circuit element 220. In an embodiment, the first wiring portion 230 may include a plurality of wiring layers 236, which are spaced apart from each other while the first insulating layer 232 is interposed therebetween, and are electrically connected through the contact path 234 and form a desired path. The wiring layer 236 or the contact path 234 may include a conductive material, and the first insulating layer 232 may include an insulating material. For example, the wiring layer 236 disposed at the uppermost portion adjacent to the cell region 100 among the plurality of wiring layers 236 may include or constitute a pad portion to which the gate contact portion 184, the source contact portion, the through plug 188, etc. are connected.

[0064] refer to Figures 3 to 5 as well as Figure 1 and Figure 2 , the first transistor 260 and the second transistor 270 will be described in more detail. Figure 3 It is schematically shown Figure 1 FIG. 1 is a partial cross-sectional view of a circuit region 200 included in the semiconductor device 10 . Figure 4 It is schematically shown Figure 1 FIG. 2 is a cross-sectional view of a partial portion of a circuit region 200 included in a semiconductor device 10 . Figure 5 It is schematically shown Figure 3 FIG. 2 is a plan view of a first transistor 260 and a second transistor 270 included in the circuit region 200 .

[0065] Figure 4 is along Figure 5 For the sake of simplicity and clear understanding, Figure 5 , the first gate electrode 268 and the first and second regions 264a and 264b of the first transistor 260 are mainly shown, and the gate contact 234g, the first contact 234a and the second contact 234b electrically connected to the first gate electrode 268, the first and second regions 264a and 264b, respectively, are shown with dotted lines.

[0066] refer to Figures 1 to 5 In an embodiment, the first substrate 210 may include a body region 210 b , a second region 264 b which is a local portion of the first transistor 260 , and a source region 274 s and a drain region 274 d which are local portions of the second transistor 270 .

[0067] For example, the body region 210b may be or include a local region of a semiconductor substrate having a first conductivity type (e.g., p-type or n-type). The second region 264b may be or include another region of the semiconductor substrate having a second conductivity type (e.g., n-type or p-type) opposite to the first conductivity type. The source region 274s and the drain region 274d of the second transistor 270 may be or include another region of the semiconductor substrate having a second conductivity type (e.g., n-type or p-type) opposite to the first conductivity type.

[0068] In an embodiment, the body region 210b and the second region 264b are portions including the same material (e.g., the same semiconductor material) and having the same crystal structure while having opposite conductivity types to each other. The second region 264b may be formed by doping with a dopant having a conductivity type opposite to that of the body region 210b. Similarly, the body region 210b and the source region 274s and the drain region 274d are portions including the same material (e.g., the same semiconductor material) and having the same crystal structure while having opposite conductivity types to each other. The source region 274s and the drain region 274d may be formed by doping with a dopant having a conductivity type opposite to that of the body region 210b.

[0069] For example, the body region 210b may include a single crystalline semiconductor material having a p-type (e.g., single crystalline silicon), the second region 264b may include a single crystalline semiconductor material having an n-type (e.g., single crystalline silicon), and the source region 274s and the drain region 274d may include a single crystalline semiconductor material having an n-type (e.g., single crystalline silicon). For example, the p-type dopant may include boron, gallium, etc., and the n-type dopant may include phosphorus, arsenic, etc.

[0070] However, the embodiment is not necessarily limited thereto. A conductive well having the second conductivity type may be formed, and a source region 274 s and a drain region 274 d having the first conductivity type of the second transistor 270 may be included in the second transistor 270 .

[0071] In an implementation, the first substrate 210 may be provided with a plurality of transistors 260 , 270 . The plurality of transistors 260 and 270 may include a first transistor 260 and a second transistor 270 having an operating voltage less than that of the first transistor 260 .

[0072] The first transistor 260 may be a high voltage (HV) transistor having an operating voltage relatively higher than that of the second transistor 270, and the second transistor 270 may be a low voltage (LV) transistor having an operating voltage relatively lower than that of the first transistor 260. For example, the second transistor 270 may have an operating voltage ranging from about 0.1V to about 10V, and the first transistor 260 may have an operating voltage greater than that of the second transistor 270, for example, ranging from about 10V to about 100V. For example, the operating voltage of the first transistor 260 may be about 20V or higher (e.g., about 20V to about 100V). However, embodiments are not necessarily limited thereto.

[0073] The first transistor 260 as a high voltage transistor can be applied to a transistor that generates or transmits a high voltage. For example, the decoder circuit 1110 (see Fig.16 )、Page buffer 1120 (refer to Fig.16 ) and the like may be configured as a first transistor 260. For example, the first transistor 260 may be connected to a through-plug 188 electrically connected to the gate contact portion 184, and thus a voltage may be applied to the gate contact portion 184. The second transistor 270, which is a low voltage transistor, may have high-speed operation characteristics and thus may be applied to a transistor requiring high-speed operation.

[0074] In the drawings, the first transistor 260 may be disposed at a lower portion of the connection region 104, and the second transistor 270 may be disposed at a lower portion of the cell array region 102. In some embodiments, the first transistor 260 and the second transistor 270 may be disposed together at a lower portion of the cell array region 102. In some embodiments, the first transistor 260 and the second transistor 270 may be disposed together at a lower portion of the connection region 104. However, it is not necessarily limited thereto, and the positions of the first transistor 260 and the second transistor 270 may be modified.

[0075] In an implementation, the first transistor 260 may include an insulating structure 232a, a channel region 262, a first region 264a and a second region 264b, a first gate insulating layer 266, and a first gate electrode 268. The second transistor 270 may include a source region 274s and a drain region 274d, a second gate insulating layer 276 and a second gate electrode 278. The first transistor 260 and the second transistor 270 may have different structures.

[0076] In an embodiment, the first transistor 260 may have a vertical structure. For example, the first transistor 260 may have a vertical channel structure. Here, the vertical structure may refer to a structure in which the channel region 262 or the first gate electrode 268 includes a portion extending in a direction intersecting the first surface 2101 or the second surface 2102 of the first substrate 210 (e.g., in a direction oblique to or perpendicular to the first surface 2101 or the second surface 2102 of the first substrate 210). The vertical channel structure may refer to a structure in which the channel region 262 includes a portion extending in a direction intersecting the first surface 2101 or the second surface 2102 of the first substrate 210 (e.g., in a direction oblique to or perpendicular to the first surface 2101 or the second surface 2102 of the first substrate 210).

[0077] In an embodiment, the second transistor 270 may have a structure different from that of the first transistor 260. For example, the second transistor 270 may have a planar structure. For example, the second transistor 270 may have a planar channel structure. Here, the planar structure may refer to a structure in which a channel portion between the source region 274s and the drain region 274d or a second gate electrode 278 includes a portion parallel to the first surface 2101 or the second surface 2102 of the first substrate 210. Here, the planar channel structure may refer to a structure in which a channel portion between the source region 274s and the drain region 274d includes a portion parallel to the first surface 2101 or the second surface 2102 of the first substrate 210.

[0078] In the first transistor region A1 provided with the first transistor 260, the insulating structure 232a may be provided on the first substrate 210. The channel region 262 and / or the first gate electrode 268 may be provided adjacent to the insulating structure 232a. For example, the channel region 262 and / or the first gate electrode 268 may be formed on the side surface of the insulating structure 232a. The insulating structure 232a may include a first portion 2321 and a second portion 2322. The second portion 2322 may have a thickness T1 of a predetermined value so that the channel region 262 formed on the side surface of the insulating structure 232a has a sufficient length.

[0079] The first portion 2321 may fill the trench 210 t of the first substrate 210 .

[0080] In an embodiment, the first portion 2321 may be a device separation portion or a shallow trench isolation separating the first transistor 260. The channel region 262, the first gate electrode 268, etc. may be disposed on the side surface of the second portion 2322. The first portion 2321 and the second portion 2322 may include the same material or different materials. In the final structure, the boundary between the first portion 2321 and the second portion 2322 may be seen or confirmed, or the boundary between the first portion 2321 and the second portion 2322 may not be seen or confirmed.

[0081] The channel region 262 may extend in a direction intersecting the first substrate 210 and be disposed on a side surface of the insulating structure 232a (e.g., a side surface of the insulating structure 232a adjacent to the groove 232t). For example, the channel region 262 may include a side extension portion extending in a direction oblique to or perpendicular to the first surface 2101 or the second surface 2102 of the first substrate 210.

[0082] The insulating structure 232a may include an insulating material such as, for example, an oxide, a nitride, or a nitride oxide. For example, the insulating structure 232a may include an insulating material such as silicon oxide, silicon nitride, or silicon nitride oxide. However, the embodiment is not necessarily limited thereto, and the material of the insulating structure 232a may be modified.

[0083] In an embodiment, the channel region 262 may be or include a first semiconductor layer including a semiconductor material. The channel region or the first semiconductor layer may be a layer separated from the first substrate 210 and have a material or crystal structure different from that of the first substrate 210. The first semiconductor layer of the channel region 262 may have the same first conductivity type (e.g., p-type or n-type) as the body region 210b of the first substrate 210. The dopant included in the channel region 262 may be the same as or different from the dopant included in the body region 210b of the first substrate 210. For example, the p-type dopant may include boron, gallium, etc., and the n-type dopant may include phosphorus, arsenic, etc. For example, the channel region 262 may be or include a polycrystalline semiconductor layer having a first conductivity type. For example, the channel region 262 may include polycrystalline silicon, polycrystalline germanium, polycrystalline silicon germanium, etc.

[0084] The embodiments are not necessarily limited to the material of the channel region 262 , the crystal structure of the channel region 262 , the dopant doped into the channel region 262 , and the like.

[0085] The source region and the drain region of the first transistor 260 may be respectively electrically connected to the channel region 262. In an embodiment, the first region 264a as one of the source region and the drain region of the first transistor 260 and the second region 264b as the other of the source region and the drain region of the first transistor 260 may have different materials or different crystal structures.

[0086] For example, the first region 264a may be or include a second semiconductor layer including a semiconductor material. The first region 264 or the second semiconductor layer may be a layer separated from the first substrate 210 and have a material or crystal structure different from that of the first substrate 210. Here, the second semiconductor layer of the first region 264a may have a second conductivity type (e.g., n-type or p-type) opposite to the channel region 262. For example, the first region 264a may be or include a polycrystalline semiconductor layer having a second conductivity type. For example, the first region 264a may include polycrystalline silicon, polycrystalline germanium, polycrystalline silicon germanium, etc.

[0087] The first semiconductor layer of the channel region 262 and the second semiconductor layer of the first region 264a may be connected to each other and have a layer shape. The first semiconductor layer of the channel region 262 and the second semiconductor layer of the first region 264a may include the same semiconductor material and may have substantially similar thicknesses. For example, the thickness difference between the first semiconductor layer of the channel region 262 and the second semiconductor layer of the first region 264a may be about 10% or less of the thickness of the first semiconductor layer of the channel region 262 or the second semiconductor layer of the first region 264a.

[0088] The channel region 262 and the first region 264a may have the same material and the same crystal structure while having opposite conductivity types to each other. The first region 264a may be formed by doping a dopant having a conductivity type opposite to that of the channel region 262. For example, the channel region 262 may include a polycrystalline semiconductor material (e.g., polysilicon) having a p-type, and the first region 264a may include a polycrystalline semiconductor material (e.g., polysilicon) having an n-type.

[0089] The second region 264b may be adjacent to the first substrate 210 and may be or include a partial portion of the first substrate 210. Therefore, the second region 264b may have the same conductivity type as the first region 264a while having a different material or a different crystal structure than the first region 264a.

[0090] In an embodiment, the thickness of the channel region 262 or the thickness of the first region 264a may be less than the thickness of the first substrate 210. The thickness of the channel region 262 or the thickness of the first region 264a may be the minimum thickness measured in a direction perpendicular to the side surface 232s or the upper surface 232u of the insulating structure 232a. The thickness of the first substrate 210 may be the minimum thickness measured in a direction perpendicular to the first substrate 210 (Z-axis direction). For example, the thickness of the channel region 262 or the thickness of the first region 264a may be 200nm or less. Thus, the manufacturing time of the channel region 262 or the first region 264a may be reduced. However, the embodiment is not necessarily limited thereto, and the thickness of the channel region 262 or the thickness of the first region 264a may be greater than 200nm.

[0091] The thickness of the channel region 262 or the thickness of the first region 264a may be different from the thickness of the second region 264b. The thickness of the second region 264b may be the maximum thickness measured in a direction perpendicular to the first substrate 210 (Z-axis direction). This is because the channel region 262 or the first region 264a is in the semiconductor layer, and the second region 264b is in the first substrate 210. For example, the thickness of the channel region 262 or the thickness of the first region 264a may be less than the thickness of the second region 264b. Thus, the manufacturing time of the channel region 262 or the first region 264a can be reduced, and the second region 264b can be stably formed to have a sufficient size. However, the embodiment is not necessarily limited thereto. In some embodiments, the thickness of the channel region 262 or the thickness of the first region 264a may be the same as or greater than the thickness of the second region 264b.

[0092] In an embodiment, the semiconductor layer may be disposed on the side surface 232s and the upper surface 232u of the insulating structure 232a. The first region 264a or the second semiconductor layer may be disposed on the upper surface 232u of the insulating structure 232a, and the channel region 262 or the first semiconductor layer may be disposed adjacent to the side surface 232s of the insulating structure 232a.

[0093] The channel region 262 or the first semiconductor layer may extend from a first side adjacent to the upper surface 232u of the insulating structure 232a to a second side adjacent to the first substrate 210 on the insulating structure 232a. For example, the bottom end of the channel region 262 may contact the first substrate 210. The first side of the channel region 262 may be connected to a first region 264a on the upper surface 232u of the insulating structure 232a, and the second side of the channel region 262 may be connected to one surface of the first substrate 210 or a second region 264b.

[0094] In an embodiment, the second region 264b may include a low concentration region 2642 having a relatively low doping concentration and a contact region 2641 having a doping concentration higher than that of the low concentration region 2642. The contact region 2641 may be a region having a relatively high doping concentration and may be referred to as a high concentration region. The second contact 234b may be connected to the contact region 2641, thereby reducing the contact resistance of the second contact 234b. The low concentration region 2642 may be formed in a region other than the contact region 2641. Therefore, a depletion region may be stably formed, and the performance of the first transistor 260 may be enhanced. In an embodiment, the second side of the channel region 262 may be connected to the low concentration region 2642.

[0095] The first gate insulating layer 266 may be disposed adjacent to the channel region 262. For example, the first gate insulating layer 266 may be in contact with the channel region 262. The first gate insulating layer 266 may include at least one of an oxide, a nitride, an oxynitride, a high dielectric constant material having a higher dielectric constant than silicon oxide, a low dielectric constant material having a lower dielectric constant than silicon oxide, or a combination thereof. For example, the first gate insulating layer 266 may include at least one of silicon oxide, silicon nitride, silicon oxynitride, hafnium oxide, aluminum oxide, and tantalum oxide. The first gate insulating layer 266 may include an insulating layer or multiple insulating layers.

[0096] In the accompanying drawings, it is shown as an example that the first gate insulating layer 266 can be disposed on the entire area of ​​the upper surface 232u including the first substrate 210, the channel region 262, the first region 264a, and the insulating structure 232a. Thus, the first gate insulating layer 266 can be formed without an additional patterning process. However, the embodiment is not necessarily limited to this. In some embodiments, the first gate insulating layer 266 can be disposed on a local portion of the area of ​​the upper surface 232u including the first substrate 210, the channel region 262, the first region 264a, and the insulating structure 232a. Although the boundaries of the first gate insulating layer 266 are shown in the drawings for clear understanding, the boundaries of the first gate insulating layer 266 may not be seen or confirmed in the final structure.

[0097] In an embodiment, the channel region 262 of the first transistor 260 may include a portion (e.g., a side extension portion) at least partially surrounded by the insulating structure 232a and the first gate insulating layer 266. For example, four outer surfaces of a local portion (i.e., the side extension portion) of the channel region 262 on the side surface 232s of the insulating structure 232a may be surrounded by the insulating structure 232a and the first gate insulating layer 266.

[0098] The first gate electrode 268 may be disposed on the first gate insulating layer 266 disposed on the channel region 262. The first gate electrode 268 may extend in a direction intersecting the first substrate 210 on the channel region 262 and the first gate insulating layer 266 located on the side surface 232s of the insulating structure 232a (e.g., the side surface of the insulating structure 232a adjacent to the groove 232t). For example, the first gate electrode 268 may include a side extension portion extending in a direction oblique to or perpendicular to the first surface 2101 or the second surface 2102 of the first substrate 210.

[0099] The first gate electrode 268 may include a conductive material. For example, the first gate electrode 268 may include at least one of a metal, a metal alloy, a metal nitride, a metal silicide, and a doped semiconductor material. Here, the metal or metal alloy included in the first gate electrode 268 may include at least one of titanium, tungsten, molybdenum, aluminum, copper, cobalt, tantalum, and ruthenium. The metal nitride included in the first gate electrode 268 may include at least one of titanium nitride, tungsten nitride, molybdenum nitride, and tantalum nitride. The first gate electrode 268 may further include a metal oxide or a metal oxynitride in which the above materials are oxidized. The doped semiconductor material may include a semiconductor material (e.g., a polycrystalline semiconductor material) doped with an n-type or p-type dopant.

[0100] The interlayer insulating layer 232m may be disposed on the insulating structure 232a, the channel region 262 and the first region 264a, the first gate insulating layer 266, and the first gate electrode 268 disposed on the first substrate 210. The contact path 234 may penetrate the first gate insulating layer 266 and / or the interlayer insulating layer 232m. The contact path 234 may include a gate contact 234g connected to the first gate electrode 268, a first contact 234a connected to the first region 264a, and a second contact 234b connected to the second region 264b. The contact path 234 may further include a body contact 234c connected to the first substrate 210. The first wiring layer 2361 connected to the contact path 234 connected to the first transistor 260 may be disposed on the interlayer insulating layer 232m.

[0101] In the first transistor region A1, the first wiring layer 2361 may include a first electrode wiring connected to the first region 264a through a first contact 234a, a second electrode wiring connected to the second region 264b through a second contact 234b, and a first gate electrode wiring connected to the first gate electrode 268 through a gate contact 234g.

[0102] One or more interlayer insulating layers 232 m and one or more second wiring layers 2362 may be further provided on the first wiring layer 2361 .

[0103] In a plan view, the gate contact 234g connected to the first gate electrode 268 may be disposed at a first position ( Figure 5 ), and the first contact 234a connected to the first region 264a and the second contact 234b connected to the second region 264b may be disposed at a second position (X-axis direction) different from the first position. Figure 5 Thus, the gate contact 234g, the first contact 234a, and the second contact 234b can be stably positioned.

[0104] In an embodiment, the first region 264a as a local portion of the semiconductor layer in the first transistor 260 may be a source region, and the second region 264b as a local portion of the first substrate 210 may be a drain region. In this case, the through-plug 188 connected to the gate line 130 may be electrically connected to the first region 264a. However, the embodiment is not necessarily limited thereto.

[0105] For example, the second region 264b may be shared by a pair of first transistors 260a and 260b adjacent to each other in one direction (Y-axis direction). For example, one second region 264b may be included in a pair of first transistors 260a and 260b, and the pair of first transistors 260a and 260b may have a symmetrical structure in one direction (Y-axis direction). Thus, the size of the second transistor 270 may be effectively reduced.

[0106] The trench 210t may be provided in the second transistor region A2 provided with the second transistor 270, and the first insulating layer 232 may fill the trench 210t. In an embodiment, the trench 210t filled with the first insulating layer 232 may be a device separation portion or a shallow trench isolation separating the second transistor 270.

[0107] The first insulating layer 232 in the second transistor region A2 may include an insulating material. For example, the first insulating layer 232 may include an insulating material such as an oxide, a nitride, or a nitride oxide. For example, the first insulating layer 232 may include an insulating material such as silicon oxide, silicon nitride, or silicon nitride oxide. However, the embodiment is not necessarily limited thereto, and the material of the first insulating layer 232 may be modified.

[0108] In the accompanying drawings, it is shown as an example that the second width of the trench 210t in the second transistor region A2 is smaller than the first width of the trench 210t in the first transistor region A1. Thus, in the first transistor region A1 where the first transistor 260 of the high voltage transistor is located, the active region of the first transistor can be stably separated. However, the embodiment is not necessarily limited to this. In some embodiments, the first width of the trench 210t in the first transistor region A1 can be equal to or smaller than the second width of the trench 210t in the second transistor region A2.

[0109] In an embodiment, the second transistor 270 may include a second gate insulating layer 276, a second gate electrode 278, and a source region 274s and a drain region 274d. The second gate insulating layer 276 may be horizontally disposed on the first substrate 210. The second gate electrode 278 may be horizontally disposed on the second gate insulating layer 276. The source region 274s and the drain region 274d may be disposed at a portion of the first substrate 210 located on both sides of the second gate electrode 278 in a plan view. The second transistor 270 may further include a gate capping layer and / or a gate spacer.

[0110] In the second transistor 270, the channel portion may include or be formed of a local portion of the body region 210b of the first substrate 210 between the source region 274s and the drain region 274d below the second gate electrode 278 and the second gate insulating layer 276. The channel portion of the second transistor 270 may be different from the channel region 262 of the first transistor 260, which is a channel region separated from the first substrate 210 and located on the side surface 232s of the insulating structure 232a.

[0111] The second gate insulating layer 276 may extend horizontally to be parallel to the first surface 2101 or the second surface 2102 of the first substrate 210. The second gate insulating layer 276 may be different from the first gate insulating layer 266 including a portion perpendicular to or inclined to the first surface 2101 or the second surface 2102 of the first substrate 210. The thickness of the second gate insulating layer 276 may be less than the thickness of the first gate insulating layer 266. This is because the first transistor 260 is a high voltage transistor and the second transistor 270 is a low voltage transistor. In some embodiments, the thickness of the second gate insulating layer 276 may be the same as or greater than the thickness of the first gate insulating layer 266.

[0112] The second gate insulating layer 276 may include at least one of oxide, nitride, oxynitride, a high dielectric constant material having a higher dielectric constant than silicon oxide, and a low dielectric constant material having a lower dielectric constant than silicon oxide. For example, the second gate insulating layer 276 may include at least one of silicon oxide, silicon nitride, silicon oxynitride, hafnium oxide, aluminum oxide, and tantalum oxide. The second gate insulating layer 276 may include one insulating layer or may include a plurality of insulating layers.

[0113] The second gate electrode 278 may include a conductive material. For example, the second gate electrode 278 may include at least one of a metal, a metal alloy, a metal nitride, a metal silicide, and a doped semiconductor material. The metal or metal alloy included in the second gate electrode 278 may include at least one of titanium, tungsten, molybdenum, aluminum, copper, cobalt, tantalum, and ruthenium. The metal nitride included in the second gate electrode 278 may include at least one of titanium nitride, tungsten nitride, molybdenum nitride, and tantalum nitride. The second gate electrode 278 may further include a metal oxide or a metal oxynitride in which the above materials are oxidized. The doped semiconductor material may include a semiconductor material doped with an n-type or p-type dopant (e.g., a polycrystalline semiconductor material).

[0114] The gate capping layer may be disposed on the second gate electrode 278, and the gate spacer may be disposed on the side surface of the second gate electrode 278. The gate capping layer may serve as a mask layer in the process of forming the second gate insulating layer 276 and the second gate electrode 278. The gate spacer may be disposed on the side surface of the second gate electrode 278, and insulate the second gate electrode 278 from the source region 274s and the drain region 274d. For example, the gate spacer may be disposed at both side surfaces of the second gate electrode 278 at least in a lateral direction (Y-axis direction) transverse to the extension direction of the second gate electrode 278, and may extend in the extension direction (X-axis direction) of the second gate electrode 278. The gate spacer may be disposed on the side surface of the gate capping layer, or the gate capping layer may be disposed on the gate spacer.

[0115] The gate capping layer or gate spacer may include any of various materials, such as oxide, nitride, oxynitride, etc. For example, the gate capping layer or gate spacer may include at least one of silicon oxide, silicon nitride, and silicon oxynitride. The gate capping layer or gate spacer may include one insulating layer or may include multiple insulating layers.

[0116] However, embodiments are not necessarily limited thereto.The second gate insulating layer 276 , the second gate electrode 278 , the gate capping layer, the gate spacer, and / or the source region 274 s and the drain region 274 d may have any of various materials, structures, and the like.

[0117] The interlayer insulating layer 232m may be disposed on the second gate insulating layer 276 and the second gate electrode 278 disposed on the first substrate 210. The contact path 234 may penetrate the interlayer insulating layer 232m. The contact path 234 may include a gate contact connected to the second gate electrode 278 and a source contact 234s and a drain contact 234d connected to the source region 274s and the drain region 274d. The first wiring layer 2361 connected to the contact path 234 connected to the second transistor 270 may be disposed on the interlayer insulating layer 232m.

[0118] In the second transistor region A2, the first wiring layer 2361 may include a source electrode wiring connected to the source region 274s through the source contact 234s, a drain electrode wiring connected to the drain region 274d through the drain contact 234d, and a second gate electrode wiring connected to the first gate electrode 278 through the gate contact. For example, the first wiring layer 2361 including the source electrode wiring, the drain electrode wiring, and the second gate electrode wiring in the second transistor region A2 may be disposed on the same plane or on the same layer as the first wiring layer 2361 including the first electrode wiring, the second electrode wiring, and the first gate electrode wiring in the first transistor region A1.

[0119] One or more interlayer insulating layers 232 m and one or more second wiring layers 2362 may be further provided on the first wiring layer 2361 .

[0120] In an embodiment, the thickness T1 of the insulating structure 232a, the length L of the side surface 232s of the insulating structure 232a, or the length of the channel region 262 in the first transistor 260 may be greater than the thickness T2 of the second gate electrode 278 in the second transistor 270. Thus, the channel length of the channel region 262 of the first transistor 260 may be sufficiently ensured.

[0121] Here, the thickness T1 of the insulating structure 232a may refer to the thickness of the second portion 2322 on the first surface 2101 of the first substrate 210, in which the groove 210t is not provided. The thickness T1 of the insulating structure 232a may be measured in a direction perpendicular to the first substrate 210 (Z-axis direction). The length L of the side surface 232s of the insulating structure 232a may refer to the minimum length among the lengths measured along the side surface 232s of the insulating structure 232a. The length of the channel region 262 may be the minimum length among the lengths between the first region 264a and the second region 264b or between the first region 264a and the first substrate 210 along the channel region 262. The thickness T2 of the second gate electrode 278 may be the thickness measured in a direction perpendicular to the first substrate 210 (Z-axis direction in the figure).

[0122] In an embodiment, the thickness T1 of the insulating structure 232a, the length L of the side surface 232s of the insulating structure 232a, or the length of the channel region 262 in the first transistor 260 may be greater than the distance between the source region 274s and the drain region 274d (i.e., the length of the channel portion) in the second transistor 270. Thus, the channel length of the channel region 262 of the first transistor 260 may be sufficiently ensured. Here, in the second transistor 270, the length of the channel portion or the distance between the source region 274s and the drain region 274d or the distance between the first region 264a and the first substrate 210 may refer to a minimum distance.

[0123] According to an embodiment, the first transistor 260 as a high voltage transistor has a vertical structure (eg, a vertical channel structure), and thus the size or area of ​​the first transistor 260 may be reduced through three-dimensional (3D) integration. Thus, the integration degree may be improved.

[0124] The second region 264b, which is one of the source region and the drain region of the first transistor 260, may be or include a partial portion of the first substrate 210. Therefore, the first transistor 260 (e.g., the channel region 262) may have a structure coupled or connected to the first substrate 210 having a large volume. Thus, problems caused by the floating body effect may be prevented or suppressed, and punch-through may be prevented from occurring in an off state. Therefore, the performance of the first transistor 260 that generates or transmits a high voltage may be enhanced.

[0125] On the other hand, in a high voltage transistor having a conventional vertical structure, a source region, a channel region, and a drain region may be separated from a semiconductor substrate to form a floating body. Then, in a high voltage transistor that generates or transmits a high voltage, punch-through may occur in an off state through a depletion region, and therefore, the high voltage transistor may not be suitable for driving as a high voltage transistor.

[0126] In an embodiment, a semiconductor device 10 including a cell region 100 having a memory cell structure may include a circuit region 200 including a first substrate 210, a first transistor 260, and a second transistor 270. For example, the semiconductor device 10 including the circuit region 200 according to an embodiment may be a flash memory device. This is because the high voltage transistor or the first transistor 260 of the flash memory device is operated by a higher voltage than the transistor of another memory device or another semiconductor device. Therefore, in a flash memory device including a high voltage transistor or the first transistor 260 operated by a large operating voltage, performance and integration can be improved. For example, the first transistor 260 may be included in a flash memory device including a large number of gate lines 130 and the first transistor 260 to increase data storage capacity, thereby greatly improving integration.

[0127] In the drawings, it is shown as an example that the extension direction of the first gate electrode 268 or the second gate electrode 278 (the X-axis direction in the drawings) is perpendicular to the extension direction of the gate line 130. In addition, it is shown as an example that the direction in which the source region 274s and the drain region 274d are positioned or the direction in which the first region 264a and the second region 264b are positioned (the Y-axis direction) is parallel to the extension direction of the gate line 130. However, the embodiment is not necessarily limited to this. In some embodiments, the extension direction (X-axis) of the first gate electrode 268 or the second gate electrode 278 may be parallel to the extension direction of the gate line 130, and the direction in which the source region 274s and the drain region 274d are positioned or the direction in which the first region 264a and the second region 264b are positioned (the Y-axis direction) may be transverse to the extension direction of the gate line 130.

[0128] Will combine Figures 1 to 5 Reference Figures 6 to 12 An example of a method for manufacturing the semiconductor device 10 having the above structure is described in detail. To the extent that an element is not described in detail below, it is understood that the element is at least similar to a corresponding element that has been described elsewhere in the present disclosure. Parts not described above will be described in detail below.

[0129] Figures 6 to 12 is a cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment. Figures 6 to 12 , the first transistor 260 in the circuit region 200 of the semiconductor device 10 is mainly shown, and a method for manufacturing the first transistor 260 in the circuit region 200 of the semiconductor device 10 will be mainly described below.

[0130] like Figure 6 As shown, a plurality of first transistors 260 (see FIG. 2 ) may be formed on the first surface 2101 of the first substrate 210 to expose the first transistors 260. Fig.10 ). The first mask layer 240a of the boundary of the first substrate 210 is formed by etching a local portion of the first substrate 210 using the first mask layer 240a at the first surface 2101 of the first substrate 210. During the etching process, a process such as dry etching may be applied. In this case, the first substrate 210 may be composed of or include a body region 210b having a first conductivity type.

[0131] Then, if Figure 7 As shown, an insulating structure 232a including a first portion 2321 filling the trench 210t may be formed. The insulating structure 232a may include a first portion 2321 filling the trench 210t of the first substrate 210 and a second portion 2322 disposed on the first surface 2101 of the first substrate 210 with a predetermined thickness.

[0132] In an embodiment, a process for forming the first portion 2321 filling the groove 210t of the first substrate 210 and a process for forming the second portion 2322 may be performed separately. For example, an insulating material layer may be formed and the groove 210t of the first substrate 210 may be filled. Then, a chemical mechanical polishing process may be performed and the first portion 2321 may be formed. The first mask layer 240a may be removed during the chemical mechanical polishing process, but the embodiment is not necessarily limited thereto. An insulating material layer may be formed on the first substrate 210 to form the second portion 2322. In some embodiments, after the second portion 2322 is formed, a chemical mechanical polishing process may be performed.

[0133] As a process for forming the insulating material layer, any of various processes, for example, a deposition process (for example, chemical vapor deposition or physical vapor deposition) or the like may be used.

[0134] In an embodiment, between the process of forming the first portion 2321 and the process of forming the second portion 2322, a process of forming the second region 264b of the first transistor 260 may be performed. The second region 264b may be formed by doping a second conductive type dopant into a local portion of the first substrate 210. However, the process is not necessarily limited thereto, and the process of forming the second region 264b may be performed by any of a variety of doping processes. For example, the second region 264b may be formed after the process of forming the groove 232t.

[0135] Then, if Figure 8 As shown, a second mask layer 240b exposing a region of the first substrate 210 between the trenches 210t of the first substrate 210 may be formed on the insulating structure 232a. The recess 232t may be formed by etching a local portion of the insulating structure 232a using the second mask layer 240b disposed at an upper portion of the insulating structure 232a. During the etching process, a process such as dry etching may be applied.

[0136] exist Figure 7 and Figure 8 2 shows as an example that the entire second portion 2322 is formed and then the groove 232t is formed by a patterning process, but the embodiment is not necessarily limited thereto. For example, the second portion 2322 having the groove 232t may be formed during the process of forming the second portion 2322.

[0137] Then, if Fig. 9 As shown, a channel region 262 and a first region 264 a of a first transistor 260 may be formed.

[0138] In an embodiment, a semiconductor layer may be formed on the upper surface 232u and the side surface 232s of the insulating structure 232a, and a portion of the first surface 2101 of the first substrate 210 is exposed by the groove 232t. For example, the semiconductor layer may also be formed by a method such as deposition. Then, a portion other than the region corresponding to the channel region 262 and the first region 264a may be etched, and thus, a portion of the semiconductor layer corresponding to the channel region 262 and the first region 264a may be retained. For example, the semiconductor layer may be patterned by dry etching using a mask layer. However, embodiments are not necessarily limited thereto.

[0139] Through the patterning process, the semiconductor layer may include a portion on the upper surface 232u and the side surface 232s of the insulating structure 232a on one side of the groove 232t and another portion on the upper surface 232u and the side surface 232s of the insulating structure 232a on the other side of the groove 232t. Thus, the portion on one side of the groove 232t may be included in one first transistor 260, and the other portion on the other side of the groove 232t may be included in another first transistor 260. Therefore, the process may be simplified and the size of the first transistor 260 may be reduced.

[0140] For example, a first semiconductor layer having a first conductive type dopant is formed in a process of forming a semiconductor layer, and then, the first region 264a may be formed by doping a second conductive type dopant into a local portion corresponding to the first region 264a. The remaining portion of the first semiconductor layer not doped with the second conductive type dopant may constitute the channel region 262. Thus, the properties of the channel region 262 may be maintained and the process may be simplified. However, the embodiment is not necessarily limited thereto.

[0141] In some embodiments, a second semiconductor layer having a second conductive type dopant is formed in a process of forming a semiconductor layer, and then the channel region 262 may be formed by doping a first conductive type dopant into a local portion corresponding to the channel region 262. In some embodiments, after an undoped semiconductor layer (e.g., a semiconductor layer not including a dopant) is formed in a process of forming a semiconductor layer, the channel region 262 and the first region 264a may be formed by doping a first conductive type dopant into a local portion corresponding to the channel region 262 and doping a second conductive type dopant into a local portion corresponding to the first region 264a.

[0142] Then, if Fig.10 As shown, a first gate insulating layer 266 and a first gate electrode 268 may be formed.

[0143] The first gate insulating layer 266 may be formed on the first surface 2101 of the first substrate 210 and cover the insulating structure 232a, the channel region 262 and the first region 264a. The first gate insulating layer 266 may be formed by deposition or the like.

[0144] The first gate electrode 268 may be formed on the first gate insulating layer 266. The entire first gate electrode 268 may be formed, and then the portion other than the portion on the side surface 232s of the insulating structure 232a may be removed by a patterning process. Thus, the first gate electrode 268 may be formed on the channel region 262, and the first gate insulating layer 266 may be formed on the side surface 232s of the insulating structure 232a. The first gate electrode 268 may be formed by methods such as deposition, electroplating, etc. The patterning process of the first gate electrode 268 may be performed by dry etching using a mask layer. However, the embodiment is not necessarily limited thereto.

[0145] Then, if Fig.11 As shown, an interlayer insulating layer 232m located on the insulating structure 232a and filling the groove 232t may be formed on the first gate insulating layer 226. For example, an insulating material may be formed and fill the groove 232t. Then, a chemical mechanical polishing process may be performed and the interlayer insulating layer 232m may be formed.

[0146] A contact via 234 penetrating the first gate insulating layer 266 and / or the interlayer insulating layer 232m and a first wiring layer 2361 connected to the contact via 234 may be formed. In this case, the contact via 234 may include a gate contact 234g connected to the first gate electrode 268 (refer to Figure 4 ), a first contact 234a connected to the first region 264a, and a second contact 234b connected to the second region 264b. The contact path 234 may further include a body contact 234c connected to the first substrate 210. For example, the contact path 234 may be formed by filling a conductive material into the penetration portion. For example, the first wiring layer 2361 may be formed by forming another interlayer insulating layer 232m exposing the contact path 234 and then performing a chemical mechanical polishing process. However, the embodiment is not necessarily limited thereto, and modifications are possible.

[0147] Then, if Fig.12 As shown, the first wiring portion 230 may be formed by further forming one or more interlayer insulating layers 232 m and one or more second wiring layers 2362 disposed on the first wiring layer 2361 .

[0148] In the following, reference Figures 13 to 15, semiconductor devices according to other embodiments different from the above-described embodiments will be described in more detail. To the extent that an element is not described in detail below, it is understood that the element is at least similar to a corresponding element that has been described elsewhere in the present disclosure. The parts not described above will be described in detail below.

[0149] Fig.13 1 is an enlarged plan view showing a partial portion of a semiconductor device according to an embodiment. Fig.13 In the figure, it is shown that Figure 3 The part corresponding to the part shown in .

[0150] Reference Fig.13 In the first transistor 260 according to the embodiment, the second region 264b may include a contact region 2641 locally formed and corresponding to the second contact 234b, but does not include a low concentration region 2642 (refer to Figure 3 ). In this example, the channel region 262 of the first transistor 260 may be connected to the body region 210 b of the first substrate 210. Thus, the size or area of ​​the doping region of the first substrate 210 may be reduced.

[0151] Fig.14 1 is an enlarged plan view showing a partial portion of a semiconductor device according to an embodiment. Fig.14 In the figure, it is shown that Figure 3 The part corresponding to the part shown in .

[0152] Reference Fig.14 In the embodiment, each of the gate contacts 234g (refer to Figure 4 ), a first wiring layer 2361 connected to the first gate electrode 268, the first region 264a, and the second region 264b of the first contact 234a and the second contact 234b may be included in the first transistor 260. In the first transistor region A1, the first wiring layer 2361 may be a wiring layer disposed closest to the first transistor 260 among the plurality of wiring layers 236. For example, in the first transistor region A1, the first wiring layer 2361 may be disposed below the second wiring layer 2362.

[0153] In the first transistor region A1, the first wiring layer 2361 may include a first electrode wiring connected to the first region 264a through a first contact 234a, a second electrode wiring connected to the second region 264b through a second contact 234b, and a first gate electrode wiring connected to the first gate electrode 268 through a gate contact 234g.

[0154] In the second transistor region A2, an additional wiring layer 2364 may be provided between the first wiring layer 2361 and the second transistor 270. The first wiring layer 2361 in the second transistor region A2 may be disposed on the same layer or the same plane as the first wiring layer 2361 in the first transistor region A1. Therefore, among the plurality of wiring layers 236 in the second transistor region A2, the additional wiring layer 2364 may be disposed closer to the second transistor 270 than the first wiring layer 2361. For example, the additional wiring layer 2364 in the second transistor region A2 may be disposed below the first wiring layer 2361.

[0155] In the second transistor region A2, the additional wiring layer 2364 may include a source electrode wiring connected to the source region 274s through the source contact 234s, a drain electrode wiring connected to the drain region 274d through the drain contact 234d, and a second gate electrode wiring connected to the second gate electrode 278 through the gate contact. For example, in an embodiment, the additional wiring layer 2364 including the source electrode wiring, the drain electrode wiring, and the second gate electrode wiring in the second transistor region A2 may be a layer different from the first wiring layer 2361 including the first electrode wiring, the second electrode wiring, and the first gate electrode wiring in the transistor region A1.

[0156] The thickness of the second gate electrode 278 of the second transistor 270 may be smaller than the thickness of the insulating structure 232a included in the first transistor 260. Therefore, the additional wiring layer 2364 may be disposed between the second transistor 270 and the first wiring layer 2361, thereby improving the integration degree of the wiring layer 236.

[0157] Fig.15 is a cross-sectional view schematically showing a semiconductor device 20 according to an embodiment.

[0158] Reference Fig.15 , the semiconductor device 20 according to the embodiment may have a chip-to-chip (C2C) structure bonded by a wafer bonding type. For example, a lower chip including a circuit region 200a having a first substrate 210 may be manufactured, an upper chip including a cell region 100a having a second substrate 110a may be manufactured, and then the semiconductor device 20 may be manufactured by bonding the lower chip and the upper chip.

[0159] The circuit region 200a may include a first substrate 210, a circuit element 220, a first wiring portion 230, and a first bonding structure 240 electrically connected to the first wiring portion 230 at a surface facing the cell region 100a. A region other than the first bonding structure 240 at a surface facing the cell region 100a may be covered by a first insulating layer 232.

[0160] The cell region 100a may include a second substrate 110a, a gate stack structure 120, a channel structure CH, a second wiring portion 180, and a second bonding structure 194 electrically connecting the second wiring portion 180 at a surface facing the circuit region 200a. A region other than the second bonding structure 194 may be covered by an insulating layer 196.

[0161] In an embodiment, the second substrate 110a may be a semiconductor substrate including a semiconductor material. For example, the second substrate 110a may be a semiconductor substrate of a semiconductor material, or may be a semiconductor substrate in which a semiconductor layer is on a base substrate. For example, the second substrate 110a may include single crystal or polycrystalline silicon, germanium, silicon germanium, silicon on insulator, germanium on insulator, etc. In some embodiments, the second substrate 110a may be a support member including an insulating layer or an insulating material. This is because the semiconductor substrate provided in the cell region 100a may be removed after the cell region 100a is bonded to the circuit region 200a and the support member including the insulating layer, or an insulating material may be formed.

[0162] In an embodiment, the gate stack structure 120 may be sequentially stacked on a lower portion of the second substrate 110a in the drawings, and may have a structure such as Figure 1 The gate stack structure 120 shown in FIG. 1 is arranged in a vertically inverted manner. The channel structure CH penetrating the gate stack structure 120 may have a structure in which Figure 2 The channel structure CH shown is arranged in a vertically inverted manner. Therefore, in the cross-sectional view, the channel structure CH may have an inclined side surface so that the width of the channel structure CH decreases as the channel structure CH moves from the circuit region 200a toward the second substrate 110a. The upper portion ( Fig.15 The channel pad 144 and the second wiring portion 180 at a lower portion (in the middle) may be disposed adjacent to the circuit region 200a.

[0163] For example, the first bonding structure 240 and / or the second bonding structure 194 may include aluminum, copper, tungsten, or an alloy containing aluminum, copper, or tungsten. For example, the first bonding structure 240 and the second bonding structure 194 may include copper, so that the cell region 100a and the circuit region 200a may be bonded to each other (e.g., directly bonded) by copper-to-copper bonding.

[0164] exist Fig.15 In the embodiment, the gate stack structure 120 includes a plurality of gate stack structures as an example. However, it is not necessarily limited thereto. In some embodiments, the gate stack structure 120 may include one gate stack structure or three or more gate stack structures. Unless otherwise specified, the reference 120 may be applied as is. Figure 1 and Figure 2The gate stack structure 120 and the channel structure CH are described in detail. Fig.15 In the figure, the electrical connection structure between the channel structure CH and the horizontal conductive layers 112 and 114 and / or the second substrate 110 is shown as an example. Figure 2 However, the embodiment is not necessarily limited thereto, and the electrical connection structure between the channel structure CH and the horizontal conductive layers 112 and 114 and / or the second substrate 110 may be modified.

[0165] The semiconductor device 20 according to the embodiment may include an input / output pad and a through plug or input / output connection wiring electrically connected to the input / output pad. The through plug or the input / output connection wiring may be electrically connected to a portion of the second bonding structure 194. For example, the input / output pad may be provided on an insulating layer covering the outer surface of the second substrate 110a. In some embodiments, an additional input / output pad electrically connected to the circuit region 200a may be provided.

[0166] In an embodiment, the circuit region 200a may include a first transistor 260 and a second transistor 270. The first region 264a of the first transistor 260 may be electrically connected to the gate contact portion 184 through the first wiring portion 230, the second bonding structure 240, and the second bonding structure 194. According to an embodiment, the first transistor 260 may be formed without a through plug 188 (see FIG. 1 ). Figure 1 ) is connected to the gate contact portion 184, thereby simplifying the structure. Unless otherwise specified, refer to Figures 1 to 12 The description of the structure of the circuit region 200 described may be applied to the circuit region 200 a as it is.

[0167] For example, the circuit region 200a and the unit region 100a may be respectively Fig.16 The electronic system 1000 shown in FIG. 1 includes a first structure 1100F and a second structure 1100S of the semiconductor device 1100. In some embodiments, the circuit region 200a and the unit region 100a may include Fig.19 Regions of a first structure 4100 and a second structure 4200 of a semiconductor chip 2200 a are shown.

[0168] Hereinafter, an example of an electronic system including a semiconductor device will be described in detail.

[0169] Fig.16 is a view schematically illustrating an electronic system including a semiconductor device according to an embodiment.

[0170] Reference Fig.16, an electronic system 1000 according to an embodiment may include a semiconductor device 1100 and a controller 1200 electrically connected to the semiconductor device 1100. The electronic system 1000 may be a storage device including one or more semiconductor devices 1100 or an electronic device including a storage device. For example, the electronic system 1000 may be a solid state drive (SSD) device, a universal serial bus (USB), a computing system, a medical device, or a communication device including one or more semiconductor devices 1100.

[0171] The semiconductor device 1100 may be a nonvolatile memory device, such as, for example, a Figures 1 to 15 The NAND flash memory device described herein. The semiconductor device 1100 may include a first structure 1100F and a second structure 1100S disposed on the first structure 1100F. In some embodiments, the first structure 1100F may be disposed next to the second structure 1100S. The first structure 1100F may be a peripheral circuit structure including a decoder circuit 1110, a page buffer 1120, and a logic circuit 1130. The second structure 1100S may be a memory cell structure including a bit line BL, a common source line CSL, a word line WL, a first gate upper line UL1 and a second gate upper line UL2, a first gate lower line LL1 and a second gate lower line LL2, and a memory cell string CSTR disposed between the bit line BL and the common source line CSL.

[0172] In the second structure 1100S, each memory cell string CSTR may include lower transistors LT1 and LT2 disposed adjacent to a common source line CSL, upper transistors UT1 and UT2 disposed adjacent to a bit line BL, and a plurality of memory cell transistors MCT disposed between the lower transistors LT1 and LT2 and the upper transistors UT1 and UT2. The number of the lower transistors LT1 and LT2 and the number of the upper transistors UT1 and UT2 may be modified according to the embodiment.

[0173] In an embodiment, the lower transistors LT1 and LT2 may include ground selection transistors, and the upper transistors UT1 and UT2 may include string selection transistors. The first gate lower line LL1 and the second gate lower line LL2 may be gate lines of the lower transistors LT1 and LT2, respectively. The word line WL may be a gate line of the memory cell transistor MCT, and the gate upper lines UL1 and UL2 may be gate lines of the upper transistors UT1 and UT2, respectively.

[0174] The common source line CSL, the first and second gate lower lines LL1 and LL2, the word line WL, and the first and second gate upper lines UL1 and UL2 may be electrically connected to the decoder circuit 1110 through the first connection wiring 1115 extending from the first structure 1100F toward the second structure 1100S. The bit line BL may be electrically connected to the page buffer 1120 through the second connection wiring 1125 extending from the first structure 1100F toward the second structure 1100S.

[0175] In the first structure 1100F, the decoder circuit 1110 and the page buffer 1120 may perform a control operation on at least one memory cell transistor selected from a plurality of memory cell transistors MCT. The decoder circuit 1110 and the page buffer 1120 may be controlled by a logic circuit 1130. The semiconductor device 1100 may communicate with the controller 1200 through an input / output pad 1101 electrically connected to the logic circuit 1130. The input / output pad 1101 may be electrically connected to the logic circuit 1130 through an input / output connection wiring 1135 extending from the first structure 1100F to the second structure 1100S.

[0176] The controller 1200 may include a processor 1210 , a NAND controller 1220 , and a host interface 1230 . According to an embodiment, the electronic system 1000 may include a plurality of semiconductor devices 1100 , and in this case, the controller 1200 may control the plurality of semiconductor devices 1100 .

[0177] The processor 1210 may control the overall operation of the electronic system 1000 including the controller 1200. The processor 1210 may operate according to a predetermined firmware, and may access the semiconductor device 1100 by controlling the NAND controller 1220. The NAND controller 1220 may include a NAND interface 1221 that processes communication with the semiconductor device 1100. A control command for controlling the semiconductor device 1100, data to be written into the memory cell transistor MCT of the semiconductor device 1100, and data to be read from the memory cell transistor MCT of the semiconductor device 1100, etc. may be sent through the NAND interface 1221. The host interface 1230 may provide a communication function between the electronic system 1000 and an external host. When a control command is received from the external host through the host interface 1230, the processor 1210 may control the semiconductor device 1100 in response to the control command.

[0178] Fig.17 is a perspective view schematically showing an electronic system including a semiconductor device according to an embodiment.

[0179] Reference Fig.17, an electronic system 2000 according to an embodiment may include a main substrate 2001, a controller 2002 disposed on the main substrate 2001, one or more semiconductor packages 2003, and a dynamic random access memory (DRAM) 2004. The semiconductor package 2003 and the DRAM 2004 may be connected to the controller 2002 through a wiring pattern 2005 at the main substrate 2001.

[0180] The main substrate 2001 may include a connector 2006 including a plurality of pins connected to an external host. The number and arrangement of the plurality of pins in the connector 2006 may vary according to the communication interface between the electronic system 2000 and the external host. In an embodiment, the electronic system 2000 may communicate with the external host according to any one of interfaces such as a universal serial bus (USB), a peripheral component interconnect fast (PCI-Express), a serial advanced technology attachment (SATA), and M-Phy for universal flash memory (UFS). In an embodiment, the electronic system 2000 may be operated by power supplied from an external host through the connector 2006. The electronic system 2000 may further include a power management integrated circuit (PMIC) that distributes power supplied from an external host to the controller 2002 and the semiconductor package 2003.

[0181] The controller 2002 may write data in the semiconductor package 2003 or may read data from the semiconductor package 2003 , and may increase the operation speed of the electronic system 2000 .

[0182] The DRAM 2004 may be a buffer memory for alleviating or buffering a speed difference between the semiconductor package 2003 and an external host as a data storage space. The DRAM 2004 included in the electronic system 2000 may also be a high-speed cache memory, and may also provide a space for temporarily storing data in a control operation of the semiconductor package 2003. When the electronic system 2000 includes the DRAM 2004, the controller 2002 may further include a DRAM controller for controlling the DRAM 2004 in addition to the NAND controller for controlling the semiconductor package 2003.

[0183] The semiconductor package 2003 may include a first semiconductor package 2003a and a second semiconductor package 2003b spaced apart from each other. Each of the first semiconductor package 2003a and the second semiconductor package 2003b may be a semiconductor package 2003 including a plurality of semiconductor chips 2200. Each of the first semiconductor package 2003a and the second semiconductor package 2003b may include a package substrate 2100, a semiconductor chip 2200 disposed on the package substrate 2100, an adhesive layer 2300 disposed at a lower surface of each semiconductor chip 2200, a connection structure 2400 electrically connecting the semiconductor chip 2200 and the package substrate 2100, and a mold layer 2500 at least partially covering the semiconductor chip 2200 and the connection structure 2400 on the package substrate 2100.

[0184] The package substrate 2100 may be a printed circuit board including a package upper pad 2130. Each semiconductor chip 2200 may include an input / output pad 2210. The input / output pad 2210 may correspond to Fig.16 Each semiconductor chip 2200 may include a gate stack structure 3210 and a channel structure 3220. The semiconductor chip 2200 may include a reference Figures 1 to 15 A semiconductor device is described.

[0185] In an embodiment, the connection structure 2400 may be a bonding wire electrically connecting the input / output pad 2210 and the package upper pad 2130. Therefore, in each of the first semiconductor package 2003a and the second semiconductor package 2003b, the semiconductor chips 2200 may be electrically connected to each other using a bonding wire type, and the semiconductor chips 2200 may be electrically connected to the package upper pad 2130 of the package substrate 2100. According to an embodiment, in each of the first semiconductor package 2003a and the second semiconductor package 2003b, the semiconductor chips 2200 may be electrically connected to each other through a connection structure including a through silicon via (TSV) instead of using a connection structure 2400 of a bonding wire type.

[0186] In an embodiment, the controller 2002 and the semiconductor chip 2200 may be included in one package. For example, the controller 2002 and the semiconductor chip 2200 may be mounted on a separate interposer substrate different from the main substrate 2001, and the controller 2002 and the semiconductor chip 2200 may be connected to each other through wiring at the interposer substrate.

[0187] Fig.18 and Fig.19 Each is a cross-sectional view schematically showing a semiconductor package according to an embodiment. Fig.18 and Fig.19 Described separately Fig.172003, and conceptually illustrates a semiconductor package 2003 cut along line II'. Fig.17 The area obtained by the semiconductor package 2003.

[0188] Reference Fig.18 In the semiconductor package 2003, the package substrate 2100 may be a printed circuit board. The package substrate 2100 may include a package substrate main body portion 2120, a package upper pad 2130 disposed at the upper surface of the package substrate main body portion 2120, a lower pad 2125 disposed at the lower surface of the package substrate main body portion 2120 or exposed through the lower surface of the package substrate main body portion 2120, and an internal wiring 2135 electrically connecting the package upper pad 2130 and the package lower pad 2125 within the package substrate main body portion 2120. The package upper pad 2130 may be electrically connected to the connection structure 2400. The package lower pad 2125 may be connected to the conductive connection portion 2800 as shown in FIG. Fig.17 The electronic system 2000 is shown with a wiring pattern 2005 of a main substrate 2001 .

[0189] The semiconductor chip 2200 may include a semiconductor substrate 3010 and a first structure 3100 and a second structure 3200 sequentially stacked on the semiconductor substrate 3010. The first structure 3100 may include a peripheral circuit region having a peripheral wiring 3110. The second structure 3200 may include a common source line 3205, a gate stack structure 3210 disposed on the common source line 3205, a channel structure 3220 and a separation structure 3230 penetrating the gate stack structure 3210, a bit line 3240 electrically connected to the channel structure 3220, and a word line WL electrically connected to the gate stack structure 3210 (refer to Fig.16 ) of the gate connection wiring.

[0190] In the semiconductor chip 2200 or the semiconductor device according to the embodiment, the performance and integration of the semiconductor chip 2200 or the semiconductor device may be improved by the first transistor 260 having a vertical structure and including a partial portion of a semiconductor substrate or adjacent to the semiconductor substrate.

[0191] Each semiconductor chip 2200 may include a through wiring 3245 electrically connected to the peripheral wiring 3110 of the first structure 3100 and extending into the second structure 3200. The through wiring 3245 may penetrate the gate stack structure 3210, and may be further disposed outside the gate stack structure 3210. Each semiconductor chip 2200 may further include an input / output connection wiring 3265 electrically connected to the peripheral wiring 3110 of the first structure 3100 and extending into the second structure 3200, and an input / output pad 2210 electrically connected to the input / output connection wiring 3265.

[0192] In an embodiment, in the semiconductor package 2003, the plurality of semiconductor chips 2200 may be electrically connected to each other through a connection structure 2400 having a bonding wire type. In some embodiments, the plurality of semiconductor chips 2200 or a plurality of parts constituting the plurality of semiconductor chips 2200 may be electrically connected through a connection structure including through silicon vias (TSVs).

[0193] Reference Fig.19 In the semiconductor package 2003A, each semiconductor chip 2200a may include a semiconductor substrate 4010, a first structure 4100 disposed on the semiconductor substrate 4010, and a second structure 4200 disposed on the first structure 4100 and bonded to the first structure 4100 by a wafer bonding type.

[0194] The first structure 4100 may include a peripheral circuit region including a peripheral wiring 4110 and a first bonding structure 4150. The second structure 4200 may include a common source line 4205, a gate stack structure 4210 disposed between the common source line 4205 and the first structure 4100, a channel structure 4220 and a separation structure 4230 penetrating the gate stack structure 4210, and a word line WL electrically connected to the channel structure 4220 and the gate stack structure 4210 (see Fig.16 ) of the first structure 4100. For example, the second bonding structure 4250 may be electrically connected to the channel structure 4220 and the word line WL through a bit line 4240 electrically connected to the channel structure 4220 and a gate connection wiring electrically connected to the word line WL. The first bonding structure 4150 of the first structure 4100 and the second bonding structure 4250 of the second structure 4200 may contact and bond with each other. For example, portions of the first bonding structure 4150 and the second bonding structure 4250 at which the first bonding structure 4150 and the second bonding structure 4250 are bonded may include copper (Cu).

[0195] In the semiconductor chip 2200 a or the semiconductor device according to the embodiment, the performance and integration of the semiconductor chip 2200 a or the semiconductor device may be improved by the first transistor 260 having a vertical structure and including a partial portion of a semiconductor substrate or adjacent to the semiconductor substrate.

[0196] Each semiconductor chip 2200a may further include an input / output pad 2210 and an input / output connection wiring 4265 at a lower portion of the input / output pad 2210. The input / output connection wiring 4265 may be electrically connected to a portion of the second bonding structure 4250.

[0197] In an embodiment, in the semiconductor package 2003A, the plurality of semiconductor chips 2200a may be electrically connected to each other through a connection structure 2400 having a bonding wire type. In some embodiments, the plurality of semiconductor chips 2200a or a plurality of parts constituting the plurality of semiconductor chips 2200a may be electrically connected through a connection structure including through silicon vias (TSVs).

[0198] While some examples have been described in connection with what are presently considered to be some practical embodiments, it is to be understood that the disclosure is not necessarily limited to the disclosed embodiments, and that the disclosure is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.

[0199] This application claims the priority of Korean Patent Application No. 10-2023-0151201 filed on November 3, 2023 in the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference in their entirety.

Claims

1. A semiconductor device, comprising: Semiconductor substrates; as well as A first transistor is disposed on the semiconductor substrate. The first transistor comprises: An insulating structure, disposed on the semiconductor substrate; a channel region disposed on the insulating structure and comprising a first semiconductor layer, wherein the channel region extends in a direction intersecting the semiconductor substrate; a first source region and a first drain region electrically connected to the channel region; a first gate insulating layer, disposed on the channel region; and a first gate electrode, disposed on the first gate insulating layer, The first region as one of the first source region and the first drain region and the second region as the other of the first source region and the first drain region include different materials or have different crystal structures.

2. The semiconductor device according to claim 1, wherein: The first region includes a second semiconductor layer having a conductivity type opposite to that of the channel region, and The second region includes a local portion of the semiconductor substrate.

3. The semiconductor device according to claim 2, wherein: The first semiconductor layer and the second semiconductor layer are connected to each other.

4. The semiconductor device according to claim 1, wherein: The first region is arranged on the insulating structure, wherein the second region is disposed on or at one surface of the semiconductor substrate, and A first side of the channel region is connected to the first region, and a second side of the channel region opposite to the first side of the channel region is connected to the one surface of the semiconductor substrate or the second region.

5. The semiconductor device according to claim 1, wherein: A thickness of the channel region or a thickness of the first region is smaller than a thickness of the second region.

6. The semiconductor device according to claim 1, wherein: The channel region includes a portion at least partially surrounded by the insulating structure and the first gate insulating layer.

7. The semiconductor device according to claim 1, wherein: The channel region or the first gate electrode is inclined or perpendicular to the first surface or the second surface of the semiconductor substrate.

8. The semiconductor device according to claim 1, wherein: The first transistor is one of a pair of first transistors adjacent to each other in one direction, wherein the second region is shared by the pair of first transistors, The pair of first transistors has a symmetrical structure with respect to the second region in the one direction.

9. The semiconductor device according to claim 1, further comprising: a first contact connected to the first region and a second contact connected to the second region, wherein the second region includes a low concentration region and a high concentration region having a doping concentration higher than that of the low concentration region, Wherein the second contact is connected to the high concentration region.

10. The semiconductor device according to claim 9, wherein The channel region is connected to the low concentration region.

11. The semiconductor device according to claim 1, wherein: The channel region is connected to a body region of the semiconductor substrate.

12. The semiconductor device according to claim 1, further comprising: A second transistor has an operating voltage lower than that of the first transistor and has a structure different from that of the first transistor.

13. The semiconductor device according to claim 12, wherein: The second transistor includes a second gate insulating layer disposed on the semiconductor substrate, a second gate electrode disposed on the second gate insulating layer, and a second source region and a second drain region disposed on both sides of the second gate electrode, respectively. The second source region and the second drain region each include a partial portion of the semiconductor substrate.

14. The semiconductor device according to claim 13, wherein: A thickness of the insulating structure, a length of a side surface of the insulating structure, or a length of the channel region is greater than a thickness of the second gate electrode included in the second transistor.

15. The semiconductor device according to claim 13, wherein: A thickness of the insulating structure, a length of a side surface of the insulating structure, or a length of the channel region is greater than a distance between the second source region and the second drain region in the second transistor.

16. The semiconductor device according to claim 1, wherein A gate contact connected to the first gate electrode is provided at a first position in one direction, and A first contact connected to the first region and a second contact connected to the second region are provided at a second position different from the first position in the one direction.

17. The semiconductor device according to claim 1, further comprising: a circuit region including the semiconductor substrate and the first transistor; as well as The cell region is disposed on the circuit region and includes a memory cell structure.

18. A semiconductor device comprising: Semiconductor substrates; as well as a plurality of transistors disposed on the semiconductor substrate and including a first transistor and a second transistor having different structures; The first transistor comprises: An insulating structure, disposed on the semiconductor substrate; a channel region disposed on the insulating structure and comprising a first semiconductor layer, wherein the channel region extends in a direction oblique to or perpendicular to the semiconductor substrate; a source region and a drain region electrically connected to the channel region; a gate insulating layer, disposed on the channel region; and a gate electrode disposed on the gate insulating layer, One of the source region and the drain region includes a partial portion of the semiconductor substrate.

19. The semiconductor device according to claim 18, wherein: The first transistor has a vertical channel structure, and the second transistor has a planar channel structure.

20. An electronic system comprising: main substrate; A semiconductor device is arranged on the main substrate; as well as a controller electrically connected to the semiconductor device on the main substrate, The semiconductor device comprises a semiconductor substrate and a first transistor disposed on the semiconductor substrate. The first transistor comprises: An insulating structure, disposed on the semiconductor substrate; a channel region disposed on the insulating structure and comprising a first semiconductor layer, wherein the channel region extends in a direction intersecting the semiconductor substrate; a source region and a drain region electrically connected to the channel region; a gate insulating layer, disposed on the channel region; and a gate electrode disposed on the gate insulating layer, The first region as one of the source region and the drain region and the second region as the other of the source region and the drain region include different materials or have different crystal structures.

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