Array substrate, display panel and display device

Abstract

The embodiment of the invention provides an array substrate, a display panel and a display device. The array substrate comprises an active layer provided with a pixel control unit; a first conductive layer provided with a first reset trace arranged in a first direction; the first conductive layer is provided with a second reset wire and a second conductive layer arranged along a second direction, the first conductive layer is arranged between the active layer and the second conductive layer, and the first reset wire and the second reset wire are electrically connected with the pixel control unit; the first reset wire and the second reset wire are electrically connected through at least one interlayer dielectric layer between the first conductive layer and the second conductive layer, the second conductive layer is further provided with a data wire, and the first conductive layer is further provided with a first fan-out wire arranged in the first direction. The first conducting layer is provided with a first fan-out wire arranged along a first direction, the first fan-out wire is electrically connected between the data wire and a driving unit of the array substrate, the second conducting layer is provided with a second fan-out wire arranged along a second direction, and the second fan-out wire is electrically connected between the data wire and the driving unit of the array substrate.

Description

Technical Field

[0001] Embodiments of the present invention relate to the field of display technology, and in particular to an array substrate, a display panel and a display device. Background Art

[0002] The fan-out routing in active area (FIAA) technology is an advanced organic light-emitting diode (OLED) array substrate manufacturing technology. The fan-out routing is used to connect the drive unit of the array substrate with the data routing of the display pixels. By transferring the fan-out routing to the inside of the display area, the wiring space required for the border of the array substrate can be saved, so that the border of the array substrate can be made narrower, thereby improving the screen-to-body ratio and product aesthetics.

[0003] In addition, transferring the fan-out wiring to the inside of the display area is also beneficial to reducing the metal resistance of the power signal transmission, thereby reducing the light-emitting power consumption of the array substrate at the same brightness without increasing the frame of the array substrate.

[0004] In order to further reduce the cost of the array substrate, it is expected to reduce the number of conductive layers of the array substrate while ensuring fan-out routing, which will affect the wiring space of the reset routing and further make the signal reset consistency of each pixel of the array substrate poor. Summary of the invention

[0005] In view of this, embodiments of the present invention provide an array substrate, a display panel and a display device to solve the above problems.

[0006] According to a first aspect of an embodiment of the present invention, there is provided an array substrate, comprising: an active layer, on which a pixel control unit for displaying a pixel array is provided; a first conductive layer, on which a first reset line arranged along a first direction is provided; and a second conductive layer, on which a second reset line arranged along a second direction is provided, wherein the first direction intersects with the second direction; wherein the first conductive layer is arranged between the active layer and the second conductive layer, the first reset line and the second reset line are both electrically connected to the pixel control unit, and the first reset line and the second reset line are electrically connected via at least one interlayer dielectric layer between the first conductive layer and the second conductive layer.

[0007] In another implementation of the present invention, the second conductive layer is further provided with a data routing line of the pixel control unit, wherein the display pixel array includes a first pixel and a second pixel, the first pixel and the second pixel are arranged at intervals in the first direction, and the data routing line is arranged along the second direction at both the first pixel and the second pixel;

[0008] The first conductive layer is also provided with a first fan-out routing arranged along a first direction, and the first fan-out routing is electrically connected between the data routing and the driving unit of the array substrate; the second conductive layer is also provided with a second fan-out routing arranged along a second direction, and the second fan-out routing is electrically connected between the data routing and the driving unit of the array substrate.

[0009] In another implementation of the present invention, the array substrate also includes a third conductive layer, which is arranged between the first conductive layer and the second conductive layer, and the third conductive layer is provided with a first fan-out routing arranged along the first direction, and the first fan-out routing and the second fan-out routing are electrically connected via at least one interlayer dielectric layer between the second conductive layer and the third conductive layer.

[0010] In another implementation of the present invention, the array substrate includes two layers of titanium-aluminum-titanium laminated structure; preferably, the first conductive layer includes a titanium-aluminum-titanium laminated structure, and / or the second conductive layer includes a titanium-aluminum-titanium laminated structure.

[0011] In another implementation of the present invention, each first pixel includes a first sub-pixel and a second sub-pixel arranged in the first direction, and the second reset routing includes a first sub-reset routing and a second sub-reset routing, and the first sub-reset routing and the second sub-reset routing are different second reset routings corresponding to different reset signals of the pixel control unit. The first sub-reset routing is arranged along the second direction at the position of the first sub-pixel, and the second sub-reset routing is arranged along the second direction at the position of the second sub-pixel.

[0012] In another implementation of the present invention, the number of the first reset lines matches the number of reset signals of the pixel control unit, and the first reset line and the second reset line corresponding to the same reset signal are electrically connected via at least one interlayer dielectric layer between the first conductive layer and the second conductive layer.

[0013] In another implementation of the present invention, the data routing includes a first data routing and a second data routing, the first data routing is arranged at the first sub-pixel along the second direction, and the second data routing is arranged at the second sub-pixel along the second direction. In the first direction, the first sub-reset routing is adjacent to the second sub-reset routing, and the first sub-reset routing and the second sub-reset routing are arranged between the first data routing and the second data routing.

[0014] In another implementation of the present invention, the second conductive layer is further provided with a first power supply line and a second power supply line, the first power supply line is arranged along the second direction at the first sub-pixel, and the second power supply line is arranged along the second direction at the second sub-pixel. In the first direction, the first data line and the second data line are arranged between the first power supply line and the second power supply line.

[0015] In another implementation of the present invention, the first power line includes a bending portion and an extension portion, and the second power line includes a bending portion and an extension portion, wherein in the first direction, the second power line of each pixel is electrically connected to the extension portion of the first power line of an adjacent pixel, and the bending portion forms a gap.

[0016] In another implementation of the present invention, in the first direction, adjacent first pixels are spaced apart by a first number of second pixels, or adjacent second pixels are spaced apart by a second number of first pixels.

[0017] In another implementation of the present invention, in the first direction, the first pixels and the second pixels are alternately arranged.

[0018] According to a second aspect of the embodiments of the present invention, a display panel is provided, comprising the array substrate according to the first aspect.

[0019] According to a third aspect of the embodiments of the present invention, a display device is provided, comprising the array substrate according to the first aspect or the display panel according to the second aspect.

[0020] In the scheme of the embodiment of the present invention, in the second conductive layer, the second reset line and the second fan-out line are arranged along the second direction, and the FIAA technology based on the fan-out line is implemented in the array substrate. Furthermore, in the first conductive layer, the first reset line is arranged along the first direction, and the first reset line and the second reset line are electrically connected via at least one interlayer dielectric layer between the first conductive layer and the second conductive layer, thereby forming a reset line network through the first reset line and the second reset line, thereby improving the signal reset consistency of each pixel in the case of fewer conductive layers of the array substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the embodiments of the present invention. For ordinary technicians in this field, other drawings can also be obtained based on these drawings.

[0022] Figure 1ASchematic cross-sectional views of pixel driving layers of array substrates of some examples.

[0023] Figure 1B Schematic diagrams of pixel circuits in some example array substrates.

[0024] Figure 2 Schematic bottom views of some example array substrates.

[0025] Figure 3 Schematic bottom views of array substrates of other examples.

[0026] Figure 4 for Figure 3 A schematic diagram of the positional relationship between the second reset wiring and the first reset wiring in an array substrate.

[0027] Figure 5 is a schematic cross-sectional view of an array substrate according to some embodiments of the present invention.

[0028] Fig. 6A and Figure 6B for Figure 5 A schematic bottom view of an array substrate.

[0029] Figure 6C Schematic diagrams showing the positional relationship between the second reset wiring and the first reset wiring in some exemplary array substrates.

[0030] Figure 7 Schematic diagrams of display panels according to other embodiments of the present invention. DETAILED DESCRIPTION

[0031] In order to enable those skilled in the art to better understand the technical solutions in the embodiments of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. All other embodiments obtained by ordinary technicians in the field based on the embodiments in the embodiments of the present invention should fall within the scope of protection of the embodiments of the present invention.

[0032] The specific implementation of the embodiment of the present invention is further described below in conjunction with the accompanying drawings of the embodiment of the present invention.

[0033] Figure 1ASchematic cross-sectional views of the pixel driving layer of the array substrate of some examples. Specifically, the pixel driving layer is arranged in the array substrate (not shown), including an active layer (e.g., PSI layer) 110, a first metal layer 10, a second metal layer 20, a third metal layer 30, a fourth metal layer 40 and a fifth metal layer 50. It should be understood that the active layer 110 can be arranged between the substrate (the backplane in the array substrate) and the first metal layer 10. In other examples, the active layer 110 can also be arranged between the first metal layer 10 and the second metal layer 20. At the same time, an inter-dielectric layer (not shown) such as an insulating layer is also arranged between the active layer 110 and the first metal layer 10, and between each conductive layer. In order to provide a complete array substrate, a functional film layer such as a buffer layer may also be included below the active layer 110, and a functional film layer such as an anode layer, a light-emitting layer and a cathode layer may also be included above the fifth metal layer 50.

[0034] In some examples, Figure 1B Pixel circuits in array substrates of some examples are shown. Figure 1B In the embodiment, taking the 7T1C pixel circuit as an example, the pixel circuit may include a driving transistor T0, a data writing transistor T1, a threshold compensation transistor T2, a first reset transistor T3, a second reset transistor T4, a first light-emitting control transistor T5 and a second light-emitting control transistor T6. The pixel circuit may also include a storage capacitor C and a light-emitting element D.

[0035] Specifically, the gate of the driving transistor T0 is electrically connected to the first electrode of the threshold compensation transistor T2 (for example, the first node N1), the second electrode of the first reset transistor T3 and the first electrode of the storage capacitor C, the first electrode of the driving transistor T0 is electrically connected to the second electrode of the threshold compensation transistor T2 and the first electrode of the second light-emitting control transistor T6, the second electrode of the driving transistor T0 is electrically connected to the first electrode of the data writing transistor T1 and the first electrode of the first light-emitting control transistor T5, the second electrode of the data writing transistor T1 is connected to the data signal terminal (for example, DATA), the first electrode of the first reset transistor T3 and the first electrode of the second reset transistor T4 are connected to the reset signal terminal (for example, Vref), the second electrode of the second reset transistor T4 is connected to the second electrode of the second light-emitting control transistor T6 and the anode of the light-emitting element D (for example, through the third node N3), and the cathode of the light-emitting element D is connected to the negative power supply voltage PVEE. The second electrode of the first light-emitting control transistor T5 and the second electrode of the storage capacitor C (for example, the second node N2) are connected to the positive power supply voltage PVDD, the gates of the data writing transistor T1 and the threshold compensation transistor T2 are connected to the second scanning signal S2, the first reset transistor T3 and the second reset transistor T4 are connected to the first scanning signal S1, and the gates of the first light-emitting control transistor T5 and the second light-emitting control transistor T6 are connected to the light-emitting control signal EN.

[0036] Further, in Figure 1A In the example, the active layer 100 may be a semiconductor layer. For example, the first electrode and the second electrode (eg, the drain and the source) of each transistor in the pixel circuit may be formed in the active layer.

[0037] The first metal layer 10 may be a Mo (molybdenum) metal layer, for example, the drain and source gates of each transistor in the pixel circuit may be formed in the first metal layer. The second metal layer 20 may be a Mo metal layer. The third metal layer 30 may be a TAT metal layer, that is, a metal layer of a titanium-aluminum-titanium laminated structure, for example, it may be a first TAT metal layer. The fourth metal layer 40 may be a TAT metal layer, for example, it may be a second TAT metal layer. The fifth metal layer 50 may be a TAT metal layer, for example, it may be a third TAT metal layer. Further, the array substrate provided in an embodiment of the present invention may include multiple metal layers, and only two metal layers include a TAT metal layer, that is, only two metal layers include a titanium-aluminum-titanium laminated structure.

[0038] Optionally, a GATO layer 25 may be further provided between the second metal layer 20 and the third metal layer 30, and the GATO layer may be formed as a Mo metal layer or a TI metal layer. In some examples of low temperature polycrystalline silicon (LTPS), LTPS is used as a semiconductor for forming each transistor, and the GATO layer 25 may not be included in the pixel driving layer. In other examples of low temperature polycrystalline silicon (LTPO), indium gallium zinc oxide (IGZO) is used as a semiconductor for forming a reset transistor, LTPS is used as a semiconductor for forming other transistors, and the pixel driving layer may include a GATO layer 25, wherein the bottom gate of the IGZO is formed in the second metal layer 20, and the top gate of the IGZO is formed in the GATO layer 25.

[0039] Further, for each reset signal (i.e., initialization signal), a second reset line and / or a first reset line may be respectively provided in the pixel array of the array substrate. In the example where the pixel circuit is a 7T1C circuit, the reset signal includes Vref1 and Vref2, which are used to be input to the corresponding reset signal terminals in the pixel circuit. Alternatively, in the example where the pixel circuit is an 8T1C circuit, the reset signal includes Vref1, Vref2, and Vref3, which are used to be input to the corresponding reset signal terminals in the pixel circuit.

[0040] In some examples, such as Figure 2As shown, the first reset line 101, the first reset line 102, and the first reset line 103 are respectively set for the three reset signals Vref1, Vref2, and Vref3. As an example of LTPO, any of the first reset line 101, the first reset line 102, and the first reset line 103 can be set in any conductive layer of the first metal layer 10, the second metal layer 20, and the GATO layer 25. As an example of LTPS, any of the first reset line 101, the first reset line 102, and the first reset line 103 can be set in any conductive layer of the first metal layer 10 and the second metal layer 20.

[0041] Accordingly, the second reset line 310 may correspond to the first reset line 101, the first reset line 102, and the first reset line 103 (for example, corresponding to Figure 4 The second reset wiring 311, the second reset wiring 312 and the second reset wiring 313), for example, in the pixel array (for example, Figure 2 In the first direction (the range of the dotted box in the figure is one pixel), the alternately arranged second reset lines 310 correspond to the first reset lines 101, the first reset lines 102, and the first reset lines 103. In this example, the second reset lines 310 are arranged in the third metal layer 30.

[0042] Correspondingly, the second fan-out routing and the first fan-out routing are electrically connected between the data routing of the pixel control unit of the display pixel array and the driving unit of the array substrate. The first fan-out routing 410 is arranged in the fourth metal layer 40. The data routing and the second fan-out routing are arranged in the fifth metal layer 50. For example, one of the data routing and the second fan-out routing can be routing 501, and the other can be routing 502. In addition, a power routing 530 is also arranged in the fifth metal layer 50.

[0043] That is, in the FIAA technology, the fan-out wiring is used to connect the driving chip of the array substrate and the circuit wiring of the display pixel. The fan-out wiring is usually arranged in the three-layer TAT (TiAlTi, titanium aluminum titanium) conductive layer of the array substrate, wherein the second reset wiring is arranged in the first TAT metal layer, the first fan-out wiring is arranged in the second TAT metal layer, and the second fan-out wiring is arranged in the third TAT metal layer. In addition, the first reset wiring can be arranged in other conductive layers, thereby forming a reset wiring network with the second reset wiring, such as Figure 4As shown, the first reset line 101 and the second reset line 311 form a routing network of the reset signal Vref1 via an inter-dielectric layer (e.g., a via hole of the insulating layer), the first reset line 102 and the second reset line 312 form a routing network of the reset signal Vref2 via an inter-dielectric layer (e.g., a via hole of the insulating layer), and the first reset line 103 and the second reset line 313 form a routing network of the reset signal Vref3 via an inter-dielectric layer (e.g., a via hole of the insulating layer). Therefore, the signal reset consistency of each pixel of the array substrate is guaranteed.

[0044] In order to further reduce the cost of the array substrate, it is desirable to provide two TAT metal layers in the array substrate. Figure 3 As shown, the first fan-out routing 410 is arranged in the third metal layer 30. The data routing and the second fan-out routing are arranged in the fourth metal layer 40, and the fourth metal layer 40 is also provided with a power routing 530. For example, one of the data routing and the second fan-out routing may be routing 501, and the other may be routing 502.

[0045] That is to say, in order to ensure the setting of the second fan-out routing and the first fan-out routing, it is often necessary to reduce the TAT conductive layer on which the second reset routing is set, so that the reset routing network cannot be formed, resulting in poor signal reset consistency of each pixel of the array substrate. For example, the display effect of the array substrate is deteriorated in a low grayscale state. For example, the side close to the driving unit of the array substrate is darker, and the side of the array substrate away from the driving unit is brighter.

[0046] To this end, various embodiments of the present invention provide a series of solutions to significantly improve the signal reset consistency of each pixel with a relatively small number of conductive layers of the array substrate.

[0047] Figure 5 Array substrates according to some embodiments of the present invention are shown. Figure 5 The array substrate 500 includes an active layer 110 , a first conductive layer 510 and a second conductive layer 520 .

[0048] Further, the active layer 110 is provided with a pixel control unit corresponding to each pixel of the display pixel array.

[0049] It should be understood that a functional film layer such as a buffer layer may be included below the active layer 110, and a functional film layer such as an anode layer, a light-emitting layer, and a cathode layer may be included above the second conductive layer 520. The active layer 100 may be a semiconductor layer. For example, the first and second electrodes (e.g., a drain and a source) of each transistor in the pixel circuit may be formed in the active layer.

[0050] Furthermore, the first conductive layer 510 is provided with a first reset line arranged along a first direction of the display pixel array. It can be understood that the first direction may be a row direction of the display pixel array, and the second direction may be a column direction of the display pixel array.

[0051] It should be understood that the first conductive layer 510 may be at least one conductive layer among the first metal layer 10 , the second metal layer 20 and the GATO layer 25 .

[0052] Further, the second conductive layer 520 is provided with a second reset line and a second fan-out line arranged along the second direction of the display pixel array, and the first direction and the second direction intersect. The display pixel array includes a first pixel and a second pixel, and the first pixel and the second pixel can be arranged at intervals in the first direction. In addition, the first pixel can be arranged continuously in the second direction, and the second pixel can be arranged continuously in the second direction.

[0053] Further, the second fan-out line is electrically connected between the data line of the pixel control unit of the display pixel array and the driving unit of the array substrate. That is, the second reset line is arranged along the second direction of the display pixel array at the first pixel in the first direction, and the second fan-out line is arranged along the second direction of the display pixel array at the second pixel in the first direction, and the first pixel and the second pixel can be arranged at intervals in the second direction. Preferably, the first direction and the second direction can have an orthogonal relationship.

[0054] It should be understood that the second conductive layer 520 may be any one of the third metal layer 30 and the fourth metal layer 40 .

[0055] The first conductive layer 510 is arranged between the active layer 110 and the second conductive layer 520, the first reset line is electrically connected to the pixel control unit corresponding to the active layer, the second reset line is electrically connected to the pixel control unit corresponding to the active layer, and the first reset line and the second reset line are electrically connected via at least one interlayer dielectric layer between the first conductive layer 510 and the second conductive layer 520.

[0056] It should be understood that at least one of the first reset line and the second reset line can be connected to the reset signal terminal of the pixel control unit. For example, both the first reset line and the second reset line are connected to the reset signal terminal of the pixel control unit and are electrically connected via at least one interlayer dielectric layer between the first conductive layer and the second conductive layer.

[0057] In the scheme of the embodiment of the present invention, in the second conductive layer, the second reset line and the second fan-out line are arranged along the second direction of the display pixel array, and the FIAA technology based on the fan-out line is implemented in the array substrate. Furthermore, in the first conductive layer, the first reset line is arranged along the first direction of the display pixel array, and the first reset line and the second reset line are electrically connected via at least one interlayer dielectric layer between the first conductive layer and the second conductive layer, thereby forming a reset line network through the first reset line and the second reset line, and improving the signal reset consistency of each pixel in the case of fewer conductive layers of the array substrate (for example, two TAT metal layers).

[0058] In other embodiments, the second conductive layer may also be provided with data routing of pixel control units of the display pixel array, and the data routing (for example, through the data signal terminal in the second conductive layer) is electrically connected to the data signal terminal of each pixel control unit arranged along the second direction of the display pixel array, wherein the data routing is arranged along the second direction of the display pixel array at the first pixel and the second pixel, thereby fully utilizing the wiring space in the second conductive layer.

[0059] In other embodiments, the array substrate also includes a third conductive layer, which is arranged between the first conductive layer and the second conductive layer, and the third conductive layer is provided with a first fan-out routing arranged along a first direction of the display pixel array, and the first fan-out routing is electrically connected between the data routing of the pixel control unit of the display pixel array and the driving unit of the array substrate.

[0060] In addition, the first fan-out trace is electrically connected to the second fan-out trace via at least one interlayer dielectric layer between the second conductive layer and the third conductive layer. The second conductive layer may be one of the third metal layer 30 or the fourth metal layer 40, and the third conductive layer may be the other of the third metal layer 30 or the fourth metal layer 40.

[0061] In some embodiments, the first conductive layer 510 may be at least one conductive layer among the first metal layer 10, the second metal layer 20 and the GATO layer 25; the second conductive layer 520 may be any one of the third metal layer 30 and the fourth metal layer 40. For example, Fig. 6AAs shown, in the case of three reset signals (Vref1, Vref2 and Vref3), the first reset line 1001, the first reset line 1002, and the first reset line 1003 are respectively set. As an example of LTPO, any of the first reset line 1001, the first reset line 1002, and the first reset line 1003 can be set in any conductive layer of the first metal layer 10, the second metal layer 20 and the GATO layer 25. As an example of LTPS, any of the first reset line 1001, the first reset line 1002, and the first reset line 1003 can be set in any conductive layer of the first metal layer 10 and the second metal layer 20. The second fan-out line 5200 can correspond to Figure 3 The routing 502.

[0062] Accordingly, the second reset line 5400 may correspond to the first reset line 101, the first reset line 102, and the first reset line 103 (for example, corresponding to Figure 6B The second reset wiring 5401, the second reset wiring 5402 and the second reset wiring 5403). For example, Figure 6B As shown, in the first direction of the pixel array, in the first pixel provided with the second reset wiring, the second reset wiring 5401 and the second reset wiring 5402 (i.e., respectively provided in the first sub-pixel and the second sub-pixel), the second reset wiring 5402 and the second reset wiring 5403 (i.e., respectively provided in the first sub-pixel and the second sub-pixel), and the second reset wiring 5403 and the second reset wiring 5401 (i.e., respectively provided in the first sub-pixel and the second sub-pixel) are alternately provided.

[0063] In the case of two reset signals (i.e., Vref1 and Vref2), a first reset line 1001 and a first reset line 1002 are provided for the two reset signals, and accordingly, in a pixel provided with a second reset line, a second reset line 5401 and a second reset line 5402 are provided. In some examples, the second reset line 5401 is provided in the first sub-pixel, and the second reset line 5402 is provided in the second sub-pixel; alternatively, the second reset line 5401 is provided in the second sub-pixel, and the second reset line 5402 is provided in the first sub-pixel.

[0064] Without loss of generality, each first pixel includes a first sub-pixel and a second sub-pixel arranged in a first direction of the display pixel array, and the second reset wiring includes a first sub-reset wiring and a second sub-reset wiring, the first sub-reset wiring is arranged at the position of the first sub-pixel along the second direction of the display pixel array, and the second sub-reset wiring is arranged at the position of the second sub-pixel along the second direction of the display pixel array.

[0065] Further, the first sub-reset routing and the second sub-reset routing are different second reset routings corresponding to different reset signals of the pixel control unit. For example, in the case of two reset signals (i.e., Vref1 and Vref2), the first sub-reset routing may be a routing of the reset signal Vref1, and the second sub-reset routing may be a routing of the reset signal Vref2. For another example, in the case of three reset signals (Vref1, Vref2, and Vref3), the first sub-reset routing and the second sub-reset routing may be an arrangement of two of the reset signals Vref1, Vref2, and Vref3, for example, Figure 6B As shown, in the first direction, the second reset line 5401 and the second reset line 5402 (i.e., respectively arranged in the first sub-pixel and the second sub-pixel) are alternately arranged as the first sub-reset line and the second sub-reset line, respectively, the second reset line 5402 and the second reset line 5403 (i.e., respectively arranged in the first sub-pixel and the second sub-pixel) are respectively used as the first sub-reset line and the second sub-reset line, and the second reset line 5403 and the second reset line 5401 (i.e., respectively arranged in the first sub-pixel and the second sub-pixel) are respectively used as the first sub-reset line and the second sub-reset line. Thus, different sub-pixels belonging to the same first pixel correspond to the arrangement of two of the multiple reset signals, and the alternating arrangement of the second reset lines of the multiple reset signals in the first pixel is realized in the first direction, and the uniform arrangement of the second reset lines of each reset signal in the first pixel is realized.

[0066] Further, in Fig. 6A and Figure 6B In the example, in the first direction of the pixel array, the first pixel and the second pixel can be alternately arranged. It should be understood that in other examples, adjacent first pixels are spaced by a first number of second pixels. For example, when the first number is five, a first pixel is arranged every five pixels, and the remaining four pixels in the interval are second pixels, that is, the ratio of the number between the first pixel and the second pixel is 1:5. In other examples, adjacent second pixels are spaced by a second number of first pixels. For example, when the second number is three, a second pixel is arranged every three pixels, and the remaining two pixels in the interval are first pixels, that is, the ratio of the number between the first pixel and the second pixel is 3:1.

[0067] Furthermore, in the case where there are multiple reset signals, the number of the first reset lines may be the same as the number of the reset signals of the pixel control unit. Figure 6CAs shown, the second reset wiring 5401 is electrically connected to the first reset wiring 1001, the second reset wiring 5402 is electrically connected to the first reset wiring 1002, and the second reset wiring 5403 is electrically connected to the first reset wiring 1003. In other words, the first reset wiring and the second reset wiring corresponding to the same reset signal are electrically connected via at least one interlayer dielectric layer between the first conductive layer and the second conductive layer, thereby ensuring the consistency of each reset signal in each pixel.

[0068] Furthermore, the data routing includes a first data routing and a second data routing, such as Fig. 6A and Figure 6B As shown, the data routing 5100 is a first data routing in the first sub-pixel, and the data routing 5100 is a second data routing in the second sub-pixel. That is, the first data routing is arranged along the second direction of the display pixel array at the first sub-pixel, and the second data routing is arranged along the second direction of the display pixel array at the second sub-pixel, so that the data routing and the second reset routing are arranged in the sub-pixel of the first pixel, which improves the compactness of the routing arrangement in the sub-pixel of the first pixel and improves the space utilization rate of the second conductive layer.

[0069] like Fig. 6A and Figure 6B As shown, in the first direction of the display pixel array, the first sub-reset routing is adjacent to the second sub-reset routing, and the first sub-reset routing and the second sub-reset routing are arranged between the first data routing and the second data routing, so that the data routing and the second reset routing are symmetrically arranged about the boundary between the first sub-pixel and the second sub-pixel, thereby improving the wiring efficiency of the second reset routing in the first sub-pixel and the second sub-pixel.

[0070] Furthermore, if Fig. 6A and Figure 6B As shown, the second conductive layer is further provided with a first power supply line 5300 and a second power supply line 5300, the first power supply line is arranged at the first sub-pixel along the second direction of the display pixel array, and the second power supply line is arranged at the second sub-pixel along the second direction of the display pixel array. For example, the first power supply line and the second power supply line are electrically connected to the power signal terminal of the pixel control unit.

[0071] like Fig. 6A As shown in the dotted box of the first sub-pixel and the dotted box of the second sub-pixel, in the first direction of the display pixel array, the first data line and the second data line are arranged between the first power line and the second power line, thereby improving the wiring efficiency of the power lines in the first sub-pixel and the second sub-pixel.

[0072] Furthermore, if Fig. 6AAs shown in the dotted frame of the pixel, the first power supply line includes a bent portion and an extended portion, and the second power supply line includes a bent portion and an extended portion, wherein in the first direction of the display pixel array, the second power supply line of each pixel is electrically connected to the extended portion of the first power supply line of the adjacent pixel, and the bent portion forms a gap. In other words, the gap formed between the first power supply line and the second power supply line provides a wiring (for example, anode wiring) space in the second conductive layer that passes through the second conductive layer to reach other conductive layers. In addition, the second power supply line of each pixel is electrically connected to the extended portion of the first power supply line of the adjacent pixel (of the pixel), further improving the wiring efficiency of the power supply line.

[0073] Combine the following Figure 7 Display panels according to other embodiments of the present invention are described in detail. Figure 7 The display panel 700 includes the array substrate 500 provided in any of the above embodiments. It should be understood that the display panel 700 can be applied to mobile phones, tablets, displays, smart watches, MP3, MP4 or other wearable devices, etc., because it includes the display panel provided in any embodiment of the present invention, and thus has the same beneficial effects, which will not be described in detail here.

[0074] The present invention further provides a display device, which includes the array substrate or display panel provided in any of the above embodiments, and thus has the same beneficial effects as the array substrate or display panel provided in any of the above embodiments, which will not be described in detail herein. The display device can be a mobile phone, a tablet, a display, a smart watch, an MP3, an MP4 or other wearable devices.

[0075] Thus far, specific embodiments of the subject matter have been described. Other embodiments are within the scope of the appended claims. In some cases, the actions recited in the claims may be performed in a different order and still achieve the desired results. Additionally, the processes depicted in the accompanying drawings do not necessarily require the specific order or sequential order shown to achieve the desired results. In some embodiments, multitasking and parallel processing may be advantageous.

[0076] It should also be noted that the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, commodity or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, commodity or device. In the absence of more restrictions, the elements defined by the sentence "comprises a ..." do not exclude the existence of other identical elements in the process, method, commodity or device including the elements.

[0077] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems or computer program products. Therefore, the present application may adopt the form of a complete hardware embodiment, a complete software embodiment or an embodiment in combination with software and hardware. Moreover, the present application may adopt the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) that contain computer-usable program code.

[0078] Each embodiment in this specification is described in a progressive manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the system embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0079] The above is only an embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various changes and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the scope of the claims of the present application.

Claims

1. An array substrate, characterized in that: include: An active layer, provided with a pixel control unit of a display pixel array; A first conductive layer is provided with a first reset trace arranged along a first direction; A second conductive layer is provided with a second reset trace arranged along a second direction, wherein the first direction intersects the second direction; Among them, the first conductive layer is arranged between the active layer and the second conductive layer, the first reset line and the second reset line are both electrically connected to the pixel control unit, and the first reset line and the second reset line are electrically connected via at least one interlayer dielectric layer between the first conductive layer and the second conductive layer.

2. The array substrate according to claim 1, characterized in that: The second conductive layer is further provided with a data line of the pixel control unit, wherein the display pixel array includes a first pixel and a second pixel, the first pixel and the second pixel are arranged at intervals in the first direction, and the data line is arranged at the first pixel and the second pixel along the second direction; The first conductive layer is also provided with a first fan-out routing arranged along a first direction, and the first fan-out routing is electrically connected between the data routing and the driving unit of the array substrate; the second conductive layer is also provided with a second fan-out routing arranged along a second direction, and the second fan-out routing is electrically connected between the data routing and the driving unit of the array substrate.

3. The array substrate according to claim 2, characterized in that: The array substrate further includes a third conductive layer disposed between the first conductive layer and the second conductive layer, the third conductive layer being provided with a first fan-out trace arranged along the first direction, the first fan-out trace being electrically connected to the second fan-out trace via at least one interlayer dielectric layer between the second conductive layer and the third conductive layer; Preferably, the array substrate comprises a two-layer titanium-aluminum-titanium laminated structure; Preferably, the first conductive layer comprises a titanium-aluminum-titanium stacked structure, and / or the second conductive layer comprises a titanium-aluminum-titanium stacked structure.

4. The array substrate according to claim 2, characterized in that: Each first pixel includes a first sub-pixel and a second sub-pixel arranged along the first direction, the second reset wiring includes a first sub-reset wiring and a second sub-reset wiring, the first sub-reset wiring and the second sub-reset wiring include different second reset wirings corresponding to different reset signals of the pixel control unit, The first sub-reset line is arranged along the second direction at the position of the first sub-pixel, and the second sub-reset line is arranged along the second direction at the position of the second sub-pixel.

5. The array substrate according to claim 4, characterized in that: The number of the first reset lines matches the number of reset signals of the pixel control unit, and the first reset lines and the second reset lines corresponding to the same reset signal are electrically connected via at least one interlayer dielectric layer between the first conductive layer and the second conductive layer.

6. The array substrate according to claim 4, characterized in that: The data routing includes a first data routing and a second data routing, the first data routing is arranged at the first sub-pixel along the second direction, and the second data routing is arranged at the second sub-pixel along the second direction, Wherein, in the first direction, the first sub-reset routing line is adjacent to the second sub-reset routing line, and the first sub-reset routing line and the second sub-reset routing line are arranged between the first data routing line and the second data routing line.

7. The array substrate according to claim 6, characterized in that: The second conductive layer is further provided with a first power supply line and a second power supply line, wherein the first power supply line is arranged along the second direction at the first sub-pixel, and the second power supply line is arranged along the second direction at the second sub-pixel. Wherein, in the first direction, the first data line and the second data line are arranged between the first power line and the second power line; Preferably, the first power supply line includes a bending portion and an extension portion, and the second power supply line includes a bending portion and an extension portion, wherein in the first direction, the second power supply line of each pixel is electrically connected to the extension portion of the first power supply line of an adjacent pixel, and the bending portion forms a gap.

8. The array substrate according to claim 2, characterized in that: In the first direction, adjacent first pixels are arranged to be spaced apart by a first number of second pixels, or adjacent second pixels are spaced apart by a second number of first pixels; Preferably, in the first direction, the first pixels and the second pixels are arranged alternately.

9. A display panel, characterized in that: include: An array substrate according to any one of claims 1 to 8.

10. A display device, characterized in that: include: An array substrate according to any one of claims 1-8 or a display panel according to claim 9.

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