Back contact battery and preparation method thereof

Abstract

The invention provides a back contact cell and a preparation method thereof, and relates to the technical field of back contact cells, the back contact cell comprises a silicon wafer, a first semiconductor layer, a second semiconductor layer, crack ink and a conductive film layer; the crack ink is arranged on the side edge of the second semiconductor opening area and is in direct contact with the second semiconductor layer, and two ends of the crack ink extend a preset distance along the horizontal direction of the silicon wafer; wherein a plurality of cracks extending to the surface of the crack ink are formed in the crack ink, and the width of the cracks is smaller than or equal to 20 microns; the conductive film layer is continuously arranged on the outer surface of the second semiconductor layer, on the crack ink and in the first semiconductor opening area, and the conductive film layer is broken at the crack on the surface of the crack ink and forms an insulating channel together with the crack. According to the invention, the deposited conductive film layer is isolated through the crack ink and the insulating channel is formed, and a special process for forming an insulating isolation groove after the conductive film is deposited is not needed, so that the process flow is simplified, and the production yield of the battery is improved.

Description

Technical Field

[0001] The present application relates to the technical field of back-contact batteries, and in particular to a back-contact battery and a method for preparing the same. Background Art

[0002] The back-contact heterojunction battery with combined passivation of the Topcon process generally uses a tunneling oxide layer as the first intrinsic semiconductor layer, a doped polycrystalline layer as the first conductive semiconductor layer, intrinsic amorphous silicon as the second intrinsic semiconductor layer, and doped amorphous / microcrystalline silicon as the second conductive semiconductor layer. The conductive film layer is etched in the upper area corresponding to the mask layer to form an isolation groove.

[0003] However, at the side edge of the second semiconductor opening region, there is a second conductive semiconductor layer (the resistivity of the second conductive semiconductor layer is about 10 -1 -10 9 Ω·cm, which is an N-type amorphous / microcrystalline silicon layer with a resistivity of about 10 -1 -10 3 Ω·cm, when it is a P-type amorphous / microcrystalline silicon layer, the resistivity is about 10 4 -10 9 Ω·cm) and the first conductive semiconductor layer (the resistivity of the first conductive semiconductor layer is about 10 -3 Ω·cm) between the second intrinsic semiconductor layer (the resistivity of the second intrinsic semiconductor layer is about 10 5 -10 10 Ω·cm) insulation phenomenon. Although the second intrinsic semiconductor layer has a high resistivity, its thickness is very thin (about 10nm). At the same time, because the first conductive semiconductor layer has very good conductivity, it is impossible to form a good insulation between the first conductive semiconductor layer and the second conductive semiconductor layer. At the same time, the conductive film layer on the surface of the second conductive semiconductor layer (the conductive film layer has a resistivity of ≤10 -4 Ω·cm) will cross the side edge of the second semiconductor opening area in the horizontal direction, making it easy for a serious leakage phenomenon to occur between the first semiconductor layer and the second semiconductor layer, thereby reducing the parallel resistance of the battery, and further reducing the battery conversion efficiency and battery yield.

[0004] The Chinese patent with patent number CN117174776B relates to a back-contact battery and its manufacturing method, including a silicon wafer, a first semiconductor layer, a second semiconductor layer, and a conductive film layer, with an isolation groove opened on the conductive film layer; it also includes: a plurality of insulating ink layers, which are all arranged between the second semiconductor layer and the conductive film layer and are arranged at intervals along the X-axis direction of the back side, and the insulating ink layer is in direct contact with the second semiconductor layer, and in the X-axis direction, the insulating ink layer spans the side edge of the second semiconductor opening area and extends at both ends respectively; wherein, the insulating ink layer satisfies: the surface pencil hardness is not less than 2H, the resistivity is greater than 1e11Ω·cm, and the mass content of volatile substances in the raw materials of the insulating ink layer is not more than 5%.

[0005] However, the patent still has the following improvements: after forming a conductive film layer on the insulating ink layer, this technology needs to use laser to etch an insulating groove on the conductive film layer on the insulating ink layer at the junction of the first semiconductor and the second semiconductor, but the process window is relatively narrow, and there is a certain degree of difficulty in using existing laser processes.

[0006] On the other hand, even if only the isolation groove is etched in the conductive film layer on the insulating ink layer without limiting the specific position, a special process is still required to form the insulating isolation groove after depositing the conductive film. At the same time, if the operation is improper, laser etching can easily damage the battery, thereby affecting the battery conversion efficiency and battery yield.

[0007] Therefore, there is an urgent need to provide a back contact battery to solve the above technical problems.

[0008] It should be noted that this part of the present invention only provides background technology related to the present invention and does not necessarily constitute prior art or known technology. Summary of the invention

[0009] In view of this, the purpose of the present application is to provide a back contact battery and a method for preparing the same, so as to at least solve the problem that the prior art process is complicated and easily reduces the battery conversion efficiency and battery yield. The present invention forms a crack ink in the area just above the side of the second semiconductor opening, and then deposits a conductive film layer. The deposited conductive film layer is isolated by the crack ink to form an insulating channel, and there is no need to form an insulating isolation groove in a special process after depositing the conductive film, thereby simplifying the process and improving the battery production yield.

[0010] In the first aspect, the present application provides a back-contact battery, comprising a silicon wafer, a first semiconductor layer, a second semiconductor layer, crack ink and a conductive film layer; the silicon wafer has a front side and a back side; the first semiconductor layer is arranged on the back side of the silicon wafer, and the first semiconductor layer is evenly spaced apart with second semiconductor opening areas; the second semiconductor layer is continuously arranged on the outer surface of the first semiconductor layer and in the second semiconductor opening area, and the second semiconductor layer is provided with first semiconductor opening areas spaced apart from the second semiconductor opening areas; the crack ink is arranged at the side edge of the second semiconductor opening area and in direct contact with the second semiconductor layer, and the two ends of the crack ink extend a preset distance along the horizontal direction of the silicon wafer respectively; wherein a plurality of cracks extending to the surface of the crack ink are formed in the crack ink, and the width of the crack is ≤20 μm; the conductive film layer is continuously arranged on the outer surface of the second semiconductor layer, on the crack ink and in the first semiconductor opening area, and the conductive film layer is disconnected at the crack on the surface of the crack ink and forms an insulating channel together with the crack.

[0011] In some embodiments, the width of both ends of the crack ink in the horizontal direction of the silicon wafer is 20-200 μm, one end of the crack ink extends ≥10 μm along the first semiconductor layer, and the other end of the crack ink extends ≥10 μm along the second semiconductor opening area.

[0012] In some embodiments, the maximum thickness of the crack ink along the vertical direction of the silicon wafer is 2-20 μm.

[0013] In some embodiments, the width of the first semiconductor opening region is 0.15-0.5 mm, and the width of the second semiconductor opening region is 0.3-0.6 mm.

[0014] In some embodiments, the crackle ink is a UV curable crackle ink or a thermosetting crackle ink.

[0015] In some embodiments, the UV-curable crack ink is composed of the following components in percentage by weight: 70-85% resin, 2-10% additive, 0.5-5% solvent, 5-15% filler and 1-5% photoinitiator.

[0016] In some embodiments, the resin is one or a combination of acrylic resin, phenolic resin, and epoxy resin.

[0017] In some embodiments, the auxiliary agent is one or a combination of benzophenone, tertiary amine acrylate, polyester solution, polyether compound, silicone oil, and mineral oil.

[0018] In some embodiments, the solvent is one or a combination of propylene glycol, ethyl acetate, butyl acetate, acetone, toluene, and ethanol.

[0019] In some embodiments, the filler is one or a combination of calcium carbonate, magnesium carbonate, barium sulfate, aluminum hydroxide, lithopone, and aluminum silicate.

[0020] In some embodiments, the first semiconductor layer includes a first intrinsic semiconductor film layer and a first conductive semiconductor film layer, and the second semiconductor layer includes a second intrinsic semiconductor film layer and a second conductive semiconductor film layer.

[0021] In some embodiments, the back contact battery further includes a metal electrode, which is disposed on the outer surface of the conductive film layer and is disposed in the first semiconductor opening region and the second semiconductor opening region.

[0022] In some embodiments, the back contact cell further includes a front film layer, which is disposed on the front side of the silicon wafer, and includes a silicon dielectric passivation layer and a silicon dielectric anti-reflection layer.

[0023] In some embodiments, the front side of the silicon wafer is a textured surface, and the surface of the silicon wafer at the second semiconductor opening region is a textured surface or a polished surface.

[0024] In a second aspect, the present application also provides a method for preparing a back contact battery, the preparation method comprising the following steps: S101, forming a first semiconductor layer having a second semiconductor opening region on the back side of the silicon wafer, disposing a second semiconductor layer on the outer surface of the first semiconductor layer and in the second semiconductor opening region, and disposing a first semiconductor opening region spaced apart from the second semiconductor opening region on the second semiconductor layer; S102, printing and curing crack ink on the side edges of the second semiconductor opening region on the back side obtained in S101; Wherein, a plurality of cracks extending to the surface of the crack ink are formed in the crack ink, and the width of the crack is ≤20 μm; S103, depositing a conductive film layer on the back surface obtained in S102; The conductive film layer is disconnected at the cracks on the surface of the crack ink and forms an insulating channel together with the cracks.

[0025] In some embodiments, in S102, when the crack ink is a UV curable crack ink, UV curing is used to form the crack ink after printing, and the UV curing energy is 500-10000 mj / cm 2 , UV curing temperature is 50-200℃.

[0026] In some embodiments, in S102, when the crack ink is a thermosetting crack ink, thermal curing is used to form the crack ink after printing, the thermal curing temperature is 150-200°C, and the thermal curing time is 5-30 minutes.

[0027] In some embodiments, before S101 , it also includes forming a textured surface and a front film layer on the front side of the silicon wafer.

[0028] In some embodiments, after S103 , the method further includes forming metal electrodes on the outer surfaces of the conductive film layers corresponding to the first semiconductor opening region and the second semiconductor opening region.

[0029] In some embodiments, the number of cracks in the cracked ink increases during the formation of the metal electrode.

[0030] In some embodiments, during the formation of the metal electrode, the width of the cracks of the crack ink increases up to 5-20 μm.

[0031] The beneficial effects that this application can achieve are: 1. Compared with the prior art in which the isolation groove is opened in the first semiconductor region, the present invention forms a crack ink in the area just above the side of the second semiconductor opening, and then deposits a conductive film layer. The deposited conductive film layer is isolated by the crack ink to form an insulating channel, which has a larger insulation resistance and can reduce micro short circuits, thereby improving battery efficiency.

[0032] 2. The existing technology also has the situation of opening the isolation groove at the junction of the first semiconductor and the second semiconductor, but when the isolation groove is opened at the junction of the first semiconductor and the second semiconductor, the process window is narrow, the difficulty of using the laser process is relatively large, and the difficulty of mass production is high. If the chemical etching method is used, the process is complicated, while the crack ink technical solution of this application has low process difficulty, simple process, and higher mass production.

[0033] 3. In the prior art, there are cases where an insulating ink layer is used for insulation (such as CN117174776B), but it still etches an isolation groove on the conductive film layer on the insulating ink layer, and if the operation is improper, laser etching can easily damage the battery, thereby affecting the battery conversion efficiency and battery yield. The crack ink technology of this application forms an insulating channel with a greater insulation resistance than the insulating groove, and there is no need to form an insulating isolation groove in a special process after depositing the conductive film, thereby simplifying the process flow and improving the battery production yield.

[0034] 4. The UV-curable crack ink of the present application includes 70-85% resin, 2-10% additive, 0.5-5% solvent, 5-15% filler and 1-5% photoinitiator. The crack ink of the present application is stable in nature and can be retained on the battery cell for a long time. In the preferred scheme of the present application, UV-curable crack ink is used, and UV curing after printing is used. The present application uses a specific crack ink formula and process parameters to form a number of cracks extending to its surface in the crack ink, and the width of the crack is ≤20um. The presence of this crack can greatly improve the insulation isolation effect.

[0035] 5. In the prior art, the conductive film layer on the surface of the second conductive semiconductor layer will cross the side edge of the second semiconductor opening area in the horizontal direction, making it easy for a serious leakage phenomenon to occur between the first semiconductor layer and the second semiconductor layer, thereby reducing the parallel resistance of the battery, and further reducing the battery efficiency and battery yield. The crack ink of the present application is set at the side edge of the second semiconductor opening area. When the conductive film layer is disconnected at the crack on the surface of the crack ink and forms an insulating channel together with the crack, the conductive film layer will not cross the side edge of the second semiconductor opening area in the horizontal direction of the silicon wafer, avoiding the leakage phenomenon between the first semiconductor layer and the second semiconductor layer, thereby greatly improving the parallel resistance of the battery, and further improving the battery efficiency and battery yield. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0037] Figure 1 This is a schematic structural diagram of a back contact battery in step S101 of Example 1 of the present invention; Figure 2 This is a schematic structural diagram of printing crack ink at the edge of the second semiconductor opening region in step S102 of embodiment 1 of the present invention; Figure 3 This is a schematic structural diagram of UV curing crack ink at the edge of the second semiconductor opening region in step S102 of embodiment 1 of the present invention; Figure 4 This is a schematic structural diagram of depositing a conductive film layer on the back side of a silicon wafer in step S103 of embodiment 1 of the present invention; Figure 5 This is a schematic structural diagram of forming metal electrodes at the first semiconductor opening region and the second semiconductor opening region on the back side of the silicon wafer in step S104 of embodiment 1 of the present invention; Figure 6 It is a schematic diagram of the structure of a conventional back-contact battery in the prior art.

[0038] Description of reference numerals: 1. Silicon wafer; 2. First intrinsic semiconductor film layer; 3. First conductive semiconductor film layer; 4. Second intrinsic semiconductor film layer; 5. Second conductive semiconductor film layer; 6. Front film layer; 7. Crack ink; 8. Conductive film layer; 9. Metal electrode; 10. Mask layer; 101. Surface of silicon wafer in the second semiconductor opening area; 102. Side edge. DETAILED DESCRIPTION

[0039] The term "comprising" in the specification and claims of the present application and the drawings is synonymous with "including", "containing" or "characterized by", and is inclusive or open-ended, and does not exclude additional undescribed elements or method steps. "Comprising" is a technical term used in the claim language, meaning that the elements are present, but other elements may also be added and still form a structure or method within the scope of the claim.

[0040] It should be noted that similar reference numerals and letters represent similar items in the following drawings, so once an item is defined in one drawing, it does not need to be further defined and explained in the subsequent drawings. In addition, the terms "first", "second", "third", etc. are only used to distinguish the description and cannot be understood as indicating or implying relative importance. The term "about" in this application means to include a small change (up to + / -10%) from the stated value.

[0041] In the first aspect, the present application provides a back-contact battery, comprising a silicon wafer, a first semiconductor layer, a second semiconductor layer, crack ink and a conductive film layer; the silicon wafer has a front side and a back side; the first semiconductor layer is arranged on the back side of the silicon wafer, and the first semiconductor layer is evenly spaced apart with second semiconductor opening areas; the second semiconductor layer is continuously arranged on the outer surface of the first semiconductor layer and in the second semiconductor opening area, and the second semiconductor layer is provided with first semiconductor opening areas spaced apart from the second semiconductor opening areas; the crack ink is arranged at the side edge of the second semiconductor opening area and in direct contact with the second semiconductor layer, and the two ends of the crack ink extend a preset distance along the horizontal direction of the silicon wafer respectively; wherein a plurality of cracks extending to the surface of the crack ink are formed in the crack ink, and the width of the crack is ≤20 μm; the conductive film layer is continuously arranged on the outer surface of the second semiconductor layer, on the crack ink and in the first semiconductor opening area, and the conductive film layer is disconnected at the crack on the surface of the crack ink and forms an insulating channel together with the crack.

[0042] It should be noted that the width of the crack is ≤20μm, which means that the width of each crack on each crack ink is no more than 20μm, but the minimum width of the crack should be greater than 0, and cracks must exist on the crack ink to form an insulating channel with the conductive film layer. The insulating channel specifically means that when the conductive film layer is deposited on the surface of the crack ink, it is only deposited on the complete and continuous surface of the crack ink, and the area with cracks on the surface of the crack ink will naturally break, and the cracks of the conductive film layer and the cracks extending inward from the crack ink together form an insulating channel. Compared with the insulating groove, the insulating channel has a deeper crack depth and a larger number, which can greatly improve the insulation isolation effect.

[0043] The present application makes the width of the crack ≤20μm. Although the insulation isolation effect will be improved as the width of the crack increases, the size of the crack ink is limited. If the width of the crack is too large, the number of cracks on each crack ink will be reduced, which will affect the insulation isolation effect. At the same time, a crack width that is too large will also increase the instability of the crack ink. Therefore, on the basis of ensuring the insulation isolation effect of a single crack, the width of the crack is limited to no more than 20μm. This can increase the number of cracks on the crack ink to a certain extent, which is beneficial to improving the insulation isolation effect.

[0044] It should be noted that the shapes of the cracks in the crack ink in the present application can be various, and the shapes of the cracks can be straight, curved, etc., and multiple cracks can also be interconnected inside the crack ink, but the above situation does not affect the technical effect of the present application, and the present application does not limit it.

[0045] Preferably, the crack ink of the present application is arranged at the side edge of the second semiconductor opening area. When the conductive film layer is disconnected at the crack on the surface of the crack ink and forms an insulating channel together with the crack, the conductive film layer will not cross the side edge of the second semiconductor opening area in the horizontal direction of the silicon wafer, thereby avoiding leakage between the first semiconductor layer and the second semiconductor layer, thereby greatly improving the parallel resistance of the battery, and further improving the battery efficiency and battery yield.

[0046] In some embodiments, the width of both ends of the crack ink along the horizontal direction of the silicon wafer is 20-200 μm, the extension distance of one end of the crack ink along the direction of the first semiconductor layer is ≥10 μm, and the extension distance of the other end of the crack ink along the direction of the second semiconductor opening area is ≥10 μm. The crack ink adopts a suitable width of different ranges, which can further reduce the short circuit leakage between the first semiconductor layer and the second semiconductor layer, and is more conducive to improving the parallel resistance of the battery and the battery conversion efficiency.

[0047] It should be noted that the horizontal direction of the silicon wafer refers to the extending direction of the first semiconductor layer or the second semiconductor layer.

[0048] In some embodiments, the maximum thickness of the crack ink along the vertical direction of the silicon wafer is 2-20 μm. Preferably, the maximum thickness of the crack ink along the vertical direction of the silicon wafer is 5-15 μm. It is understandable that the thickness of each crack ink is generally low at both ends and high in the middle, so the maximum thickness generally appears in the middle of each crack ink. At the same time, there are differences in thickness between different crack inks. Therefore, the maximum thickness in this application refers to the maximum thickness of any crack ink in the vertical direction along the silicon wafer, which is within the range of 2-20 μm. Reasonable setting of the thickness of the crack ink can further improve the battery conversion efficiency and battery yield.

[0049] It should be noted that the vertical direction of the silicon wafer refers to the stacking direction of the layers on the back side of the silicon wafer.

[0050] In some embodiments, the width of the first semiconductor opening region is 0.15-0.5 mm, and the width of the second semiconductor opening region is 0.3-0.6 mm.

[0051] In some embodiments, the crack ink is a UV-curable crack ink or a thermosetting crack ink. Preferably, the crack ink is a UV-curable crack ink. Compared with thermosetting crack ink, UV-curable crack ink is formed by UV curing after printing, which is more conducive to the formation of cracks. The possible reasons are as follows: Thermosetting crack ink mainly relies on thermal curing shrinkage to form cracks, the formation conditions are relatively simple, and the thermal curing time is long, which is not conducive to the formation of internal stress inside the material to form cracks. UV curing can first use UV light of different wavelengths to irradiate the crack ink, which can better control the formation conditions. At the same time, the UV curing time is very fast, the volume shrinkage inside the material is faster, and it is easier to generate internal stress inside the material to form cracks.

[0052] In some embodiments, the UV-curable crack ink is composed of the following components in percentage by weight: 70-85% resin, 2-10% additive, 0.5-5% solvent, 5-15% filler and 1-5% photoinitiator.

[0053] In some embodiments, the resin is one or a combination of acrylic resin, phenolic resin, and epoxy resin. Preferably, the resin is acrylic resin. The amount and type of resin affect the width of the cracks. The specific reason is that different types of resins have differences in chemical structure and properties, and these differences will cause different behaviors of the ink during drying and curing. Some resins have high flexibility, which will reduce the generation of cracks. The preferred acrylic resin in this application is relatively rigid and is more likely to shrink and stress during the drying process, thereby increasing the number of cracks.

[0054] In some embodiments, the auxiliary agent is one or a combination of benzophenone, tertiary amine acrylate, polyester solution, polyether compound, silicone oil, and mineral oil. Preferably, the auxiliary agent is a polyester solution. The purpose of adding the auxiliary agent is to modify the ink, such as viscosity, flexibility, bubbles, etc. It should be noted that the above-mentioned auxiliary agents added in the present application can reduce the flexibility of the ink as a whole to a certain extent, thereby making the ink more susceptible to shrinkage and stress during the curing process, thereby generating cracks.

[0055] In some embodiments, the solvent is one or a combination of propylene glycol, ethyl acetate, butyl acetate, acetone, toluene, and ethanol. Preferably, the solvent is ethyl acetate. The purpose of adding the solvent is to dissolve and dilute other components in the ink.

[0056] In some embodiments, the filler is one or a combination of calcium carbonate, magnesium carbonate, barium sulfate, aluminum hydroxide, lithopone, and aluminum silicate. Among them, aluminum silicate can also be replaced by kaolin. Preferably, the filler is calcium carbonate. The purpose of adding the filler is to utilize the significant difference in thermal expansion coefficient between the filler and the resin matrix to cause shear stress to form suitable cracks at the interface during curing.

[0057] It should be noted that the present application has no special requirements for the photoinitiator, and common commercial products in the field can be used.

[0058] In some embodiments, the composition of the thermosetting crack ink is similar to that of the UV curing crack ink, except that the thermosetting crack ink does not contain a photoinitiator, and the lack of photoinitiator is supplemented by a solvent.

[0059] Preferably, the crack ink of the present application has stable properties and can be retained on the battery cell for a long time. The present application uses a specific crack ink formula to form a plurality of cracks extending to the surface of the crack ink, and the cracks have a specific width. The existence of such cracks can greatly improve the insulation isolation effect.

[0060] In some embodiments, the size and number of cracks can be adjusted by adjusting the ratio of resin to additives and / or fillers.

[0061] In some embodiments, the first semiconductor layer includes a first intrinsic semiconductor film layer and a first conductive semiconductor film layer, and the second semiconductor layer includes a second intrinsic semiconductor film layer and a second conductive semiconductor film layer. Preferably, the first intrinsic semiconductor film layer is a tunneling oxide layer, the first conductive semiconductor film layer is an N-type doped polysilicon layer, the second intrinsic semiconductor film layer is an intrinsic amorphous silicon layer, and the second conductive semiconductor film layer is a P-type doped amorphous / microcrystalline silicon layer.

[0062] Those skilled in the art can select the thickness of the second semiconductor layer, the thickness ratio of the intrinsic amorphous silicon layer and the P-type doped amorphous / microcrystalline silicon layer, and the doping concentration of the P-type doped amorphous / microcrystalline silicon layer according to actual needs. For example, the thickness of the second semiconductor layer can be 10-20nm, the thickness ratio of the intrinsic amorphous silicon layer and the P-type doped amorphous / microcrystalline silicon layer can be 1:1-3, and the effective doping concentration of the P-type doped amorphous / microcrystalline silicon layer is 3e18-3e20cm -3 .

[0063] Those skilled in the art can select the thickness of the first semiconductor layer, the thickness ratio of the tunneling oxide layer and the N-type doped polysilicon layer, the doping concentration of the N-type doped polysilicon layer, and the thickness of the conductive film layer according to actual needs. For example, the thickness of the first semiconductor layer can be 60-150nm, the thickness ratio of the tunneling oxide layer and the N-type doped polysilicon layer can be 1:40-100, and the effective doping concentration of the N-type doped polysilicon layer is 1e18-1e21cm -3 For example, the thickness of the conductive film layer may be 40-100 nm.

[0064] It should be noted that the present invention is applicable to both heterojunction passivation structures and combined passivation structures with a greater risk of short circuit and leakage, and can solve the short circuit and leakage problems between the first semiconductor layer and the second semiconductor layer.

[0065] In some embodiments, the back contact battery further includes a metal electrode, which is disposed on the outer surface of the conductive film layer and disposed in the first semiconductor opening region and the second semiconductor opening region. The metal electrode is divided into two types of electrodes with different polarities, and the polarities of the metal electrode disposed on the first semiconductor opening region and the metal electrode disposed on the second semiconductor opening region are different.

[0066] In some embodiments, the back contact battery also includes a front film layer, which is arranged on the front side of the silicon wafer, and the front film layer includes a silicon dielectric passivation layer and a silicon dielectric anti-reflection layer. Those skilled in the art can select the thickness of the front film layer according to actual needs, for example, the thickness of the front film layer can be 50-120nm. Those skilled in the art can select the thickness ratio of the silicon dielectric passivation layer and the silicon dielectric anti-reflection layer according to actual needs. The silicon dielectric passivation layer can be, for example, silicon dioxide, amorphous silicon or microcrystalline silicon layer, and the silicon dielectric anti-reflection layer can be, for example, silicon nitride, silicon oxynitride or silicon dioxide.

[0067] In some embodiments, the front side of the silicon wafer is a textured surface, and the surface of the silicon wafer at the second semiconductor opening region is a textured surface or a polished surface.

[0068] In some embodiments, those skilled in the art may select the type of silicon wafer according to actual needs. For example, the silicon wafer may be N-type.

[0069] In a second aspect, the present application also provides a method for preparing a back contact battery, the preparation method comprising the following steps: S101, forming a first semiconductor layer having a second semiconductor opening region on the back side of the silicon wafer, disposing a second semiconductor layer on the outer surface of the first semiconductor layer and in the second semiconductor opening region, and disposing a first semiconductor opening region spaced apart from the second semiconductor opening region on the second semiconductor layer; S102, printing and curing crack ink on the side edges of the second semiconductor opening region on the back side obtained in S101; Wherein, each crack ink has a plurality of cracks extending to its surface, and the width of the cracks is ≤20 μm; S103, depositing a conductive film layer on the back surface obtained in S102; The conductive film layer is disconnected at the cracks on the surface of the crack ink and forms an insulating channel together with the cracks.

[0070] In some embodiments, in S102, when the crack ink is a UV curable crack ink, UV curing is used to form the crack ink after printing, and the UV curing energy is 500-10000 mj / cm 2 , can be, 500mj / cm 2 、1000mj / cm 2 、2000mj / cm 2 、3000mj / cm 2 、4000mj / cm 2 、5000mj / cm 2 、6000mj / cm 2 、7000mj / cm 2 、8000mj / cm 2 、9000mj / cm 2 、10000mj / cm 2 And any value therebetween, preferably, the UV curing energy is 3000-6000mj / cm 2 .

[0071] The UV curing temperature is 50-200°C, and can be 50°C, 100°C, 150°C, or 200°C. Preferably, the UV curing temperature is 100-150°C.

[0072] Preferably, the UV curing energy is 3000-6000mj / cm 2, UV curing temperature is 100-150℃. UV curing energy and temperature will affect the number and width of cracks. The possible reasons are as follows: UV curing energy and temperature directly affect the curing speed. Appropriate UV energy and temperature can speed up the curing speed of ink. Rapid curing helps to form crack patterns because the surface of the ink cures quickly while the inside remains soft. This difference makes it easier to form cracks. Controlling UV curing energy and temperature can also adjust the morphology of cracks. When the UV curing energy and UV curing temperature are the preferred conditions, the ideal crack width and number can be obtained. Too high or too low energy and temperature may result in a reduction in the number of cracks or uneven widths.

[0073] In some embodiments, in S102, when the crack ink is a thermosetting crack ink, thermal curing is used to form the crack ink after printing, the thermal curing temperature is 150-200°C, and the thermal curing time is 5-30 minutes.

[0074] In some embodiments, before S101 , it also includes forming a textured surface and a front film layer on the front side of the silicon wafer.

[0075] In some embodiments, the conductive film layer is deposited by physical vapor deposition technology (PVD) or activated plasma deposition technology (RPD), and the conductive film layer is an indium oxide-based film doped with tin, zinc, tungsten, titanium, etc., or a zinc oxide-based film doped with aluminum, boron, gallium, etc.

[0076] In some embodiments, after S103, metal electrodes are formed on the outer surfaces of the corresponding conductive film layers in the areas where the first semiconductor opening area and the second semiconductor opening area are located. The metal electrode can be formed by printing silver paste to form a silver paste grid electrode, electroplating to form a grid electrode, etc. It can be seen that by adopting the technical solution of the present application, after depositing the conductive film layer in S103, S104 can be directly performed to form a metal electrode. By adopting the crack ink technology of the present application, the insulating channel formed has a greater insulation resistance than the insulating groove, and there is no need to form an insulating isolation groove in a special process after depositing the conductive film, thereby simplifying the process flow and improving the battery production yield.

[0077] In some embodiments, during the process of forming a metal electrode, the number of cracks in the crack ink will increase, and the width of the cracks in the crack ink will increase to 5-20 μm. This is because pressure is applied to the crack ink during the preparation of the metal electrode, which will promote the increase in the number of cracks and the deepening of the crack width, which can further improve the insulation isolation effect.

[0078] It should be noted that the width of each crack of each crack ink is not uniform, so the width of the crack of the crack ink increases to 5-20 μm, which means that the minimum width of the crack of the crack ink is 5 μm and the maximum width of the crack of the crack ink is 20 μm.

[0079] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0080] Example 1 A method for preparing a back contact battery, the method comprising the following steps: S101, such as Figure 1 As shown, an N-type silicon wafer 1 is provided, a first semiconductor layer having a second semiconductor opening region is formed on the back side of the silicon wafer 1, a second semiconductor layer is arranged on the outer surface of the first semiconductor layer and in the second semiconductor opening region, and a first semiconductor opening region arranged at intervals with the second semiconductor opening region is arranged on the second semiconductor layer; The first semiconductor layer comprises a first intrinsic semiconductor film layer 2 (specifically a tunneling oxide layer with a thickness of 1.7 nm), a first conductive semiconductor film layer 3 (specifically an N-type doped polysilicon layer with a thickness of 100 nm and an effective doping concentration of 1e20 cm-1), and a -3 The second semiconductor layer includes a second intrinsic semiconductor film layer 4 (specifically an intrinsic amorphous silicon layer with a thickness of 6 nm), a second conductive semiconductor film layer 5 (specifically a P-type doped amorphous silicon layer with a thickness of 10 nm and an effective doping concentration of 5e19 cm -3 ), a front film layer 6 is formed on the front of the silicon wafer 1. The front film layer 6 includes a silicon dielectric passivation layer (specifically an intrinsic amorphous silicon layer with a thickness of 10nm) and a silicon dielectric anti-reflection layer (specifically silicon nitride with a thickness of 75nm). The width W1 of the first semiconductor opening area is 0.2mm, the width W2 of the second semiconductor opening area is 0.4mm, and the surface 101 of the silicon wafer in the second semiconductor opening area is a polished surface.

[0081] S102, such as Figure 2 As shown, crack ink 7 is printed on the side edge 102 of the second semiconductor opening region, the width of both ends of the crack ink 7 along the horizontal direction of the silicon wafer 1 is 90 μm, the extension distance W11 of one end of the crack ink 7 along the direction of the first semiconductor layer is 50 μm, the extension distance W12 of the other end of the crack ink 7 along the direction of the second semiconductor opening region is 40 μm, and the maximum thickness of the crack ink 7 along the vertical direction of the silicon wafer 1 is 5-15 μm; like Figure 3 As shown, crack ink 7 is a UV curable crack ink (specifically composed of 83% acrylic resin, 5% polyester solution, 1% ethyl acetate, 10% calcium carbonate and 1% photoinitiator). After printing, UV curing is used to form crack ink 7, and the UV curing energy is 5000mj / cm 2 , the UV curing temperature is 130° C.; wherein, each crack ink 7 is formed with a plurality of cracks extending to its surface, and the width of the crack W3 is ≤20 μm.

[0082] S103, such as Figure 4 As shown, in S102 , a conductive film layer 8 is deposited on the back surface, and the thickness of the conductive film layer 8 is 60 nm. The conductive film layer 8 is deposited by physical vapor deposition (PVD) technology, and the conductive film layer 8 is a tin-doped indium oxide-based thin film.

[0083] The conductive film layer 8 is disconnected at the cracks on the surface of the crack ink 7 and forms an insulating channel together with the cracks.

[0084] S104, such as Figure 5 As shown, metal electrodes 9 are formed on the outer surfaces of the corresponding conductive film layer 8 in the first semiconductor opening area and the second semiconductor opening area. The metal electrodes 9 are formed into silver paste grid electrodes by printing silver paste. In the process of forming the metal electrodes, the number of cracks in the crack ink increases and the width of the cracks in the crack ink increases until it is 5-20 μm.

[0085] Example 2 The method of Example 1 is referred to, except that the crack ink in S102 is a thermosetting crack ink (specifically composed of 80% acrylic resin, 6% polyester solution, 6% ethyl acetate, and 8% calcium carbonate), and thermal curing is used to form the crack ink after printing. The thermal curing temperature is 170°C and the thermal curing time is 20 minutes.

[0086] Example 3 The method of Example 1 is referred to, except that in S101, the maximum thickness of the crack ink along the vertical direction of the silicon wafer is 2-5 μm.

[0087] Example 4 The method of Example 1 is referred to, except that in S104, the final width of the cracks of the crack ink is 5-15 μm, and the process parameters that need to be adjusted to meet this condition are: in S102, the crack ink is a UV-curable crack ink, and the composition of the crack ink is adjusted to 78% acrylic resin, 5% polyester solution, 1% ethyl acetate, 15% calcium carbonate and 1% photoinitiator.

[0088] Example 5 The method of Example 1 is referred to, except that in S104, the final width of the crack of the crack ink is 5-15 μm. The process parameters that need to be adjusted to meet this condition are: adjusting the UV curing energy to 8000 mj / cm 2 , UV curing temperature is 150℃.

[0089] Example 6 The method of Example 1 is referred to, except that a conventional heterojunction passivation structure is adopted, the tunneling oxide layer in the first semiconductor layer is replaced by intrinsic amorphous silicon, and the N-type doped polysilicon layer is replaced by an N-type doped amorphous layer, the thickness of the intrinsic amorphous silicon is 8 nm, and the thickness of the N-type doped amorphous layer is 12 nm.

[0090] Comparative Example 1 like Figure 6 As shown, the side edge 102 is not provided with crack ink 7, the second semiconductor layer is in direct contact with the conductive film layer 8, and a mask layer 10 (specifically silicon nitride) is provided in the area between the first semiconductor opening area and the second semiconductor opening area in the horizontal direction of the silicon wafer 1, and the mask layer 10 is located between the first semiconductor layer and the second semiconductor layer, and the isolation groove is opened on the first semiconductor and does not cross the side edge of the first semiconductor. The preparation method thereof is carried out with reference to the method in the prior art.

[0091] Comparative Example 2 The method of Example 1 is referred to, except that the P / N types of the two semiconductor layers are different. Specifically, the doped polysilicon layer in the first semiconductor layer is a P-type doped polysilicon layer, and the doped amorphous silicon layer in the second semiconductor layer is an N-type doped amorphous silicon layer.

[0092] Comparative Example 3 The method of Example 1 is referred to, except that in S104, the final width of the cracks of the crack ink is greater than 20 μm, and the process parameters that need to be adjusted to meet this condition are: in S102, the crack ink is a UV-curable crack ink, and the composition of the crack ink is adjusted to 90% acrylic resin, 5% polyester solution, 1% ethyl acetate, 3% calcium carbonate and 1% photoinitiator.

[0093] Adjust UV curing energy to 6000mj / cm 2 , UV curing temperature is 150℃.

[0094] Test Case The back contact cells obtained in the above examples and comparative examples were subjected to various performance tests, and the results are shown in Table 1. The cell yield refers to the cell qualification rate when the batch production quantity is 1000 pieces.

[0095] Table 1

[0096] It can be seen from the above results that, compared with the comparative example, the crack width of the crack ink can be obtained by adopting the embodiment of the present invention, thereby increasing the parallel resistance of the back contact battery, effectively avoiding leakage, and taking into account the improvement of battery conversion efficiency and battery yield. At the same time, the crack ink technology of the present application forms an insulating channel with a greater insulation resistance than the insulating groove, and there is no need to form an insulating isolation groove in a special process after depositing the conductive film, thereby simplifying the process flow and further improving the battery production yield.

[0097] Furthermore, according to Example 1 and Example 2, compared with the thermal curing crack ink, the preferred UV curing crack ink and the method for forming the same according to the present invention can further improve the battery conversion efficiency and battery yield.

[0098] Furthermore, according to Example 1 and Example 3, the use of the solution of crack ink with the preferred maximum thickness of the present invention can further improve the battery conversion efficiency and battery yield.

[0099] Furthermore, according to Example 1 and Example 4, it can be seen that by using the preferred crack ink composition content of the present invention, cracks with more preferred widths can be obtained, which can further improve the battery conversion efficiency and battery yield.

[0100] Furthermore, according to Example 1 and Example 5, it can be seen that by adopting the preferred UV curing parameters of the present invention, cracks with more preferred widths can be obtained, which can further improve the battery conversion efficiency and battery yield.

[0101] Furthermore, according to Example 1 and Example 6, it can be seen that the solution of the present invention is particularly suitable for the solution of the combined passivation structure, which can further improve the battery conversion efficiency and battery yield.

[0102] Reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present application. The appearance of the phrase in various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0103] The embodiments of the present application are introduced in detail above. Specific examples are used in this article to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method and core idea of ​​the present application. At the same time, for general technical personnel in this field, according to the idea of ​​the present application, there will be changes in the specific implementation method and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. A back contact battery, comprising: A silicon wafer having a front side and a back side; A first semiconductor layer, wherein the first semiconductor layer is disposed on the back side of the silicon wafer, and second semiconductor opening regions are evenly spaced apart on the first semiconductor layer; A second semiconductor layer, wherein the second semiconductor layer is continuously disposed on the outer surface of the first semiconductor layer and in the second semiconductor opening region, and a first semiconductor opening region spaced apart from the second semiconductor opening region is disposed on the second semiconductor layer; It is characterized by further comprising: Crack ink, wherein the crack ink is arranged at the side edge of the second semiconductor opening area and directly contacts the second semiconductor layer, and both ends of the crack ink extend a preset distance along the horizontal direction of the silicon wafer; wherein a plurality of cracks extending to the surface of the crack ink are formed in the crack ink, and the width of the cracks is ≤20 μm; A conductive film layer is continuously arranged on the outer surface of the second semiconductor layer, on the crack ink and in the first semiconductor opening area. The conductive film layer is disconnected at the crack on the surface of the crack ink and forms an insulating channel together with the crack.

2. The back contact cell according to claim 1, characterized in that: The width of the two ends of the crack ink along the horizontal direction of the silicon wafer is 20-200 μm, the extension distance of one end of the crack ink along the direction of the first semiconductor layer is ≥10 μm, and the extension distance of the other end of the crack ink along the direction of the second semiconductor opening area is ≥10 μm; and / or, The maximum thickness of the crack ink along the vertical direction of the silicon wafer is 2-20 μm.

3. The back contact battery according to claim 1, characterized in that: The width of the first semiconductor opening region is 0.15-0.5 mm, and the width of the second semiconductor opening region is 0.3-0.6 mm.

4. The back contact cell according to claim 1, characterized in that: The crack ink is UV curable crack ink or thermosetting crack ink.

5. The back contact cell according to claim 4, characterized in that: The UV curable crack ink is composed of the following components in percentage by mass: 70-85% of resin, 2-10% of auxiliary agent, 0.5-5% of solvent, 5-15% of filler and 1-5% of photoinitiator.

6. The back contact cell according to claim 5, characterized in that: The resin is one or a combination of acrylic resin, phenolic resin and epoxy resin; and / or, The auxiliary agent is one or a combination of benzophenone, tertiary amine acrylate, polyester solution, polyether compound, silicone oil, and mineral oil; and / or, The solvent is one or a combination of propylene glycol, ethyl acetate, butyl acetate, acetone, toluene, and ethanol; and / or, The filler is one or a combination of calcium carbonate, magnesium carbonate, barium sulfate, aluminum hydroxide, lithopone, and aluminum silicate.

7. The back contact cell according to claim 1, characterized in that: The first semiconductor layer includes a first intrinsic semiconductor film layer and a first conductive semiconductor film layer, and the second semiconductor layer includes a second intrinsic semiconductor film layer and a second conductive semiconductor film layer.

8. The back contact cell according to claim 1, characterized in that: The back contact battery further comprises a metal electrode, which is arranged on the outer surface of the conductive film layer and in the first semiconductor opening region and the second semiconductor opening region; and / or, The back contact cell further comprises a front film layer, which is arranged on the front side of the silicon wafer, and comprises a silicon dielectric passivation layer and a silicon dielectric anti-reflection layer; and / or, The front side of the silicon wafer is a textured surface, and the surface of the silicon wafer at the second semiconductor opening area is a textured surface or a polished surface.

9. A method for preparing a back contact battery, characterized in that: The preparation method is used to prepare a back contact battery according to any one of claims 1 to 8, and the preparation method comprises the following steps: S101, forming a first semiconductor layer having a second semiconductor opening region on the back side of the silicon wafer, disposing a second semiconductor layer on the outer surface of the first semiconductor layer and in the second semiconductor opening region, and disposing a first semiconductor opening region spaced apart from the second semiconductor opening region on the second semiconductor layer; S102, printing and curing crack ink on the side edges of the second semiconductor opening region on the back side obtained in S101; Wherein, a plurality of cracks extending to the surface of the crack ink are formed in the crack ink, and the width of the crack is ≤20 μm; S103, depositing a conductive film layer on the back surface obtained in S102; The conductive film layer is disconnected at the cracks on the surface of the crack ink and forms an insulating channel together with the cracks.

10. The preparation method according to claim 9, characterized in that: In S102, when the crack ink is a UV curable crack ink, UV curing is used to form the crack ink after printing, and the UV curing energy is 500-10000mj / cm 2 , UV curing temperature is 50-200℃; and / or, In S102, when the crack ink is a thermosetting crack ink, thermal curing is used to form the crack ink after printing, the thermal curing temperature is 150-200°C, and the thermal curing time is 5-30 minutes.

11. The preparation method according to claim 9, characterized in that: Before S101, it also includes forming a textured surface and a front film layer on the front side of the silicon wafer; and / or, After S103 , the method further includes forming metal electrodes on the outer surfaces of the conductive film layers corresponding to the first semiconductor opening region and the second semiconductor opening region.

12. The preparation method according to claim 11, characterized in that: During the formation of the metal electrode, the number of cracks in the crack ink increases; and / or, During the formation of the metal electrode, the width of the cracks of the crack ink increases to 5-20 μm.

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