Epitaxial wafer, manufacturing method of epitaxial wafer, light-emitting chip and manufacturing method of light-emitting chip

Abstract

The invention relates to an epitaxial wafer and a manufacturing method thereof, and a light-emitting chip and a manufacturing method thereof, and the epitaxial wafer comprises a substrate, one side of the substrate is provided with a plurality of protrusions, and the surface of the substrate between the protrusions is a plane area; the nucleation guide layer is arranged on the substrate, the nucleation guide layer comprises a first guide part and a second guide part, the first guide part completely covers the plane area, the second guide part covers part of the side wall of the bulge, and the first guide part is connected with the second guide part; the buffer layer grows by taking the nucleation guide layer as the center; the first semiconductor layer, the active layer and the second semiconductor layer are sequentially grown on the buffer layer. The first guide part can guide the buffer layer to perform nucleation growth towards the c surface in the sapphire crystal structure, so that the growth of other crystal orientations is inhibited, the dislocation density generated in the growth process of the buffer layer can be greatly reduced, and the crystal quality of the epitaxial layer is improved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to an epitaxial wafer and a method for manufacturing the same, a light-emitting chip and a method for manufacturing the same. Background Art

[0002] Mini LED (Mini Light Emitting Diode, sub-millimeter light-emitting diode), which has the advantages of high brightness, wide color gamut coverage, high contrast, and more saturated colors, has been sought after by various manufacturers.

[0003] Currently, in the production process of Mini LED chips, an epitaxial layer is usually grown on a sapphire substrate. However, due to the large lattice mismatch between the epitaxial layer and sapphire, the epitaxial layer grows disorderly along different crystal directions on the sapphire substrate, resulting in a large number of dislocations in the epitaxial layer during the growth process, which greatly reduces the crystallization quality of the epitaxial layer.

[0004] Therefore, how to improve the crystallization quality of the epitaxial layer is an urgent problem to be solved. Summary of the invention

[0005] In view of the deficiencies of the above-mentioned related technologies, the purpose of the present application is to provide an epitaxial wafer and a method for manufacturing the same, a light-emitting chip and a method for manufacturing the same, aiming to solve the problem of poor crystal quality of the epitaxial layer.

[0006] An epitaxial wafer, comprising:

[0007] A substrate, wherein one side of the substrate has a plurality of protrusions, and a surface of the substrate between the protrusions is a plane area;

[0008] a nucleation guide layer disposed on the substrate, the nucleation guide layer comprising a first guide portion completely covering the planar area, and a second guide portion covering a portion of the sidewall of the protrusion, the first guide portion being connected to the second guide portion;

[0009] a buffer layer growing around the nucleation guide layer; and

[0010] A first semiconductor layer, an active layer, and a second semiconductor layer are sequentially grown on the buffer layer.

[0011] In the above-mentioned epitaxial wafer, a nucleation guide layer is arranged on one side of the substrate, wherein the first guide portion of the nucleation guide layer is arranged in a plane area on the surface of the substrate, and the plane area corresponds to the c-plane in the sapphire crystal structure. Therefore, the first guide portion can guide the buffer layer to nucleate and grow toward the c-plane in the sapphire crystal structure, inhibiting the growth of other crystal directions, greatly reducing the dislocation density generated during the growth of the buffer layer, and improving the crystal quality of the buffer layer, thereby making the crystal quality of the first semiconductor layer grown on this buffer layer better, and optimizing the light-emitting effect of the light-emitting chip. Moreover, the second guide portion is arranged on the side wall of the protrusion, which can solve the problem that the side wall portion of the protrusion is prone to generate voids when nucleating and growing along the c-plane. The arrangement of the second guide portion can release the residual stress of the lattice mismatch between the sapphire and the buffer layer in the side wall portion of the protrusion, reducing the number of voids generated during crystallization, and further improving the crystal quality.

[0012] Based on the same inventive concept, the present application also provides a method for manufacturing the epitaxial wafer as described above, comprising:

[0013] Disposing the nucleation guide layer on the substrate so that the first guide portion of the nucleation guide layer completely covers the plane area, and the second guide portion of the nucleation guide layer covers a portion of the side wall of the protrusion;

[0014] growing a buffer layer with the nucleation guide layer as the center;

[0015] A first semiconductor layer, an active layer and a second semiconductor layer are sequentially grown on the buffer layer.

[0016] In the above-mentioned method for making an epitaxial wafer, a nucleation guide layer is arranged on the substrate, so that the first guide portion of the nucleation guide layer completely covers the plane area, and the second guide portion of the nucleation guide layer covers part of the side wall of the protrusion. The plane area on the substrate surface corresponds to the c-plane in the sapphire crystal structure, so the first guide portion can guide the buffer layer to nucleate and grow toward the c-plane in the sapphire crystal structure, inhibiting the growth of other crystal directions, greatly reducing the dislocation density generated during the growth of the buffer layer, and improving the crystal quality of the buffer layer, thereby making the crystal quality of the first semiconductor layer grown on this buffer layer better, and optimizing the light-emitting effect of the light-emitting chip. Moreover, the second guide portion is arranged on the side wall of the protrusion, which can solve the problem that the side wall portion of the protrusion is prone to generate voids when nucleating and growing along the c-plane. The arrangement of the second guide portion can release the residual stress of the lattice mismatch between the sapphire and the buffer layer in the side wall portion of the protrusion, reducing the number of voids generated during crystallization, and further improving the crystal quality.

[0017] Based on the same inventive concept, the present application also provides a method for manufacturing a light-emitting chip, comprising:

[0018] Providing the epitaxial wafer as described above;

[0019] Fabricating a first electrode and a second electrode on the epitaxial wafer;

[0020] The epitaxial wafer is cut into a plurality of independent light-emitting chips.

[0021] In the above-mentioned method for manufacturing the light-emitting chip, in the epitaxial wafer provided, the first guide portion of the nucleation guide layer is arranged in a plane area, and the plane area corresponds to the c-plane in the sapphire crystal structure. Therefore, the first guide portion can guide the buffer layer to nucleate and grow toward the c-plane in the sapphire crystal structure, inhibiting the growth of other crystal directions, greatly reducing the dislocation density generated during the growth of the buffer layer, and improving the crystal quality of the buffer layer, thereby making the crystal quality of the first semiconductor layer grown on this buffer layer better, and optimizing the light-emitting effect of the light-emitting chip. Moreover, the second guide portion is arranged on the side wall of the protrusion, which can solve the problem that the side wall portion of the protrusion is prone to generate voids when nucleating and growing along the c-plane. The setting of the second guide portion can release the residual stress of the lattice mismatch between the sapphire and the buffer layer in the side wall portion of the protrusion, reducing the number of voids generated during crystallization, further improving the crystal quality, and making the light-emitting effect of the light-emitting chip better.

[0022] Based on the same inventive concept, the present application also provides a light-emitting chip, which is manufactured using the light-emitting chip manufacturing method as described above, and the light-emitting chip includes the first electrode and the second electrode, the first electrode is electrically connected to the first semiconductor layer of the epitaxial wafer, and the second electrode is electrically connected to the second semiconductor layer of the epitaxial wafer.

[0023] The above-mentioned light-emitting chip is made of the above-mentioned epitaxial wafer, and the epitaxial wafer is provided with a nucleation guide layer on the substrate, and the first guide part of the nucleation guide layer is provided in a plane area, and the plane area corresponds to the c-plane in the sapphire crystal structure. Therefore, the first guide part can guide the buffer layer to nucleate and grow toward the c-plane in the sapphire crystal structure, inhibit the growth of other crystal directions, greatly reduce the dislocation density generated during the growth of the buffer layer, and improve the crystal quality of the buffer layer, thereby making the crystal quality of the first semiconductor layer grown on this buffer layer better, and optimizing the light-emitting effect of the light-emitting chip. Moreover, the second guide part is provided on the side wall of the protrusion, which can solve the problem that the side wall part of the protrusion is prone to generate voids when nucleating and growing along the c-plane. The provision of the second guide part can release the residual stress of the lattice mismatch between the sapphire and the buffer layer in the side wall part of the protrusion, reduce the number of voids generated during crystallization, further improve the crystal quality, and make the light-emitting effect of the light-emitting chip better. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 A schematic diagram of the structure of an epitaxial wafer provided in an embodiment of the present application;

[0025] Figure 2 A schematic diagram of the structure of a substrate provided in an embodiment of the present application;

[0026] Figure 3 A flow chart of a method for manufacturing an epitaxial wafer provided in another optional embodiment of the present application;

[0027] Figure 4 A flow chart of providing a nucleation guide layer on a substrate provided in another optional embodiment of the present application;

[0028] Figure 5 A schematic structural diagram of a nucleation film layer provided on a substrate according to another optional embodiment of the present application;

[0029] Figure 6 A schematic diagram of a structure for providing a photoresist layer provided in another optional embodiment of the present application;

[0030] Figure 7 A schematic diagram of a structure for setting a mask provided in another optional embodiment of the present application;

[0031] Figure 8 A schematic diagram of a structure after exposure and development provided by another optional embodiment of the present application;

[0032] Fig. 9 A schematic diagram of the structure after removing the nucleation film layer not covered by the photoresist provided in another optional embodiment of the present application.

[0033] Fig.10 A schematic structural diagram of a nucleation guide layer provided on a substrate according to another optional embodiment of the present application;

[0034] Fig.11 A schematic diagram of a process of forming a nucleation guide layer when providing a protective layer provided in another optional embodiment of the present application;

[0035] Fig.12 A flowchart of a method for manufacturing a light-emitting chip provided in yet another optional embodiment of the present application;

[0036] Fig.13 A schematic structural diagram of a light-emitting chip provided in yet another optional embodiment of the present application;

[0037] Description of reference numerals:

[0038] 1-substrate; 101-planar area; 102-sidewall; 103-protrusion; 2-nucleation guide layer; 201-first guide part; 202-second guide part; 3-buffer layer; 4-first semiconductor layer; 5-active layer; 6-second semiconductor layer; 7-first electrode; 8-second electrode; 9-photoresist layer; 10-mask; 11-protective layer; 12-nucleation film layer. DETAILED DESCRIPTION

[0039] In order to facilitate the understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present application are given in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thoroughly and comprehensively understood.

[0040] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0041] In the process of manufacturing Mini LED chips, a GaN epitaxial layer is usually grown on a sapphire substrate. However, due to the large lattice mismatch between the GaN epitaxial layer and sapphire, the GaN epitaxial layer grows randomly along different crystal directions on the sapphire substrate, which causes a large number of dislocations in the epitaxial layer during growth, greatly reducing the crystal quality of the epitaxial layer. At present, the sapphire substrate is usually a patterned sapphire substrate with several protruding structures.

[0042] Based on this, the present application hopes to provide a solution that can solve the above-mentioned technical problems, the details of which will be described in the subsequent embodiments.

[0043] The present application embodiment provides an epitaxial wafer, such as Figure 1 , Figure 2 As shown, it includes a substrate 1, a nucleation guide layer 2, a buffer layer 3, a first semiconductor layer 4, an active layer 5, and a second semiconductor layer 6.

[0044] In this embodiment, one side of the substrate 1 has a plurality of protrusions 103, and the surface of the substrate 1 between the protrusions 103 is a plane area 101. It is understood that the side wall 102 of the protrusion 103 in this embodiment may be an inclined surface, and the inclined surface and the plane area 101 are at an angle of less than 90 degrees. In this embodiment, the inclined surface may be a plane that is not parallel to the plane area 101, or a curved surface. In this embodiment, the height of the protrusion 103 may be, but not limited to, 1.7 μm-1.9 μm, and the distance between the bottoms of the protrusions 103, that is, the width of the plane area 101 may be, but not limited to, 2.9 μm-3.1 μm. The substrate 1 in this embodiment may be, but not limited to, a patterned sapphire substrate 1, and the shape of the protrusion 103 may be a cone with a small top and a large bottom, or a prism with a small top and a large bottom, or other protrusion structures formed after patterning. The plane area 101 in this embodiment corresponds to the c-plane in the sapphire crystal structure.

[0045] like Fig.10 As shown, the nucleation guide layer 2 in this embodiment is provided on the substrate 1, and the nucleation guide layer 2 includes a first guide portion 201 that completely covers the plane area 101, and a second guide portion 202 that covers part of the side wall 102 of the protrusion 103, and the first guide portion 201 is connected to the second guide portion 202. It can be understood that the first guide portion 201 and the second guide portion 202 in this embodiment can be an integral structure formed at one time, or the first guide portion 201 and the second guide portion 202 can also be formed separately, and the material of the nucleation guide layer 2 in this embodiment includes AlN.

[0046] The buffer layer 3 in this embodiment is grown with the nucleation guide layer 2 as the center; the first semiconductor layer 4, the active layer 5, and the second semiconductor layer 6 are grown on the buffer layer 3 in sequence. It can be understood that the buffer layer 3 can be but not limited to a GaN buffer layer 3, or an AlN buffer layer 3, and the buffer layer 3 can solve the problem of large lattice mismatch between the GaN epitaxial layer and the sapphire, and optimize the crystal growth of the GaN epitaxial layer. The first semiconductor layer 4 in this embodiment can be an N-type semiconductor layer, and the first semiconductor layer 4 can be a P-type semiconductor layer, wherein the N-type semiconductor layer may include an undoped uGaN layer and a doped n-type GaN layer, and the undoped uGaN layer is located between the buffer layer 3 and the n-type GaN layer; the active layer 5 in this embodiment may include an InGaN / GaN multi-quantum well structure, and may also include other structures.

[0047] In some embodiments, Fig.10 As shown, the distance H from one end of the second guide portion 202 away from the plane region 101 to the plane region 101 is less than or equal to 0.5 μm, for example, it can be 0.2 μm or 0.3 μm. This can ensure that the buffer layer 3 nucleates and grows toward the c-plane, and can also solve the problem of easy generation of voids between the side wall 102 of the protrusion 103 and the buffer layer 3. In this embodiment, the thickness of the nucleation guide layer 2 can be, but is not limited to, 16 nm to 30 nm.

[0048] In the above epitaxial wafer, a nucleation guide layer 2 is provided on one side of the substrate 1, wherein the first guide portion 201 of the nucleation guide layer 2 is provided in the plane region 101, and the plane region 101 corresponds to the c-plane in the sapphire crystal structure. Therefore, the first guide portion 201 can guide the buffer layer 3 to nucleate and grow toward the c-plane in the sapphire crystal structure, inhibit the growth of other crystal directions, greatly reduce the dislocation density generated during the growth of the buffer layer 3, and improve the crystal quality of the buffer layer 3, thereby making the crystal quality of the first semiconductor layer 4 grown on this buffer layer 3 better, and optimizing the light-emitting effect of the light-emitting chip. Moreover, the second guide portion 202 is provided on the side wall 102 of the protrusion 103, which can solve the problem that the side wall 102 of the protrusion 103 is prone to generate voids when the side wall 102 of the protrusion 103 is nucleated and grown along the c-plane. The provision of the second guide portion 202 can release the residual stress of the lattice mismatch between the sapphire and the buffer layer 3 in the side wall 102 of the protrusion 103, reduce the number of voids generated during crystallization, and further improve the crystal quality.

[0049] Another optional embodiment of the present application:

[0050] This embodiment provides a method for manufacturing the epitaxial wafer as described above, such as Figure 3-Figure 11 As shown, the following steps are included:

[0051] S11 : a nucleation guiding layer is disposed on the substrate, so that a first guiding portion of the nucleation guiding layer completely covers the plane area, and a second guiding portion of the nucleation guiding layer covers a portion of the side wall of the protrusion 103 .

[0052] The location, structure and material of the nucleation guide layer 2 in this embodiment are the same as those of the above nucleation guide layer 2, and will not be described in detail here. The nucleation guide layer 2 in this embodiment can be deposited, for example, by magnetron sputtering deposition.

[0053] S12: Grow a buffer layer with the nucleation guide layer as the center.

[0054] S13: sequentially growing a first semiconductor layer, an active layer, and a second semiconductor layer on the buffer layer.

[0055] The buffer layer 3 , the first semiconductor layer 4 , the active layer 5 , and the second semiconductor layer 6 in this embodiment are the same as those in the above embodiment, and will not be described in detail herein.

[0056] In some embodiments, providing a nucleation guide layer 2 on the substrate 1 may include:

[0057] S111: a nucleation film layer is provided on the substrate, and the nucleation film layer completely covers the side of the substrate having the plurality of protrusions.

[0058] The nucleation film layer 12 is provided as Figure 5As shown, the nucleation film layer 12 in this embodiment is a whole layer structure, which can be but not limited to deposited. The material of the nucleation film layer 12 can be AlN.

[0059] S112: Disposing a photoresist layer on the nucleation film layer.

[0060] The photoresist layer 9 is provided as Figure 6 As shown, the photoresist layer 9 in this embodiment completely covers the nucleation film layer 12, and the thickness of the photoresist layer 9 needs to be greater than the height of the protrusion 103 on the substrate 1. In this embodiment, the thickness of the photoresist layer 9 can be greater than 2 μm. This embodiment does not limit the specific setting method of the photoresist, and the photoresist layer 9 can be formed.

[0061] S113: Setting a mask on the photoresist layer.

[0062] The mask 10 is set as Figure 7 As shown, the mask 10 in this embodiment is light-shielded at the portion corresponding to the nucleation guide layer, and the remaining portion may be provided with a light-transmitting or light-transmissive window.

[0063] S114: Expose and develop to remove the photoresist that is not blocked by the mask.

[0064] The structure after exposure and development is as follows Figure 8 shown.

[0065] S115: etching and removing the portion of the nucleation film layer that is not blocked by the photoresist, and the remaining portion of the nucleation film layer after being etched and removed forms a nucleation guide layer including a first guide portion and a second guide portion.

[0066] The structure after etching away the portion of the nucleation film layer 12 not blocked by the photoresist is as follows: Fig. 9 In this embodiment, in order to prevent the photoresist residue from affecting the nucleation guide layer 2, as shown in FIG. Fig.11 As shown, before disposing the photoresist layer 9 on the nucleation film layer 12, the following steps may also be included:

[0067] A protective layer 11 is disposed on the nucleation film layer 12. The protective layer 11 in this embodiment may be, but is not limited to, SiO2, which has high stability. In this embodiment, the protective layer 11 may be formed by, but is not limited to, deposition, for example, magnetron sputtering.

[0068] After the exposure and development to remove the photoresist not blocked by the mask 10, the following steps are also included:

[0069] The portions of the protective layer 11 and the nucleation film layer 12 that are not blocked by the photoresist are removed by etching; and then the photoresist and the protective layer 11 on the nucleation guide layer 2 are removed.

[0070] The protective layer 11 prevents the photoresist from directly contacting the nucleation guide layer 2, which is more conducive to the subsequent growth of the buffer layer 3. Finally, the photoresist on the nucleation guide layer 2 can be removed by a degumming solution, and after organic cleaning, the protective layer 11 on the nucleation guide layer 2 can be removed by wet etching, thereby obtaining a finished epitaxial wafer.

[0071] In the above-mentioned method for manufacturing an epitaxial wafer, a nucleation guide layer 2 is provided on the substrate 1, so that the first guide portion 201 of the nucleation guide layer 2 completely covers the plane area 101, and the second guide portion 202 of the nucleation guide layer 2 covers part of the side wall 102 of the protrusion 103. The plane area 101 on the substrate 1 corresponds to the c-plane in the sapphire crystal structure, so the first guide portion 201 can guide the buffer layer 3 to nucleate and grow toward the c-plane in the sapphire crystal structure, inhibiting the growth of other crystal directions, greatly reducing the dislocation density generated during the growth of the buffer layer 3, and improving the crystal quality of the buffer layer 3, thereby making the crystal quality of the first semiconductor layer 4 grown on this buffer layer 3 better, and optimizing the light-emitting effect of the light-emitting chip. Moreover, the second guide portion 202 is arranged on the side wall 102 of the protrusion 103, which can solve the problem that voids are easily generated when the side wall 102 of the protrusion 103 nucleates and grows along the c-plane. The setting of the second guide portion 202 can release the residual stress of the lattice mismatch between the sapphire on the side wall 102 of the protrusion 103 and the buffer layer 3, thereby reducing the number of voids generated during crystallization and further improving the crystallization quality.

[0072] Another optional embodiment of the present application:

[0073] This embodiment provides a method for manufacturing a light emitting chip. Fig.12 , Fig.13 As shown, including:

[0074] S21: Providing an epitaxial wafer.

[0075] The epitaxial wafer structure and its manufacturing method in this embodiment are the same as those in the above embodiment, and will not be described in detail here.

[0076] S22: Fabricating a first electrode and a second electrode on the epitaxial wafer.

[0077] In this embodiment, the first electrode 7 is electrically connected to the first semiconductor layer 4, and the second electrode 8 is electrically connected to the second semiconductor layer 6. Before manufacturing the electrodes, the epitaxial wafer may be processed by etching or other processes to form a plurality of light-emitting units on the substrate 1. In this embodiment, the materials of the first electrode 7 and the second electrode 8 are not specifically limited. For example, in some embodiments, the materials of the electrodes may include but are not limited to at least one of Cr, Ni, Al, Ti, Au, Pt, W, Pb, Rh, Sn, Cu, and Ag.

[0078] S23: Cutting the epitaxial wafer into a plurality of independent light-emitting chips.

[0079] The light-emitting chip in this embodiment may be a micro LED chip, for example including but not limited to Mini LED (MiniLight Emitting Diode, sub-millimeter light-emitting diode), Micro LED (Micro Light Emitting Diode, micrometer-scale light-emitting diode), nanometer-scale light-emitting diode, and the like.

[0080] In the above-mentioned method for manufacturing the light-emitting chip, in the epitaxial wafer provided, the first guide portion 201 of the nucleation guide layer 2 is arranged in the plane region 101, and the plane region 101 corresponds to the c-plane in the sapphire crystal structure. Therefore, the first guide portion 201 can guide the buffer layer 3 to nucleate and grow toward the c-plane in the sapphire crystal structure, inhibit the growth of other crystal directions, greatly reduce the dislocation density generated during the growth of the buffer layer 3, and improve the crystal quality of the buffer layer 3, thereby making the crystal quality of the first semiconductor layer 4 grown on this buffer layer 3 better, and optimizing the light-emitting effect of the light-emitting chip. Moreover, the second guide portion 202 is arranged on the side wall 102 of the protrusion 103, which can solve the problem that the side wall 102 of the protrusion 103 is prone to generate voids when the side wall 102 of the protrusion 103 is nucleated and grown along the c-plane. The setting of the second guide portion 202 can release the residual stress of the lattice mismatch between the sapphire and the buffer layer 3 in the side wall 102 of the protrusion 103, reduce the number of voids generated during crystallization, further improve the crystal quality, and make the light-emitting effect of the light-emitting chip better.

[0081] Another optional embodiment of the present application:

[0082] This embodiment provides a light emitting chip, such as Fig.13 As shown, the light-emitting chip is manufactured by the manufacturing method of the light-emitting chip as described above, and the light-emitting chip includes a first electrode 7 and a second electrode 8. The first electrode 7 is electrically connected to the first semiconductor layer 4 of the epitaxial wafer, and the second electrode 8 is electrically connected to the second semiconductor layer 6 of the epitaxial wafer.

[0083] The above-mentioned light-emitting chip is made of the above-mentioned epitaxial wafer, and the epitaxial wafer is provided with a nucleation guide layer 2 on a substrate 1, and the first guide portion 201 of the nucleation guide layer 2 is provided in a plane region 101, and the plane region 101 corresponds to the c-plane in the sapphire crystal structure. Therefore, the first guide portion 201 can guide the buffer layer 3 to nucleate and grow toward the c-plane in the sapphire crystal structure, inhibit the growth of other crystal directions, greatly reduce the dislocation density generated during the growth of the buffer layer 3, and improve the crystal quality of the buffer layer 3, thereby making the crystal quality of the first semiconductor layer 4 grown on this buffer layer 3 better, and optimizing the light-emitting effect of the light-emitting chip. Moreover, the second guide portion 202 is arranged on the side wall 102 of the protrusion 103, which can solve the problem that the side wall 102 of the protrusion 103 is prone to generate voids when the side wall 102 of the protrusion 103 nucleates and grows along the c-plane. The setting of the second guide portion 202 can release the residual stress of the lattice mismatch between the sapphire on the side wall 102 of the protrusion 103 and the buffer layer 3, thereby reducing the number of voids generated during crystallization, further improving the crystallization quality, and making the light-emitting effect of the light-emitting chip better.

[0084] It should be understood that the application of the present application is not limited to the above examples. For ordinary technicians in this field, improvements or changes can be made based on the above description. All these improvements and changes should fall within the scope of protection of the claims attached to this application.

Claims

1. An epitaxial wafer, characterized in that: include: A substrate, wherein one side of the substrate has a plurality of protrusions, and a surface of the substrate between the protrusions is a plane area; a nucleation guide layer disposed on the substrate, the nucleation guide layer comprising a first guide portion completely covering the planar area, and a second guide portion covering a portion of the sidewall of the protrusion, the first guide portion being connected to the second guide portion; a buffer layer growing around the nucleation guide layer; as well as A first semiconductor layer, an active layer, and a second semiconductor layer are sequentially grown on the buffer layer.

2. The epitaxial wafer according to claim 1, characterized in that: A distance between an end of the second guide portion away from the planar region and the planar region is less than or equal to 0.5 μm.

3. The epitaxial wafer according to claim 1, characterized in that: The material of the nucleation guide layer includes AlN.

4. The epitaxial wafer according to any one of claims 1 to 3, characterized in that: The thickness of the nucleation guide layer is 16nm-30nm.

5. A method for manufacturing an epitaxial wafer according to any one of claims 1 to 4, characterized in that: include: Disposing the nucleation guide layer on the substrate so that the first guide portion of the nucleation guide layer completely covers the planar area, and the second guide portion of the nucleation guide layer covers a portion of the side wall of the protrusion; growing a buffer layer with the nucleation guide layer as the center; A first semiconductor layer, an active layer and a second semiconductor layer are sequentially grown on the buffer layer.

6. The method for manufacturing an epitaxial wafer according to claim 5, characterized in that: The step of providing the nucleation guide layer on the substrate comprises: Disposing a nucleation film layer on the substrate, wherein the nucleation film layer completely covers a side of the substrate having the plurality of protrusions; Disposing a photoresist layer on the nucleation film layer; Disposing a mask on the photoresist layer; Exposing and developing to remove the photoresist not blocked by the mask; The portion of the nucleation film layer not blocked by the photoresist is removed by etching, and the remaining portion of the nucleation film layer after being etched away forms the nucleation guide layer including the first guide portion and the second guide portion.

7. The method for manufacturing an epitaxial wafer according to claim 6, characterized in that: Before providing a photoresist layer on the nucleation film layer, the method further includes: Disposing a protective layer on the nucleation film layer; After the exposure and development to remove the photoresist not blocked by the mask, the method further comprises: Etching and removing the portions of the protective layer and the nucleation film layer that are not blocked by the photoresist; The protection layer on the nucleation guide layer is removed.

8. The method for manufacturing an epitaxial wafer according to claim 7, characterized in that: The protective layer includes SiO2.

9. A method for manufacturing a light-emitting chip, characterized in that: include: Providing an epitaxial wafer as claimed in any one of claims 1 to 4; Fabricating a first electrode and a second electrode on the epitaxial wafer; The epitaxial wafer is cut into a plurality of independent light-emitting chips.

10. A light-emitting chip, characterized in that: The light-emitting chip is manufactured using the light-emitting chip manufacturing method as described in claim 9, and the light-emitting chip includes the first electrode and the second electrode, the first electrode is electrically connected to the first semiconductor layer of the epitaxial wafer, and the second electrode is electrically connected to the second semiconductor layer of the epitaxial wafer.

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