Coplanar common-cathode Micro-LED display chip and preparation method and application thereof

Abstract

The invention discloses a coplanar common-cathode Micro-LED display chip and a preparation method and application thereof, and the Micro-LED display chip comprises a substrate and an n-GaN layer on the substrate, and also comprises a plurality of chip structures connected through the n-GaN layer, a DBR layer, an n electrode and a p electrode. The chip structure comprises a multi-quantum well active layer, a p-GaN layer and a transparent conductive layer from bottom to top. The n electrode comprises a first connecting end in contact with the n-GaN layer and a first epitaxial end; the p electrode comprises a second connecting end in contact with the transparent conductive layer and a second epitaxial end; the first extension end is flush with the second extension end; the space among the n-GaN layer, the chip structure, the n electrode and the p electrode is filled with the DBR layer to form a plane structure. According to the invention, a coplanar and common-cathode display chip structure is adopted, so that the integration difficulty of the Micro-LED display chip can be reduced, and the compatibility of the Micro-LED display chip with 3D packaging of a future integrated circuit is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor light-emitting devices, and in particular to a co-planar common cathode Micro-LED display chip and a preparation method thereof. Background Art

[0002] Micro-LED display chips have the characteristics of high resolution, high contrast, high efficiency and energy saving, which makes them have important application prospects in wearable devices, biomedical applications, virtual reality (VR) and augmented reality (AR) and are expected to become the next generation of display technology.

[0003] The most common technology in the integration of full-color Micro-LED display screens is mass transfer technology, which realizes the transfer of Micro-LED display chips from wafers to substrates, but this technology faces many challenges in terms of manufacturing costs and yield. The use of a common cathode / anode flip-chip structure can effectively alleviate the problems existing in the mass transfer process. In the conventional common cathode / anode flip-chip structure, there is a height difference between the n-electrode pad and the p-electrode pad, which requires the chip to be bonded using a tin-based soft soldering process during the packaging process, but the pressure applied when melting the tin may cause solder extrusion, thereby causing short circuits between adjacent Micro-LED display chips. In order to solve this problem, coplanar electrode technology came into being. This technology makes the electrode layout more compact by designing the n-type and p-type electrodes on the same plane, which is conducive to improving the integration and performance of the device. In addition, the coplanar electrode structure can also simplify the manufacturing process, reduce production costs, and improve the connection reliability of the electrodes and the overall performance of the device. In order to meet the application requirements of high-performance chips, the future advanced packaging interconnection technology will continue to develop in the direction of high density and high reliability. Copper-to-copper low-temperature bonding technology is the core technology of advanced packaging. Compared with the mainstream tin-based soft soldering process, its interconnection pitch is narrower, the electrical and thermal conductivity is stronger, and the reliability is better. At the same time, the inherent self-heating effect of light-emitting diodes is also an important factor affecting the luminous efficiency and service life of Micro-LED display chips.

[0004] Therefore, a new type of co-planar common cathode / anode Micro-LED display chip is needed to solve the above problems. Summary of the invention

[0005] The purpose of the present invention is to provide a co-planar and co-cathode Micro-LED display chip, improve the heat dissipation capacity, luminous efficiency and light extraction efficiency of the Micro-LED display chip, and reduce the difficulty of integrating the Micro-LED display chip.

[0006] In order to achieve the above-mentioned object, the present invention provides a coplanar common cathode Micro-LED display chip, comprising a substrate and an n-GaN layer on the substrate, and also comprising a plurality of chip structures connected by the n-GaN layer, and a DBR layer, an n-electrode and a p-electrode; The chip structure includes a multi-quantum well active layer, a p-GaN layer, and a transparent conductive layer from bottom to top; The n-electrode includes a first connection end and a first epitaxial end in contact with the n-GaN layer; The p-electrode includes a second connection end and a second epitaxial end in contact with the transparent conductive layer; The first epitaxial end and the second epitaxial end are flush; The space between the n-GaN layer, the chip structure, the n-electrode and the p-electrode is filled by the DBR layer to form a planar structure.

[0007] Furthermore, the transparent conductive layer includes an Al-doped ITO layer and an anti-etching layer from bottom to top.

[0008] Further, the n-GaN layer includes a base layer and a protrusion on the base layer; The chip structure is arranged on the protrusion; The cross-sections of the protrusion and the chip structure are trapezoidal.

[0009] Furthermore, the bottom angle between the protrusion and the trapezoidal cross section of the chip structure is 40°-60°.

[0010] Furthermore, the material of the first epitaxial end of the n-electrode and the second epitaxial end of the p-electrode is Cu.

[0011] The present invention also provides a method for preparing a co-planar common cathode Micro-LED display chip, comprising: An n-GaN material, a multi-quantum well active material, and a p-GaN material are sequentially grown on a substrate, a transparent conductive layer is grown after patterning the p-GaN material, and then the p-GaN material, the multi-quantum well active material, and the n-GaN material are etched to obtain a substrate, an n-GaN layer on the substrate, and a plurality of chip structures connected with the n-GaN layers, namely, an intermediate product, wherein the chip structure includes a multi-quantum well active layer, a p-GaN layer, and a transparent conductive layer from bottom to top; Growing a DBR material on the surface of the intermediate product away from the substrate, patterning the DBR material, and then etching the DBR material to obtain an n-electrode hole and a p-electrode hole, wherein one end of the n-electrode hole directly reaches the n-GaN layer and the other end is connected to the external environment, and one end of the p-electrode hole directly reaches the transparent conductive layer and the other end is connected to the external environment; Electrode materials are grown in the n-electrode hole and the p-electrode hole, and then excess electrode materials and DBR materials are removed to form n-electrodes and p-electrodes, wherein the n-electrode includes a first connection end in contact with the n-GaN layer and a first epitaxial end; the p-electrode includes a second connection end in contact with the transparent conductive layer and a second epitaxial end; the first epitaxial end and the second epitaxial end are flush.

[0012] Furthermore, the step of growing a transparent conductive layer after patterning the p-GaN material comprises: ITO material, Al film and anti-etching material are sequentially grown on the patterned p-GaN layer, and then annealed to obtain a transparent conductive layer, namely an Al-doped ITO layer and an anti-etching layer. Preferably, the annealing adopts a rapid thermal annealing process, annealing in a protective gas atmosphere at 500-800°C for 1-5 minutes.

[0013] Furthermore, the Al film has a thickness of 0.5-1.5 nm.

[0014] Furthermore, before etching the patterned DBR material to obtain the n-electrode holes and the p-electrode holes, an anti-etching material is deposited on the surface of the patterned DBR material.

[0015] It should be noted that the growth and etching used in the present invention are commonly used methods in the art and do not need to be strictly limited. For example, the growth can be carried out by magnetron sputtering, thermal evaporation process, electron beam evaporation, etc.; the etching can be carried out by neutral beam etching, inductively coupled plasma etching, mechanical polishing, etc. There is no need to strictly limit the anti-etching material. The specific selection needs to be combined with the etching process used subsequently. For example, the material of the anti-etching layer in the transparent conductive layer can be selected as Ni; the material of the anti-etching layer of the DBR material can be selected as Al.

[0016] The present invention also provides application of the above-mentioned co-planar common cathode Micro-LED display chip in a light-emitting device.

[0017] Compared with the prior art, the present invention has the following beneficial effects: The present invention adopts a coplanar and co-cathode chip structure, which can reduce the integration difficulty of the Micro-LED display chip and increase its compatibility with future integrated circuit 3D packaging. The present invention uses Al-doped ITO material as a transparent conductive layer, which can effectively improve the light transmittance of the Micro-LED display chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0019] Figure 1 A schematic diagram of the structure of the initial product is shown; Figure 2 A schematic diagram of the structure of the intermediate product is shown; Figure 3 A schematic diagram showing the structure of growing a DBR material on the surface of an intermediate product; Figure 4 Shows Figure 3 Schematic diagram of a structure with deposited anti-etching material; Figure 5 A schematic diagram of the structure after electrode materials are deposited in the n-electrode hole and the p-electrode hole is shown; Figure 6 A schematic diagram of the structure of a coplanar common cathode Micro-LED display chip is shown; Figure 7 The surface morphology of the Al-doped ITO layer before annealing in the preparation process of the co-planar common cathode Micro-LED display chip of Example 1 is shown; Figure 8 The surface morphology of the Al-doped ITO layer after annealing in the preparation process of the co-planar common cathode Micro-LED display chip of Example 1 is shown; Fig. 9 The surface morphology of the Al-doped ITO layer after annealing in the preparation process of the co-planar and co-cathode Micro-LED display chip of Comparative Example 2 is shown; Fig.10 The surface morphology of the Al-doped ITO layer after annealing in the preparation process of the co-planar common cathode Micro-LED display chip of Comparative Example 3 is shown; Fig.11 The transmittance curves of the Al-doped ITO layers of Example 1, Comparative Example 2 and Comparative Example 3, and the ITO layer of Comparative Example 1 are shown; Description of reference numerals: 1. Substrate; 2. n-GaN material; 3. Multi-quantum well active material; 4. p-GaN material; 5. Transparent conductive layer; 501. Al-doped ITO layer; 502. Anti-etching layer; 6. n-GaN layer; 601. Base layer; 602. Protrusion; 7. Multi-quantum well active layer; 8. p-GaN layer; 9. DBR material; 10. Anti-etching material; 11. Electrode material; 12. n-electrode; 13. p-electrode; 14. DBR layer. DETAILED DESCRIPTION

[0020] In the description of the present invention, it should be understood that the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of this application, "plurality" means two or more, unless otherwise clearly and specifically defined.

[0021] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, an electrical connection, or mutual communication; it can be a direct connection, or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0022] The following will be combined with the specific embodiments of the present invention and the drawings of the specification to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0023] Example 1 A method for preparing a coplanar common cathode Micro-LED display chip, the steps are as follows: Step 1, growing n-GaN material 2, multi-quantum well active material 3, and p-GaN material 4 on substrate 1 in sequence; Step 2, patterning the p-GaN material 4 to prepare a nanoscale pattern; Step 3: Deposit ITO material on the patterned p-GaN material 4 by a sputtering system, and sequentially evaporate Al film and Ni film with a thickness of 1 nm on the ITO material by an electron beam evaporation process, such as Figure 1 In the initial product shown, the Ni film serves as an anti-etching layer 502 for subsequent etching operations; Step 4: selectively etch GaN by using a neutral beam etching method, etching from the p-GaN material 4 to the n-GaN material 2, to form an n-GaN layer 6 with a base layer 601 and a plurality of protrusions 602 on the base layer 601, and a chip structure on each protrusion 602, wherein the chip structure comprises a multi-quantum well active layer 7, a p-GaN layer 8, and a transparent conductive layer 5 arranged in sequence, and the cross-section of the protrusion 602 and the chip structure is a trapezoid with a bottom angle of 40°-60°; Step 5: Rapid thermal annealing is performed in a N2 atmosphere at 600°C for 2 minutes to dope Al into the ITO to form an Al-doped ITO layer 501, and to establish an ohmic contact between the transparent conductive layer 5 and the p-GaN layer 8, thereby obtaining a Figure 2 In the intermediate product shown, the doping of metal Al can improve the light transmittance of the transparent conductive layer 5 and enhance the ohmic contact performance between the transparent conductive layer 5 and the p-GaN layer 8; Step 6: Figure 3 As shown, a DBR material 9 is grown on the surface of the intermediate product away from the substrate, and the DBR material 9 is patterned, as shown in FIG. Figure 4 The anti-etching material 10 is shown to be deposited by electron beam; Step 7: selectively etch the DBR material 9 using an inductively coupled plasma etching technique to obtain an n-electrode hole and a p-electrode hole, wherein one end of the n-electrode hole directly reaches the n-GaN layer 6 and the other end is connected to the external environment, and one end of the p-electrode hole directly reaches the transparent conductive layer 5 and the other end is connected to the external environment; Step 8: Figure 5 As shown, electrode material 11 is grown in the n-electrode hole and the p-electrode hole; Step 9: Remove excess Cu by chemical mechanical polishing to form an n-electrode and a p-electrode, wherein the n-electrode 12 includes a first connection end in contact with the n-GaN layer and a first epitaxial end; the p-electrode 13 includes a second connection end in contact with the transparent conductive layer and a second epitaxial end; the first epitaxial end and the second epitaxial end are at the same level, and the space between the n-GaN layer 6, the chip structure, the n-electrode 12 and the p-electrode 13 is filled with a DBR layer 14 to form a planar structure, that is, a coplanar common cathode Micro-LED display chip is obtained, such as Figure 6 shown.

[0024] In this embodiment, the substrate is sapphire; and the anti-etching material deposited on the surface of the patterned DBR material is Al.

[0025] In this embodiment, the electrode material is grown in the n-electrode hole and the p-electrode hole specifically by first depositing a Ti / Cu seed layer in the n-electrode hole and the p-electrode hole, and then electroplating Cu. Therefore, the first epitaxial end of the n-electrode 12 and the second epitaxial end of the p-electrode 13 are both made of Cu. The preparation of the n-electrode and the p-electrode first deposits a Ti / Cu seed layer and then electroplates Cu. The Ti / Cu seed layer can ensure the uniform distribution of current during the electroplating process, thereby forming a high-quality Cu electrode in the electrode hole. In addition, the Ti / Cu seed layer can also improve the adhesion between the substrate and the Cu electrode, and improve the adhesion and uniformity of the Cu electrode. The thickness of the Ti / Cu seed layer is about 100-300nm. The material of the first epitaxial end and the second epitaxial end is Cu. Cu has the characteristics of low resistance, low inductance, low thermal resistance, good heat dissipation performance and anti-electromigration performance, and small bump contact spacing. It can reduce the chip forward voltage, improve the chip heat dissipation efficiency, reduce the chip self-heating effect, and improve the luminous efficiency of the Micro-LED display chip and extend its service life. At the same time, the chip can be connected to the substrate using copper-to-copper low-temperature bonding technology.

[0026] Comparative Example 1 Compared with Example 1, the difference is that in step 3, the Al film and the Ni film with a thickness of 1 nm are not evaporated.

[0027] Comparative Example 2 Compared with Example 1, the difference is that in step 3, an Al film with a thickness of 3 nm is evaporated.

[0028] Comparative Example 3 Compared with Example 1, the difference is that in step 3, an Al film with a thickness of 6 nm is evaporated.

[0029] Test Case The surface morphology of the Al-doped ITO layer before and after annealing in the preparation process of the coplanar common cathode Micro-LED display chip of Example 1 was observed by scanning electron microscopy. The results are as follows: Figure 7 and Figure 8 shown. The surface morphologies of the Al-doped ITO layer before and after annealing in the preparation process of the coplanar and co-cathode Micro-LED display chips of Comparative Examples 2 and 3 are respectively as follows: Fig. 9 and Fig.10 As shown, it can be seen that the Al-doped ITO layer formed in Comparative Example 2 with a 3 nm thick Al film evaporated has a small amount of particles on the surface and cracks and holes on the surface; the Al-doped ITO layer formed in Comparative Example 2 with a 6 nm thick Al film evaporated has more particles on the surface and cracks and holes on the surface, which indicates that it is difficult to obtain a uniform structure when an Al film that is too thick is grown on the surface of the ITO material.

[0030] The light transmission properties of the Al-doped ITO layer of Example 1 and the ITO layer of Comparative Example 1 were also tested. Fig.11 As shown. The results show that the Al-doped ITO layer formed by evaporating a 1 nm thick Al film in Example 1 has a higher transmittance than Comparative Example 1 without evaporating an Al film, and Comparative Examples 2 and 3 with over-thick Al films. The incorporation of Al changes the original band structure of ITO. The band structure of ITO determines its absorption and transmission of light of a specific wavelength. As an doping element, Al has different atomic radius and electronic structure from the main elements of ITO. After entering the lattice, it adjusts the band gap. Appropriate Al doping increases the band gap, which reduces the absorption of photons when electrons transition from the valence band to the conduction band in the visible light range, because only photons with energy greater than the band gap can be absorbed for electronic transitions. The degree of visible light absorption is reduced, and more visible light is transmitted, thereby improving the transmittance of the Micro-LED chip in the visible light region and optimizing its optical performance. At the same time, doping Al in the ITO material can improve the transparent conductivity of the Micro-LED display chip, mainly because Al doping can significantly increase the carrier concentration and improve the electron mobility. As a donor dopant, Al introduces additional electrons into the ITO lattice, thereby increasing the carrier concentration. In addition, Al doping can also optimize the crystal structure of ITO, making the migration path of electrons in the lattice smoother, further improving the mobility of electrons. These effects work together to make the ITO film have lower resistivity and better conductivity while maintaining high transmittance.

[0031] Finally, it should be noted that the above is only a preferred embodiment of the present invention and is not intended to limit the present invention. Although the present invention has been described in detail with reference to the aforementioned embodiments, it is still possible for those skilled in the art to modify the technical solutions described in the aforementioned embodiments or to make equivalent substitutions for some of the technical features therein. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A coplanar common cathode Micro-LED display chip, comprising a substrate and an n-GaN layer on the substrate, characterized in that: It also includes several chip structures connected by n-GaN layers, as well as DBR layers, n-electrodes and p-electrodes; The chip structure includes, from bottom to top, a multi-quantum well active layer, a p-GaN layer, and a transparent conductive layer; The n-electrode includes a first connection end and a first epitaxial end in contact with the n-GaN layer; The p-electrode includes a second connection end and a second epitaxial end in contact with the transparent conductive layer; The first epitaxial end and the second epitaxial end are flush; The space between the n-GaN layer, the chip structure, the n-electrode and the p-electrode is filled by the DBR layer to form a planar structure.

2. The co-planar common cathode Micro-LED display chip according to claim 1, characterized in that: The transparent conductive layer comprises, from bottom to top, an Al-doped ITO layer and an anti-etching layer.

3. The co-planar common cathode Micro-LED display chip according to claim 1, characterized in that: The n-GaN layer includes a base layer and a protrusion on the base layer; The chip structure is arranged on the protrusion; The cross-sections of the protrusion and the chip structure are trapezoidal.

4. The co-planar common cathode Micro-LED display chip according to claim 3, characterized in that: The protrusion and the lower base angle of the trapezoidal cross section of the chip structure are 40°-60°.

5. The co-planar common cathode Micro-LED display chip according to claim 1, characterized in that: The material of the first epitaxial end of the n-electrode and the second epitaxial end of the p-electrode is Cu.

6. A method for preparing a coplanar common cathode Micro-LED display chip, characterized in that: include, An n-GaN material, a multi-quantum well active material, and a p-GaN material are sequentially grown on a substrate, a transparent conductive layer is grown after patterning the p-GaN material, and then the p-GaN material, the multi-quantum well active material, and the n-GaN material are etched to obtain a substrate, an n-GaN layer on the substrate, and a plurality of chip structures connected with the n-GaN layers, namely, an intermediate product, wherein the chip structure includes a multi-quantum well active layer, a p-GaN layer, and a transparent conductive layer from bottom to top; Growing a DBR material on the surface of the intermediate product away from the substrate, patterning the DBR material, and then etching the patterned DBR material to obtain an n-electrode hole and a p-electrode hole, wherein one end of the n-electrode hole directly reaches the n-GaN layer and the other end is connected to the external environment, and one end of the p-electrode hole directly reaches the transparent conductive layer and the other end is connected to the external environment; Electrode materials are grown in the n-electrode hole and the p-electrode hole, and then excess electrode materials and DBR materials are removed to form n-electrodes and p-electrodes, wherein the n-electrode includes a first connection end in contact with the n-GaN layer and a first epitaxial end; the p-electrode includes a second connection end in contact with the transparent conductive layer and a second epitaxial end; the first epitaxial end and the second epitaxial end are flush.

7. The method for preparing a coplanar common cathode Micro-LED display chip according to claim 6, characterized in that: The step of growing a transparent conductive layer after patterning the p-GaN material comprises: An ITO material, an Al film and an anti-etching material are sequentially grown on the patterned p-GaN layer, and then annealed to obtain a transparent conductive layer, namely an Al-doped ITO layer and an anti-etching layer.

8. The method for preparing a coplanar common cathode Micro-LED display chip according to claim 6, characterized in that: The Al film has a thickness of 0.5-1.5 nm.

9. The method for preparing a co-planar common cathode Micro-LED display chip according to claim 6, characterized in that: Before etching the patterned DBR material to obtain the n-electrode holes and the p-electrode holes, an anti-etching material is deposited on the surface of the patterned DBR material.

10. Application of the co-planar common cathode Micro-LED display chip as claimed in any one of claims 1 to 5 in a light-emitting device.

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