Miniature light emitting diode chip based on hybrid bonding and manufacturing method thereof

Abstract

The present invention relates to a hybrid bonding-based micro light emitting diode chip, comprising: an upper stack comprising: a first insulating layer configured to accommodate a light emitting mesa and a first through hole contact portion; a light emitting mesa configured to emit light wherein a top surface area of the light emitting mesa is greater than a bottom surface area of the light emitting mesa; the first through hole contact part is electrically connected with the bottom of the light-emitting mesa and penetrates through the first insulating layer; and a lower stack including: a second insulating layer configured to accommodate the second via contact portion; a second via contact portion passing through the second insulating layer; and a driving backplane electrically connected to the second via contact portion, in which the lower stack is bonded to the upper stack by hybrid bonding such that the first via contact portion is bonded to the second via contact portion, and the first insulating layer is bonded to the second insulating layer. The invention also relates to a method for producing such a micro-light-emitting diode chip. According to the invention, the inverted trapezoidal structure of the light-emitting table top can be realized, and meanwhile, the through hole contact part, such as an I C copper column, can be manufactured at the bottom of the light-emitting table top.

Description

Technical Field

[0001] The present invention generally relates to the field of semiconductors, and more specifically to a micro light emitting diode chip based on hybrid bonding. In addition, the present invention also relates to a method for manufacturing such a micro light emitting diode chip. Background Art

[0002] Micro Light Emitting Diode (MLED) is a new type of LED structure obtained by thin-filming, miniaturization and arraying the original LED structure. It integrates arrayed micron-level LED units on an active addressing drive panel to realize the lighting and individual control of the LED units, thereby outputting the desired display image. The core structure of the MLED is a PN junction diode, which is composed of direct bandgap semiconductor materials. When the upper and lower electrodes apply a forward bias to the MLED to allow current to pass through, electrons and holes recombine in the active region (Active region) and emit single color light photons at the same time.

[0003] The light-emitting mesa is a micro-light-emitting diode, which is composed of semiconductor materials of different conductivity types. For example, the common P-type semiconductor layer and N-type semiconductor layer, between these two layers is the light-emitting layer. Taking gallium nitride (GaN)-based micro-light-emitting diode as an example, the N-type semiconductor layer generally uses N-type doped GaN, the P-type semiconductor layer is P-type doped GaN, and the light-emitting layer is mostly InGaN quantum well structure. When current passes through, electrons and holes recombine in the light-emitting layer, thereby generating photons to emit light.

[0004] At present, there are generally two types of structures for light-emitting mesas, that is, the light-emitting mesas are either exposed outside the insulating layer or contained in the insulating layer. When the light-emitting mesas are contained in the insulating layer, better protection and insulation can be provided for the light-emitting mesas. However, the process difficulty of this embedded structure is that, due to the limitations of existing processes, it is difficult to realize the inverted trapezoidal structure of the light-emitting mesas while also making IC copper pillars at the bottom of the light-emitting mesas. Summary of the invention

[0005] Based on the prior art, the task of the present invention is to provide a micro light-emitting diode chip based on hybrid bonding and a manufacturing method thereof. Through the micro light-emitting diode chip and the method, it is possible to realize an inverted trapezoidal structure of the light-emitting table while also making a through-hole contact portion, such as an IC copper column, at the bottom of the light-emitting table.

[0006] In a first aspect of the present invention, the aforementioned object is achieved by a micro light emitting diode chip based on hybrid bonding, the chip comprising:

[0007] The upper stack comprises:

[0008] a first insulating layer configured to accommodate the light emitting mesa and the first via contact;

[0009] a light emitting mesa configured to emit light, wherein a top surface area of ​​the light emitting mesa is greater than a bottom surface area of ​​the light emitting mesa; and

[0010] a first through-hole contact portion electrically connected to the bottom of the light-emitting mesa and passing through the first insulating layer; and

[0011] The lower stack comprises:

[0012] a second insulating layer configured to accommodate a second through-hole contact;

[0013] a second through-hole contact passing through the second insulating layer; and

[0014] a driving backplane electrically connected to the second through-hole contact, wherein the lower stack is bonded to the upper stack by hybrid bonding such that the first through-hole contact is bonded to the second through-hole contact,

[0015] And the first insulating layer is bonded to the second insulating layer.

[0016] In one embodiment of the present invention, it is provided that:

[0017] The upper stack also includes a first bonding mark, which is disposed in the first insulating layer and exposes a first mark surface;

[0018] The lower stack further includes a second bonding mark disposed in the second insulating layer and exposing a second mark surface; and

[0019] During hybrid bonding, the first marking surface is aligned with the second marking surface to align the upper stack and the lower stack.

[0020] In another embodiment of the present invention, the light-emitting table comprises:

[0021] a first epitaxial layer extending beyond the recess of the first insulating layer and in electrical contact with the light emitting layer;

[0022] a light emitting layer in the recess and between the first epitaxial layer and the second epitaxial layer; and

[0023] A second epitaxial layer is in the recess and is in electrical contact with the light emitting layer and the first through hole contact. In another embodiment of the present invention, the upper stack further includes:

[0024] a transparent conductive layer on the first epitaxial layer and electrically connecting the cathode to the first epitaxial layer;

[0025] a passivation layer surrounding the side surfaces of the light-emitting mesa and extending to the upper surface of the first insulating layer;

[0026] a cathode, surrounding the light-emitting mesa; and

[0027] The anode is electrically connected to the driving back plate through a third through-hole contact portion that passes through the first insulating layer and the second insulating layer.

[0028] In another embodiment of the present invention, the cathode is a reflective electrode, which is made of metal.

[0029] In another embodiment of the present invention, it is provided that:

[0030] The side of the edge cathode facing the light-emitting mesa is an inclined surface; and

[0031] Both sides of the middle cathode facing the light-emitting table are inclined surfaces.

[0032] In another embodiment of the present invention, the first epitaxial layer partially passes through the edge cathode and completely passes through the middle cathode, wherein an edge of the first epitaxial layer in the edge cathode is an inclined surface.

[0033] In another embodiment of the present invention, the upper stack further comprises:

[0034] The reflector layer is between the inner wall of the recess and the passivation layer, wherein the reflector layer has an inclined surface on a side facing the light-emitting mesa to reflect light from the light-emitting mesa upward.

[0035] In another embodiment of the present invention, the upper stack further comprises a microlens, which comprises:

[0036] a lens portion, which is located at the outermost side and is configured to shape the light from the light-emitting mesa; and

[0037] The spacer is disposed between the lens portion and the light emitting mesa to adjust the focal position of the lens portion.

[0038] In another embodiment of the present invention, the first through hole contact portion has a first opening at the surface of the first insulating layer, wherein the first opening has an interface metal layer, and the area of ​​the interface metal layer is larger than the area of ​​the first opening; and / or

[0039] The second through hole contact portion has a second opening at the surface of the second insulating layer, wherein an interface metal layer is provided at the second opening, and an area of ​​the interface metal layer is larger than an area of ​​the first opening.

[0040] In another embodiment of the present invention, a passivation layer is provided between the reflector layer and the inner wall of the recess.

[0041] In another embodiment of the present invention, the first epitaxial layers of adjacent light emitting mesas are continuous with each other through the middle cathode.

[0042] In another embodiment of the present invention, the first and second through-hole contacts are IC copper pillars, and a metal layer is disposed on the surface of the driving backplane, the IC copper pillars are electrically connected to the metal layer, and each light-emitting mesa corresponds to an IC copper pillar.

[0043] In another embodiment of the present invention, the material of the passivation layer is SiO2 film or Al2O3 film or SiO2 / Al2O3 composite structure film.

[0044] In another embodiment of the present invention, it is provided that:

[0045] The thickness of the first insulating layer is 0.6 to 1.4 μm; and / or

[0046] The thickness of the second insulating layer is 0.6 to 1.4 μm.

[0047] In another embodiment of the present invention, it is provided that:

[0048] The diameter of the first through-hole contact is 0.6 to 1.4 μm; and / or

[0049] The diameter of the second via contact is 0.8 to 1.6 μm.

[0050] In another embodiment of the present invention, it is provided that:

[0051] The thickness of the passivation layer between the reflector layer and the light-emitting mesa is 1000 to 1600 angstroms; and / or

[0052] The thickness of the passivation layer between the reflector layer and the inner wall of the recess is 300 to 600 angstroms; and / or

[0053] The material of the reflector layer includes silver, and its thickness is 3000 to 3500 angstroms.

[0054] In another embodiment of the present invention, it is provided that:

[0055] The top width of the light-emitting mesa is 1.0 to 2.0 μm; and / or

[0056] The first epitaxial layer has a thickness of 4000 to 5000 angstroms; and / or

[0057] The thickness of the light emitting layer is 3500 to 4000 angstroms; and / or

[0058] The thickness of the second epitaxial layer is 2500 to 3500 angstroms.

[0059] In another embodiment of the present invention, it is provided that:

[0060] The width of the microlens is 1 to 3 μm; and / or

[0061] The distance between the lens portion and the cathode is 0.1 to 0.3 μm.

[0062] In a second aspect of the present invention, the aforementioned object is achieved by a method for manufacturing a micro-light emitting diode chip, the method comprising the following steps:

[0063] Forming a portion of an upper stack on a temporary substrate, comprising:

[0064] Depositing a light-emitting layer and a second epitaxial layer of the light-emitting mesa on a temporary substrate;

[0065] depositing a passivation layer on the light-emitting mesa;

[0066] depositing a first insulating layer on the light emitting mesa;

[0067] Etching a first through-hole contact portion on the first insulating layer, wherein the bottom of the first through-hole contact portion exposes the bottom of the light-emitting mesa;

[0068] depositing metal in the first via contact; and

[0069] debonding the upper stack from the temporary substrate;

[0070] A lower stack is formed, comprising:

[0071] forming a driving backplane;

[0072] Depositing a second insulating layer on the driver backplane;

[0073] Etching a second through-hole contact portion on the second insulating layer, wherein the bottom of the second through-hole contact portion exposes an electrical contact portion of the driving backplane; and

[0074] depositing metal in the second via contact; and

[0075] The upper stack layer is hybrid-bonded to the lower stack layer, so that the first through-hole contact is bonded to the second through-hole contact, and the first insulating layer is bonded to the second insulating layer.

[0076] In one embodiment of the present invention, the method further comprises the following steps:

[0077] depositing a passivation layer on the top surface of the light emitting mesa and the first insulating layer;

[0078] etching the passivation layer to expose the light-emitting layer of the light-emitting mesa;

[0079] depositing a first epitaxial layer on the light emitting layer;

[0080] depositing a transparent conductive layer on the first epitaxial layer;

[0081] depositing a cathode on the transparent conductive layer;

[0082] depositing microlenses on the cathode and the transparent conductive layer;

[0083] Etching the first and second insulating layers at the side of the light-emitting mesa to form a third through-hole contact portion, the bottom of the third through-hole contact portion exposes the electrical contact portion of the driving backplane; and

[0084] A metal is deposited in the third via contact to form an anode.

[0085] The present invention has at least the following beneficial effects:

[0086] (1) The present invention solves the technical difficulty encountered when manufacturing an inverted trapezoidal light-emitting table with a large upper surface and a small lower surface, namely, the problem of electrical connection between the light-emitting table and the driving backplane, by separately manufacturing an upper stack and a lower stack and then bonding the two to each other through hybrid bonding. The present invention realizes the electrical connection between the light-emitting table and the driving backplane through hybrid bonding, so that both the upper stack and the lower stack can be manufactured from the surface opposite to the hybrid bonding surface toward the hybrid bonding surface, thereby realizing a high-quality conductive structure, such as a through-hole contact portion (such as an IC copper column), and the length of the conductive structure can also be flexibly selected.

[0087] (2) The present invention makes the first epitaxial layer on the upper surface of the light-emitting table protrude out of the recess of the insulating layer, so that the surface area of ​​the first epitaxial layer is not limited by the recess opening, thereby significantly increasing the area and thickness of the first epitaxial layer; in addition, since the recess only needs to accommodate the light-emitting layer and the second epitaxial layer, these two layers have a larger area and thickness compared with the structure of the prior art that needs to accommodate three layers, thereby better increasing the area and thickness of the epitaxial layer and improving the light emission.

[0088] (3) The present invention also increases the metal bonding surface by coating metal at the through-hole contact portion of the hybrid bonding surface, thereby improving the bonding strength and improving the conductivity; in addition, the present invention also promotes the alignment of the upper and lower stacks by respectively setting bonding marks in the upper and lower stacks, thereby improving the bonding accuracy. BRIEF DESCRIPTION OF THE DRAWINGS

[0089] The present invention will be further described below in conjunction with specific embodiments with reference to the accompanying drawings.

[0090] Figure 1 A schematic diagram of a micro light emitting diode chip based on hybrid bonding according to the present invention is shown;

[0091] Figure 2 showing the interface metal layers of the first and second via contacts;

[0092] Figure 3 A top view and a cross-sectional view along a cross-sectional line B of a micro light emitting diode chip based on hybrid bonding according to the present invention are shown; and

[0093] FIG. 4 shows a process of forming a micro light emitting diode chip based on hybrid bonding according to the present invention. DETAILED DESCRIPTION

[0094] In the following description, the present invention is described with reference to various embodiments. However, those skilled in the art will recognize that the various embodiments may be implemented without one or more specific details or with other alternative and / or additional methods, materials or components. In other cases, well-known structures, materials or operations are not shown or described in detail to avoid obscuring the inventive point of the present invention. Similarly, for the purpose of explanation, specific quantities, materials and configurations are set forth to provide a comprehensive understanding of the embodiments of the present invention. However, the present invention is not limited to these specific details.

[0095] It should be noted that the components in the figures may be shown exaggeratedly for the sake of illustration and are not necessarily true to scale. In the figures, identical or functionally identical components are provided with the same reference numerals.

[0096] In the present invention, unless otherwise specified, "arranged on...", "arranged above..." and "arranged above..." do not exclude the existence of an intermediate between the two. In addition, "arranged on or above..." merely indicates the relative positional relationship between two components, and in certain cases, such as after reversing the product direction, it can also be converted into "arranged below or below...", and vice versa.

[0097] In the present invention, each embodiment is only intended to illustrate the aspects of the present invention and should not be construed as limiting.

[0098] In the present invention, unless otherwise specified, the quantifiers "a", "an" and "an" do not exclude the presence of a plurality of elements.

[0099] In the present invention, the term “connected” may refer to both being directly connected or being indirectly connected via an intermediate element.

[0100] In the present application, the term "configuration" refers to the setting of the shape, structure, material and / or function of the target object to achieve the desired technical effect, wherein "configuration" includes a variety of alternative technical means for achieving the technical effect, which become obvious under the teaching of the present application.

[0101] In this specification, reference to "one embodiment" or "the embodiment" means that a particular feature, structure, or characteristic described in conjunction with the embodiment is included in at least one embodiment of the present invention. The phrase "in one embodiment" appearing in various places in this specification does not necessarily all refer to the same embodiment.

[0102] It should be noted that the embodiments of the present invention describe the process steps in a specific order, but this is only for the purpose of illustrating the specific embodiment, rather than limiting the order of the steps. On the contrary, in different embodiments of the present invention, the order of the steps can be adjusted according to the adjustment of the process.

[0103] In the present invention, the term "upper part of the light-emitting mesa" refers to the part of the light-emitting mesa facing the microlens or the light-emitting side, and the term "lower part of the light-emitting mesa" refers to the part of the light-emitting mesa facing the driving backplane or the anode. Similarly, the term "upper surface or top surface of the light-emitting mesa" refers to the surface of the light-emitting mesa facing the microlens or the light-emitting side, and the term "lower surface or bottom surface of the light-emitting mesa" refers to the surface of the light-emitting mesa facing the driving backplane or the anode.

[0104] Figure 1 FIG. 1 is a schematic diagram of a micro light emitting diode chip 100 based on hybrid bonding according to the present invention.

[0105] like Figure 1 As shown, the micro-LED chip 100 based on hybrid bonding according to the present invention comprises an upper laminate 100A and a lower laminate 100B, wherein the upper laminate 100A and the upper laminate 100B are hybrid-bonded to each other at an interface A to form a complete micro-LED chip 100. The structures and components of the upper laminate 100A and the lower laminate 100B are described in detail below.

[0106] Upper layer

[0107] The upper stack 100A includes a first insulating layer 111A, a light emitting mesa 101, a transparent conductive layer 108, a first electrode 104 (cathode), a first via contact 102, a second electrode 110 (anode), a first bonding mark 109A, and a microlens 105. Each component is described below.

[0108] A first insulating layer 111A, which is configured to accommodate at least a portion of the light-emitting mesa 101 and provide electrical insulation therefor. Here, the first electrical insulating layer 111A has a recess 107, which is configured to accommodate the light-emitting layer and the second epitaxial layer of the light-emitting mesa 101 and the auxiliary structure of the light-emitting mesa 101. For a detailed description of the light-emitting mesa 101 and its auxiliary structures (such as a passivation layer, a reflector layer, etc.), reference can be made to the light-emitting mesa 101 and its description. Here, it should be noted that the recess 107 can be formed after the light-emitting mesa 101, that is, the light-emitting mesa 101 and its auxiliary structures are first formed on a temporary substrate, and then the first insulating layer 111A surrounding them is formed on the light-emitting mesa 101 and its auxiliary structures. The material of the first insulating layer 111A can be, for example, silicon dioxide, silicon nitride, a high dielectric constant material (such as hafnium oxide, aluminum oxide, etc.), etc. The first insulating layer 111A can be formed by thermal oxidation, chemical vapor deposition (CVD), etc. The thickness of the first insulating layer 111A is, for example, 1 to 3 μm, preferably 2 μm, and more preferably 0.6 to 1.4 μm. In addition, the first insulating layer 111A may be planarized at the interface A (eg, by chemical mechanical polishing (CMP)) to facilitate hybrid bonding with the second insulating layer 111B.

[0109] A light-emitting mesa 101 configured to emit light, wherein the top surface area of ​​the light-emitting mesa 01 is larger than the bottom surface area of ​​the light-emitting mesa. The light-emitting mesa 101 includes a first epitaxial layer 101A, a light-emitting layer 101B, and a second epitaxial layer 101C, wherein the first epitaxial layer 101A is arranged on the top of the light-emitting mesa, i.e., on the side facing the light-emitting surface, the light-emitting layer 101B is arranged in the recess 107 and between the first epitaxial layer 101A and the second epitaxial layer 101C, and the second epitaxial layer 101C is arranged on the bottom of the light-emitting mesa 101, i.e., on the side facing the driving backplane 106. The light-emitting layer 101B, for example, includes a multi-quantum well layer and an electron blocking layer. In one embodiment of the present invention, the first epitaxial layer 101A is an N-type GaN layer or an N-type Al GaN layer, and the second epitaxial layer 101C is a P-type GaN layer or a P-type Al GaN layer, that is, the material of the second epitaxial layer 101C can be a material layer of the second conductivity type including at least two or more elements of Ga, N, As, Al, In, and P, and the first epitaxial layer 101A can be a material layer of the first conductivity type including at least two or more elements of Ga, N, As, Al, In, and P. The multi-quantum well layer is an InGaN / GaN multi-quantum well layer or an InGaN / Al GaN multi-quantum well layer or an InGaAs / Al GaAs multi-quantum well layer. The electron blocking side is arranged on the first side of the light-emitting layer, and the first side refers to the side along which the electrons migrate out of the light-emitting layer. In another embodiment of the present invention, the first epitaxial layer can also be a P-type GaN layer or a P-type Al GaN layer, and the second epitaxial layer can be an N-type GaN layer or an N-type Al GaN layer. The top width of the light-emitting mesa 101 is, for example, 0.5 to 3 μm, preferably 1.0 to 2.0 μm. The thickness of the first epitaxial layer 101A is, for example, 4000 to 5000 angstroms, the thickness of the light-emitting layer 101B is, for example, 3500 to 4000 angstroms, and the thickness of the second epitaxial layer 101C is, for example, 2500 to 3500 angstroms. 1 angstrom = 10^(-10) meters. Figure 1It can be seen that the first epitaxial layer 101A is located outside the recess 107, while the light-emitting layer 101B and the second epitaxial layer 101C are located inside the recess 107. In this way, the surface area of ​​the first epitaxial layer 101A is not limited by the opening area of ​​the recess 107, but can be significantly larger than the opening area of ​​the recess 107, thereby significantly increasing the area and thickness of the first epitaxial layer 101A; in addition, since the recess 107 only needs to accommodate the light-emitting layer 101B and the second epitaxial layer 101C, these two layers have a larger area and thickness compared with the structure of the prior art that needs to accommodate three layers, thereby better increasing the area and thickness of the epitaxial layer 101 and improving the light emission. It can also be seen here that the first epitaxial layer 101A passes through the first electrode 104 (here, the cathode) from below, so that the first epitaxial layers 101A of adjacent light-emitting mesas 101 can be connected to each other, so that in the case of a common cathode structure (i.e., the first epitaxial layers of all micro-LEDs in the same array are connected to a common cathode), the conductivity between the cathode 104 and the first epitaxial layer 101A can be significantly enhanced compared to the case where the cathode 104 is connected only by the transparent conductive layer 108 covering it, thereby increasing its power supply. In addition, the contact cross section between the first epitaxial layer 101A and the cathode 104 at the edge is partially flat and partially inclined. Compared with the vertical surface, the inclined surface increases the contact area between the first epitaxial layer 101A and the cathode 104, thereby increasing the conductivity.

[0110] The light emitting mesa 101 further includes auxiliary structures such as passivation layers 112 and 113, a reflector layer 115, etc. The passivation layer 112 is arranged between the light emitting mesa 101 and the reflector layer 115, and optionally extends on the upper surface of the first insulating layer 111A, while the passivation layer 113 is arranged between the inner wall of the recess 107 and the reflector layer 115, and optionally extends on the upper surface of the first insulating layer 111A. In another embodiment, only one of the passivation layers 112 and 113 extends on the upper surface of the first insulating layer 111A, or both do not extend on the upper surface of the first insulating layer 111A, instead, they only extend to the upper surface of the first insulating layer 111A, and the upper surface of the first insulating layer 111A is covered by another insulating layer or a dielectric layer. The role of the passivation layers 112 and 113 is not only to reduce the current leakage at the sidewall, but also to passivate the sidewall defects, and prevent water, oxygen, etc. from damaging the light-emitting mesa during operation, and to prevent the metal in the reflector layer 115, cathode 104, etc. from diffusing to the first insulating layer 111 or the light-emitting mesa 101. The passivation layers 112 and 113 can be formed by depositing SiO2 material using a CVD process, or by depositing Al2O3 material using an ALD process. The reflector layer 115 is configured to reflect light from the light-emitting mesa 101 upward. To this end, the reflector layer 115 has an inclined surface on the side facing the light-emitting mesa 101. The material of the reflector layer 115 is, for example, silver, or a combination of multiple metal layers of nickel, silver, platinum, etc., and its thickness is 2000 to 4000 angstroms, preferably 3000 to 3500 angstroms. The reflector layer 115 can be formed, for example, by evaporation, sputtering, chemical vapor deposition (CVD), etc. The thickness of the passivation layer 112 between the reflector layer 112 and the light-emitting mesa 101 is 800 to 2000 angstroms, preferably 1000 to 1600 angstroms. The thickness of the passivation layer 113 between the reflector layer 115 and the recess inner wall 107 is 200 to 800 angstroms, preferably 300 to 600 angstroms.

[0111] A transparent conductive layer 108 is arranged on the first epitaxial layer 101A and electrically connects the first electrode 104 (cathode) to the first epitaxial layer 101A. Here, the transparent conductive layer 108 extends on the first epitaxial layer 101A and completely covers the first epitaxial layer 101A, thereby providing a more uniform power supply for the first epitaxial layer 101A. In other embodiments, the transparent conductive layer 108 may also only partially cover the first epitaxial layer 101A. In addition, the transparent conductive layer 108 also extends under the first electrode 104, which is the cathode in this case, so that the transparent conductive layer 108 extends continuously on the first epitaxial layer 101A of the adjacent light-emitting mesa 101A, thereby increasing the coverage area of ​​the first epitaxial layer 101A. The material of the transparent conductive layer 108 is, for example, a metal oxide, such as indium tin oxide ITO, zinc oxide ZnO, etc., and its formation method includes, for example, physical vapor deposition (PVD), chemical vapor deposition (CVD), sol-gel method, solution coating method, etc.

[0112] The first electrode 104, here a cathode, is arranged to surround the light-emitting mesa 104. The cathode 104 and its connecting parts can be made of materials such as metal (such as copper, silver or aluminum), graphene, ITO, aluminum-doped zinc oxide (AZO) or fluorine-doped tin oxide (FTO) or any combination of the above materials. In another embodiment of the present invention, the cathode 104 and its connecting parts can be made of non-transparent or transparent conductive materials, such as indium tin oxide (ITO). In a preferred embodiment, the cathode 104 is made of a reflective metal (such as copper, silver or aluminum), so that the cathode 104 can reflect light from the light-emitting mesa 101 while optically isolating adjacent light-emitting mesas 101 from each other, for example, reflecting the light upward to the microlens 105, thereby increasing the light output. In another embodiment, a reflective layer, such as a silver layer, can be coated on the surface of the cathode 104 to provide a reflective capability. Here, the surface of the cathode 104 facing the light-emitting mesa 101A is an inclined surface, and is inclined to both sides (i.e., inclined from the bottom surface to both sides), so that the light falling thereon can be reflected upward, i.e., to the light-emitting side. In addition, the cathode 104 can be divided into an edge cathode 104A and a middle cathode 104B, wherein the edge cathode 104A is arranged between the second electrode 110 (here, the anode) and the edgemost light-emitting mesa 101, wherein a part of the edge cathode 104A is arranged on the passivation layer 112, and another part is arranged on the transparent conductive layer 108, and the middle cathode 104B is arranged between adjacent light-emitting mesas 101, wherein the middle cathode 104B is arranged on the transparent conductive layer 108. In this way, the edge cathode 104A can completely cover the side of the first epitaxial layer 101A and be in electrical contact with it, thereby increasing the electrical contact area between the cathode 104 and the first epitaxial layer 101A.

[0113] · A first via contact 102, which is electrically connected to the bottom of the light-emitting mesa 101 and passes through the first insulating layer 111A. The first via contact 102 is used for hybrid bonding with the second via contact 103, and thereby electrically connects the bottom of the light-emitting mesa 101, especially the second epitaxial layer 101C, to the second electrode 110 (here, the anode). The first via contact 102 is preferably a cylindrical through-hole, and the inner wall and / or the middle space is filled with a conductor, such as metal copper. The diameter of the first via contact 102 is 0.3 to 2 μm, preferably 0.6 to 1.4 μm. The first via contact 102 can be planarized at the interface A (for example, by chemical mechanical polishing CMP) to facilitate hybrid bonding with the second via contact 103. In addition, see Figure 2 In order to promote the bonding strength between the first through-hole contact 102 and the second through-hole contact 103 and improve the conductivity, a first interface metal layer 201 may be arranged at the first opening 203 of the first through-hole contact 102, and the area of ​​the first interface metal layer 201 is larger than the area of ​​the first opening 203. Similarly, a second interface metal layer 202 may be arranged at the second opening 204 of the second through-hole contact 103, and the area of ​​the second interface metal layer 202 is larger than the area of ​​the second opening 204. The areas of the first interface metal layer 201 and the second interface metal layer 20 may be equal, or the area of ​​the first interface metal layer 201 may be larger or smaller than the area of ​​the second interface metal layer 202. After the first interface metal layer 201 and the second interface metal layer 202 are bonded to each other, the bonding surface formed is larger than the bonding surface formed by direct bonding of the first opening of the first through-hole contact 102 and the second opening 204 of the second through-hole contact 103, thereby increasing the bonding strength and improving the conductivity between the first through-hole contact 102 and the second through-hole contact 103. The first interface metal layer 201 and the second interface metal layer 202 are made of, for example, a conductive metal, such as copper. The formation method thereof may include, for example, physical vapor deposition (PVD), chemical vapor deposition (CVD), electroplating, chemical plating, etc. The formation method of the first through-hole contact 103 may be, for example, as follows: forming a light-emitting mesa 101 and a first insulating layer 111A on a temporary substrate, then etching the first insulating layer 111A to form a through hole leading to the bottom of the light-emitting mesa 101, then depositing metal in the through hole, and finally flattening the opening of the through hole to form a bonding surface.

[0114] The second electrode 110, which is an anode in this case, is electrically connected to the driving backplane 106 through a third through-hole contact 114 that passes through the first insulating layer 111A and the second insulating layer 111B. The anode 110 can be connected to an external power source or a control source, for example, to power or control the micro-LED chip 100. Here, the third through-hole contact 114 can include a plurality of through-hole contacts, so as to connect the second epitaxial layer 101C of the plurality of light-emitting mesas to the anode 110. Here, it is exemplarily shown that the third through-hole contact 114 includes two through-hole contacts, but this is merely exemplary, and other numbers of through-hole contacts 114 are also conceivable. The third through-hole contact 114 can be formed either before or after hybrid bonding. If the third through-hole contact 114 is formed before hybrid bonding, the upper and lower parts of the third through-hole contact 114 are first formed in the upper stack 100A and the lower stack 100B, respectively, and then the two are connected through the through-hole contact after hybrid bonding, and then the first insulating layer 111A is etched from above to form the anode 110 on the third through-hole contact 114. If the third through-hole contact 114 is formed after hybrid bonding, the first insulating layer 111A is etched from above to form a through hole leading to the driving backplane 106, and then metal is deposited in the through hole, and then the third through-hole contact 114 is etched to form a recess, and then metal is deposited in the recess to form the anode 110. The anode 110 and its connecting parts can be made of materials such as metal (such as copper, silver or aluminum), graphene, ITO, aluminum-doped zinc oxide (AZO) or fluorine-doped tin oxide (FTO) or any combination of the above materials.

[0115] · A first bonding mark 109A, which is disposed in the first insulating layer 111A and exposes a first mark surface, i.e., an opening of the first bonding mark. The first bonding mark 109A in the upper stack 100A serves as a mark for alignment with the second bonding mark 109B in the lower stack 100B, thereby achieving precise hybrid bonding, wherein the second bonding mark 109B is disposed in the second insulating layer 100B and exposes a second mark surface, i.e., an opening of the second bonding mark. The alignment method of the first bonding mark 109A and the second bonding mark 109B is that during hybrid bonding, the first mark surface is aligned and attached to the second mark surface, at which point the upper stack 100A and the lower stack 100B have been aligned, and then hybrid bonding can be performed. The first bonding mark 109A and the second bonding mark 109B can be metal vias, and the two can be bonded at the interface. In addition, the first bonding mark 109A and the second bonding mark 109B may have enlarged openings and / or the openings may be coated with a metal layer to facilitate identification of their positions and increase bonding strength.

[0116] A microlens 105 is disposed above the light-emitting mesa 101 to shape the light emitted therefrom, such as converging or collimating. The microlens includes a lens portion 105A and a spacer 105B. The lens portion 105A is disposed at the outermost side, i.e., the uppermost side, and is configured to shape the light from the light-emitting mesa 101. The spacer 105B is disposed between the lens portion 105A and the light-emitting mesa 101 to adjust the focal position of the lens portion 105A. For example, the focal point of the lens portion 105A can be exactly located in the light-emitting mesa 101 of the micro-LED by adjusting the thickness of the spacer 105B and the curvature of the lens portion 105A. The width of the microlens 105 is, for example, 0.8 to 4 μm, preferably 1 to 3 μm. The distance between the lens portion 105A and the cathode 104 is, for example, 0.05 to 4 μm, preferably 0.1 to 0.3 μm. The microlens 105 corresponds to the light-emitting mesa 101 one by one. Meanwhile, in this embodiment, there is a gap between adjacent microlenses 105 and the bottoms thereof are connected to each other. The bottom of the gap is higher than the top of the light-emitting mesa 101, or higher than the bottom of the light-emitting layer 101B of the light-emitting mesa 101, and the lens portion 104A is located above the cathode 104. The microlenses 105 can be formed by multiple depositions. In the process of forming the microlenses, a SiO2 film layer needs to be deposited first, and then ion etching is performed. The microlenses are formed on the surface of the transparent conductive layer 108 at positions corresponding to each light-emitting mesa 101.

[0117] Lower stack

[0118] The lower stack 100B includes a second insulating layer 111B, a second through-hole contact 103, a driving back plate 106, and a second bonding mark 109B. Each component will be described below.

[0119] A second insulating layer 111B, which is arranged on the driving backplane 106 and is configured to accommodate the second through-hole contact 103. The material of the second insulating layer 111B can be, for example, silicon dioxide, silicon nitride, a high dielectric constant material (such as hafnium oxide, aluminum oxide, etc.), etc. The second insulating layer 111B can be formed on the driving backplane 106, for example, by thermal oxidation, chemical vapor deposition (CVD), etc. The thickness of the second insulating layer 111B is, for example, 1 to 3 μm, preferably 2 μm, and more preferably 0.6 to 1.4 μm. In addition, the second insulating layer 111B can be planarized at the interface A (for example, by chemical mechanical polishing CMP) to promote hybrid bonding with the first insulating layer 111A.

[0120] · A second via contact 103, which passes through the second insulating layer 111B. The second via contact 103 is configured to be hybrid bonded with the first via contact 102 at the interface A, and thereby electrically connects the bottom of the light-emitting mesa 101, especially the second epitaxial layer 101C, to the second electrode 110 (here, the anode). The second via contact 103 is preferably a cylindrical through-hole, and the inner wall and / or the middle space is filled with a conductor, such as metal copper. The diameter of the second via contact 103 is 0.5 to 2.2 μm, preferably 0.8 to 1.6 μm. The second via contact 103 can be planarized at the interface A (for example, by chemical mechanical polishing CMP) to promote hybrid bonding with the first via contact 102. In addition, see Figure 2 In order to promote the bonding strength between the second through-hole contact 103 and the first through-hole contact 102 and improve the conductivity, a second interface metal layer 202 may be arranged at the second opening 204 of the second through-hole contact 103, and the area of ​​the second interface metal layer 202 is larger than the area of ​​the second opening 204. Similarly, a first interface metal layer 201 may be arranged at the first opening 203 of the first through-hole contact 102, and the area of ​​the first interface metal layer 201 is larger than the area of ​​the first opening 203. The areas of the first interface metal layer 201 and the second interface metal layer 202 may be equal, or the area of ​​the first interface metal layer 201 may be larger or smaller than the area of ​​the second interface metal layer 202. After the first interface metal layer 201 and the second interface metal layer 202 are bonded to each other, the bonding surface formed is larger than the bonding surface formed by direct bonding of the first opening of the first through-hole contact 102 and the second opening 204 of the second through-hole contact 103, thereby increasing the bonding strength and improving the conductivity between the first through-hole contact 102 and the second through-hole contact 103. The first interface metal layer 201 and the second interface metal layer 202 are made of, for example, a conductive metal, such as copper. The formation method thereof may include, for example, physical vapor deposition (PVD), chemical vapor deposition (CVD), electroplating, chemical plating, etc. The formation method of the second through-hole contact 103 may be, for example, as follows: providing a driving backplane 106, then forming a second insulating layer 111B on the driving backplane 106, then etching the second insulating layer 111B to form a through hole leading to the top of the driving backplane 106, then depositing metal in the through hole, and finally flattening the opening of the through hole to form a bonding surface.

[0121] A driving backplane 106, which is electrically connected to the second through-hole contact 103 so as to electrically connect the second epitaxial layer 101C of the light-emitting mesa 101 to the anode 110. To this end, the driving backplane 106 has a conductive circuit layer for interconnecting each second through-hole contact 103 to the corresponding anode 110. The driving backplane 106 can be, for example, a thin film transistor TFT driving circuit, and can include a 2T1 C driving circuit, a 3T1 C driving circuit, and a 5T2C driving circuit. The driving backplane 106 is configured to drive the micro light-emitting diode, for example, to control the connection, disconnection and brightness of the micro light-emitting diode. The driving backplane 106 can include, for example, transistors, capacitors, a conductive circuit layer, an insulating layer, and a metal layer. The conductive circuit layer is formed on the substrate and is configured to supply power to the micro light-emitting diode array. The insulating layer is formed on the conductive circuit layer, wherein the insulating layer is provided with a through hole, and the through hole is provided with a through hole contact (for example, an IC copper column) for electrically connecting the conductive circuit layer to the micro light-emitting diode array. The metal layer is used for bonding and electrical contacting the micro light emitting diodes. The conductive line layer, the metal layer and the insulating layer may have been formed on the substrate 601 by deposition, such as physical vapor deposition (PVD) and chemical vapor deposition (CVD).

[0122] · A second bonding mark 109B, which is disposed in the second insulating layer 111B and exposes a second mark surface, i.e., an opening of the second bonding mark. The second bonding mark 109B in the lower stack 100B serves as a mark for alignment with the first bonding mark 109A in the upper stack 100A, thereby achieving precise hybrid bonding. The first bonding mark 109A and the second bonding mark 109B are aligned in such a way that, during hybrid bonding, the first mark surface is aligned and attached to the second mark surface, at which point the upper stack 100A and the lower stack 100B are aligned, and then hybrid bonding can be performed. The first bonding mark 109A and the second bonding mark 109B can be metal through holes, and the two can be bonded at the interface. In addition, the first bonding mark 109A and the second bonding mark 109B can have an enlarged opening and / or a metal layer can be coated at the opening to facilitate identification of their positions and increase bonding strength.

[0123] After the lower stack 100A and the upper stack 100B are formed, the lower stack 100A is bonded to the upper stack 100A by hybrid bonding, so that the first through-hole contact 102 is bonded to the second through-hole contact 103, and the first insulating layer 111A is bonded to the second insulating layer 111B, and optionally the first bonding mark 109A is bonded to the second bonding mark 109B, and the upper and lower parts of the third through-hole contact 114 are bonded to each other. The present invention solves the technical problem encountered when manufacturing an inverted trapezoidal light-emitting mesa with a large upper surface and a small lower surface, that is, the problem of electrical connection between the light-emitting mesa and the driving backplane, by separately manufacturing the upper stack 100A and the lower stack 100B and then bonding the two to each other by hybrid bonding. The present invention realizes the electrical connection from the light-emitting table 101 to the driving backplane 106 through hybrid bonding, so that the upper stack 100A and the lower stack 100B can be manufactured from the surface opposite to the hybrid bonding surface, that is, the interface A, toward the hybrid bonding surface, thereby realizing a high-quality conductive structure, such as the first to third through-hole contacts (such as IC copper pillars), and the length of the conductive structure can also be flexibly selected.

[0124] An example of a hybrid bond may include the following two parts:

[0125] (1) Dielectric-to-dielectric bonding (i.e., bonding between the first insulating layer 111A and the second insulating layer 111B): At room temperature, extremely flat and smooth dielectric surfaces obtained by chemical mechanical polishing (CMP) are activated by plasma treatment or other methods and then brought into close contact at room temperature to achieve preliminary bonding.

[0126] (2) Metal-to-metal bonding (i.e., bonding between through-hole contacts): After completing dielectric-to-dielectric bonding, the upper and lower layers are heated to 200-400°C for annealing to strengthen the dielectric bonding and promote metal-to-metal bonding, thereby achieving hybrid bonding.

[0127] Figure 3 FIG. 1 shows a top view of a micro light emitting diode chip 100 based on hybrid bonding according to the present invention and a cross-sectional view along a cross-sectional line B, wherein Figure 3 The left part of shows a top view of the micro light emitting diode chip 100 based on hybrid bonding, and the right part shows a cross-sectional view of the micro light emitting diode chip 100 along the cross-sectional line B based on hybrid bonding.

[0128] like Figure 3 As shown on the left, a hybrid bonding-based micro-LED chip 100 includes a plurality of light-emitting mesas 101. The light-emitting mesas 101 have a circular light-emitting surface, but this is merely exemplary, and light-emitting surfaces of other shapes are also conceivable. A cathode 104 is arranged to surround the light-emitting mesas 101, and a transparent conductive layer 108 is arranged under the cathode 104 and exposed at a portion of the position. Figure 2It can be seen that the light-emitting mesa 101 of the hybrid bonding-based micro LED chip 100 has an upper surface larger than a lower surface, and has a first through-hole contact portion 102 electrically connected to a driving backplane at the bottom.

[0129] Combine the following FIG. 4A to FIG. 4D The method for manufacturing a micro light emitting diode chip according to the present invention is described below.

[0130] In step S1, Figure 4A As shown, a temporary substrate 301 is provided, and a portion of the upper stack 100A is formed on the temporary substrate 301, the portion comprising:

[0131] First, a light emitting layer and a second epitaxial layer of the light emitting mesa 101 are deposited on the temporary substrate 301 .

[0132] Then, a passivation layer is deposited on the light-emitting mesa.

[0133] Next, a first insulating layer 111A is deposited on the light-emitting mesa.

[0134] Then, a first through-hole contact portion 102 is etched on the first insulating layer 111A, wherein the bottom of the first through-hole contact portion 102 is exposed from the bottom of the light-emitting mesa 101 .

[0135] Finally, metal is deposited in the first via contact 102 .

[0136] In step S2, if Figure 4B As shown, the upper stack 100A is debonded from the temporary substrate to expose the light emitting layer of the light emitting mesa 101 .

[0137] In step S3, if Figure 4C As shown, a lower stack is formed, 100B, comprising:

[0138] First, the driving back plate 106 is formed.

[0139] Then, a second insulating layer 111B is deposited on the driving backplane 106 .

[0140] Next, the second through-hole contact portion 103 is etched on the second insulating layer 111B, wherein the bottom of the second through-hole contact portion 103 exposes the electrical contact portion of the driving backplane 106 .

[0141] Then, metal is deposited in the second via contact 103 .

[0142] In step S3, if Figure 4D As shown, the upper stack and the lower stack are hybrid-bonded, so that the first via contact 102 is bonded to the second via contact 103 , and the first insulating layer 111A is bonded to the second insulating layer 111B.

[0143] In step S4, other structures are formed on the upper laminate after hybrid bonding. For example, these structures include (see Figure 1 ):

[0144] A passivation layer 112 is deposited on the top surface of the light emitting mesa 101 .

[0145] The passivation layer 112 is etched to expose the light emitting layer 101B of the light emitting mesa.

[0146] The first epitaxial layer 101A is deposited on the light emitting layer 101B. The first epitaxial layer 101A may extend beyond the recess 107 and protrude beyond the passivation layer 112 by a certain height.

[0147] A transparent conductive layer 108 is deposited on the first epitaxial layer 101A.

[0148] A cathode 104 is deposited on the transparent conductive layer 101A.

[0149] Microlenses 105 are deposited on cathode 104 and transparent conductive layer 108 .

[0150] The first and second insulating layers 111A and 111B are etched at the side of the light emitting mesa 101 to form a third via contact 114 , the bottom of which exposes an electrical contact portion of the driving backplane 106 .

[0151] Metal is deposited in the third via contact 114 to form the anode 110 .

[0152] Although some embodiments of the present invention have been described in this application document, it will be appreciated by those skilled in the art that these embodiments are merely shown as examples. Those skilled in the art may conceive of numerous variations, alternatives, and improvements under the teachings of the present invention without departing from the scope of the present invention. The appended claims are intended to define the scope of the present invention and thus cover methods and structures within the scope of these claims themselves and their equivalents.

Claims

1. A micro light emitting diode chip based on hybrid bonding, comprising: The upper stack comprises: a first insulating layer accommodating the light-emitting mesa and the first through-hole contact; a light-emitting mesa that emits light, wherein an area of ​​a top surface of the light-emitting mesa is greater than an area of ​​a bottom surface of the light-emitting mesa; and a first through-hole contact portion electrically connected to the bottom of the light-emitting mesa and passing through the first insulating layer; and The lower stack comprises: a second insulating layer accommodating a second through-hole contact; a second through-hole contact passing through the second insulating layer; and The driving back plate is electrically connected to the second via contact, wherein the lower stack is bonded to the upper stack by hybrid bonding, so that the first via contact is bonded to the second via contact, and the first insulating layer is bonded to the second insulating layer.

2. The micro light emitting diode chip according to claim 1, wherein: The upper stack also includes a first bonding mark, which is disposed in the first insulating layer and exposes a first mark surface; The lower stack further includes a second bonding mark disposed in the second insulating layer and exposing a second mark surface; and During hybrid bonding, the first marking surface is aligned with the second marking surface to align the upper stack and the lower stack.

3. The micro-LED chip according to claim 1, wherein the light-emitting mesa comprises: a first epitaxial layer extending beyond the recess of the first insulating layer and in electrical contact with the light emitting layer; a light emitting layer in the recess and between the first epitaxial layer and the second epitaxial layer; as well as A second epitaxial layer is in the recess and is in electrical contact with the light emitting layer and the first through-hole contact.

4. The micro-LED chip according to claim 3, wherein the upper stack further comprises: a transparent conductive layer on the first epitaxial layer and electrically connecting the cathode to the first epitaxial layer; a passivation layer surrounding the side surfaces of the light-emitting mesa and extending to the upper surface of the first insulating layer; cathode, surrounding the light-emitting table; as well as The anode is electrically connected to the driving back plate through a third through-hole contact portion that passes through the first insulating layer and the second insulating layer.

5. The micro-LED chip according to claim 4, wherein the cathode comprises: An edge cathode is between the anode and the edgemost light-emitting mesa, wherein a portion of the edge cathode is on the passivation layer and another portion is on the transparent conductive layer; as well as The middle cathode is between adjacent light-emitting mesas, wherein the middle cathode is on the transparent conductive layer. The micro light emitting diode chip according to claim 4 , wherein the cathode is a reflective electrode made of metal.

7. The micro light emitting diode chip according to claim 5, wherein: The side of the edge cathode facing the light-emitting table is an inclined surface; as well as Both sides of the middle cathode facing the light-emitting table are inclined surfaces. 8 . The micro light emitting diode chip according to claim 5 , wherein the first epitaxial layer partially passes through the edge cathode and completely passes through the middle cathode, wherein an edge of the first epitaxial layer in the edge cathode is an inclined surface.

9. The micro-LED chip according to claim 4, wherein the upper stack further comprises: The reflector layer is between the inner wall of the recess and the passivation layer, wherein the reflector layer has an inclined surface on a side facing the light-emitting mesa to reflect light from the light-emitting mesa upward.

10. The micro-LED chip according to claim 4, wherein the upper stack further comprises a micro-lens, which comprises: a lens portion, which is at the outermost side and is configured to shape the light from the light-emitting mesa; as well as The spacer is between the lens portion and the light-emitting table to adjust the focal position of the lens portion.

11. The micro light emitting diode chip according to claim 1, wherein the first through hole contact portion has a first opening at the surface of the first insulating layer, wherein the first opening has an interface metal layer, and the area of ​​the interface metal layer is larger than the area of ​​the first opening; and / or The second through hole contact portion has a second opening at the surface of the second insulating layer, wherein an interface metal layer is provided at the second opening, and an area of ​​the interface metal layer is larger than an area of ​​the first opening. 12 . The micro light emitting diode chip according to claim 9 , wherein a passivation layer is provided between the reflector layer and the inner wall of the recess. 13 . The micro light emitting diode chip according to claim 8 , wherein the first epitaxial layers of adjacent light emitting mesas are continuous with each other through a middle cathode.

14. The micro light emitting diode chip according to claim 1, wherein the first and second through-hole contacts are IC copper pillars, and a metal layer is provided on the surface of the driving backplane, the IC copper pillars are electrically connected to the metal layer, and each light emitting mesa corresponds to one IC copper pillar. 15 . The micro light emitting diode chip according to claim 4 , wherein the material of the passivation layer is SiO 2 film, Al 2 O 3 film or SiO 2 / Al 2 O 3 composite structure film.

16. The micro light emitting diode chip according to any one of claims 1 to 15, wherein: The thickness of the first insulating layer is 0.6 to 1.4 μm; and / or The thickness of the second insulating layer is 0.6 to 1.4 μm.

17. The micro light emitting diode chip according to any one of claims 1 to 15, wherein: The diameter of the first through-hole contact is 0.6 to 1.4 μm; and / or The diameter of the second via contact is 0.8 to 1.6 μm.

18. The micro light emitting diode chip according to claim 9, wherein: The thickness of the passivation layer between the reflector layer and the light-emitting mesa is 1000 to 1600 angstroms; and / or The thickness of the passivation layer between the reflector layer and the inner wall of the recess is 300 to 600 angstroms; and / or The material of the reflector layer includes silver, and its thickness is 3000 to 3500 angstroms.

19. The micro light emitting diode chip according to any one of claims 1 to 15, wherein: The top width of the light-emitting mesa is 1.0 to 2.0 μm; and / or The first epitaxial layer has a thickness of 4000 to 5000 angstroms; and / or The thickness of the light emitting layer is 3500 to 4000 angstroms; and / or The thickness of the second epitaxial layer is 2500 to 3500 angstroms.

20. The micro light emitting diode chip according to claim 10, wherein: The width of the microlens is 1 to 3 μm; and / or The distance between the lens portion and the cathode is 0.1 to 0.3 μm.

21. A method for manufacturing a micro light emitting diode chip, comprising the following steps: Forming a portion of an upper stack on a temporary substrate, comprising: Depositing a light-emitting layer and a second epitaxial layer of the light-emitting mesa on a temporary substrate; depositing a passivation layer on the light-emitting mesa; depositing a first insulating layer on the light emitting mesa; Etching a first through-hole contact portion on the first insulating layer, wherein the bottom of the first through-hole contact portion exposes the bottom of the light-emitting mesa; depositing metal in the first via contact; as well as debonding the upper stack from the temporary substrate; A lower stack is formed, comprising: forming a driving backplane; Depositing a second insulating layer on the driver backplane; Etching a second through-hole contact portion on the second insulating layer, wherein the bottom of the second through-hole contact portion exposes an electrical contact portion of the driving backplane; and depositing metal in the second via contact; and The upper stack layer is hybrid-bonded to the lower stack layer, so that the first through-hole contact is bonded to the second through-hole contact, and the first insulating layer is bonded to the second insulating layer.

22. The method according to claim 21, further comprising the steps of: depositing a passivation layer on the top surface of the light emitting mesa and the first insulating layer; etching the passivation layer to expose the light-emitting layer of the light-emitting mesa; depositing a first epitaxial layer on the light emitting layer; depositing a transparent conductive layer on the first epitaxial layer; depositing a cathode on the transparent conductive layer; depositing microlenses on the cathode and the transparent conductive layer; Etching the first and second insulating layers at the side of the light-emitting mesa to form a third through-hole contact portion, wherein the bottom of the third through-hole contact portion exposes an electrical contact portion of the driving backplane; as well as A metal is deposited in the third via contact to form an anode.

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