Display panel, preparation method thereof and display device

Abstract

The invention relates to the technical field of display, and particularly discloses a display panel, a preparation method thereof and a display device.The display panel comprises an array substrate and a plurality of pixel units located on one side of the array substrate, each pixel unit at least comprises a first sub-pixel unit and a second sub-pixel unit, the opening area of the second sub-pixel unit is larger than that of the first sub-pixel unit; the parasitic capacitance between the second sub-pixel unit and the array substrate is smaller than the parasitic capacitance between the first sub-pixel unit and the array substrate. The parasitic capacitance between the second sub-pixel unit and the array substrate is set to be smaller than the parasitic capacitance between the first sub-pixel unit and the array substrate, so that OLED capacitance difference caused by different opening areas of the first sub-pixel unit and the second sub-pixel unit can be made up through differential setting of the parasitic capacitance; therefore, the difference between the turn-on speed of the first sub-pixel unit and the turn-on speed of the second sub-pixel unit is made up, and finally the purpose of improving color cast is achieved.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel and a method for preparing the same, and a display device. Background Art

[0002] Organic light-emitting diode (OLED) display is a new type of display technology with the advantages of self-luminescence, high contrast, and fast response time. It is widely used in smart phones, televisions, computer monitors and other fields.

[0003] However, OLED displays may have color shift problems during use, which will seriously affect the display effect of the display. Summary of the invention

[0004] Based on this, it is necessary to provide a display panel and a method for manufacturing the same, and a display device to address the above problems.

[0005] According to a first aspect of an embodiment of the present application, a display panel is provided, comprising an array substrate and a plurality of pixel units located on one side of the array substrate, each of the pixel units comprising at least a first sub-pixel unit and a second sub-pixel unit, wherein an opening area of ​​the second sub-pixel unit is greater than an opening area of ​​the first sub-pixel unit;

[0006] The parasitic capacitance between the second sub-pixel unit and the array substrate is smaller than the parasitic capacitance between the first sub-pixel unit and the array substrate.

[0007] In one of the embodiments, the array substrate comprises a planarization layer, and a thickness of the planarization layer corresponding to the first electrode in the second sub-pixel unit is greater than a thickness of the planarization layer corresponding to the first electrode in the first sub-pixel unit.

[0008] In one embodiment, the first electrode comprises an anode.

[0009] In one of the embodiments, one side of the planarization layer is adjacent to the first electrode, and the other side of the planarization layer is adjacent to the metal layer in the array substrate.

[0010] In one embodiment, the metal layer includes a source-drain electrode layer.

[0011] In one embodiment, the parasitic capacitance between the second sub-pixel unit and the array substrate is the parasitic capacitance between the first electrode in the second sub-pixel unit and the source-drain electrode layer, and / or the parasitic capacitance between the first sub-pixel unit and the array substrate is the parasitic capacitance between the first electrode in the first sub-pixel unit and the source-drain electrode layer.

[0012] In one embodiment, the first sub-pixel unit is a red sub-pixel unit, and the second sub-pixel unit is a green sub-pixel unit.

[0013] In one embodiment, each of the pixel units further includes a third sub-pixel unit.

[0014] In one embodiment, the third sub-pixel unit is a blue light sub-pixel unit.

[0015] In one of the embodiments, the thickness of the planarization layer corresponding to the first electrode in the second sub-pixel unit is equal to the thickness of the planarization layer corresponding to the first electrode in the third sub-pixel unit.

[0016] In one embodiment, the thickness ratio of the planarization layer corresponding to the first electrode in the first sub-pixel unit, the planarization layer corresponding to the first electrode in the second sub-pixel unit, and the planarization layer corresponding to the first electrode in the third sub-pixel unit is 1:1.5:1.5-1:2:2.

[0017] According to a second aspect of an embodiment of the present application, a method for preparing a display panel is provided, comprising:

[0018] forming an array substrate, wherein the array substrate comprises a planarization layer;

[0019] A plurality of pixel units are formed on one side of the array substrate, the pixel units at least comprising a first sub-pixel unit and a second sub-pixel unit, wherein an opening area of ​​the second sub-pixel unit is larger than an opening area of ​​the first sub-pixel unit;

[0020] In the step of forming the array substrate, the planarization layer is formed by using an HTM process so that the thickness of the planarization layer corresponding to the first electrode in the second sub-pixel unit is greater than the thickness of the planarization layer corresponding to the first electrode in the first sub-pixel unit.

[0021] According to a third aspect of an embodiment of the present application, a display device is provided, comprising the display panel as described above.

[0022] The display panel provided by the embodiment of the present application includes an array substrate and a plurality of pixel units located on one side of the array substrate, each pixel unit includes at least a first sub-pixel unit and a second sub-pixel unit. Generally, due to the limitation of the FMM network, the opening area of ​​the second sub-pixel unit will be larger than the opening area of ​​the first sub-pixel unit, thereby causing the first sub-pixel unit and the second sub-pixel unit to have different light-on speeds at low grayscale, thereby causing the problem of color deviation. To address this problem, in the present embodiment, the parasitic capacitance between the second sub-pixel unit and the array substrate is set to be smaller than the parasitic capacitance between the first sub-pixel unit and the array substrate. Therefore, the OLED capacitance difference caused by the different opening areas of the first sub-pixel unit and the second sub-pixel unit can be compensated by the differentiated setting of the parasitic capacitance, thereby compensating for the difference in the light-on speeds of the first sub-pixel unit and the second sub-pixel unit, and finally achieving the purpose of improving the color deviation. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 It is a simple schematic diagram of an OLED pixel driving circuit;

[0024] Figure 2 is a schematic diagram of the arrangement of pixel units;

[0025] Figure 3 A schematic diagram of the arrangement of pixel units on an array substrate in a display panel provided in an embodiment of the present application;

[0026] Figure 4 for Figure 3 A schematic cross-sectional view along the A-A' section line;

[0027] Figure 5 for Figure 3 A schematic cross-sectional view along the B-B' section line;

[0028] Figure 6 is a graph of current-charging time of a corresponding sub-pixel unit when a planarization layer is prepared by different processes;

[0029] Figure 7 A flow chart of a method for preparing a display panel provided in one embodiment of the present application.

[0030] Description of reference numerals:

[0031] 100, pixel unit; 110, first sub-pixel unit; 120, second sub-pixel unit; 130, third sub-pixel unit; 140, first electrode; 210, planarization layer; 220, metal layer. DETAILED DESCRIPTION

[0032] In order to facilitate the understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present application are given in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to understand the disclosure of the present application more thoroughly and comprehensively.

[0033] In this application, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements, unless otherwise clearly defined. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0034] The terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include at least one of the features. In the description of this application, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0035] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application. The term "and / or" used herein includes any and all combinations of one or more of the related listed items.

[0036] Organic light-emitting diode (OLED) display is a new type of display technology, which has the advantages of self-luminescence, high contrast, fast response time, etc., and is widely used in smart phones, TVs, computer monitors, etc. However, OLED display may have color deviation problems during use, which will seriously affect the display effect of the display.

[0037] In the process of implementing the present invention, the inventors found that the following problems exist in the related art: due to the limitation of FMM network, in wearable OLED products, the opening area of ​​the green sub-pixel is often larger than the opening area of ​​the red sub-pixel, which will cause the OLED capacitance Co_oled of the green sub-pixel to be larger than the OLED capacitance Co_oled of the red sub-pixel. Figure 1According to the formula Von=Vini+Ids*t / C_oled, it can be known that when Vini, Ids and Von remain unchanged, the larger the OLED capacitance Co_oled, the larger the OLED charging time t. Since the OLED capacitance Co_oled of the green sub-pixel is greater than the OLED capacitance Co_oled of the red sub-pixel, the OLED charging time t of the green sub-pixel is greater than the OLED charging time t of the red sub-pixel. Therefore, the emission time of the green sub-pixel is shorter than that of the red sub-pixel, resulting in the brightness of the green sub-pixel being lower than that of the red sub-pixel. Therefore, the brightness of the red sub-pixel and the green sub-pixel is different, causing color deviation, especially at low grayscale, when Ids is small, the color deviation phenomenon is particularly obvious.

[0038] In order to solve the above problems, an embodiment of the present application provides a display panel, which does not have a color shift problem caused by different opening areas of pixel units during use. The display panel provided in this embodiment may include an OLED display panel, etc., and the following description takes the OLED display panel as an example.

[0039] The display panel provided in this embodiment includes an array substrate and a plurality of pixel units 100 located on one side of the array substrate. Figure 2 and Figure 3 Each of the pixel units 100 includes at least a first sub-pixel unit 110 and a second sub-pixel unit 120, wherein an opening area of ​​the second sub-pixel unit 120 is larger than an opening area of ​​the first sub-pixel unit 110. A parasitic capacitance between the second sub-pixel unit 120 and the array substrate is smaller than a parasitic capacitance between the first sub-pixel unit 110 and the array substrate.

[0040] The array substrate may include a substrate and a pixel circuit layer disposed on the substrate, wherein a planarization layer 210 is disposed on a side of the pixel circuit layer away from the substrate, and a plurality of pixel units 100 are disposed on a side of the planarization layer 210 away from the substrate. Each pixel unit 100 may be arranged in an array, and each pixel unit 100 includes a plurality of sub-pixel units, wherein each pixel unit 100 may include at least a first sub-pixel unit 110 and a second sub-pixel unit 120, and the display colors of the first sub-pixel unit 110 and the second sub-pixel unit 120 are different.

[0041] In this embodiment, the opening area of ​​the second sub-pixel unit 120 is larger than the opening area of ​​the first sub-pixel unit 110. This is because, in the actual manufacturing process, due to the limitation of the FMM (Fine Metal Mas, high-precision metal mask) mesh, the opening area of ​​the second sub-pixel unit 120 will be larger than the opening area of ​​the first sub-pixel unit 110, which will cause the OLED capacitance of the second sub-pixel unit 120 to be larger than the OLED capacitance of the first sub-pixel unit 110. According to the formula Von = Vini + Ids*t / C_oled, when Vini, Ids and Von remain unchanged, the larger the OLED capacitance Co_oled, the larger the OLED charging time t. Since the OLED capacitance Co_oled of the second sub-pixel unit 120 is greater than the OLED capacitance Co_oled of the first sub-pixel unit 110, the OLED charging time t of the second sub-pixel unit 120 is greater than the OLED charging time t of the first sub-pixel unit 110, that is, the lighting speed of the second sub-pixel unit 120 is slower than the lighting speed of the first sub-pixel unit 110, so the light-emitting time of the second sub-pixel unit 120 is shorter than the light-emitting time of the first sub-pixel unit 110, resulting in the brightness of the second sub-pixel unit 120 being lower than the brightness of the first sub-pixel unit 110, thereby causing the first sub-pixel unit 110 and the second sub-pixel unit 120 to have different brightness and cause color deviation, especially at low grayscale, Ids is small and the color deviation phenomenon is particularly obvious.

[0042] In view of the above color shift problem, in this embodiment, the parasitic capacitance between the second sub-pixel unit 120 and the array substrate is set to be smaller than the parasitic capacitance between the first sub-pixel unit 110 and the array substrate. The OLED capacitance of the first sub-pixel unit 110 also includes a parasitic capacitance, and similarly, the OLED capacitance of the second sub-pixel unit 120 also includes a parasitic capacitance. By changing the size of the parasitic capacitance of each sub-pixel unit, the size of the OLED capacitance of each sub-pixel unit can be changed. In the conventional technology, the OLED capacitance of the second sub-pixel unit 120 is greater than the OLED capacitance of the first sub-pixel unit 110. When the parasitic capacitance between the second sub-pixel unit 120 and the array substrate in the present embodiment is less than the parasitic capacitance between the first sub-pixel unit 110 and the array substrate, the difference between the OLED capacitance of the second sub-pixel unit 120 and the OLED capacitance of the first sub-pixel unit 110 can be reduced, and thus the difference between the OLED charging time of the second sub-pixel unit 120 and the OLED charging time of the first sub-pixel unit 110 can be reduced, that is, the difference between the light-on speed of the second sub-pixel unit 120 and the light-on speed of the first sub-pixel unit 110 can be reduced, and thus the difference between the light-emitting time of the second sub-pixel unit 120 and the light-emitting time of the first sub-pixel unit 110 can be reduced, that is, the difference between the brightness of the second sub-pixel unit 120 and the brightness of the first sub-pixel unit 110 can be reduced, thereby achieving the effect of improving the color shift problem.

[0043] In this embodiment, the pixel unit 100 includes each pixel defining region and a sub-pixel region between adjacent pixel defining regions, each sub-pixel region includes a first electrode 140, a light-emitting layer, and a second electrode, for example, the first sub-pixel unit 110 includes a first electrode 140, a first light-emitting layer, and a second electrode, and the second sub-pixel unit 120 includes a first electrode 140, a second light-emitting layer, and a second electrode. The first electrode 140 is located on a side of the planarization layer 210 away from the substrate, that is, the planarization layer 210 is disposed on a side of the first electrode 140 away from the light-emitting layer. The first electrode may include an anode, and the second electrode may include a cathode.

[0044] Among them, the material of the planarization layer 210 may include an organic material, such as a resin, etc. The material of the first electrode 140 may include indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO) or aluminum zinc oxide (AZO). The light-emitting layer may include a light-emitting material, which may be a small molecule, a polymer or a mixture of a small molecule polymer. The material of the cathode may include silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), or a mixture of any of the above materials.

[0045] Among them, any one or more layers of a hole injection layer, a hole transport layer, and an electron blocking layer may be included between the first electrode 140 and the light-emitting layer, and any one or more layers of a hole blocking layer, an electron transport layer, and an electron injection layer may be included between the light-emitting layer and the second electrode.

[0046] Reference Figure 3-Figure 5 In this embodiment, the thickness of the planarization layer 210 corresponding to the first electrode 140 in the second sub-pixel unit 120 is greater than the thickness of the planarization layer 210 corresponding to the first electrode 140 in the first sub-pixel unit 110. The planarization layer 210 corresponding to the first electrode 140 in the second sub-pixel unit 120 refers to the planarization layer 210 located directly below the first electrode 140 in the second sub-pixel unit 120. Specifically, the array substrate may include a substrate, and the planarization layer 210 corresponding to the first electrode 140 in the second sub-pixel unit 120 refers to the orthographic projection of the planarization layer 210 on the substrate overlapping with the orthographic projection of the first electrode 140 in the second sub-pixel unit 120 on the substrate. Similarly, the planarization layer 210 corresponding to the first electrode 140 in the first sub-pixel unit 110 refers to the planarization layer 210 located in the area directly below the first electrode 140 in the first sub-pixel unit 110. Specifically, the planarization layer 210 corresponding to the first electrode 140 in the first sub-pixel unit 110 refers to the overlap of the orthographic projection of the planarization layer 210 on the substrate with the orthographic projection of the first electrode 140 in the first sub-pixel unit 110 on the substrate. That is, by setting the thickness of the planarization layer 210 corresponding to the first electrode 140 in the second sub-pixel unit 120 to be greater than the thickness of the planarization layer 210 corresponding to the first electrode 140 in the first sub-pixel unit 110, the parasitic capacitance of the second sub-pixel unit 120 can be made smaller than the parasitic capacitance of the first sub-pixel unit 110. This method is relatively simple to implement and has low cost.

[0047] In practical applications, the specific thickness value of the planarization layer 210 corresponding to the first electrode 140 in the second sub-pixel unit 120 and the specific thickness value of the planarization layer 210 corresponding to the first electrode 140 in the first sub-pixel unit 110 can be set according to actual needs, as long as the parasitic capacitance of the second sub-pixel unit 120 can be smaller than the parasitic capacitance of the first sub-pixel unit 110, so as to reduce the difference between the OLED capacitance of the second sub-pixel unit 120 and the OLED capacitance of the first sub-pixel unit 110.

[0048] Specifically, the planarization layer 210 can be prepared by the HTM (HalfTone) process, so that the planarization layer 210 corresponding to the first electrode 140 in the second sub-pixel unit 120 is completely retained, and the planarization layer 210 corresponding to the first electrode 140 in the first sub-pixel unit 110 is partially retained, thereby achieving the purpose of making the thickness of the planarization layer 210 corresponding to the first electrode 140 in the second sub-pixel unit 120 greater than the thickness of the planarization layer 210 corresponding to the first electrode 140 in the first sub-pixel unit 110.

[0049] In one embodiment, one side of the planarization layer 210 is adjacent to the first electrode 140, and the other side of the planarization layer 210 is adjacent to the metal layer 220 in the array substrate. That is, the parasitic capacitance between the second sub-pixel unit 120 and the array substrate is generated between the first electrode 140 and the metal layer 220 in the array substrate.

[0050] In one embodiment, the metal layer 220 includes a source-drain electrode layer. Specifically, the parasitic capacitance between the second sub-pixel unit 120 and the array substrate is the parasitic capacitance between the first electrode 140 and the source-drain electrode layer in the second sub-pixel unit 120, and / or, the parasitic capacitance between the first sub-pixel unit 110 and the array substrate is the parasitic capacitance between the first electrode and the source-drain electrode layer in the first sub-pixel unit 110. That is, the metal layer 220 contacted by the planarization layer 210 is not unique, and it can be the first source-drain electrode layer in the array substrate, or it can be the second source-drain electrode layer in the array substrate. In addition, the metal layer 220 can also be other metal layers 220 in the array substrate, as long as it contacts the planarization layer 210, it can generate parasitic capacitance with the first electrode 140 on the other side of the planarization layer 210. Specifically, one of the first source-drain electrode layer and the second source-drain electrode layer is a source, and the other is a drain.

[0051] In one embodiment, the first sub-pixel unit 110 is a red sub-pixel unit, and the second sub-pixel unit 120 is a green sub-pixel unit. That is, in practical applications, due to the limitation of the FMM network, in the same pixel unit 100, the opening area of ​​the green sub-pixel unit is often larger than the opening area of ​​the red sub-pixel unit, which leads to the OLED capacitance of the green sub-pixel unit being larger than the OLED capacitance of the red sub-pixel unit, which leads to the different brightness of the green sub-pixel unit and the red sub-pixel unit, causing color deviation. Therefore, in this embodiment, the first sub-pixel unit 110 can be a red sub-pixel unit, and the second sub-pixel unit 120 can be a green sub-pixel unit.

[0052] In one embodiment, each of the pixel units 100 further includes a third sub-pixel unit 130. The luminous colors of the first sub-pixel unit 110, the luminous colors of the second sub-pixel unit 120, and the luminous colors of the third sub-pixel unit 130 are all different. In addition, in the present embodiment, in the same pixel unit 100, the number of the first sub-pixel unit 110, the second sub-pixel unit 120, and the third sub-pixel unit 130 may be one or more.

[0053] In one embodiment, the third sub-pixel unit 130 is a blue sub-pixel unit, that is, a pixel unit 100 may include a red sub-pixel unit, a green sub-pixel unit and a blue sub-pixel unit.

[0054] In one embodiment, the thickness of the planarization layer 210 corresponding to the first electrode 140 in the second sub-pixel unit 120 may be equal to the thickness of the planarization layer 210 corresponding to the first electrode 140 in the third sub-pixel unit 130. That is, the thickness of the planarization layer under the anode in the blue sub-pixel unit may be the same as the thickness of the planarization layer under the anode in the green sub-pixel unit.

[0055] Further, the thickness ratio of the planarization layer 210 corresponding to the first electrode 140 in the first sub-pixel unit 110, the planarization layer 210 corresponding to the first electrode 140 in the second sub-pixel unit 120, and the planarization layer 210 corresponding to the first electrode 140 in the third sub-pixel unit 130 is 1:1.5:1.5-1:2:2, and specifically can be 1:1.5:1.5, 1:1.6:1.6, 1:1.7:1.7, 1:1.8:1.8, 1:1.9:1.9 or 1:2:2. Specifically, the thickness ratio of the planarization layer under the anode in the red sub-pixel unit, the planarization layer under the anode in the green sub-pixel unit, and the planarization layer under the anode in the blue sub-pixel unit can be 1:1.5:1.5-1:2:2.

[0056] In one embodiment, a method for preparing a display panel is also provided. Figure 7 , including the following steps:

[0057] Step S100, forming an array substrate, wherein the array substrate includes a planarization layer 210;

[0058] Step S200, forming a plurality of pixel units on one side of the array substrate, wherein the pixel units at least include a first sub-pixel unit 110 and a second sub-pixel unit 120, wherein an opening area of ​​the second sub-pixel unit 120 is larger than an opening area of ​​the first sub-pixel unit 110;

[0059] In which, in the step of forming the array substrate, the planarization layer 210 is formed by using the HTM process so that the thickness of the planarization layer 210 corresponding to the first electrode 140 in the second sub-pixel unit 120 is greater than the thickness of the planarization layer 210 corresponding to the first electrode 140 in the first sub-pixel unit 110.

[0060] In this embodiment, by setting the thickness of the planarization layer 210 corresponding to the first electrode 140 in the second sub-pixel unit 120 to be greater than the thickness of the planarization layer 210 corresponding to the first electrode 140 in the first sub-pixel unit 110, the parasitic capacitance of the second sub-pixel unit 120 can be made smaller than the parasitic capacitance of the first sub-pixel unit 110. The difference between the OLED capacitance of the second sub-pixel unit 120 and the OLED capacitance of the first sub-pixel unit 110 can be reduced, and the difference between the OLED charging time of the second sub-pixel unit 120 and the OLED charging time of the first sub-pixel unit 110 can be reduced, that is, the difference between the light-on speed of the second sub-pixel unit 120 and the light-on speed of the first sub-pixel unit 110 can be reduced, and the difference between the light-emitting time of the second sub-pixel unit 120 and the light-emitting time of the first sub-pixel unit 110 can be reduced, that is, the difference between the brightness of the second sub-pixel unit 120 and the brightness of the first sub-pixel unit 110 can be reduced, so as to achieve the effect of improving the color shift problem.

[0061] Specifically, the planarization layer 210 can be prepared by the HTM process, so that the planarization layer 210 corresponding to the first electrode 140 in the second sub-pixel unit 120 is completely retained, and the planarization layer 210 corresponding to the first electrode 140 in the first sub-pixel unit 110 is partially retained, thereby achieving the purpose of making the thickness of the planarization layer 210 corresponding to the first electrode 140 in the second sub-pixel unit 120 greater than the thickness of the planarization layer 210 corresponding to the first electrode 140 in the first sub-pixel unit 110.

[0062] Figure 6 is a curve of current and charging time corresponding to each sub-pixel unit, Ioled_R is a curve corresponding to the first sub-pixel unit 110 after the planarization layer 210 is prepared by conventional process, Ioled_R' is a curve corresponding to the first sub-pixel unit 110 after the planarization layer 210 is prepared by HTM process, and Ioled_G is a curve corresponding to the second sub-pixel unit 120. Figure 6 It can be seen that, compared with the conventional process for preparing the planarization layer 210 , after the HTM process is used to prepare the planarization layer 210 , the difference between the charging time of the first sub-pixel unit 110 and the charging time of the second sub-pixel unit 120 is smaller.

[0063] In one embodiment, a display device is further provided, including the display panel provided in the above embodiment. For the specific structure of the display panel, please refer to the specific description in the above embodiment, which will not be repeated here. In this embodiment, the display device may include a mobile phone, a computer, a television, a monitor, a wearable device, etc., and this application does not specifically limit this.

[0064] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0065] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be construed as limiting the scope of the patent. It should be noted that, for a person of ordinary skill in the art, several modifications and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the attached claims.

Claims

1. A display panel, characterized in that: It includes an array substrate and a plurality of pixel units located on one side of the array substrate, each of the pixel units includes at least a first sub-pixel unit and a second sub-pixel unit, wherein an opening area of ​​the second sub-pixel unit is larger than an opening area of ​​the first sub-pixel unit; The parasitic capacitance between the second sub-pixel unit and the array substrate is smaller than the parasitic capacitance between the first sub-pixel unit and the array substrate.

2. The display panel according to claim 1, characterized in that: The array substrate comprises a planarization layer, and the thickness of the planarization layer corresponding to the first electrode in the second sub-pixel unit is greater than the thickness of the planarization layer corresponding to the first electrode in the first sub-pixel unit; Preferably, the first electrode comprises an anode.

3. The display panel according to claim 2, characterized in that: One side of the planarization layer is adjacent to the first electrode, and the other side of the planarization layer is adjacent to the metal layer in the array substrate.

4. The display panel according to claim 3, characterized in that: The metal layer includes a source-drain electrode layer.

5. The display panel according to claim 4, characterized in that: The parasitic capacitance between the second sub-pixel unit and the array substrate is the parasitic capacitance between the first electrode in the second sub-pixel unit and the source-drain electrode layer; and / or the parasitic capacitance between the first sub-pixel unit and the array substrate is the parasitic capacitance between the first electrode in the first sub-pixel unit and the source-drain electrode layer.

6. The display panel according to claim 1, characterized in that: The first sub-pixel unit is a red sub-pixel unit, and the second sub-pixel unit is a green sub-pixel unit; Preferably, each of the pixel units further includes a third sub-pixel unit; Preferably, the third sub-pixel unit is a blue light sub-pixel unit.

7. The display panel according to claim 6, characterized in that: The thickness of the planarization layer corresponding to the first electrode in the second sub-pixel unit is equal to the thickness of the planarization layer corresponding to the first electrode in the third sub-pixel unit.

8. The display panel according to claim 7, characterized in that: The thickness ratio of the planarization layer corresponding to the first electrode in the first sub-pixel unit, the planarization layer corresponding to the first electrode in the second sub-pixel unit, and the planarization layer corresponding to the first electrode in the third sub-pixel unit is 1:1.5:1.5-1:2:

2.

9. A method for preparing a display panel, characterized in that: include: forming an array substrate, wherein the array substrate comprises a planarization layer; A plurality of pixel units are formed on one side of the array substrate, the pixel units at least comprising a first sub-pixel unit and a second sub-pixel unit, wherein an opening area of ​​the second sub-pixel unit is larger than an opening area of ​​the first sub-pixel unit; In the step of forming the array substrate, the planarization layer is formed by using an HTM process so that the thickness of the planarization layer corresponding to the first electrode in the second sub-pixel unit is greater than the thickness of the planarization layer corresponding to the first electrode in the first sub-pixel unit.

10. A display device, characterized in that: A display panel comprising the display panel according to claims 1-8 or a display panel prepared by the method for preparing a display panel according to claim 9.

Images