Memory control method and memory storage device

Abstract

The invention provides a memory control method and a memory storage device, which can keep the stability of writing speed. The memory control method is used for a rewritable nonvolatile memory module. The rewritable nonvolatile memory module comprises a plurality of entity units. The memory control method comprises the following steps: selecting a plurality of target entity units from a plurality of entity units, wherein the plurality of target entity units comprise a first number of first target entity units and a second number of second target entity units; when a first write operation in the continuous write operations is executed, the write mode of a second write operation is determined according to the switching condition, the second write operation is the next write operation of the first write operation, and the write modes comprise the first write mode and the second write mode, the first target entity unit corresponds to a first write-in mode, the second target entity unit corresponds to a second write-in mode, and the first write-in mode is different from the second write-in mode.

Description

Technical Field

[0001] The present invention relates to the field of storage technology, and in particular to a memory control method and a memory storage device. Background Art

[0002] Smart phones, tablet computers and personal computers have grown rapidly in the past few years, resulting in a rapid increase in consumer demand for storage media. Rewritable non-volatile memory modules (e.g., flash memory) are very suitable for being built into the various portable multimedia devices listed above because they are non-volatile, power-saving, small in size, and have no mechanical structure.

[0003] In the field of storage technology, a fixed write mode is often used to perform continuous write operations, which results in large changes in the write speed. Therefore, how to maintain the stability of the data write speed is a key research topic for those skilled in the art. Summary of the invention

[0004] An exemplary embodiment of the present invention provides a memory control method and a memory storage device, which can maintain the stability of the writing speed.

[0005] An exemplary embodiment of the present invention provides a memory control method for a rewritable non-volatile memory module. The rewritable non-volatile memory module includes a plurality of physical units. The memory control method includes: selecting a plurality of target physical units from the plurality of physical units, wherein the plurality of target physical units include a first number of first target physical units and a second number of second target physical units; when performing a first write operation in a continuous write operation, determining a write mode of the second write operation according to a switching condition, wherein the second write operation is the next write operation of the first write operation, wherein the write mode includes a first write mode and a second write mode, the first target physical unit corresponds to the first write mode, the second target physical unit corresponds to the second write mode, and the first write mode is different from the second write mode.

[0006] In an exemplary embodiment of the present invention, the memory control method further includes: before executing the continuous write operation, obtaining a first write speed, a second write speed and a target write speed corresponding to the continuous write operation; and calculating a first ratio according to the target write speed, the first write speed and the second write speed.

[0007] In an exemplary embodiment of the present invention, the first writing speed is a writing speed required to complete the continuous writing operation in the first writing mode, and the second writing speed is a writing speed required to complete the continuous writing operation in the second writing mode.

[0008] In an exemplary embodiment of the present invention, the step of determining the write mode of the second write operation according to the switching condition includes: obtaining a first data amount of the first target physical unit and a second data amount of the second target physical unit; calculating a second ratio according to the first data amount and the second data amount; and determining the write mode of the second write operation according to the first ratio and the second ratio.

[0009] In an exemplary embodiment of the present invention, the first data amount is the amount of data written into the first target physical unit, and the second data amount is the amount of data written into the second target physical unit.

[0010] In an exemplary embodiment of the present invention, the multiple target physical units respectively have multiple logical-to-physical information, and the multiple logical-to-physical information are respectively used to record the writing order of the multiple target physical units and the mapping relationship between the physical addresses and logical addresses of the multiple target physical units.

[0011] In an exemplary embodiment of the present invention, after the second target physical unit is full, the first target physical unit is no longer used to store data.

[0012] In an exemplary embodiment of the present invention, the memory control method further includes: if the logical address is mapped to multiple physical addresses of the multiple target physical units, querying the latest physical address among the multiple physical addresses according to the writing order of the multiple target physical units in the multiple logical-to-physical information.

[0013] In an exemplary embodiment of the present invention, the memory control method further includes: in the process of executing the continuous write operation, establishing a first switching schedule and a second switching schedule, wherein the first switching schedule is used to record the physical address and timestamp corresponding to the latest data stored in the second target physical unit when switching from the second write mode to the first write mode, and the second switching schedule is used to record the physical address and timestamp corresponding to the latest data stored in the first target physical unit when switching from the first write mode to the second write mode.

[0014] In an exemplary embodiment of the present invention, the memory control method further includes: if the logical address is mapped to multiple physical addresses of the multiple target physical units, querying the multiple physical addresses from the multiple logical-to-physical information; querying multiple timestamps corresponding to the multiple physical addresses from at least one of the first switching schedule and the second switching schedule; and determining the latest physical address among the multiple physical addresses based on the multiple timestamps.

[0015] An exemplary embodiment of the present invention further provides a memory storage device, which includes a connection interface unit, a rewritable non-volatile memory module and a memory control circuit unit. The memory control circuit unit is coupled to the connection interface unit and the rewritable non-volatile memory module. The connection interface unit is used to couple to a host system. The rewritable non-volatile memory module includes a plurality of physical units. The memory control circuit unit is used to select a plurality of target physical units from the plurality of physical units, wherein the plurality of target physical units include a first number of first target physical units and a second number of second target physical units. When performing a first write operation in a continuous write operation, the memory control circuit unit is also used to determine a write mode of a second write operation according to a switching condition, wherein the second write operation is the next write operation of the first write operation, wherein the write mode includes a first write mode and a second write mode, the first target physical unit corresponds to the first write mode, the second target physical unit corresponds to the second write mode, and the first write mode is different from the second write mode.

[0016] In an exemplary embodiment of the present invention, before performing the continuous write operation, the memory control circuit unit is also used to obtain a first write speed, a second write speed and a target write speed corresponding to the continuous write operation, and calculate a first ratio based on the target write speed, the first write speed and the second write speed.

[0017] In an exemplary embodiment of the present invention, the memory control circuit unit is further used to obtain a first data amount of the first target physical unit and a second data amount of the second target physical unit. The memory control circuit unit is further used to calculate a second ratio according to the first data amount and the second data amount. The memory control circuit unit is further used to determine a write mode of the second write operation according to the first ratio and the second ratio.

[0018] In an exemplary embodiment of the present invention, if the logical address is mapped to multiple physical addresses of the multiple target physical units, the memory control circuit unit is also used to query the latest physical address among the multiple physical addresses according to the writing order of the multiple target physical units in the multiple logical-to-physical information.

[0019] In an exemplary embodiment of the present invention, during the execution of the continuous write operation, the memory control circuit unit is also used to establish a first switching schedule and a second switching schedule, wherein the first switching schedule is used to record the physical address and timestamp corresponding to the latest data stored in the second target physical unit when switching from the second write mode to the first write mode, and the second switching schedule is used to record the physical address and timestamp corresponding to the latest data stored in the first target physical unit when switching from the first write mode to the second write mode.

[0020] In an exemplary embodiment of the present invention, if the logical address is mapped to the multiple physical addresses of the multiple target physical units, the memory control circuit unit is further configured to query the multiple physical addresses from the multiple logical-to-physical information. The memory control circuit unit is further configured to query multiple timestamps corresponding to the multiple physical addresses from at least one of the first switching schedule and the second switching schedule. The memory control circuit unit is further configured to determine the latest physical address among the multiple physical addresses according to the multiple timestamps.

[0021] Based on the above, the present invention provides a memory control method and a memory storage device, which can realize write speed control within a small data amount (i.e., the write data amount corresponding to the continuous write operation) by performing continuous write operations on multiple target physical units and switching the write mode of the continuous write operation in a timely manner to improve the stability of the write speed.

[0022] In order to make the above features and advantages of the present invention more clearly understood, embodiments are given below with reference to the accompanying drawings for detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 is a schematic diagram of a host system, a memory storage device, and an input / output (I / O) device according to an exemplary embodiment of the present invention;

[0024] Figure 2 is a schematic diagram of a host system, a memory storage device, and an I / O device according to an exemplary embodiment of the present invention;

[0025] Figure 3is a schematic diagram of a host system and a memory storage device according to an exemplary embodiment of the present invention;

[0026] Figure 4 is a schematic diagram of a memory storage device according to an exemplary embodiment of the present invention;

[0027] Figure 5 is a schematic diagram of a memory control circuit unit according to an exemplary embodiment of the present invention;

[0028] Figure 6 is a flow chart of a memory control method according to an exemplary embodiment of the present invention;

[0029] Figure 7 is a schematic diagram of a first open pool and a second open pool according to an exemplary embodiment of the present invention;

[0030] Figure 8 is a schematic diagram showing logic-to-physical information according to an exemplary embodiment of the present invention;

[0031] Fig. 9 is a schematic diagram of a first switching schedule and a second switching schedule according to an exemplary embodiment of the present invention;

[0032] Fig.10 is a flow chart of a memory control method according to an exemplary embodiment of the present invention. DETAILED DESCRIPTION

[0033] Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0034] Generally speaking, a memory storage device (also known as a memory storage system) includes a rewritable non-volatile memory module and a controller (also known as a control circuit). The memory storage device can be used together with a host system so that the host system can write data to the memory storage device or read data from the memory storage device.

[0035] Figure 1 is a schematic diagram of a host system, a memory storage device, and an input / output (I / O) device according to an exemplary embodiment of the present invention. Figure 2 is a schematic diagram of a host system, a memory storage device, and an I / O device according to an exemplary embodiment of the present invention.

[0036] Please refer to Figure 1 and Figure 2The host system 11 may include a processor 111, a random access memory (RAM) 112, a read only memory (ROM) 113, and a data transmission interface 114. The processor 111, the random access memory 112, the read only memory 113, and the data transmission interface 114 may be coupled to a system bus 110.

[0037] In an exemplary embodiment, the host system 11 may be coupled to the memory storage device 10 via the data transmission interface 114. For example, the host system 11 may store data to the memory storage device 10 or read data from the memory storage device 10 via the data transmission interface 114. In addition, the host system 11 may be coupled to the I / O device 12 via the system bus 110. For example, the host system 11 may transmit an output signal to the I / O device 12 or receive an input signal from the I / O device 12 via the system bus 110.

[0038] In an exemplary embodiment, the processor 111, the random access memory 112, the read-only memory 113 and the data transmission interface 114 may be disposed on the motherboard 20 of the host system 11. The number of the data transmission interface 114 may be one or more. Through the data transmission interface 114, the motherboard 20 may be coupled to the memory storage device 10 via a wired or wireless manner.

[0039] In an exemplary embodiment, the memory storage device 10 may be, for example, a flash drive 201, a memory card 202, a solid state drive (SSD) 203, or a wireless memory storage device 204. The wireless memory storage device 204 may be, for example, a near field communication (NFC) memory storage device, a wireless fax (WiFi) memory storage device, a Bluetooth memory storage device, or a low power Bluetooth memory storage device (e.g., iBeacon) or other memory storage devices based on various wireless communication technologies. In addition, the motherboard 20 may also be coupled to various I / O devices such as a global positioning system (GPS) module 205, a network interface card 206, a wireless transmission device 207, a keyboard 208, a screen 209, a speaker 210, etc. through the system bus 110. For example, in an exemplary embodiment, the motherboard 20 may access the wireless memory storage device 204 through the wireless transmission device 207.

[0040] In one exemplary embodiment, the host system 11 is a computer system. In one exemplary embodiment, the host system 11 can be any system that can substantially cooperate with the memory storage device to store data. In one exemplary embodiment, the host system 11 is a vehicle-mounted system. In one exemplary embodiment, the memory storage device 10 and the host system 11 can respectively include Figure 3 A memory storage device 30 and a host system 31.

[0041] Figure 3 is a schematic diagram of a host system and a memory storage device according to an exemplary embodiment of the present invention.

[0042] Please refer to Figure 3 , the memory storage device 30 can be used in conjunction with a host system 31 to store data. For example, the host system 31 can be a system such as a digital camera, a video camera, a communication device, an audio player, a video player, or a tablet computer. For example, the memory storage device 30 can be various non-volatile memory storage devices such as a Secure Digital (SD) card 32, a Compact Flash (CF) card 33, or an embedded storage device 34 used by the host system 31. The embedded storage device 34 includes various types of embedded storage devices that directly couple the memory module to the substrate of the host system, such as an embedded Multi Media Card (eMMC) 341 and / or an embedded Multi Chip Package (eMCP) storage device 342.

[0043] Figure 4 is a schematic diagram of a memory storage device according to an exemplary embodiment of the present invention.

[0044] Please refer to Figure 4 The memory storage device 10 includes a connection interface unit 41 , a memory control circuit unit 42 and a rewritable non-volatile memory module 43 .

[0045] The connection interface unit 41 is used to couple the memory storage device 10 to the host system 11. The memory storage device 10 can communicate with the host system 11 via the connection interface unit 41. In an exemplary embodiment, the connection interface unit 41 is compatible with the Peripheral Component Interconnect Express (PCI Express) standard. In an exemplary embodiment, the connection interface unit 41 may also comply with the Serial Advanced Technology Attachment (SATA) standard, the Parallel Advanced Technology Attachment (PATA) standard, the Institute of Electrical and Electronic Engineers (IEEE) 1394 standard, the Universal Serial Bus (USB) standard, the SD interface standard, the Ultra High Speed-I (UHS-I) interface standard, the Ultra High Speed-II (UHS-II) interface standard, the Memory Stick (MS) interface standard, the MCP interface standard, the MMC interface standard, the eMMC interface standard, the Universal Flash Storage (UFS) interface standard, the eMCP interface standard, the CF interface standard, the Integrated Device Electronics (IDE) standard or other suitable standards. The connection interface unit 41 and the memory control circuit unit 42 may be packaged in one chip, or the connection interface unit 41 may be disposed outside a chip including the memory control circuit unit 42 .

[0046] The memory control circuit unit 42 is coupled to the connection interface unit 41 and the rewritable non-volatile memory module 43. The memory control circuit unit 42 is used to execute a plurality of logic gates or control instructions implemented in hardware or firmware and to perform operations such as writing, reading and erasing data in the rewritable non-volatile memory module 43 according to the instructions of the host system 11.

[0047] The rewritable non-volatile memory module 43 is used to store data written by the host system 11. The rewritable non-volatile memory module 43 may include a single-level cell (SLC) NAND flash memory module (i.e., a flash memory module that can store 1 bit in one storage cell), a multi-level cell (MLC) NAND flash memory module (i.e., a flash memory module that can store 2 bits in one storage cell), a triple-level cell (TLC) NAND flash memory module (i.e., a flash memory module that can store 3 bits in one storage cell), a quad-level cell (QLC) NAND flash memory module (i.e., a flash memory module that can store 4 bits in one storage cell), other flash memory modules, or other memory modules with the same characteristics.

[0048] Each memory cell in the rewritable non-volatile memory module 43 stores one or more bits by changing the voltage (hereinafter also referred to as the critical voltage). Specifically, there is a charge capture layer between the control gate and the channel of each memory cell. By applying a write voltage to the control gate, the amount of electrons in the charge capture layer can be changed, thereby changing the critical voltage of the memory cell. This operation of changing the critical voltage of the memory cell is also called "writing data to the memory cell" or "programming the memory cell". As the critical voltage changes, each memory cell in the rewritable non-volatile memory module 43 has multiple storage states. By applying a read voltage, it is possible to determine which storage state a memory cell belongs to, thereby obtaining one or more bits stored in this memory cell.

[0049] In an exemplary embodiment, the memory cells of the rewritable non-volatile memory module 43 may constitute a plurality of physical programming cells, and these physical programming cells may constitute a plurality of physical cells. Specifically, the memory cells on the same word line may constitute one or more physical programming cells. If each memory cell can store more than 2 bits, the physical programming cells on the same word line may be classified into at least a lower physical programming cell and an upper physical programming cell. For example, the least significant bit (LSB) of a memory cell belongs to the lower physical programming cell, and the most significant bit (MSB) of a memory cell belongs to the upper physical programming cell. Generally speaking, in an MLC NAND flash memory, the write speed of the lower physical programming cell is greater than the write speed of the upper physical programming cell, and / or the reliability of the lower physical programming cell is higher than the reliability of the upper physical programming cell.

[0050] In one exemplary embodiment, the physical programming unit is the smallest unit of programming. That is, the physical programming unit is the smallest unit for writing data. For example, the physical programming unit may be a physical page or a physical sector. If the physical programming unit is a physical page, these physical programming units may include a data bit area and a redundancy bit area. The data bit area includes a plurality of physical sectors for storing user data, and the redundancy bit area is used to store system data (for example, management data such as error correction codes). In this exemplary embodiment, the data bit area includes 32 physical sectors, and the size of a physical sector is 512 bytes (byte, B). However, in other exemplary embodiments, the data bit area may also include 8, 16 or more or less physical sectors, and the size of each physical sector may also be larger or smaller. On the other hand, the physical unit is the smallest unit of erasure. That is, each physical unit contains the minimum number of storage cells that are erased together. For example, the physical unit is a physical block.

[0051] Figure 5 FIG. 4 is a schematic diagram of a memory control circuit unit according to an exemplary embodiment of the present invention.

[0052] Please refer to Figure 5 The memory control circuit unit 42 includes a memory management circuit 51 , a host interface 52 and a memory interface 53 .

[0053] The memory management circuit 51 is used to control the overall operation of the memory control circuit unit 42. Specifically, the memory management circuit 51 has a plurality of control instructions, and when the memory storage device 10 operates, these control instructions are executed to perform operations such as writing, reading and erasing data. The following description of the operation of the memory management circuit 51 is equivalent to the description of the operation of the memory control circuit unit 42.

[0054] In an exemplary embodiment, the control instructions of the memory management circuit 51 are implemented in the form of firmware. For example, the memory management circuit 51 has a microprocessor unit (not shown) and a read-only memory (not shown), and these control instructions are recorded in the read-only memory. When the memory storage device 10 is operating, these control instructions are executed by the microprocessor unit to perform operations such as writing, reading and erasing data.

[0055] In an exemplary embodiment, the control instructions of the memory management circuit 51 can also be stored in a specific area of ​​the rewritable non-volatile memory module 43 (for example, a system area in the memory module dedicated to storing system data) in the form of code. In addition, the memory management circuit 51 has a microprocessor unit (not shown), a read-only memory (not shown) and a random access memory (not shown). In particular, the read-only memory has a boot code, and when the memory control circuit unit 42 is enabled, the microprocessor unit will first execute the boot code to load the control instructions stored in the rewritable non-volatile memory module 43 into the random access memory of the memory management circuit 51. Afterwards, the microprocessor unit will run these control instructions to perform operations such as writing, reading and erasing data.

[0056] In an exemplary embodiment, the control instructions of the memory management circuit 51 can also be implemented in a hardware form. For example, the memory management circuit 51 includes a microcontroller, a storage unit management circuit, a memory write circuit, a memory read circuit, a memory erase circuit and a data processing circuit. The storage unit management circuit, the memory write circuit, the memory read circuit, the memory erase circuit and the data processing circuit are coupled to the microcontroller. The storage unit management circuit is used to manage the storage unit or storage unit group of the rewritable non-volatile memory module 43. The memory write circuit is used to issue a write instruction sequence to the rewritable non-volatile memory module 43 to write data into the rewritable non-volatile memory module 43. The memory read circuit is used to issue a read instruction sequence to the rewritable non-volatile memory module 43 to read data from the rewritable non-volatile memory module 43. The memory erase circuit is used to issue an erase instruction sequence to the rewritable non-volatile memory module 43 to erase data from the rewritable non-volatile memory module 43. The data processing circuit is used to process data to be written to the rewritable non-volatile memory module 43 and data to be read from the rewritable non-volatile memory module 43. The write command sequence, the read command sequence and the erase command sequence may each include one or more codes or instruction codes and are used to instruct the rewritable non-volatile memory module 43 to perform corresponding write, read and erase operations. In an exemplary embodiment, the memory management circuit 51 may also issue other types of command sequences to the rewritable non-volatile memory module 43 to instruct the execution of corresponding operations.

[0057] The host interface 52 is coupled to the memory management circuit 51. The memory management circuit 51 can communicate with the host system 11 through the host interface 52. The host interface 52 can be used to receive and identify instructions and data transmitted by the host system 11. For example, the instructions and data transmitted by the host system 11 can be transmitted to the memory management circuit 51 through the host interface 52. In addition, the memory management circuit 51 can transmit data to the host system 11 through the host interface 52. In this exemplary embodiment, the host interface 52 is compatible with the PCI Express standard. However, it should be understood that the present invention is not limited to this, and the host interface 52 can also be compatible with the SATA standard, the PATA standard, the IEEE 1394 standard, the USB standard, the SD standard, the UHS-I standard, the UHS-II standard, the MS standard, the MMC standard, the eMMC standard, the UFS standard, the CF standard, the IDE standard or other suitable data transmission standards.

[0058] The memory interface 53 is coupled to the memory management circuit 51 and is used to access the rewritable non-volatile memory module 43. For example, the memory management circuit 51 can access the rewritable non-volatile memory module 43 through the memory interface 53. That is, the data to be written to the rewritable non-volatile memory module 43 will be converted into a format acceptable to the rewritable non-volatile memory module 43 through the memory interface 53. Specifically, if the memory management circuit 51 wants to access the rewritable non-volatile memory module 43, the memory interface 53 will transmit a corresponding command sequence. For example, these command sequences may include a write command sequence indicating writing data, a read command sequence indicating reading data, an erase command sequence indicating erasing data, and corresponding command sequences for indicating various memory operations (for example, changing a read voltage level or performing a garbage collection operation, etc.). These command sequences are, for example, generated by the memory management circuit 51 and transmitted to the rewritable non-volatile memory module 43 through the memory interface 53. These command sequences may include one or more signals, or data on a bus. These signals or data may include instruction codes or codes. For example, in a read instruction sequence, information such as a read identification code, a memory address, etc. may be included.

[0059] In an exemplary embodiment, the memory control circuit unit 42 further includes an error checking and correction circuit 54 , a buffer memory 55 , and a power management circuit 56 .

[0060] The error checking and correction circuit 54 is coupled to the memory management circuit 51 and is used to perform error checking and correction operations to ensure the correctness of data. Specifically, when the memory management circuit 51 receives a write command from the host system 11, the error checking and correction circuit 54 generates a corresponding error correcting code (ECC) and / or error detecting code (EDC) for the data corresponding to the write command, and the memory management circuit 51 writes the data corresponding to the write command and the corresponding error correcting code and / or error detecting code into the rewritable non-volatile memory module 43. Afterwards, when the memory management circuit 51 reads data from the rewritable non-volatile memory module 43, the error correcting code and / or error detecting code corresponding to the data will be read at the same time, and the error checking and correction circuit 54 will perform error checking and correction operations on the read data according to the error correcting code and / or error detecting code.

[0061] The buffer memory 55 is coupled to the memory management circuit 51 and used for temporarily storing data. The power management circuit 56 is coupled to the memory management circuit 51 and used for controlling the power of the memory storage device 10 .

[0062] In an exemplary embodiment, Figure 4 The rewritable non-volatile memory module 43 may include a flash memory module. In an exemplary embodiment, Figure 4 The memory control circuit unit 42 may include a flash memory controller. In an exemplary embodiment, Figure 5 The memory management circuit 51 may include a flash memory management circuit.

[0063] Most of the current memory storage devices 10 use a single open block as a unit to manage the storage space of the rewritable non-volatile memory module 43. However, this open block is single and fixed, for example, it is written based on a single-level cell (SLC) write mode, or it is written based on a triple-level cell (TLC) write mode. The method of using a single open block as a unit to manage the storage space is difficult to meet the needs of continuous write operations, thereby affecting the write speed.

[0064] In view of this, the present invention provides a memory management method, which can use multiple target physical units as units to manage the storage space of a rewritable non-volatile memory module 43, and in the process of executing continuous write operations, timely switch the write mode of the continuous write operation, thereby realizing write speed control within a small data amount (that is, the write data amount corresponding to the continuous write operation) to improve the stability of the write speed.

[0065] Figure 6 is a flow chart of a memory control method according to an exemplary embodiment of the present invention; Figure 7 is a schematic diagram of a first open pool and a second open pool according to an exemplary embodiment of the present invention. Figure 6 to Figure 7 .

[0066] In step S601, the memory management circuit 51 may select a plurality of target physical units OB11-OB13, OB21 from a plurality of physical units. In an exemplary embodiment, the target physical units OB11-OB13, OB21 are respectively a physical erase unit (eg, a physical block).

[0067] In an exemplary embodiment, if Figure 7As shown, the plurality of target physical units OB11-OB13, OB21 include a first number (for example, 3) of first target physical units OB11-OB13 and a second number (for example, 1) of second target physical units OB21. The first target physical units OB11-OB13 correspond to a first write mode, for example, the first target physical units OB11-OB13 can be written based on a single-level cell (SLC) write mode. The second target physical unit OB21 corresponds to a second write mode, for example, the second target physical unit OB21 can be written based on a second-level cell (MLC) write mode, a third-level cell (TLC) write mode, or a fourth-level cell (QLC) write mode. The first write mode is different from the second write mode. The first target physical units OB11-OB13 are associated with a first open pool P1. The second target physical unit OB21 is associated with a second open pool P2. That is to say, the memory management circuit 51 can manage the storage space of the rewritable non-volatile memory module 43 by using three first target physical units OB11 ˜ OB13 and one second target physical unit OB21 as units.

[0068] In step S602 , the memory management circuit 51 may obtain a first writing speed, a second writing speed, and a target writing speed corresponding to a continuous writing operation.

[0069] In an exemplary embodiment, the memory management circuit 51 may determine the first write speed, the second write speed, and the target write speed, for example, based on historical write data, user usage habits, and / or the performance of the memory storage device 10. Specifically, the first write speed is the write speed required to complete the continuous write operation in the first write mode (for example, the SLC write mode), and the second write speed is the write speed required to complete the continuous write operation in the second write mode (for example, the TLC write mode).

[0070] To further illustrate, the memory management circuit 51 may, for example, calculate the average write speed required for the memory storage device 10 to complete continuous write operations using only a single target physical unit based on historical write data, user usage habits and / or the performance of the memory storage device 10. For example, the average write speed required to complete continuous write operations using only a single target physical unit corresponding to the SLC write mode is the first write speed. For example, the average write speed required to complete continuous write operations using only a single target physical unit corresponding to the TLC write mode is the second write speed. Accordingly, the memory management circuit 51 may establish the target write speed required to complete continuous write operations using multiple target physical units corresponding to different write modes based on the first write speed and the second write speed. Alternatively, the target write speed may also be designed by the user according to needs, and the present invention is not limited thereto.

[0071] In step S603 , the memory management circuit 51 may calculate a first ratio according to the target writing speed, the first writing speed, and the second writing speed.

[0072] In an exemplary embodiment, since the write operations corresponding to different write modes have different write speeds, there is a problem of unstable write speed when performing continuous write operations. In the process of performing continuous write operations, in order to achieve the effect of having the same write speed (that is, the target write speed) in different write modes, the memory management circuit 51 can calculate a first ratio according to the first write speed, the second write speed and the target write speed as a basis for switching the operation mode. The first ratio can be obtained by formula (1) and formula (2).

[0073] Formula (1):

[0074]

[0075] Formula (2):

[0076]

[0077] Wherein, X represents the data volume (capacity of a physical page) in a single-level cell (SLC) mode; and Y represents the data volume (capacity of a physical page) in a triple-level cell (TLC) mode.

[0078] In an exemplary embodiment, during the execution of a continuous write operation, the memory management circuit 51 may first write write data to the target physical unit OB21 based on the TLC write mode, and after the memory management circuit 51 writes write data with a data amount of Y in the target physical unit OB21, the write mode is switched to the SLC write mode. Afterwards, after the memory management circuit 51 writes write data with a data amount of X in the target physical unit OB11 (or the target physical unit OB12, the target physical unit OB13), the write mode is switched to the TLC write mode, and this is repeated until the continuous write operation is completed. In this way, the memory management circuit 51 can maintain the write speed of the continuous write operation at the target write speed by using multiple target physical units OB11~OB13, OB21 to ensure the stability of the write speed.

[0079] For example, assume that the rewritable non-volatile memory module 43 is a triple level cell (TLC) NAND flash memory module, and the rewritable non-volatile memory module 43 has 4 physical planes, and the rewritable non-volatile memory module 43 has 4000 physical pages. If the target write speed corresponding to the continuous write operation is 200MB / s, the first write speed is 250MB / s, and the second write speed is 100MB / s, the first ratio can be derived as 5 by substituting into formula (1) and formula (2). It should be noted that the minimum write unit of the TLC NAND flash memory is 3 physical pages. The 3 physical pages are respectively a lower physical page, a middle physical page, and an upper physical page. The capacity of a physical page can be, for example, 16KB, so the minimum write amount is 16*3=48KB. Since the rewritable non-volatile memory module 43 has 4 physical planes, the total write amount is 48*4=192KB.

[0080] That is to say, in the process of performing a continuous write operation, the memory management circuit 51 may first write the write data to the first 3 physical pages in the target physical unit OB21 based on the TLC write mode, and then switch to the SLC write mode to write the write data to the first 3*5=15 physical pages in the target physical unit OB11 (or the target physical unit OB12, the target physical unit OB13), and then switch the write mode to the TLC write mode, and repeat this process until the continuous write operation is completed, so as to maintain the write speed of the continuous write operation at the target write speed (i.e., 200MB / s).

[0081] To further explain, in order to maintain the write speed of the continuous write operation above the target write speed (i.e., 200MB / s), the memory management circuit 51 may switch to the TLC write mode to write 192KB of data after writing 192*5=960KB of data in the SLC write mode, and then switch back to the SLC write mode, and repeat this process until the continuous write operation is completed. Accordingly, the amount of data corresponding to a complete write cycle is 192+960=1152KB. In other words, the amount of data (chunk size) corresponding to a complete write cycle is approximately equal to 1MB (i.e., 1024KB). Therefore, the memory control method of the present invention can evenly and stably control the write speed of the amount of data corresponding to a complete write cycle at 200MB / s.

[0082] If the writing speed is controlled in the traditional way by taking the data amount of a physical unit (for example, an open block) as the unit, there will be a problem that the writing speed fluctuates greatly due to multiple switching of physical erasing units in different modes.

[0083] It should be noted that in a conventional 2D NAND flash memory, a physical block includes, for example, 32 to 128 physical pages, wherein the capacity of each physical page is, for example, 4096B to 8192B. With respect to a 3D NAND flash memory, the size (capacity) of the physical block may be different due to the different structures. Specifically, the capacity of a physical block of a 3D NAND flash memory can reach 16MB. Accordingly, whether the capacity of a physical block in a 2D NAND flash memory or the capacity of a physical block in a 3D NAND flash memory, will be greater than the data volume of a complete write cycle (chunk size, i.e., 1MB) as described above.

[0084] According to the above, the method of controlling the write speed in units of chunk size provided by the exemplary embodiment of the present invention helps to improve the write efficiency and reduce write amplification. At the same time, the write speed is controlled at the target write speed (200MB / s) to alternately write data to the first target physical unit and the second target physical unit, which can balance the write load, thereby improving the performance of the memory storage device 10. In addition, the method of alternately writing data to the first target physical unit and the second target physical unit also helps to achieve a more uniform wear distribution, avoid excessive wear of specific physical units, and thus improve the reliability and durability of the memory storage device 10.

[0085] In step S604 , the memory management circuit 51 may obtain the first data volume of the first target physical units OB11 ˜ OB13 and the second data volume of the second target physical unit OB21 when performing the first write operation of the consecutive write operations.

[0086] In an exemplary embodiment, during the execution of the continuous write operation, the memory management circuit 51 sequentially executes multiple write operations. In other words, the continuous write operation includes multiple write operations. When the memory management circuit 51 executes the first write operation (i.e., the current write operation) in the continuous write operation, the memory management circuit 51 can determine the write mode of the next write operation (i.e., the second write operation) according to the switching condition (i.e., the first ratio mentioned above) so that the write speed of the continuous write operation is maintained at the target write speed.

[0087] Assume that the first write operation is the first write operation in the continuous write operation. During the first write operation, the memory management circuit 51 may first write the write data corresponding to the first write operation in the continuous write operation into the first three physical pages of the target physical unit OB21 based on the TLC write mode, and obtain the first data amount of the first target physical unit OB11-OB13 and the second data amount of the second target physical unit OB21. The first data amount is the amount of data written into the first target physical unit OB11-OB13, and the second data amount is the amount of data written into the second target physical unit OB21. At this time, the first data amount of the first target physical unit OB11-OB13 is the capacity of 0 physical pages, and the second data amount of the second target physical unit OB21 is the capacity of 3 physical pages.

[0088] In step S605 , the memory management circuit 51 may calculate a second ratio according to the first data amount and the second data amount.

[0089] In an exemplary embodiment, the second ratio may be, for example, a ratio of the first data volume to the second data volume. For example, in the first write operation described above, the second ratio is a ratio of the capacity of 0 physical pages to the capacity of 3 physical pages, that is, 0.

[0090] In step S606 , the memory management circuit 51 may determine a writing mode of the second writing operation according to the first ratio and the second ratio.

[0091] In an exemplary embodiment, assuming that the first ratio is 1, since in the process of performing a continuous write operation, the memory management circuit 51 needs to write the write data to the target physical units OB11-OB13 and OB21 according to the first ratio in order to maintain the stability of the write speed. Therefore, after writing the write data to the three physical pages in the target physical unit OB21 in the TLC write mode, the memory management circuit 51 needs to change to the SLC write mode to write the write data to the three physical pages of the target physical units OB11-OB13 before switching back to the TLC write mode, and repeat this until the continuous write operation is completed. Accordingly, in the process of performing a continuous write operation, the memory management circuit 51 can determine the write mode of the second write operation by comparing the size of the second ratio with the first ratio.

[0092] Specifically, the second ratio is the ratio of the amount of data written to the target physical units OB11 to OB13 to the amount of data written to the target physical unit OB21. If the second ratio corresponding to the current write operation is less than the first ratio, it means that the next write operation needs to be performed based on the SLC write mode to maintain the stability of the write speed. Conversely, if the second ratio corresponding to the current write operation is not less than the first ratio, it means that the next write operation needs to be performed based on the TLC write mode to maintain the stability of the write speed.

[0093] During the first write operation, the second ratio is 0. Since the second ratio is smaller than the first ratio (ie, 1), the memory management circuit 51 changes to the SLC write mode to perform the next write operation (ie, the second write operation in the continuous write operation).

[0094] According to the above, during the execution of a write operation in a continuous write operation (i.e., the current write operation), the memory management circuit 51 can determine the write mode of the next write operation based on the first ratio derived from the target write speed and the second ratio used to reflect the written data of the target physical units OB11~OB13, OB21, so as to switch the write mode of the continuous write operation in a timely manner during the execution of the continuous write operation, thereby realizing write speed control within a small amount of data and improving the stability of the write speed.

[0095] On the other hand, since the present invention uses a plurality of target physical units OB11-OB13, OB21 corresponding to different write modes to store the write data of the continuous write operation, that is, the present invention uses a plurality of target physical units OB11-OB13, OB21 as units to manage the storage space of the rewritable non-volatile memory module 43. For this, the memory management circuit 51 needs to establish mapping information and / or a record table to manage the target physical units OB11-OB13, OB21.

[0096] Figure 8 is a schematic diagram showing the logic-to-physical information according to an exemplary embodiment of the present invention. Figure 8 In an exemplary embodiment, the memory management circuit 51 may establish respective logical-to-physical information T11-T13, T21 for the target physical units OB11-OB13, OB21. That is, the target physical units OB11-OB13, OB21 have respective logical-to-physical information T11-T13, T21. Specifically, the logical-to-physical information T11-T13, T21 is used to record the writing order of the target physical units OB11-OB13, OB21 and the mapping relationship between the physical addresses and logical addresses of the target physical units OB11-OB13, OB21.

[0097] like Figure 8 As shown, the memory storage device 10 has four physical planes pl0-pl3, the target physical units OB11-OB13 have 1000 physical pages respectively, and the target physical unit OB21 has 3000 physical pages respectively. The numbers in the logic-to-physical information T11-T13 and T21 indicate the order in which the physical pages in the target physical units OB11-OB13 are written during the continuous operation. In other words, the smaller the number, the older the data stored in the corresponding physical page.

[0098] In an exemplary embodiment, the first ratio is 1. In the process of performing the continuous write operation, the memory management circuit 51 may first write the write data corresponding to the first write operation in the continuous write operation into the physical pages p0-p2 of the target physical unit OB21 based on the TLC write mode, and record the mapping relationship between the physical addresses of the physical pages p0-p2 of the target physical unit OB21 and their corresponding logical addresses in the logical-to-physical information T21, and mark the physical pages p0-p2 as number 0 in the logical-to-physical information T21.

[0099] Next, the memory management circuit 51 can switch to the SLC write mode to sequentially write the write data corresponding to the second write operation in the continuous write operation into the physical page p0 of the target physical unit OB11, write the write data corresponding to the third write operation in the continuous write operation into the physical page p1 of the target physical unit OB11, and write the write data corresponding to the fourth write operation in the continuous write operation into the physical page p2 of the target physical unit OB11.

[0100] At this time, the memory management circuit 51 may record the mapping relationship between the physical addresses of the physical pages p0-p2 of the target physical unit OB11 and their corresponding logical addresses in the logical-to-physical information T11, and mark the physical pages p0-p2 as number 1 in the logical-to-physical information T11.

[0101] It should be noted that, although the physical pages p0-p2 of the target physical unit OB11 store write data corresponding to the second to fourth write operations in the continuous write operation, these three write operations are sequentially written into the target physical unit OB11 based on the same write mode, so the memory management circuit 51 regards the write order of these three write operations as the same, so as to mark the physical pages p0-p2 as number 1 in the logical to physical information T11.

[0102] Afterwards, the memory management circuit 51 can switch back to the TLC write mode, and write the write data corresponding to the fifth write operation in the continuous write operation into the physical pages p3~p5 of the target physical unit OB21, and record the mapping relationship between the physical addresses of the physical pages p3~p5 of the target physical unit OB21 and their corresponding logical addresses in the logical to physical information T21, and mark the physical pages p3~p5 as the number 2 in the logical to physical information T21, and repeat this process until the continuous write operation is completed.

[0103] It should be noted that, during the above-mentioned continuous write operation, the memory management circuit 51 may Figure 6 The timing of switching the write mode is determined by the method, so it will not be repeated here.

[0104] In an exemplary embodiment, since the memory management circuit 51 can record the write order of the physical pages in the target physical units OB11-OB13, OB21 in the logical-to-physical information T11-T13, T21. Therefore, when multiple physical addresses of multiple (more than two) physical pages in the target physical units OB11-OB13, OB21 are mapped to the same logical address, the memory management circuit 51 can query the storage location of the latest data corresponding to the logical address according to the write order in the logical-to-physical information T11-T13, T21. In other words, the memory management circuit 51 can query the latest physical address among the multiple physical addresses mapped to the same logical address from the logical-to-physical information T11-T13, T21.

[0105] It should be noted that, in actual application scenarios, when the target physical unit OB21 corresponding to the TLC write mode is fully written, the last target physical unit OB13 corresponding to the SLC write mode may not be fully written. Since the information stored in the logic-to-physical information T11-T13, T21 reflects the actual situation of performing continuous write operations according to the first ratio, in order to ensure the correctness of the write order in the logic-to-physical information T11-T13, T21, after the target physical unit OB21 is fully written, the target physical units OB11-OB13 will no longer be used to store data.

[0106] Fig. 9 is a schematic diagram of a first switching schedule and a second switching schedule according to an exemplary embodiment of the present invention. Fig. 9 .

[0107] In addition to the above-mentioned method of using the logic-to-physical information T11-T13, T21 to manage the target physical units OB11-OB13, OB21, the present invention also provides the following Fig. 9The first switching schedule TS1 and the second switching schedule TS2 are shown to manage the target physical units OB11 ˜ OB13 , OB21 .

[0108] In an exemplary embodiment, during the execution of the continuous write operation, the memory management circuit 51 may establish the first switching schedules TS1 and TS2.

[0109] Specifically, the switching time table TS1 is used to record the physical address corresponding to the latest data stored in the target physical unit OB21 when switching from the second writing mode (e.g., TLC writing mode) to the first writing mode (e.g., SLC writing mode). Similarly, the switching time table TS2 is used to record the physical address corresponding to the latest data stored in the target physical units OB11-OB13 when switching from the SLC writing mode to the TLC writing mode.

[0110] In the process of performing the continuous write operation, the memory management circuit 51 may first write the write data into the target physical unit OB21 based on the TLC write mode, then switch the write mode to write the write data into the target physical unit OB11 based on the SLC write mode, and then switch back to the TLC write mode to write the write data into the target physical unit OB21, and repeat this process until the continuous write operation is completed. Each time the write mode is switched, the memory management circuit 51 may record the physical address corresponding to the latest data stored in the target physical unit OB21 (or the target physical units OB11 to OB13) in the switching schedule TS1 (or the switching schedule TS2).

[0111] like Fig. 9 As shown, the time stamps ts-0 to ts-11 in the switching schedules TS1 and TS2 can be used to indicate the switching sequence of the write mode. The time stamp ts-0 indicates the first switching of the write mode, the time stamp ts-1 indicates the second switching of the write mode, and so on.

[0112] In the process of performing continuous write operations, when the memory management circuit 51 switches the write mode for the first time (for example, from the TLC write mode to the SLC write mode), the memory management circuit 51 may record the timestamp ts-0 and the physical address PCA-0 corresponding to the latest data stored in the target physical unit OB21 in the switching time table TS1. Next, when the memory management circuit 51 switches the write mode again (that is, switches from the SLC write mode back to the TLC write mode), the memory management circuit 51 may record the timestamp ts-1 and the physical address PCA-1 corresponding to the latest data stored in the target physical unit OB11 to OB13 in the switching time table TS2. Thereafter, when the memory management circuit 51 switches the write mode again (that is, switches from the TLC write mode to the SLC write mode), the memory management circuit 51 may record the timestamp ts-2 and the physical address PCA-2 corresponding to the latest data stored in the target physical unit OB21 in the switching time table TS1. The other contents in the switching time tables TS1 and TS2 can be deduced by analogy with the above process.

[0113] In an exemplary embodiment, when multiple physical addresses of multiple (more than two) physical pages in the target physical units OB11-OB13, OB21 are mapped to the same logical address, the memory management circuit 51 may first query multiple physical addresses corresponding to the logical address from the logical-to-physical information T11-T13, T21. Afterwards, the memory management circuit 51 may query multiple time stamps corresponding to the above multiple physical addresses from the switching time tables TS1, TS2, and determine the order of the multiple time stamps to determine the latest physical address among the above multiple physical addresses.

[0114] In general, the switching schedules TS1 and TS2 can be used to indicate the order in which data is written into the target physical units OB11-OB13 and OB21. Therefore, when multiple physical addresses of multiple (more than two) physical pages in the target physical units OB11-OB13 and OB21 are mapped to the same logical address, the memory management circuit 51 can query the storage location of the latest data corresponding to the logical address according to the timestamps in the switching schedules TS1 and TS2.

[0115] In this way, it is possible to no longer rely on the writing order recorded in the logic-to-physical information T11-T13, T21 to determine the newness of the data. Therefore, when the logic-to-physical information T11-T13, T21 and the switching schedules TS1, TS2 are used at the same time, when the target physical unit OB21 is full, the target physical units OB11-OB13 that are not full (for example, the target physical unit OB13) can continue to be used to store data.

[0116] In an exemplary embodiment, during the execution of a continuous write operation, if the target entity unit (e.g., target entity unit OB13) that is not filled with data is not written after a preset time period, the target entity unit OB13 is no longer used to store data. The preset time period can be designed by the user according to the needs, and the present invention is not limited. Accordingly, the exemplary embodiment of the present invention can be implemented, when the target entity unit OB21 is filled with data, the remaining target entity units (e.g., target entity unit OB13) that are not filled with data continue to be used to improve the utilization rate of the rewritable non-volatile memory module 43, and based on the preset time period, avoid the problem of the target storage unit OB13 not being used for a long time and not being closed.

[0117] Fig.10 is a flow chart of a memory management method according to an exemplary embodiment of the present invention. Fig.10 . In step S1001, multiple target entity units are selected from multiple entity units, wherein the multiple target entity units include a first number of first target entity units and a second number of second target entity units. In step S1002, when performing a first write operation in a continuous write operation, a write mode of a second write operation is determined according to a switching condition, wherein the second write operation is a next write operation of the first write operation, the write mode includes a first write mode and a second write mode, the first target entity unit corresponds to the first write mode, the second target entity unit corresponds to the second write mode, and the first write mode is different from the second write mode.

[0118] However, Fig.10 The steps in the above are described in detail, so I will not repeat them here. It is worth noting that Fig.10 Each step in the above process can be implemented as multiple program codes or circuits, and the present invention is not limited thereto. Fig.10 The method can be used in combination with the above embodiments or can be used alone, and the present invention is not limited thereto.

[0119] In summary, the memory control method and memory storage device proposed in the exemplary embodiments of the present invention can use multiple target physical units as units to manage the storage space of the rewritable non-volatile memory module, and in the process of executing continuous write operations, the write mode of the continuous write operation can be switched in a timely manner, thereby realizing write speed control within a small amount of data to improve the stability of the write speed.

[0120] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A memory control method, characterized in that: For a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module includes a plurality of physical units, and the memory control method includes: Selecting a plurality of target entity units from the plurality of entity units, wherein the plurality of target entity units includes a first number of first target entity units and a second number of second target entity units; When performing a first write operation in a continuous write operation, a write mode of a second write operation is determined according to a switching condition, wherein The second write operation is the next write operation of the first write operation, the write mode includes a first write mode and a second write mode, the first target entity unit corresponds to the first write mode, the second target entity unit corresponds to the second write mode, and the first write mode is different from the second write mode.

2. The memory control method according to claim 1, further comprising: Before executing the continuous write operation, obtaining a first write speed, a second write speed, and a target write speed corresponding to the continuous write operation; as well as A first ratio is calculated according to the target writing speed, the first writing speed, and the second writing speed.

3. The memory control method according to claim 2, wherein the first write speed is a write speed required to complete the continuous write operation in the first write mode, and the second write speed is a write speed required to complete the continuous write operation in the second write mode.

4. The memory control method according to claim 2, wherein the step of determining the write mode of the second write operation according to the switching condition comprises: Obtaining a first data volume of the first target entity unit and a second data volume of the second target entity unit; Calculating a second ratio according to the first data amount and the second data amount; as well as A writing mode of the second writing operation is determined according to the first ratio and the second ratio. 5 . The memory control method according to claim 4 , wherein the first data amount is the amount of data written into the first target physical unit, and the second data amount is the amount of data written into the second target physical unit.

6. The memory control method according to claim 1, wherein the plurality of target physical units respectively have a plurality of logical-to-physical information, and the plurality of logical-to-physical information are respectively used to record the writing order of the plurality of target physical units and the mapping relationship between the physical addresses and logical addresses of the plurality of target physical units. 7 . The memory control method according to claim 6 , wherein after the second target physical unit is full, the first target physical unit is no longer used to store data.

8. The memory control method according to claim 7, further comprising: If the logical address is mapped to the physical addresses of the target physical units, the latest physical address among the physical addresses is queried according to the written order of the target physical units in the logical-to-physical information.

9. The memory control method according to claim 6, further comprising: During the execution of the continuous write operation, a first switching schedule and a second switching schedule are established, wherein The first switching schedule is used to record the physical address and timestamp corresponding to the latest data stored in the second target physical unit when switching from the second writing mode to the first writing mode, and The second switching time table is used to record the physical address and timestamp corresponding to the latest data stored in the first target physical unit when switching from the first writing mode to the second writing mode.

10. The memory control method according to claim 9, further comprising: If the logical address is mapped to a plurality of physical addresses of the plurality of target physical units, querying the plurality of physical addresses from the plurality of logical-to-physical information; querying a plurality of timestamps corresponding to the plurality of physical addresses from at least one of the first switching schedule and the second switching schedule; as well as A latest physical address among the multiple physical addresses is determined according to the multiple timestamps.

11. A memory storage device, characterized in that: include: A connection interface unit for coupling to a host system; A rewritable non-volatile memory module, wherein the rewritable non-volatile memory module comprises a plurality of physical units; as well as A memory control circuit unit is coupled to the connection interface unit and the rewritable non-volatile memory module. The memory control circuit unit is used to: Selecting a plurality of target entity units from the plurality of entity units, wherein the plurality of target entity units includes a first number of first target entity units and a second number of second target entity units; When performing a first write operation in a continuous write operation, a write mode of a second write operation is determined according to a switching condition, wherein the second write operation is a next write operation of the first write operation, wherein The write mode includes a first write mode and a second write mode, the first target physical unit corresponds to the first write mode, the second target physical unit corresponds to the second write mode, and the first write mode is different from the second write mode.

12. The memory storage device according to claim 11, wherein before performing the continuous write operation, the memory control circuit unit is further used to obtain a first write speed, a second write speed and a target write speed corresponding to the continuous write operation, and calculate a first ratio according to the target write speed, the first write speed and the second write speed.

13. The memory storage device according to claim 12, wherein the first write speed is a write speed required to complete the continuous write operation in the first write mode, and the second write speed is a write speed required to complete the continuous write operation in the second write mode.

14. The memory storage device according to claim 12, wherein the memory control circuit unit is further configured to: Obtaining a first data volume of the first target entity unit and a second data volume of the second target entity unit; Calculating a second ratio according to the first data amount and the second data amount; and A writing mode of the second writing operation is determined according to the first ratio and the second ratio. 15 . The memory storage device according to claim 14 , wherein the first data amount is the amount of data written into the first target physical unit, and the second data amount is the amount of data written into the second target physical unit.

16. According to the memory storage device of claim 11, the multiple target physical units respectively have multiple logical-to-physical information, and the multiple logical-to-physical information are respectively used to record the writing order of the multiple target physical units and the mapping relationship between the physical addresses and logical addresses of the multiple target physical units. 17 . The memory storage device according to claim 16 , wherein after the second target physical unit is full, the first target physical unit is no longer used to store data.

18. The memory storage device according to claim 17, wherein the memory control circuit unit is further configured to: If the logical address is mapped to the physical addresses of the target physical units, the latest physical address among the physical addresses is queried according to the written order of the target physical units in the logical-to-physical information.

19. The memory storage device according to claim 16, wherein the memory control circuit unit is further configured to: During the execution of the continuous write operation, a first switching schedule and a second switching schedule are established, wherein The first switching schedule is used to record the physical address and timestamp corresponding to the latest data stored in the second target physical unit when switching from the second writing mode to the first writing mode, and The second switching time table is used to record the physical address and timestamp corresponding to the latest data stored in the first target physical unit when switching from the first writing mode to the second writing mode.

20. The memory storage device according to claim 19, wherein the memory control circuit unit is further configured to: If the logical address is mapped to a plurality of physical addresses of the plurality of target physical units, querying the plurality of physical addresses from the plurality of logical-to-physical information; querying a plurality of time stamps corresponding to the plurality of physical addresses from at least one of the first switching schedule and the second switching schedule; and A latest physical address among the multiple physical addresses is determined according to the multiple timestamps.

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