Breakpoint debugging method, breakpoint debugging device and readable medium

Abstract

The present disclosure provides a breakpoint debugging method, comprising: performing flip-flop detection for each cycle, determining flip-flop matching information of the cycle, the flip-flop matching information being information of a flip-flop matched with an instruction; performing priority arbitration on the flip-flop matching information of different cycles to obtain information of a target flip-flop; in a case where an instruction matched with the target flip-flop reaches a commit stage and it is determined that the target flip-flop triggers, determining an execution action according to the information of the target flip-flop, so that a processing core executes the execution action; the flip-flop detection logic and flip-flop detection information synchronization logic have low coupling degree with a main stream, are based on a superscalar out-of-order pipeline design, have good scalability, and can reduce the difficulty of secondary development of developers on different microarchitectures. The present disclosure also provides a breakpoint debugging device and a readable medium.

Description

Technical Field

[0001] This disclosure relates to the field of computer technology, specifically to a breakpoint debugging method, a breakpoint debugging device, and a readable medium. Background Technology

[0002] The RISC-CV instruction set architecture boasts technical characteristics such as simplicity, modularity, scalability, and open source. As an emerging instruction set, RISC-CV can be used to build microprocessors suitable for any field through the combination and extension of a limited set of instructions.

[0003] Due to the high licensing fees and royalties, as well as technology embargoes, associated with mainstream instruction sets like ARM, numerous research institutions, tech giants, and startups have joined the competition and development of RISC-V, seeking to break the monopoly of ARM and other mainstream instruction sets in the mobile and server fields. This has led to the emergence of numerous commercial IPs and System-on-Chips (SoCs) based on the RISC-V core. In the RISC-V core, hardware breakpoints and hardware watchpoints are indispensable features and debugging tools that must be implemented at the hardware level.

[0004] However, RISC-CV, as an emerging instruction set architecture, is still evolving and developing. Currently, its core commercial applications are mainly concentrated in fields such as the Internet of Things (IoT) and artificial intelligence (AI). Therefore, most current RISC-CV hardware breakpoints and watchpoints are designed based on sequential pipelines, tightly coupled to the main pipeline, and have relatively simple features, such as the lack of a trigger chain. These solutions lack scalability and significant reference value, and there are currently no breakpoint debugging solutions for RISC-CV hardware breakpoints and watchpoints based on superscalar out-of-order main pipelines. Summary of the Invention

[0005] This disclosure provides a breakpoint debugging method, a breakpoint debugging device, and a readable medium.

[0006] In a first aspect, embodiments of this disclosure provide a breakpoint debugging method, including:

[0007] For each cycle, trigger detection is performed to determine the trigger matching information for that cycle, wherein the trigger matching information is the information of the trigger that matches the instruction;

[0008] Priority arbitration is performed on the matching information of the triggers in different periods to obtain the information of the target trigger;

[0009] When an instruction matching the target trigger arrives at the submission stage and it is determined that the target trigger has been triggered, an execution action is determined based on the information of the target trigger, so that the processing core can execute the execution action.

[0010] In another aspect, embodiments of this disclosure also provide a breakpoint debugging device, comprising:

[0011] The trigger detection module is used to perform trigger detection for each cycle and determine the trigger matching information for the cycle. The trigger matching information is the information of the trigger that matches the instruction.

[0012] The trigger detection information synchronization module is used to perform priority arbitration on the trigger matching information of different periods to obtain the information of the target trigger;

[0013] The trigger submission module is used to determine an execution action based on the information of the target trigger when the instruction matched by the target trigger reaches the submission stage and it is determined that the target trigger has been triggered, so that the processing core can execute the execution action.

[0014] In another aspect, embodiments of this disclosure also provide a breakpoint debugging apparatus, comprising: one or more processors; a storage device storing one or more programs thereon; when the one or more programs are executed by the one or more processors, causing the one or more processors to implement the breakpoint debugging method as described above; and one or more I / O interfaces connected between the processors and the storage device, configured to enable information interaction between the processors and the storage device.

[0015] In another aspect, embodiments of this disclosure also provide a computer-readable medium having a computer program stored thereon, wherein the program, when executed, implements the breakpoint debugging method as described above.

[0016] The breakpoint debugging method provided in this disclosure includes: performing trigger detection for each cycle, determining the trigger matching information for the cycle, wherein the trigger matching information is the information of a trigger that matches an instruction; performing priority arbitration on the trigger matching information of different cycles to obtain the information of a target trigger; and determining an execution action based on the information of the target trigger when an instruction matching the target trigger reaches the submission stage and the target trigger is determined to be triggered, so that the processing core can execute the execution action. The breakpoint debugging method in this disclosure provides an implementation scheme for RISCV hardware breakpoints and hardware watchpoints, wherein the trigger detection logic and the trigger detection information synchronization logic are lowly coupled with the main pipeline. When extending the trigger scheme, only minor modifications are needed while keeping the trigger detection logic and the trigger detection information synchronization logic unchanged. The trigger submission logic, which is highly coupled with the main pipeline, is not related to the type and number of triggers. Furthermore, this disclosure is based on a superscalar out-of-order pipeline design, which has good scalability and can reduce the difficulty for developers to perform secondary development on different microarchitectures. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of the breakpoint debugging process provided in the embodiments of this disclosure;

[0018] Figure 2 This is a schematic diagram illustrating the breakpoint debugging principle provided in the embodiments of this disclosure;

[0019] Figure 3 A schematic diagram illustrating instruction address trigger detection provided in an embodiment of this disclosure;

[0020] Figure 4 A schematic diagram illustrating memory address trigger detection provided in an embodiment of this disclosure;

[0021] Figure 5 Schematic diagram of the breakpoint debugging device provided in the embodiments of this disclosure Figure 1 ;

[0022] Figure 6 Schematic diagram of the breakpoint debugging device provided in the embodiments of this disclosure Figure 2 . Detailed Implementation

[0023] Exemplary embodiments will be described more fully below with reference to the accompanying drawings; however, these exemplary embodiments may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will enable those skilled in the art to fully understand the scope of this disclosure.

[0024] As used herein, the term “and / or” includes any and all combinations of one or more related enumerated entries.

[0025] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. As used herein, the singular forms “a” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It will also be understood that when the terms “comprising” and / or “made of” are used in this specification, the presence of the said feature, integral, step, operation, element, and / or component is specified, but the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof is not excluded.

[0026] The embodiments described herein can be described with reference to plan views and / or cross-sectional views using the ideal schematic diagrams of this disclosure. Therefore, the example illustrations can be modified according to manufacturing techniques and / or tolerances. Therefore, the embodiments are not limited to those shown in the drawings, but include modifications to configurations formed based on manufacturing processes. Therefore, the areas illustrated in the drawings are schematic in nature, and the shapes of the areas shown in the figures illustrate specific shapes of areas of an element, but are not intended to be limiting.

[0027] Unless otherwise specified, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art. It will also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and this disclosure, and will not be interpreted as having an idealized or overly formal meaning, unless expressly so defined herein.

[0028] This disclosure provides a breakpoint debugging method, which is applied to a breakpoint debugging device. The breakpoint debugging device may include a trigger match module, a trigger match information synchronization module, a trigger control status register (Trigger CSR), and a trigger commit module.

[0029] The trigger detection module includes an instruction address trigger detection (PC Trigger Match) submodule and a memory access address trigger detection (LS Trigger Match) submodule, which perform trigger detection during the instruction decoding stage and the memory access execution stage, respectively.

[0030] The trigger detection information synchronization module performs synchronous caching processing on different triggers that match the same instruction or triggers that match different instructions collected from different pipeline stages / time points. It caches the information of the oldest and second oldest triggers (chains) in the main pipeline. The oldest trigger (chain) in the main pipeline means that, in a superscalar out-of-order processor, the lifecycle of an instruction ends only upon commit, which involves fetching, decoding, renaming, issuing, executing, and committing. Therefore, in the main pipeline, there will be multiple instructions in their lifecycle. Triggers (chains) will match on some of these instructions, and the age of these matching triggers (chains) is distinguished according to the instruction's age information. That is, among the instructions that match the triggers (chains), the trigger (chain) matched on the oldest instruction is called the oldest trigger (chain).

[0031] The trigger control status register mainly implements read and write operations on the status registers related to the trigger, and sends the value of the trigger control status register to the two trigger detection modules in real time. Depending on the type of trigger implemented, the implemented control status register will be different. The embodiments disclosed in this disclosure involve the trigger select (tselect) register, the trigger data1 (tdata1) register, and the trigger data2 (tdata2) register.

[0032] During the instruction submission phase, the trigger submission module determines whether the trigger will be triggered and the execution action after triggering based on the priority between the trigger and the exception event in the processor core.

[0033] Figure 1 This is a schematic diagram of the breakpoint debugging process provided in the embodiments of this disclosure. Figure 2 This is a schematic diagram illustrating the breakpoint debugging principle provided in an embodiment of this disclosure. Figure 2 As shown, this disclosure provides a superscalar out-of-order pipeline architecture with a main pipeline of 3 issues and a memory access pipeline of 2 issues to illustrate the design scheme of RISC-V hardware breakpoints and hardware watchpoints. Figure 2 The diagram only shows the pipeline stages related to the implementation of the triggers, namely decoding, renaming and dispatching, execution (only the memory access execution unit, Lsu, is shown), and instruction commit and retirement unit (Iru). This disclosure uses the implementation of four triggers as an example to illustrate its design principles.

[0034] Combination Figure 1 and Figure 2 As shown, the breakpoint debugging method includes the following steps:

[0035] Step S11: Perform trigger detection for each cycle to determine the trigger matching information for the cycle, wherein the trigger matching information is the information of the trigger that matches the instruction.

[0036] The trigger matching information differs for different cycles and can include instruction address trigger matching information and memory access address trigger matching information. The value of the Trigger Control Status Register (Trig CSR) is output to the trigger detection module in real time. In the program flow executed in the processor core, the instruction address trigger detection submodule matches the instruction addresses on the multi-issue channels during the instruction decoding stage and outputs the instruction address trigger matching information; the memory access address trigger detection submodule matches the memory access addresses on the memory access pipeline in the first stage of the memory access pipeline and outputs the memory access address trigger matching information.

[0037] Step S12: Priority arbitration is performed on the matching information of triggers with different cycles to obtain the information of the target trigger.

[0038] During the time interval between trigger matching and triggering, the trigger matching information needs to be cached. For instruction address trigger matching information output by the instruction address trigger detection submodule, it needs to be pipelined to the dispatch stage before being output to the trigger detection information synchronization module for arbitration and storage. For memory access address trigger matching information output by the memory access address trigger detection submodule, it is directly output to the trigger detection information synchronization module for arbitration and storage in the second stage of the memory access pipeline. It should be noted that, in addition to the cached trigger information, the trigger detection information synchronization module also stores the matched instruction address and the corresponding reordered cache sequence number.

[0039] Step S13: When an instruction matching the target trigger arrives at the submission stage and it is determined that the target trigger has been triggered, an execution action is determined based on the information of the target trigger, so that the processing core can execute the execution action.

[0040] When an instruction matching the target trigger arrives at the commit stage and it is determined that the target trigger has been triggered, the first submodule (Trig Commit1) of the trigger commit module determines whether the target trigger will ultimately be triggered based on the priority of the target trigger and other exceptions on the instruction. If it is determined that the trigger has been triggered, the information of the target trigger, such as the address of the instruction matching the target trigger and the execution action configured for the target trigger, is output to the second submodule (TrigCommit2) of the trigger commit module.

[0041] After the trigger submission module determines that the target trigger has been triggered, the processor core determines the action to be executed based on the action field of the trigger control status register: if the action field is 1, the processor core will enter debug mode; if the action field is 0, the processor core will enter the corresponding exception service routine.

[0042] It should be noted that before step S11, the following steps also need to be performed: initialization, processor entering debug mode, configuring trigger CSR, processor returning from debug and executing program flow, etc.

[0043] (1) Initialization

[0044] Initialization refers to the processor core performing system initialization, which involves configuring system registers, loading running programs and data, etc., so that the processor core can begin executing the program. Of course, the initialization steps also include the initialization of registers and storage queues in the hardware breakpoint and hardware watchpoint schemes mentioned above. For example, the two sets of registers in the trigger detection information synchronization module (which can be regarded as queues with a depth of 2) are initialized to 0, and the enable field of the trigger control status register is initialized to invalid.

[0045] (2) The processor enters debug mode.

[0046] The debugger initiates a debug interrupt request through the debug module. The processor core responds to the debug interrupt request after emptying the pipeline and enters debug mode.

[0047] (3) Configure the CSR trigger

[0048] The debugger configures the trigger control status registers located in the processor core through the debug module, and configures the triggerselect (tselect) register, trigger data1 (tdata1) register, and trigger data2 (tdata2) register in sequence.

[0049] (4) The processor returns from debugging and executes the program flow.

[0050] The debugger initiates a resume request to the processor core through the debug module. The processor core returns from debug mode to the previously executed mode and resumes the previous debug interrupt context or starts executing the program flow from the instruction fetch address specified by the debugger.

[0051] The breakpoint debugging method provided in this disclosure includes: performing trigger detection for each cycle, determining the trigger matching information for the cycle, wherein the trigger matching information is the information of a trigger that matches an instruction; performing priority arbitration on the trigger matching information of different cycles to obtain the information of a target trigger; and determining an execution action based on the information of the target trigger when an instruction matching the target trigger reaches the submission stage and the target trigger is determined to be triggered, so that the processing core can execute the execution action. The breakpoint debugging method in this disclosure provides an implementation scheme for RISCV hardware breakpoints and hardware watchpoints, wherein the trigger detection logic and the trigger detection information synchronization logic are lowly coupled with the main pipeline. When extending the trigger scheme, only minor modifications are needed while keeping the trigger detection logic and the trigger detection information synchronization logic unchanged. The trigger submission logic, which is highly coupled with the main pipeline, is not related to the type and number of triggers. Furthermore, this disclosure is based on a superscalar out-of-order pipeline design, which has good scalability and can reduce the difficulty for developers to perform secondary development on different microarchitectures.

[0052] In some embodiments, the step of performing trigger detection for each cycle and determining the trigger matching information of the cycle (i.e., step S11) includes the following steps: for each first cycle, performing instruction address trigger detection during the instruction decoding stage to determine the instruction address trigger matching information of the first cycle; and for each second cycle, performing memory access trigger detection during the memory access execution stage to determine the memory access trigger matching information of the second cycle.

[0053] In some embodiments, the instruction address trigger matching information for the first cycle may include information about the instruction address trigger corresponding to the oldest instruction that matches the trigger within the first cycle, or information about the instruction address trigger corresponding to the oldest instruction that matches the trigger within the first cycle and information about the instruction address trigger corresponding to the second oldest instruction that matches the trigger within the first cycle. The memory access trigger matching information for the second cycle may include information about the memory access trigger corresponding to the oldest instruction that matches the trigger within the second cycle, or information about the memory access trigger corresponding to the oldest instruction that matches the trigger within the second cycle and information about the memory access trigger corresponding to the second oldest instruction that matches the trigger within the second cycle.

[0054] In some embodiments, the step of determining the instruction address trigger matching information for the first cycle includes: determining the instruction address trigger matching information for the first cycle based on the trigger chain membership attribute of the instruction address trigger and the age and type of the instruction within the first cycle. In this embodiment, the trigger chain membership attribute indicates whether the trigger is a trigger in a trigger chain, i.e., whether the trigger belongs to the trigger chain.

[0055] The following combination Figure 3 This section details the various scenarios for determining the instruction address trigger match information for the first cycle. The instruction address trigger match (PC Trigger Match) submodule is located at the same pipeline stage as the decoding module. Within the instruction address trigger match submodule, during the first cycle, for each instruction on each issue channel of the processor core, each trigger is compared with that instruction to determine and output the instruction address trigger match information for the first cycle.

[0056] like Figure 3 As shown, the instruction address trigger matching information for the first cycle is determined, including the following cases:

[0057] (1) If the trigger that matches the instruction in the first cycle is not a trigger in the trigger chain, the instruction address trigger matching information of the first cycle is determined to be the information of the instruction address trigger corresponding to the oldest instruction among the instructions matched by the instruction address triggers in the first cycle. That is, the trigger that matches the older instruction has higher output priority. If there is no trigger chain among the matched triggers, only the matching information of the oldest trigger among all the matched triggers in the current cycle (i.e., the first cycle) is output (here, the oldest refers to the oldest instruction corresponding to the trigger).

[0058] like Figure 3 In case (a), if trigger1 and trigger2 that match the instruction are not triggers in the trigger chain during the first cycle, since the instruction C0 that matches trigger2 is older than the instruction C1 that matches trigger1, the instruction address trigger matching information for the first cycle is the information of the oldest trigger (trigger2) among all the matching triggers during the first cycle, that is, only the information of trigger2 is output.

[0059] (2) If the oldest trigger that matches the instruction in the first cycle is a trigger in the trigger chain, and the instruction matched by the oldest trigger is a memory access instruction, and other instruction address triggers match the instruction in the first cycle, then the instruction address trigger matching information for the first cycle is determined to be the trigger chain information and the instruction address trigger information corresponding to the second oldest instruction among the instructions matched by the instruction address triggers in the first cycle. That is, if there is a trigger chain among the matched triggers, and the instruction address trigger that matches one of the two triggers in the trigger chain is the oldest trigger among all the matched triggers in this cycle (i.e., the first cycle) and the instruction that matches that trigger is a memory access instruction, then the trigger chain matching information is output. Furthermore, if the second oldest trigger also matches, then the second oldest trigger matching information also needs to be output.

[0060] like Figure 3 In case (b), within the first cycle, the triggers that match the instruction include trigger0, trigger3, and trigger1 in the trigger chain. The oldest trigger is trigger1, and the instruction C0 matched by trigger1 is a memory access instruction. Within the first cycle, trigger0 and trigger3 also match the instruction. Therefore, the instruction address trigger matching information in the first cycle is the information of the trigger chain, i.e., trigger1 (chain), and the information of trigger0 corresponding to the second oldest instruction (C1) matched within the first cycle.

[0061] (3) If the oldest trigger that matches the instruction in the first cycle is not a trigger in the trigger chain, the trigger matching information of the instruction address in the first cycle is determined to be the information of the oldest trigger that matches the instruction in the first cycle. That is, if the oldest trigger among all the matching triggers in this cycle (i.e., the first cycle) is not a trigger in the trigger chain, then referring to the above case (1), it is only necessary to output the information of the oldest trigger.

[0062] like Figure 3 In case (c), the oldest trigger that matches the instruction in the first cycle is trigger0. If trigger0 is not a trigger in the trigger chain, then the trigger matching information for the instruction address in the first cycle is the information that the oldest trigger that matches the instruction is trigger0.

[0063] (4) If the instruction in the first cycle is an ebreak instruction and the ebreak_en field in the debug register is valid, the instruction address trigger matching information for the first cycle will not be generated.

[0064] For triggers whose action is "raise a breakpoint exception" (refer to RISC-VExternal Debug Support Version 0.13.2), a special case needs to be handled when determining whether it matches the instruction in the first cycle. That is, the instruction is an ebreak instruction, and the ebreak_en field in the DCSR (debug CSR) is configured to be valid. In this case, the priority of ebreak is higher than that of the trigger whose action is "raise a breakpoint exception", so the trigger does not fire.

[0065] The aforementioned trigger chain is defined as follows: it begins with the first trigger whose chain field (configuration field in the tselect register) has a value of 1 and ends with the first trigger whose chain field has a value of 0. For a trigger chain to satisfy the triggering condition, all triggers in the chain must match the same instruction. The execution action of the last trigger in the chain (the action field in tselect) is taken as the execution action of the entire trigger chain. In this embodiment, the trigger chain length is 2 because this embodiment only involves two types of triggers (instruction address triggers and memory access address triggers). If the scheme is extended based on this embodiment to implement other types of triggers, the maximum length of the trigger chain will also change accordingly.

[0066] In some embodiments, the step of determining the memory address trigger matching information of the second cycle includes the following steps: if a trigger chain exists, determining the memory address trigger matching information of the second cycle based on the matching result of the instruction in the second cycle with the memory address trigger, the matching result of the instruction address trigger in the trigger chain in the first cycle, the trigger chain membership attribute of the memory address trigger, the age of the instruction in the second cycle, and the age of the instruction in the trigger chain that matches the instruction address trigger.

[0067] The following combination Figure 4 This section provides a detailed explanation of various scenarios for determining the memory address trigger match information for the second cycle. The LS Trigger Match submodule is located at the same pipeline stage as the first pipeline stage of the Memory Execution Unit (LSU). The LS Trigger Match submodule determines and outputs the memory address trigger match information for the second cycle.

[0068] like Figure 4 As shown, the memory address trigger matching information for the second cycle is determined, including the following cases:

[0069] (1) If there is no matching trigger chain in the second cycle and there is no trigger chain among the triggers that are matched with instructions in the second cycle, or if there is no matching trigger chain in the second cycle and there is a trigger chain among the triggers that are matched with instructions in the second cycle, but the instruction address trigger that is matched in the first cycle is younger than the oldest trigger among the memory address triggers matched in the second cycle, the memory address trigger matching information of the second cycle is determined to be the information of the oldest trigger among the memory address triggers matched in the second cycle.

[0070] like Figure 4In case (a), since the memory address trigger in the trigger chain does not match the instruction in the second cycle, the trigger chain is not matched, meaning there is no trigger chain matching in the second cycle. In the second cycle, the triggers that match the instruction include trigger2 and trigger3, where trigger2 is older than trigger3, meaning trigger2 is the oldest memory address trigger matched in the second cycle. If the instruction address trigger 0 matched in the first cycle is younger than the oldest memory address trigger 2 matched in the second cycle, then the memory address trigger matching information for the second cycle is the information for trigger2. In other words, if there is no trigger chain among the matched triggers and no trigger chain among the unmatched triggers, or if there is a trigger chain among the unmatched triggers but the instruction corresponding to the matched instruction address trigger in that chain is younger than the instruction corresponding to the oldest matched trigger in this cycle (i.e., the second cycle), then only the information of the oldest matched trigger in this cycle is output.

[0071] (2) If no memory access trigger matches the instruction in the second cycle, or if only the memory address trigger in the trigger chain matches the instruction in the second cycle and the instruction address trigger in the trigger chain did not match the instruction in the first cycle, then no memory address trigger matching information for the second cycle will be generated. In other words, if the instruction address trigger in the trigger chain did not match the instruction in the first cycle before this, then the memory address trigger in that trigger chain will not output anything, regardless of whether it matches or not.

[0072] like Figure 4 In case (b), only the memory address trigger 0 in the trigger chain matches the instruction in the second cycle, but the instruction address trigger 1 in the trigger chain does not match the instruction in the first cycle. This situation indicates that the trigger chain does not match, so the memory address trigger matching information for the second cycle is not output.

[0073] (3) If the instruction matched by the instruction address trigger in the trigger chain is older than the target instruction, and the memory address triggers in the trigger chain match within the second cycle, the memory address trigger matching information for the second cycle is determined to be the information of the memory address triggers in the trigger chain. The target instruction is the oldest instruction matched by any other memory address trigger besides those in the trigger chain within the second cycle.

[0074] like Figure 4In case (c), the target instruction is the instruction (i7) that matches trigger2, and the instruction (i2) in the trigger chain that matches trigger0 is older than the target instruction (i7). Therefore, the memory address trigger matching information for the second cycle is the information of the memory address trigger (trigger1) in the trigger chain. It should be noted that regardless of whether the memory address triggers in the trigger chain match, the information of the memory address triggers in that trigger chain must be output.

[0075] (4) If the instruction matched by the instruction address trigger in the trigger chain is older than the target instruction, and the memory address trigger in the trigger chain does not match the instruction in the second cycle, and other memory address triggers outside the trigger chain match the instruction in the second cycle, the memory address trigger matching information in the second cycle is determined to be the information of the memory address triggers not matching in the trigger chain and the information of the oldest trigger among the other memory address triggers outside the trigger chain that match the instruction in the second cycle.

[0076] like Figure 4 In case (d), the target instruction is the instruction (i4) that matches trigger3. The instruction (i2) in the trigger chain that matches the instruction address trigger0 is older than the target instruction (i4). The memory address trigger1 in the trigger chain does not match the instruction in the second cycle. The other memory address triggers (trigger2 and trigger3 outside the trigger chain) all match the instruction in the second cycle. Therefore, the memory address trigger matching information in the second cycle is the information that the memory address trigger1 in the trigger chain does not match, and the information of the oldest trigger (trigger3) among the other memory address triggers outside the trigger chain.

[0077] (5) If the instruction matched by the instruction address trigger in the trigger chain is older than the target instruction, and the memory address trigger in the trigger chain does not match the instruction in the second cycle, and the memory address triggers in other trigger chains besides the trigger chain match the instruction in the second cycle, the memory address trigger matching information in the second cycle is determined to be the information of the memory address triggers not matching in the trigger chain and the information of the memory address triggers in other trigger chains besides the trigger chain that match the instruction in the second cycle.

[0078] like Figure 4 In case (e), with trigger chain 1 (i.e. Figure 4Taking the first trigger chain shown in e as an example, the target instruction is the instruction (i4) matched by trigger2. The instruction (i2) matched by the instruction address trigger in trigger chain 1 is older than the target instruction (i4), and the memory access trigger 1 in trigger chain 1 does not match the instruction in the second cycle. Furthermore, trigger chain 2 (i.e....) Figure 4 If the memory address trigger 2 in the second trigger chain (shown in e) matches the instruction in the second cycle, then the memory address trigger matching information for the second cycle includes the information that the memory address trigger 1 in trigger chain 1 does not match, and the information of trigger 2 in trigger chain 2. In other words, besides outputting the information about the memory address triggers that do not match in the trigger chain, it is also necessary to output the information of the oldest trigger among the other matching memory address triggers in this cycle.

[0079] As can be seen from the above situations (3)-(5), if the instruction address trigger in the trigger chain has been matched before, and the instruction corresponding to the matched trigger is older than the instruction corresponding to the trigger in other non-trigger chains that are matched in the current cycle (i.e., the second cycle), then the information of the memory address trigger needs to be output regardless of whether the memory address trigger in the trigger chain is matched. If the memory address trigger in the trigger chain is not matched, and there are other memory address triggers that are matched in the current cycle (i.e., the second cycle), then the information of the oldest trigger among the other matched memory address triggers also needs to be output.

[0080] In some embodiments, the step of priority arbitration of trigger matching information of different cycles to obtain the information of the target trigger (i.e., step S12) includes the following steps: according to a preset first rule and a preset second rule, priority arbitration is performed on the instruction address trigger matching information of the first cycle and the memory address trigger matching information of the second cycle to obtain the information of the target trigger; wherein, the first rule is a rule based on the trigger chain membership attribute, and the second rule is a rule based on the instruction age relationship between the currently input memory address trigger matching information and the saved trigger matching information.

[0081] Because there is a time interval between trigger matching and triggering (the actual triggering decision is made during the instruction submission phase based on the trigger matching information and the priority of other events and triggers in the system), multiple triggers may be matched on different instructions during this time. Therefore, the trigger matching information output by the two trigger detection submodules needs to be cached. The most direct and effective method is to add some hardware resources to each entry in the reordering cache to record the matching trigger information of the instruction stored in that entry. However, this requires adding hardware resources to each entry in the reordering cache, resulting in significant hardware overhead. Therefore, using a dedicated queue to cache the matched trigger information is a relatively better approach. However, if all trigger matching information is stored directly without processing, the hardware overhead is also relatively high. In fact, we only need to record the oldest matched trigger in the current pipeline. An exception is that for a trigger chain, if the instruction address trigger matches but the memory access trigger does not, and because the instruction address trigger detection logic on the same instruction executes before the memory access trigger detection logic, the instruction address trigger detection submodule may output the oldest and second oldest trigger matching information. Therefore, the trigger detection information synchronization module can, following the above approach, prioritize and arbitrate the trigger matching information from the two trigger detection submodules, and record the information of the two oldest triggers (chains). This information can include the trigger action, the trigger time (the timing field in the tselect register), the address of the matched instruction, and its corresponding reordering cache sequence number. It should be noted that since the minimum length of a trigger chain is 2, when expanding the scheme to implement more triggers, such as 6, the trigger detection information synchronization module needs to record the information of the three oldest triggers (chains), and so on.

[0082] Therefore, in some embodiments, the information of the target trigger may include the information of the oldest trigger (chain); the information of the target trigger may also include the information of the oldest trigger (chain) or the second oldest trigger (chain). That is, after synchronous processing based on the trigger detection information, only the information of the oldest one or two triggers (chains) in the pipeline can be cached, which can greatly save the hardware overhead of its implementation in a superscalar out-of-order processor.

[0083] In this embodiment of the disclosure, the oldest trigger matching information in the current pipeline is recorded by a first array, and the second oldest trigger matching information in the current pipeline is recorded by a second array. The oldest trigger matching information in the current pipeline refers to the information of the oldest trigger in the current pipeline that matches the instruction; the second oldest trigger matching information in the current pipeline refers to the information of the second oldest trigger in the current pipeline that matches the instruction.

[0084] The first rule includes at least one of the following:

[0085] (1) The second array is invalid if the trigger matching information in the first array is not the information of the trigger in the trigger chain.

[0086] (2) If the trigger matching information in the first array is information about triggers in the trigger chain, the trigger matching information in the second array includes information about the trigger chain or information about triggers outside the trigger chain. That is, if the first array records trigger matching of the trigger chain, the second array is allowed to record information about the trigger chain or a single trigger.

[0087] (3) If the trigger matching information in the first array is the information of the triggers in the trigger chain, and both the instruction address triggers and memory access address triggers in the trigger chain match the instruction, then the second array is invalidated. That is, for the first array, if the currently recorded information is the information of the trigger chain, and the instruction address triggers in it are matched, then if the memory access address trigger detection submodule outputs a matching memory access address trigger in the trigger chain, then the second array is invalidated, i.e., only the first array is retained.

[0088] (4) For either the first array or the second array, if the trigger matching information of the array is the information of the triggers in the trigger chain, and the instruction address triggers in the trigger chain match the instructions, but the memory address triggers in the trigger chain do not match the instructions, then the array is invalidated; wherein, if the array is the first array, then the second array is marked as the first array in the current cycle. That is, for each of the two arrays, if the array currently records the information of the trigger chain, and the instruction address triggers therein are matched, then if the memory address trigger detection submodule outputs that the memory address triggers in the trigger chain do not match, then the array is invalidated; if the first array is invalidated, then the original second array is marked as the first array in the current cycle.

[0089] For each of the two arrays, the local information recorded in the trigger detection information synchronization module and the input information from the two trigger detection submodules need to be updated according to the second rule.

[0090] The second rule includes at least one of the following:

[0091] (1) If the first array is stored locally but the second array is not stored, and the information in the first array is the matching information of the instruction address trigger in the trigger chain, if the instruction matched by the currently input memory address trigger is the same age as the instruction matched by the instruction address trigger, then the trigger chain of the first array is matched; if the instruction matched by the currently input memory address trigger is older than the instruction matched by the instruction address trigger in the trigger chain of the first array, then the first array is updated with the matching information of the currently input memory address trigger; if the instruction matched by the currently input memory address trigger is younger than the instruction matched by the instruction address trigger, then the second array is updated with the matching information of the currently input memory address trigger.

[0092] In other words, the local system only records the first array, and the first array is a trigger chain. That is, the instruction address triggers in the trigger chain of the first array have already been matched. If the instruction of the currently input matching memory address trigger has the same age as the instruction corresponding to the trigger in the first array recorded locally, it means that the memory address triggers in this trigger chain also match, and the current trigger chain of the first array is matched. If the instruction of the currently input matching memory address trigger has an older age than the instruction corresponding to the trigger in the first array recorded locally, and the currently input matching memory address trigger has a higher priority, then the trigger chain recorded in the first array will be invalidated, and the information of the currently input matching memory address trigger will be updated to the first array. If the instruction of the currently input matching memory address trigger has a younger age than the instruction corresponding to the trigger in the first array recorded locally, then the information of the currently input matching memory address trigger will be updated to the second array.

[0093] (2) If the first array is stored locally but the second array is not stored, and the information in the first array is not the matching information of the triggers in the trigger chain, if the age of the instruction matched by the currently input memory address trigger is different from that of the instruction matched by the instruction address trigger, then the first array is updated to the matching information of the trigger corresponding to the instruction with the older age; if the age of the instruction matched by the currently input memory address trigger is the same as that of the instruction matched by the instruction address trigger, then the execution action of the currently input memory address trigger is determined to be the execution action of the instruction address trigger. If the execution actions are inconsistent, then the execution action is determined to be the first preset action, and the first array is updated to the first target trigger matching information corresponding to the first preset action.

[0094] In other words, if only the first array is recorded locally and the first array is not a trigger chain, then among the triggers in the first array and the memory address triggers that match the current input, the older one has higher priority. If the two are the same age, then the execution actions of the two are further judged. If the execution actions of the two are consistent, it can be determined that the trigger type of the first array recorded locally is an instruction address trigger, so the first array recorded locally has higher priority. If the execution actions of the two are inconsistent, the one whose execution action is "entry debug mode" has higher priority. The trigger information with higher priority is used to update the first array recorded locally in the next cycle.

[0095] (3) If the first array and the second array are stored locally, and the information in the first array is the matching information of the triggers in the trigger chain, and the information in the second array is the matching information of the triggers in the trigger chain or the matching information of triggers not in the trigger chain, then if the instruction matched by the currently input memory address trigger is the same age as the instruction matched by the instruction address trigger in the first array, then the second array is invalid; if the instruction matched by the currently input memory address trigger is older than the instruction matched by the instruction address trigger in the first array, then the second array is invalid, and the first array is updated to the matching information of the previously input memory address trigger .... If the matched instruction is younger and older than the instruction matched by the instruction address trigger in the second array, then the second array is updated with the matching information of the currently input memory address trigger. If the instruction matched by the currently input memory address trigger is younger than the instruction matched by the instruction address trigger in the first array and has the same age as the instruction matched by the instruction address trigger in the second array, and the information in the second array is not the matching information of the trigger in the trigger chain, then it is determined whether the execution action of the currently input memory address trigger is the same as the execution action of the instruction address trigger in the second array. If the execution actions are inconsistent, then the execution action is determined to be the second preset action, and the second array is updated with the matching information of the second target trigger corresponding to the second preset action.

[0096] In other words, if the local database contains two sets of information: the first set represents the matching information for a trigger chain, and the second set represents the matching information for a trigger chain or a single trigger, and the instruction of the currently input matching memory address trigger has the same age as the instruction corresponding to the first number recorded locally, then the memory address triggers in this trigger chain also match, and the trigger chain in the first set matches. In this case, the second set is invalidated. If the currently input matching memory address trigger is older than the instruction corresponding to the first and second sets recorded locally, and the currently input matching memory address trigger has a higher priority, then both the first and second sets are invalidated, and the information of the currently input matching memory address trigger is updated in the first set. If the instruction of the currently input matching memory address trigger is younger than the instruction in the first set recorded locally but older than the instruction corresponding to the second set recorded locally, then the first set remains unchanged, and the second set is invalidated. The system first sets up an array of memory access address triggers and updates the second array with the information of the currently matched memory access address triggers. If the instruction of the currently matched memory access address trigger is younger than the instruction corresponding to both arrays recorded locally, then both arrays remain unchanged. If the instruction of the currently matched memory access address trigger is younger than the instruction corresponding to the first array recorded locally but the same age as the instruction corresponding to the second array recorded locally, and if the second array is a trigger chain, then the currently matched memory access address trigger is a trigger in that chain, and the trigger chain matches. If the second array is not a trigger chain, then the execution actions of both are further determined. If the execution actions are the same, then the trigger type of the second array recorded locally is an instruction address trigger, and therefore the priority of the second array recorded locally is higher than the priority of the currently matched memory access address trigger. If the execution actions are different, the execution action of "entry debug mode" has a higher priority, and the trigger matching information of the higher priority set is used to update the second array recorded locally in the next cycle.

[0097] It should be noted that the trigger detection information synchronization module records the matching information of high-priority triggers. After updating the local information recorded by the trigger detection information synchronization module in this period according to the second rule mentioned above, it sends the information of the first array to the trigger submission module in real time.

[0098] In some embodiments, determining that the target trigger has been triggered includes the following steps: determining whether the target trigger has been triggered based on the exception priority of the instruction.

[0099] The exception priorities of the instructions are shown in Table 1:

[0100] Table 1

[0101]

[0102] In some embodiments, determining the action to be executed based on the information of the target trigger (step S13) includes the following steps: determining the action to be executed based on the information of the target trigger and the priority of the flushing pipeline.

[0103] In some embodiments, the priority of debug requests is higher than the priority of interrupts, which is higher than the priority of exceptions in debug mode, which is higher than the priority of exceptions in non-debug mode; wherein, among the priorities of debug requests, the priority of trigger execution actions is higher than the priority of software breakpoints, which is higher than the priority of debug interrupt requests, which is higher than the priority of single-step debug requests.

[0104] The trigger commit module consists of two submodules: Trig Commit1 and Trig Commit2. The first submodule handles the logic under the reordering cache. In this submodule, when a trigger-matched instruction is committed, the trigger's activation is determined based on its priority relative to any exceptions on that instruction. Exception priorities are shown in Table 1. For triggers determined to be activated, their information (such as the address of the matching instruction and the configured execution action) is output to the second submodule configured in the Instruction Execution Unit (IRU). In the second submodule, further processing is performed based on the priorities of the execution action and interrupts, exceptions, and debug requests after trigger activation. This ultimately determines the next execution action and state of the processor core. Priority determination in this part follows the definitions in the RISC-CV manual. The priority definitions for the flush pipeline are as follows:

[0105] Debug requests > Interruptions > Exceptions in debug mode > Exceptions in non-debug mode > Other;

[0106] The priority of debug requests is defined as follows: trigger (action == 1) > software breakpoint > debug module halt request > single-step debugging.

[0107] The trigger submission module is the part most coupled with the main water in this embodiment of the disclosure. However, this part is related to the microarchitecture of the processor core, and when the number and types of triggers are extended based on the scheme of this embodiment of the disclosure, it does not involve the modification of this part. Therefore, this part will not be described in detail.

[0108] This disclosure provides a RISC-based hardware breakpoint and hardware watchpoint scheme based on superscalar out-of-order pipelines. The scheme can be easily extended based on specific superscalar out-of-order pipeline architectures. Compared to schemes that temporarily store breakpoint detection information using reorder buffers or other dedicated queues, this disclosure offers lower hardware overhead and power consumption for processing breakpoint detection information. In the RISC instruction set manual, hardware breakpoints and hardware watchpoints are implemented based on debugging logic and trigger logic. The core of implementing hardware breakpoints and hardware watchpoints lies primarily in the implementation of triggers. Therefore, this disclosure focuses on the design and implementation of triggers based on superscalar out-of-order pipelines, mainly consisting of a trigger detection module, a trigger detection information synchronization module, a trigger control register, and a trigger commit module.

[0109] The embodiments disclosed herein have good scalability. When expanding the scheme, only minor modifications are needed to the trigger detection strategy and the rules for trigger detection information synchronization. Furthermore, when caching trigger matching information, the embodiments disclosed herein only require a queue with a depth of 2, which saves hardware overhead compared to directly storing it in a reordering cache or directly storing it in a dedicated queue without trigger detection and information synchronization.

[0110] The embodiments disclosed herein are applicable to any application that uses a processor, especially a high-performance processor, such as a CPU / SOC chip, a mobile phone, a computer, a data center server, etc.

[0111] This disclosure also provides a breakpoint debugging device, such as... Figure 5 As shown, the breakpoint debugging device includes:

[0112] The trigger detection module 501 is used to perform trigger detection for each cycle and determine the trigger matching information for the cycle, wherein the trigger matching information is the information of the trigger that matches the instruction;

[0113] The trigger detection information synchronization module 502 is used to perform priority arbitration on the trigger matching information of different periods to obtain the information of the target trigger;

[0114] The trigger submission module 503 is used to determine an execution action based on the information of the target trigger when the instruction matched by the target trigger reaches the submission stage and it is determined that the target trigger has been triggered, so that the processing core can execute the execution action.

[0115] This disclosure also provides a breakpoint debugging device, such as... Figure 6As shown, the breakpoint debugging device includes: one or more processors 601, a storage device 602, and one or more I / O interfaces 603; wherein, the storage device 602 stores one or more programs, and when the one or more programs are executed by the one or more processors, the one or more processors 601 implement the breakpoint debugging method provided in the foregoing embodiments; the I / O interface 603 is connected between the processor 601 and the storage device 601, and is configured to realize information interaction between the processor 601 and the storage device 602.

[0116] The processor 601 is a device with data processing capabilities, including but not limited to a central processing unit (CPU); the storage device 602 is a device with data storage capabilities, including but not limited to random access memory (RAM, more specifically SDRAM, DDR, etc.), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), and flash memory (FLASH); the I / O interface (read / write interface) 603 is connected between the processor 601 and the storage device 602, enabling information exchange between the processor 601 and the storage device 602, including but not limited to a data bus.

[0117] This disclosure also provides a computer-readable medium having a computer program stored thereon, wherein the computer program, when executed, implements the breakpoint debugging method provided in the foregoing embodiments.

[0118] It will be understood by those skilled in the art that all or some of the steps in the methods disclosed above, and the functional modules / units in the apparatus, can be implemented as software, firmware, hardware, and suitable combinations thereof. In hardware implementations, the division between functional modules / units mentioned in the above description does not necessarily correspond to the division of physical components; for example, a physical component may have multiple functions, or a function or step may be performed collaboratively by several physical components. Some or all physical components may be implemented as software executed by a processor, such as a central processing unit, digital signal processor, or microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit. Such software may be distributed on a computer-readable medium, which may include computer storage media (or non-transitory media) and communication media (or transient media). As is known to those skilled in the art, the term computer storage media includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technologies, CD-ROM, digital versatile disc (DVD) or other optical disc storage, magnetic cartridges, magnetic tape, disk storage or other magnetic storage devices, or any other medium that can be used to store desired information and can be accessed by a computer. Furthermore, it is well known to those skilled in the art that communication media typically contain computer-readable instructions, data structures, program modules, or other data in modulated data signals such as carrier waves or other transmission mechanisms, and may include any information delivery medium.

[0119] Example embodiments have been disclosed herein, and while specific terminology has been used, it is for illustrative purposes only and should be construed as such, and is not intended to be limiting. In some instances, it will be apparent to those skilled in the art that features, characteristics, and / or elements described in conjunction with particular embodiments may be used alone, or in combination with features, characteristics, and / or elements described in conjunction with other embodiments, unless otherwise expressly indicated. Therefore, those skilled in the art will understand that various changes in form and detail may be made without departing from the scope of the invention as set forth in the appended claims.

Claims

1. A breakpoint debugging method, characterized in that, include: For each clock cycle, trigger detection is performed to determine the trigger matching information for that clock cycle, wherein the trigger matching information is the information of the trigger that matches the instruction; Priority arbitration is performed on the matching information of the triggers for different clock cycles to obtain the information of the target trigger; When an instruction matching the target trigger arrives at the submission stage and it is determined that the target trigger has been triggered, an execution action is determined based on the information of the target trigger, so that the processing core can execute the execution action; The step of performing trigger detection for each clock cycle to determine the trigger matching information for that clock cycle includes: For each first cycle, instruction address trigger detection is performed during the instruction decoding stage to determine the instruction address trigger matching information for the first cycle; wherein, the first cycle is the clock cycle from instruction to the instruction decoding stage; the instruction address trigger matching information for the first cycle includes the information of the instruction address trigger corresponding to the oldest instruction that matches the trigger within the first cycle, or, the information of the instruction address trigger corresponding to the oldest instruction that matches the trigger within the first cycle and the information of the instruction address trigger corresponding to the second oldest instruction that matches the trigger within the first cycle; For each second cycle, memory address trigger detection is performed during the memory access execution phase to determine the memory address trigger matching information for the second cycle; wherein, the second cycle is the clock cycle in which the instruction arrives at the memory access execution phase; the memory address trigger matching information for the second cycle includes the information of the memory address trigger corresponding to the oldest instruction that matches the trigger within the second cycle, or the information of the memory address trigger corresponding to the oldest instruction that matches the trigger within the second cycle and the information of the memory address trigger corresponding to the second oldest instruction that matches the trigger within the second cycle.

2. The method as described in claim 1, characterized in that, The determination of the instruction address trigger matching information for the first cycle includes: Based on the trigger chain membership attribute of the instruction address trigger and the age and type of the instruction in the first cycle, determine the instruction address trigger matching information for the first cycle.

3. The method as described in claim 2, characterized in that, The step of determining the instruction address trigger matching information for the first cycle based on the trigger chain membership attribute of the instruction address trigger and the age and type of the instruction within the first cycle includes: If the trigger that matches the instruction in the first cycle is not a trigger in the trigger chain, the instruction address trigger matching information of the first cycle is determined to be the information of the instruction address trigger corresponding to the oldest instruction among the instructions that match the instruction address triggers in the first cycle. The oldest trigger that matches the instruction in the first cycle is the trigger in the trigger chain, and the instruction matched by the oldest trigger is a memory access instruction. If there are other instruction address triggers that match the instruction in the first cycle, the instruction address trigger matching information of the first cycle is determined to be the information of the trigger chain and the information of the instruction address trigger corresponding to the second oldest instruction among the instructions matched by the instruction address triggers in the first cycle. If the oldest trigger that matches the instruction in the first cycle is not a trigger in the trigger chain, the trigger matching information of the instruction address in the first cycle is determined to be the information of the oldest trigger that matches the instruction in the first cycle.

4. The method as described in claim 1, characterized in that, The determination of the memory access address trigger matching information for the second cycle includes: In the presence of a trigger chain, the memory address trigger matching information for the second cycle is determined based on the matching results of the instructions in the second cycle with the memory address triggers, the matching results of the instruction address triggers in the trigger chain in the first cycle, the trigger chain membership attribute of the memory address triggers, the age of the instructions in the second cycle, and the age of the instructions in the trigger chain that match the instruction address triggers.

5. The method as described in claim 4, characterized in that, The step of determining the memory address trigger matching information for the second cycle based on the matching results of instructions and memory address triggers in the second cycle, the matching results of instruction address triggers in the trigger chain in the first cycle, the trigger chain membership attribute of the memory address triggers, the age of instructions in the second cycle, and the age of instructions in the trigger chain that match instruction address triggers, includes: If there is no matching trigger chain in the second cycle, and there is no trigger chain among the triggers that do not match the instruction in the second cycle, or if there is no matching trigger chain in the second cycle, and there is a trigger chain among the triggers that do not match the instruction in the second cycle, but the instruction address trigger that matches in the first cycle is younger than the oldest trigger among the memory address triggers that match in the second cycle, then the memory address trigger matching information of the second cycle is determined to be the information of the oldest trigger among the memory address triggers that match in the second cycle. If no memory access trigger matches the instruction in the second cycle, or if only the memory access address trigger in the trigger chain matches in the second cycle and the instruction address trigger in the trigger chain does not match the instruction in the first cycle, then no memory access address trigger matching information for the second cycle will be generated. If the instruction matched by the instruction address trigger in the trigger chain is older than the target instruction, and the memory address trigger in the trigger chain is matched within the second cycle, the memory address trigger matching information of the second cycle is determined to be the information of the memory address trigger in the trigger chain. If the instruction matched by the instruction address trigger in the trigger chain is older than the target instruction, and the memory address trigger in the trigger chain does not match the instruction in the second cycle, and other memory address triggers outside the trigger chain match the instruction in the second cycle, the memory address trigger matching information in the second cycle is determined to be the information of the memory address triggers not matching in the trigger chain and the information of the oldest trigger among the other memory address triggers outside the trigger chain that match the instruction in the second cycle. If the instruction matched by the instruction address trigger in the trigger chain is older than the target instruction, and the memory address trigger in the trigger chain does not match the instruction in the second cycle, and the memory address triggers in other trigger chains besides the trigger chain match the instruction in the second cycle, then the memory address trigger matching information in the second cycle is determined to be the information of the memory address triggers not matching in the trigger chain and the information of the memory address triggers in other trigger chains besides the trigger chain that match the instruction in the second cycle. The target instruction is the oldest instruction matched by any memory address trigger other than the memory address triggers in the trigger chain during the second cycle.

6. The method as described in claim 1, characterized in that, The priority arbitration of the trigger matching information of different periods to obtain the target trigger information includes: According to the preset first rule and the preset second rule, priority arbitration is performed on the instruction address trigger matching information of the first cycle and the memory access address trigger matching information of the second cycle to obtain the information of the target trigger; the first rule is a rule based on the trigger chain membership attribute, and the second rule is a rule based on the instruction age relationship between the currently input memory access address trigger matching information and the saved trigger matching information.

7. The method as described in claim 6, characterized in that, The first array records the oldest trigger matching information in the current pipeline, and the second array records the second oldest trigger matching information in the current pipeline; the first rule includes at least one of the following: If the trigger matching information in the first array is not the information of a trigger in the trigger chain, the second array is invalid. When the trigger matching information of the first array is the information of the triggers in the trigger chain, the trigger matching information of the second array includes the information of the trigger chain or the information of the triggers outside the trigger chain. If the trigger matching information in the first array is the information of the triggers in the trigger chain, and both the instruction address triggers and the memory access address triggers in the trigger chain match the instruction, then the second array is invalid. For either the first array or the second array, if the trigger matching information of the array is the information of the triggers in the trigger chain, and the instruction address trigger in the trigger chain matches the instruction, and the memory access address trigger in the trigger chain does not match the instruction, then the array is invalid; wherein, if the array is the first array, then the second array is marked as the first array in this cycle.

8. The method as described in claim 6, characterized in that, The first array records the matching information of the oldest trigger in the current pipeline, and the second array records the matching information of the second oldest trigger in the current pipeline; the second rule includes at least one of the following: If the first array is stored locally but the second array is not stored, and the information in the first array is the matching information of the instruction address triggers in the trigger chain, then if the instruction matched by the currently input memory address trigger has the same age as the instruction matched by the instruction address trigger, the trigger chain of the first array is matched; if the instruction matched by the currently input memory address trigger is older than the instruction matched by the instruction address trigger in the trigger chain of the first array, then the first array is updated with the matching information of the currently input memory address trigger; if the instruction matched by the currently input memory address trigger is younger than the instruction matched by the instruction address trigger, then the second array is updated with the matching information of the currently input memory address trigger. If the first array is stored locally but the second array is not stored, and the information in the first array is not the matching information of the triggers in the trigger chain, if the age of the instruction matched by the currently input memory address trigger is different from that of the instruction matched by the instruction address trigger, then the first array is updated to the matching information of the trigger corresponding to the instruction with the older age; if the age of the instruction matched by the currently input memory address trigger is the same as that of the instruction matched by the instruction address trigger, then it is determined that the execution action of the currently input memory address trigger is different from that of the instruction address trigger. If the execution actions are inconsistent, then the execution action is determined to be the first preset action, and the first array is updated to the first target trigger matching information corresponding to the first preset action. If the first array and the second array are stored locally, and the information in the first array is matching information of triggers in the trigger chain, and the information in the second array is matching information of triggers in the trigger chain or matching information of triggers not in the trigger chain, then if the instruction matched by the currently input memory address trigger is the same age as the instruction matched by the instruction address trigger in the first array, then the second array is invalid; if the instruction matched by the currently input memory address trigger is older than the instruction matched by the instruction address trigger in the first array, then the second array is invalid, and the first array is updated to the previously input memory address trigger matching information; if the instruction matched by the currently input memory address trigger is older than the instruction matched by the instruction address trigger in the first array, then the second array is invalid, and the first array is updated to the previously input memory address trigger matching information; if the instruction matched by the currently input memory address trigger is older than the instruction matched by the instruction address trigger in the first array, then the second array is invalid, and the first array is updated to the previously input memory address trigger matching information. If the matched instruction is younger and older than the instruction matched by the instruction address trigger in the second array, then the second array is updated with the matching information of the currently input memory address trigger. If the instruction matched by the currently input memory address trigger is younger than the instruction matched by the instruction address trigger in the first array and has the same age as the instruction matched by the instruction address trigger in the second array, and the information in the second array is not the matching information of the trigger in the trigger chain, then it is determined that the execution action of the currently input memory address trigger is inconsistent with the execution action of the instruction address trigger in the second array. If the execution action is inconsistent, then the execution action is determined to be the second preset action, and the second array is updated with the matching information of the second target trigger corresponding to the second preset action.

9. The method as described in claim 1, characterized in that, Determining the target trigger to fire includes: Whether the target trigger is triggered is determined based on the exception priority of the instruction.

10. The method as described in claim 1, characterized in that, Determining the action to be executed based on the information of the target trigger includes: The action to be executed is determined based on the information from the target trigger and the priority of the flushing line.

11. The method as described in claim 10, characterized in that, In the priority of the flushing pipeline, the priority of debug requests is higher than that of interrupts, which is higher than that of exceptions in debug mode, which is higher than that of exceptions in non-debug mode; among the priorities of debug requests, the priority of trigger execution actions is higher than that of software breakpoints, which is higher than that of debug interrupt requests, which is higher than that of single-step debug requests.

12. A breakpoint debugging device, characterized in that, include: A trigger detection module is used to perform trigger detection for each clock cycle and determine the trigger matching information for the clock cycle. The trigger matching information is the information of triggers that match the instruction. Specifically, for each first cycle, instruction address trigger detection is performed during the instruction decoding stage to determine the instruction address trigger matching information for the first cycle. The first cycle is the clock cycle from the instruction to the instruction decoding stage. The instruction address trigger matching information for the first cycle includes the information of the instruction address trigger corresponding to the oldest instruction that matches the trigger within the first cycle, or the information of the instruction address trigger corresponding to the oldest instruction that matches the trigger within the first cycle and the... Information on the instruction address trigger corresponding to the second oldest instruction that matches the trigger within the first cycle; for each second cycle, memory address trigger detection is performed during the memory access execution phase to determine the memory address trigger matching information for the second cycle; wherein, the second cycle is the clock cycle in which the instruction arrives at the memory access execution phase; the memory address trigger matching information for the second cycle includes information on the memory address trigger corresponding to the oldest instruction that matches the trigger within the second cycle, or information on the memory address trigger corresponding to the oldest instruction that matches the trigger within the second cycle and information on the memory address trigger corresponding to the second oldest instruction that matches the trigger within the second cycle; The trigger detection information synchronization module is used to perform priority arbitration on the trigger matching information of different clock cycles to obtain the information of the target trigger. The trigger submission module is used to determine an execution action based on the information of the target trigger when the instruction matched by the target trigger reaches the submission stage and it is determined that the target trigger has been triggered, so that the processing core can execute the execution action.

13. A breakpoint debugging device, comprising: One or more processors; A storage device on which one or more programs are stored; When the one or more programs are executed by the one or more processors, the one or more processors implement the breakpoint debugging method as described in any one of claims 1-11; One or more I / O interfaces are connected between the processor and the storage device and configured to enable information interaction between the processor and the storage device.

14. A computer-readable medium having a computer program stored thereon, wherein, When the program is executed, it implements the breakpoint debugging method as described in any one of claims 1-11.

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