Dma transfer method and apparatus

Abstract

The present application provides a DMA transmission method and device, by obtaining a DMA command descriptor, a transmission command is obtained; wherein the DMA descriptor at least includes a maximum parallel transmission unit size and a destination address; the transmission command is distributed to a target number of DMA transmission units according to the maximum parallel transmission unit size, and a plurality of parallel burst transmission commands are obtained; wherein the parallel burst transmission command includes the target transmission command of all DMA transmission units; the parallel burst transmission command is executed. The present application increases the field of the maximum parallel transmission unit size in the DMA descriptor, disperses the user's data setting or data moving demand for the specified range address to a plurality of PORTs for parallel transmission, and conforms to the maximum parallel transmission unit size required by the destination address terminal MEM, so that the performance can reach the maximum performance provided by the terminal MEM as much as possible, and the data transmission efficiency is increased.

Description

Technical Field

[0001] This invention relates to the field of data storage technology, and in particular to a DMA transfer method and apparatus. Background Technology

[0002] Currently, there are two main methods for accessing data between memory (MEM): one is through the Central Processing Unit (CPU), and the other is through Direct Memory Access (DMA). When transferring data via the CPU, the CPU needs to execute a series of read and write instructions to move the data. Specifically, the CPU first reads the data from the source address and then writes the data to the destination address. While this method is simple, it consumes a significant amount of CPU resources, preventing the CPU from efficiently executing other tasks and thus affecting the overall system performance. DMA is a more efficient data transfer method. A DMA controller can transfer data directly between memory and peripherals without going through the CPU. This way, the CPU only needs to intervene at the beginning and end of the transfer, greatly reducing the CPU's burden and improving the system's parallel processing capabilities.

[0003] DMA can complete large-scale data transfers without consuming CPU resources, thus offering significant efficiency advantages when processing large datasets. The DMA controller can operate independently of the CPU, performing data transfers in the background, thereby improving the overall system's parallel processing capabilities.

[0004] However, in certain scenarios, traditional DMA devices suffer from performance limitations. Examples of such scenarios are as follows: In a bus system, a DMA device connects to PORT0 of a DDRC (Dynamic Random Access Memory Controller) via the bus to read and write data to PORT0. Limited by bus and interface bandwidth, the data transfer performance between the DMA device and DDRC PORT0 has an upper limit. A DDRC typically controls multiple DRAM (Dynamic Random Access Memory) chips and provides multiple PORTs, allowing parallel access from multiple PORTs. Theoretically, multiple PORT access can increase bandwidth and improve overall transfer performance. However, simply using multiple DMA devices, connecting DMA0 to PORT0 and DMA1 to PORT1, and performing parallel data transfer to the DDRC by multiple DMAs, can very likely result in worse performance than a single DMA. The reason is as follows: Although the DDRC provides multiple PORTs to increase bandwidth, its internal processing is limited by the DRAM chips.

[0005] Specifically, DDRC address configuration typically maps different address bits to access different CS (ChipSelect), BG (Bank Group), BA (Bank Address), COL (Column Address), and ROW (Row Address). If different rows need to be accessed, precharge and activation are required first. Therefore, the ROW bit is usually placed in the high-order bits of the address. This avoids the problem of DDRC needing to frequently precharge and activate when accessing a DRAM address range, which would reduce performance.

[0006] If the addresses of the two ports are on the same ROW, the DDRC can quickly respond on both ports. If the addresses of the two ports are not on the same ROW, the DDRC cannot quickly respond on both ports. It can be assumed that the maximum address range with unchanged ROW is the maximum parallel transmission range of the two ports.

[0007] Using a single DMA device to transfer data from a single port ensures that the addresses are sequential and that the DDRC does not frequently switch ROWs, thus preventing performance degradation. However, using 2DMA from two ports requires user-configured address settings, making it difficult to guarantee that the addresses on both ports are on the same ROW. Operations on different ROWs cause frequent precharge and activation within the DDRC, severely reducing DMA transfer performance. In similar scenarios, traditional DMA devices cannot improve transfer performance simply by increasing the number of devices; their performance remains limited. Summary of the Invention

[0008] This invention provides a DMA transfer method and apparatus to overcome the limitations of transmission performance in the prior art and improve transmission efficiency.

[0009] This invention provides a DMA transfer method, comprising the following steps: Obtain the DMA command descriptor to get the transfer command; wherein, the DMA command descriptor includes at least the maximum parallel transfer unit size and the destination address; The transmission command is allocated to the target number of DMA transmission units according to the maximum parallel transmission unit size, resulting in multiple parallel burst transmission commands; wherein, the parallel burst transmission command includes the target transmission command of all DMA transmission units; Execute the parallel burst transmission command.

[0010] According to a DMA transfer method provided by the present invention, the transfer command is allocated to a target number of DMA transfer units according to the maximum parallel transfer unit size according to a preset formula; The preset formula includes: Where α refers to the DMA transfer unit number, β refers to the number of targets, δ refers to the δth parallel transfer, DMA_DEST_ADDR(α,β,δ) means that there are β DMA transfer units in total, the destination address of the δth parallel transfer of the αth DMA transfer unit, DEST_ADDR_ALIGNED refers to the base address of the simplified destination address, which satisfies the alignment constraint of the maximum parallel transfer unit size, and MULTI_SIZE refers to the maximum parallel transfer unit size.

[0011] According to a DMA transfer method provided by the present invention, the DMA transfer unit executes the target transfer command in parallel.

[0012] According to a DMA transfer method provided by the present invention, a target number of DMA transfer units are connected to a target number of ports on a bus.

[0013] According to a DMA transfer method provided by the present invention, the parallel burst transfer command is executed, and then the method further includes: After all parallel burst transfer commands are completed, the completion status is written to the DMA completion status buffer.

[0014] According to a DMA transfer method provided by the present invention, after completing all parallel burst transfer commands, the completion status is written to the DMA completion status buffer, and then the method further includes: Users retrieve command completion status based on the DMA completion status cache.

[0015] The present invention also provides a DMA transfer device, comprising the following modules: The command module is used to obtain a DMA command descriptor and get a transfer command; wherein, the DMA command descriptor includes at least the maximum parallel transfer unit size and the destination address; The control module is used to allocate the transmission command to a target number of DMA transmission units according to the maximum parallel transmission unit size, thereby obtaining multiple parallel burst transmission commands; wherein, the parallel burst transmission command includes the target transmission command of all DMA transmission units. An execution module is used to execute the parallel burst transmission command.

[0016] The present invention also provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement the DMA transfer method as described above.

[0017] The present invention also provides a non-transitory computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the DMA transfer method as described above.

[0018] The present invention also provides a computer program product, including a computer program that, when executed by a processor, implements any of the DMA transfer methods described above.

[0019] The DMA transfer method and apparatus provided by this invention obtain transfer commands by acquiring a DMA command descriptor; wherein the DMA command descriptor includes at least a maximum parallel transfer unit size and a destination address; the transfer commands are allocated to a target number of DMA transfer units according to the maximum parallel transfer unit size, resulting in multiple parallel burst transfer commands; wherein the parallel burst transfer commands include the target transfer commands for all DMA transfer units; and the parallel burst transfer commands are executed. This invention adds a maximum parallel transfer unit size field to the DMA command descriptor, distributing the user's data setting or data transfer requirements for a specified range of addresses across multiple ports for parallel transfer, while conforming to the maximum parallel transfer unit size required by the destination terminal MEM, thereby maximizing the performance that the terminal MEM can provide and increasing data transfer efficiency. Attached Figure Description

[0020] To more clearly illustrate the technical solutions in this invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0021] Figure 1 This is a flowchart illustrating the DMA transfer method provided by the present invention.

[0022] Figure 2 This is a schematic diagram illustrating an implementation scenario of the DMA transfer method provided by the present invention.

[0023] Figure 3 This is a schematic diagram illustrating the execution of parallel burst transfer commands in an embodiment of the DMA transfer method provided by the present invention.

[0024] Figure 4 This is a schematic diagram of the DMA transfer device provided by the present invention.

[0025] Figure 5 This is a schematic diagram of the structure of the electronic device provided by the present invention. Detailed Implementation

[0026] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.

[0027] The following is combined with Figures 1-3 The DMA transfer method of the present invention is described. Figure 1 This is a flowchart illustrating the DMA transfer method provided by the present invention, as shown below. Figure 1 As shown, the method includes the following steps.

[0028] Step 110: Obtain the DMA command descriptor to get the transfer command; wherein the DMA command descriptor includes at least the maximum parallel transfer unit size and the destination address.

[0029] It should be noted that DMA, or Direct Memory Access, as referred to in this invention, is a technology that allows certain hardware subsystems to directly access system memory without going through the Central Processing Unit (CPU).

[0030] This invention does not restrict the source of the DMA command descriptor obtained in step 110. In one specific embodiment, the central processing unit generates and sends the DMA command descriptor and writes it to the DMA command descriptor via the control bus.

[0031] A DMA command descriptor includes at least the maximum parallel transfer unit size and the destination address. In some embodiments, the DMA command descriptor also includes an ID, source address, mode, transfer length, set data, and set data size.

[0032] Furthermore, the setting of the maximum parallel transfer unit size is related to the configuration of the Dynamic Random Access Memory Controller (DDRC). Specifically, it is the maximum address range of two parallel ports that do not require time-consuming ROW switching operations within the DDRC. This invention adds a maximum parallel transfer unit size to the DMA command descriptor, providing finer control over DMA transfers and ensuring that parallel transfers achieve the best results.

[0033] The dynamic random access memory controller is a hardware or software component used to manage dynamic random access memory (DRAM). It is responsible for coordinating data read and write operations to ensure efficient memory usage and performance optimization.

[0034] A transfer command refers to the transfer action corresponding to a DMA command descriptor, including setting data within a specified address range and moving data from the source address to the destination address.

[0035] Step 120: Distribute the transmission command to the target number of DMA transmission units according to the maximum parallel transmission unit size to obtain multiple parallel burst transmission commands; wherein, the parallel burst transmission command includes the target transmission command of all DMA transmission units.

[0036] It is understood that traditional DMA, through parsing its configured DMA command descriptor, allows the DMA transfer module to perform data setting functions within a specified address range and data transfer functions from the source address to the destination address. After completion, the result is written to the command completion status area, awaiting reading to determine if the command corresponding to the DMA command descriptor has been executed successfully by the DMA device. This invention does not directly execute the transfer action corresponding to the DMA command descriptor, but rather decomposes it and executes the decomposed transfer command.

[0037] Specifically, in step 120, after obtaining the DMA command descriptor, the field is parsed. That is, based on the minimum parallel transfer unit size field in the DMA command descriptor, the amount of data to be transferred in parallel is divided, and the DMA transfer command is decomposed into parallel operations on multiple DMA transfer units. The destination address and transfer size of the parallel operations are within the range of the maximum parallel transfer size.

[0038] In other words, in order to ensure that the operating PORT can achieve the highest parallel performance, the present invention configures and divides the transmission destination address of the DMA transmission unit according to the maximum parallel transmission size, so that the DDRC does not need to perform time-consuming ROW switching operations, and the performance can reach the maximum performance that the terminal MEM can provide.

[0039] The aforementioned port (PORT) is used to describe a logical channel in the memory controller or bus interface that allows hardware devices or system components to read and write to memory.

[0040] Furthermore, the aforementioned "burst" refers to an efficient data transmission mode. In this mode, data is transmitted in consecutive blocks (i.e., bursts) rather than as individual bytes or words. Burst transmissions can significantly improve data transmission efficiency because they reduce the number of setup and synchronization steps required between each transmission on the bus or interface.

[0041] Step 130: Execute the parallel burst transmission command.

[0042] In step 130, after receiving multiple parallel burst transfer commands, the DMA transfer unit performs parallel transfer according to the corresponding parallel burst transfer commands. After the current parallel burst transfer is completed, the next parallel burst transfer is issued, until all transfers required by the DMA command corresponding to the DMA command descriptor are completed. This ensures that the data transferred in each parallel transfer is within the maximum parallel transfer unit size, ensuring that the PORT of the operation can achieve the highest parallel performance.

[0043] It should be emphasized that during the execution process, all parallel burst transmission commands can be allocated at once and then executed one by one, or execution can begin immediately after the current parallel burst transmission command is obtained, and then the next allocated parallel burst transmission command can be executed after the current command is completed. This invention does not limit this.

[0044] The following provides a further explanation of step 120. In some embodiments, the transmission command is allocated to the target number of DMA transmission units according to the maximum parallel transmission unit size using a preset formula; The preset formula includes: Where α refers to the DMA transfer unit number, β refers to the target number, i.e. the number of DMA transfer units, δ refers to the δth parallel transfer, DMA_DEST_ADDR(α,β,δ) means that there are β DMA transfer units in total, the destination address of the δth parallel transfer of the αth DMA transfer unit, DEST_ADDR_ALIGNED refers to the base address of the simplified destination address, which satisfies the alignment constraint of the maximum parallel transfer unit size, and MULTI_SIZE refers to the maximum parallel transfer unit size.

[0045] Specifically, the configuration of the DMA transfer unit's destination address in step 120 can be simplified to calculating the DMA destination address using a preset formula.

[0046] Furthermore, in some embodiments, the DMA transfer unit executes the target transfer command in parallel.

[0047] Specifically, the implementation scenario of the present invention includes multiple DMA transfer units. During the decomposition of the transfer command, each DMA transfer unit is divided into destination address configurations according to the maximum parallel transfer unit size to form the target transfer command for each DMA transfer unit. After all DMA transfer units are allocated the target transfer command, the current parallel burst transfer command is obtained. The allocation of the next parallel burst transfer command is carried out in this way.

[0048] Furthermore, based on the above embodiments, in some embodiments, a target number of the DMA transfer units are connected to a target number of ports on the bus.

[0049] Specifically, such as Figure 2 As shown, in the implementation scenario of the present invention, a target number of DMA transfer modules are integrated and connected to a target number of PORTs on the bus, realizing parallel transmission of data through multiple interfaces.

[0050] In this context, a bus refers to a set of wires or channels used in computers and other electronic systems to transmit data, addresses, and control signals. It is a key infrastructure for communication and data exchange between various components within the system.

[0051] This invention adds a field – Maximum Parallel Transfer Unit Size – to the DMA command descriptor. This distributes the user's needs for setting or moving data within a specified range of addresses across multiple ports for parallel transmission, while conforming to the maximum parallel transfer unit size required by the destination terminal MEM. This maximizes the performance that the terminal MEM can provide, thereby improving data transmission efficiency.

[0052] Further, after executing the parallel burst transmission command, the process also includes: After all parallel burst transfer commands are completed, the completion status is written to the DMA completion status buffer.

[0053] Specifically, once all the decomposed commands have been executed, the completion status is written to the DMA completion status buffer, waiting to be read out so that the user can determine whether the command corresponding to the DMA command descriptor has been executed.

[0054] Furthermore, based on the above embodiments, after completing all parallel burst transmission commands, the completion status is written to the DMA completion status buffer, and then the process further includes: Users retrieve command completion status based on the DMA completion status cache.

[0055] Specifically, during implementation, the user (CPU, etc.) obtains the command completion status from the DMA completion status cache through the control bus and completes the required DMA transfer.

[0056] Based on the above embodiments, a specific embodiment is given for more detailed explanation. For example... Figure 3As shown, in a certain configuration of the DDRC in this embodiment, the maximum parallel transmission unit size is 128KiB. If the two ports of the DDRC receive reads and writes that are not within the same 128KiB aligned address range, the DDRC needs to continuously switch ROWs internally to provide corresponding responses on the two ports. In this case, the performance of multi-port access is not only not improved, but is also lower than that of single-port access. If the address range of the two parallel ports can be guaranteed to be within the same 128KiB address range, the DDRC does not need to perform time-consuming ROW switching operations internally and can quickly provide corresponding responses on the two ports. In this case, the performance of multi-port access is higher than that of single-port access, thus improving transmission efficiency.

[0057] In existing technologies, if two traditional DMAs require multi-core CPUs for configuration, it is difficult to guarantee that the two DMAs can write in parallel within the same 128KiB range. If the length of a single transfer is greater than 128KiB, even more problems will arise, making it difficult to achieve.

[0058] Based on the DMA transfer method provided by this invention, if we want to achieve a transfer from MEM_A to DDR_A, with a source address of 0x40, a destination address of 0x10000040, and a transfer size of 256 KiB, we can directly configure the write operation in the descriptor to achieve parallel writing. Specifically, allocate data to DMA_0 from 0x10000040 to 0x1000FFFF, with a transfer size of 65472 bytes; allocate data to DMA_1 from 0x10010000 to 0x1001FFFF, with a transfer size of 64 KiB. These two transfers can be performed in parallel. After the current transfer is completed, the data is then allocated to DMA_0. Starting from 0x10020000 to 0x1002FFFF, a transfer size of 64 KiB is allocated to DMA_1. From 0x10030000 to 0x1003FFFF, a transfer size of 64 KiB is completed in parallel and then allocated to DMA_0. From 0x10040000 to 0x1004003F, a transfer size of 64 Bytes is completed. After all transfers are complete, the results are written to the command completion status area, thus completing this transfer.

[0059] The DMA transfer method provided by this invention obtains a transfer command by acquiring a DMA command descriptor; wherein the DMA command descriptor includes at least a maximum parallel transfer unit size and a destination address; the transfer command is allocated to a target number of DMA transfer units according to the maximum parallel transfer unit size, resulting in multiple parallel burst transfer commands; wherein the parallel burst transfer commands include the target transfer commands for all DMA transfer units; and the parallel burst transfer commands are executed. This invention adds a maximum parallel transfer unit size field to the DMA command descriptor, distributing the user's data setting or data transfer requirements for a specified range of addresses across multiple ports for parallel transfer, while conforming to the maximum parallel transfer unit size required by the destination terminal MEM, thereby maximizing the performance that the terminal MEM can provide and increasing data transfer efficiency.

[0060] The DMA transfer apparatus provided by the present invention will be described below. The DMA transfer apparatus described below can be referred to in correspondence with the DMA transfer method described above. For example... Figure 4 As shown, the device includes the following modules: Command module 410 is used to obtain a DMA command descriptor and obtain a transfer command; wherein, the DMA command descriptor includes at least the maximum parallel transfer unit size and the destination address; The control module 420 is used to distribute the transmission command to a target number of DMA transmission units according to the maximum parallel transmission unit size, thereby obtaining multiple parallel burst transmission commands; wherein, the parallel burst transmission command includes the target transmission command of all DMA transmission units. The execution module 430 is used to execute the parallel burst transmission command.

[0061] According to a DMA transfer device provided by the present invention, the transfer command is allocated to a target number of DMA transfer units according to the maximum parallel transfer unit size according to a preset formula; The preset formula includes: Where α refers to the DMA transfer unit number, β refers to the number of targets, δ refers to the δth parallel transfer, DMA_DEST_ADDR(α,β,δ) means that there are β DMA transfer units in total, the destination address of the δth parallel transfer of the αth DMA transfer unit, DEST_ADDR_ALIGNED refers to the base address of the simplified destination address, which satisfies the alignment constraint of the maximum parallel transfer unit size, and MULTI_SIZE refers to the maximum parallel transfer unit size.

[0062] According to a DMA transfer device provided by the present invention, the DMA transfer unit executes the target transfer command in parallel.

[0063] According to a DMA transfer device provided by the present invention, a target number of DMA transfer units are connected to a target number of ports on a bus.

[0064] According to a DMA transfer device provided by the present invention, after executing the parallel burst transfer command, the device further includes: After all parallel burst transfer commands are completed, the completion status is written to the DMA completion status buffer.

[0065] According to a DMA transfer apparatus provided by the present invention, after completing all parallel burst transfer commands, the completion status is written to the DMA completion status buffer, and then the apparatus further includes: Users retrieve command completion status based on the DMA completion status cache.

[0066] The DMA transfer device provided by this invention obtains transfer commands by acquiring a DMA command descriptor; wherein the DMA command descriptor includes at least a maximum parallel transfer unit size and a destination address; the transfer commands are allocated to a target number of DMA transfer units according to the maximum parallel transfer unit size, resulting in multiple parallel burst transfer commands; wherein the parallel burst transfer commands include the target transfer commands for all DMA transfer units; and the parallel burst transfer commands are executed. This invention adds a maximum parallel transfer unit size field to the DMA command descriptor, distributing the user's data setting or data transfer requirements for a specified range of addresses across multiple ports for parallel transfer, while conforming to the maximum parallel transfer unit size required by the destination terminal MEM, thereby maximizing the performance that the terminal MEM can provide and increasing data transfer efficiency.

[0067] Figure 5 An example is a schematic diagram of the physical structure of an electronic device, such as... Figure 5As shown, the electronic device may include a processor 510, a communications interface 520, a memory 530, and a communication bus 540, wherein the processor 510, communications interface 520, and memory 530 communicate with each other via the communication bus 540. The processor 510 can call logical instructions in the memory 530 to execute a DMA transfer method, which includes: obtaining a DMA command descriptor to obtain a transfer command; wherein the DMA command descriptor includes at least a maximum parallel transfer unit size and a destination address; allocating the transfer command to a target number of DMA transfer units according to the maximum parallel transfer unit size to obtain multiple parallel burst transfer commands; wherein the parallel burst transfer commands include the target transfer commands for all DMA transfer units; and executing the parallel burst transfer commands.

[0068] Furthermore, the logical instructions in the aforementioned memory 530 can be implemented as software functional units and, when sold or used as independent products, can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0069] On the other hand, the present invention also provides a computer program product, the computer program product comprising a computer program that can be stored on a non-transitory computer-readable storage medium. When the computer program is executed by a processor, the computer is able to execute the DMA transfer method provided by the above methods. The method includes: acquiring a DMA command descriptor to obtain a transfer command; wherein the DMA command descriptor includes at least a maximum parallel transfer unit size and a destination address; allocating the transfer command to a target number of DMA transfer units according to the maximum parallel transfer unit size to obtain multiple parallel burst transfer commands; wherein the parallel burst transfer command includes the target transfer command for all DMA transfer units; and executing the parallel burst transfer command.

[0070] In another aspect, the present invention also provides a non-transitory computer-readable storage medium storing a computer program thereon, which, when executed by a processor, implements the DMA transfer method provided by the above methods. The method includes: acquiring a DMA command descriptor to obtain a transfer command; wherein the DMA command descriptor includes at least a maximum parallel transfer unit size and a destination address; allocating the transfer command to a target number of DMA transfer units according to the maximum parallel transfer unit size to obtain multiple parallel burst transfer commands; wherein the parallel burst transfer commands include target transfer commands for all DMA transfer units; and executing the parallel burst transfer commands.

[0071] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Those skilled in the art can understand and implement this without any creative effort.

[0072] Through the above description of the embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus necessary general-purpose hardware platforms, and of course, it can also be implemented by hardware. Based on this understanding, the above technical solutions, in essence or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute the methods described in the various embodiments or some parts of the embodiments.

[0073] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A DMA transfer method, characterized in that, include: Obtain the DMA command descriptor to get the transfer command; wherein, the DMA command descriptor includes at least the maximum parallel transfer unit size and the destination address; the maximum parallel transfer unit size is the maximum address range that can be accessed simultaneously by two parallel PORT ports within the dynamic random access memory controller without the need for row address switching; The transmission command is allocated to the target number of DMA transmission units according to the maximum parallel transmission unit size, resulting in multiple parallel burst transmission commands; wherein, the parallel burst transmission command includes the target transmission command of all DMA transmission units; Execute the parallel burst transmission command.

2. The DMA transfer method according to claim 1, characterized in that, The transmission command is allocated to the target number of DMA transmission units according to the maximum parallel transmission unit size, based on a preset formula. The preset formula includes: ； Where α refers to the DMA transfer unit number, β refers to the number of targets, δ refers to the δth parallel transfer, DMA_DEST_ADDR(α,β,δ) means that there are β DMA transfer units in total, the destination address of the δth parallel transfer of the αth DMA transfer unit, DEST_ADDR_ALIGNED refers to the base address of the simplified destination address, which satisfies the alignment constraint of the maximum parallel transfer unit size, and MULTI_SIZE refers to the maximum parallel transfer unit size.

3. The DMA transfer method according to claim 1, characterized in that, The DMA transfer unit executes the target transfer command in parallel.

4. The DMA transfer method according to claim 1, characterized in that, The target number of DMA transfer units are connected to the target number of ports on the bus.

5. The DMA transfer method according to claim 1, characterized in that, Executing the parallel burst transmission command, followed by: After all parallel burst transfer commands are completed, the completion status is written to the DMA completion status buffer.

6. The DMA transfer method according to claim 5, characterized in that, After all parallel burst transfer commands are completed, the completion status is written to the DMA completion status buffer, followed by: Users retrieve command completion status based on the DMA completion status cache.

7. A DMA transfer device, characterized in that, include: The command module is used to obtain a DMA command descriptor and get a transfer command; wherein, the DMA command descriptor includes at least the maximum parallel transfer unit size and the destination address; the maximum parallel transfer unit size is the maximum address range that can be accessed simultaneously by two parallel PORT ports within the dynamic random access memory controller without the need for row address switching; The control module is used to allocate the transmission command to a target number of DMA transmission units according to the maximum parallel transmission unit size, thereby obtaining multiple parallel burst transmission commands; wherein, the parallel burst transmission command includes the target transmission command of all DMA transmission units. An execution module is used to execute the parallel burst transmission command.

8. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements the DMA transfer method as described in any one of claims 1 to 6.

9. A non-transitory computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the DMA transfer method as described in any one of claims 1 to 6.

10. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by the processor, it implements the DMA transfer method as described in any one of claims 1 to 6.

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