A simulation implementation method and system of controllable ideal voltage source

Abstract

The application discloses a simulation implementation method and system of a controllable ideal voltage source, aiming at solving the problem that voltage sources cannot be dynamically adjusted to adapt to circuit state changes in existing analog circuit simulation. The method includes initializing voltage reference value, selecting the number of power supply voltage sources, configuring power-up parameters, detecting power-up completion and stable voltage, selectively adding noise, detecting circuit stability, setting power-down parameters, executing power-down process, and detecting circuit state after power-down. The application can improve the flexibility and efficiency of simulation, making the circuit design and verification process more efficient and accurate.

Description

Technical Field

[0001] This invention relates to a simulation implementation method for a controllable ideal voltage source, and also to a simulation implementation system for a controllable ideal voltage source, belonging to the field of analog circuit design technology. Background Technology

[0002] In modern electronic devices, voltage sources are core components for power management and signal processing. An ideal voltage source, capable of providing a constant output voltage regardless of load changes, is crucial for fields such as test equipment, analog circuit system simulation, and design. They not only provide stable reference voltages but also ensure the required voltage levels for signal processing and transmission. However, current technologies have limitations in analog circuit simulation: voltage levels can only be predicted before simulation and cannot be flexibly adjusted according to different situations. This necessitates multiple simulations and manual selection when testing complex application scenarios, significantly reducing the efficiency of verification work. Furthermore, analog circuit simulation is slow, involving continuous-time signal processing, especially in complex circuits or large-scale systems, where simulation times are long. Simultaneously, analog circuits in large-scale simulations can consume significant computational resources, especially when requiring extensive parameter scanning and optimization, leading to a substantial increase in resource consumption.

[0003] To address these challenges, controllable ideal voltage sources play a crucial role in the electronics field. First, they provide precise voltage output, essential for testing and validating electronic devices and circuits. Engineers can adjust the voltage source's output to simulate voltage variations under different operating conditions, thereby evaluating the performance and stability of electronic equipment. Second, during the design and verification of electronic systems, controllable ideal voltage sources allow engineers to test and adjust the voltages of individual components, ensuring the proper functioning of the entire system. By simulating voltage conditions under various operating conditions, engineers can construct complex application scenarios, optimize system designs, and identify and resolve potential design problems.

[0004] However, existing technologies still have a common drawback: the voltage source output excitation is based on the voltage value at a pre-set time point, which lacks the ability to respond to changes in the state during simulation. It cannot judge and adjust according to changes in the scenario during simulation, thus limiting the flexibility and accuracy of simulation. Summary of the Invention

[0005] The primary technical problem to be solved by this invention is to provide a simulation implementation method for a controllable ideal voltage source.

[0006] Another technical problem to be solved by the present invention is to provide a simulation implementation system for a controllable ideal voltage source.

[0007] To achieve the above objectives, the present invention adopts the following technical solution:

[0008] According to a first aspect of the present invention, a simulation implementation method for a controllable ideal voltage source is provided, comprising the following steps:

[0009] Step 1: Initialize the voltage reference value;

[0010] Step 2: Select the number of power supply voltage sources;

[0011] Step 3: Configure the power-on parameters for multiple power supplies, including setting the starting voltage value, power-on completion voltage value, and power-on time for each power supply, and enabling the corresponding power-on function.

[0012] Step 4: Check that the power-on is complete and the voltage is stable, turn on the stable state enable, and ensure that the voltage source remains stable at the set voltage value;

[0013] Step 5: Selectively add noise;

[0014] Step Six: Check circuit stability. If the flag signal indicating an abnormal circuit state is pulled high, the simulation will stop and an instability message will be displayed.

[0015] Step 7: Set the power-down parameters, including setting the power supply's initial power-down voltage value, power-down completion voltage value, power-down time, and enabling the corresponding power-down function;

[0016] Step 8: Execute the power-down process, select and enable power-down, and start simulating the power-down process of the circuit;

[0017] Step 9: Check the circuit status after power failure. If the flag signal is not pulled high, it indicates that no error occurred in the circuit during the power failure process, and the simulation stops after the power failure is completed.

[0018] According to a second aspect of the present invention, a simulation implementation system for a controllable ideal voltage source is provided, comprising a processor and a memory, wherein the processor and the memory are coupled together; wherein the memory is used to store a computer program; and the processor is used to run the computer program stored in the memory to execute the above-described simulation implementation method for a controllable ideal voltage source.

[0019] Unlike traditional voltage sources that can only preset voltage values ​​before simulation, this invention can select and change the power-on state based on the current circuit state during simulation. This eliminates the need for manual time calculations and re-simulation for certain circuit states, significantly reducing the complexity and time required for verification. During simulation, this invention can adjust the preset time and voltage values ​​in real time based on the signal state, enabling the re-presetting of signal time and voltage during the simulation process. This capability greatly improves the flexibility and efficiency of simulation, making circuit design and verification more efficient and accurate. Attached Figure Description

[0020] Figure 1 This is a structural diagram of the simulation environment used to implement embodiments of the present invention;

[0021] Figure 2 A flowchart illustrating the simulation implementation method of a controllable ideal voltage source provided in an embodiment of the present invention;

[0022] Figure 3 This is a waveform logic diagram of the interaction process for finding the attack voltage value in an embodiment of the present invention;

[0023] Figure 4 This is a schematic diagram illustrating the interactive process of dynamically adjusting the voltage source in an embodiment of the present invention;

[0024] Figure 5 This is a waveform logic diagram of the interaction process of multiple consecutive power-on and power-off cycles in an embodiment of the present invention;

[0025] Figure 6 This is a schematic diagram of a simulation implementation system for a controllable ideal voltage source provided in an embodiment of the present invention. Detailed Implementation

[0026] The technical content of the present invention will now be described in detail with reference to the accompanying drawings and specific embodiments.

[0027] The technical concept of this invention lies in the function of dynamically adjusting the voltage source output according to the real-time signal state of the circuit during simulation. This improvement solves the problem that traditional voltage sources can only be preset to a fixed voltage value and cannot adapt to changing states during simulation, thereby improving the efficiency and flexibility of simulation. Through this real-time adjustment, engineers can select and adjust the ideal voltage source in the simulation according to different circuit operating scenarios, avoiding the inefficiency caused by multiple manual selections and repeated simulations. Furthermore, by changing the preset time voltage according to the signal state during simulation, the ability to re-preset the signal time voltage during simulation is achieved, thus more accurately simulating circuit behavior under real operating conditions.

[0028] First Embodiment

[0029] Figure 1 A simulation environment for implementing embodiments of the present invention is shown. This simulation environment consists of multiple cooperating functional modules to ensure accurate simulation and verification of the circuit under test under various conditions.

[0030] First, the simulation vector driver module (St_driver.vams), as the starting point of the simulation flow, is responsible for activating the circuit under test (DUT) in netlist.vams. It ensures the circuit functions correctly at the start of the simulation by sending control signals, such as enable signals. Next, the digital-to-analog conversion rule control module (Connrules.vams) intervenes, defining the conversion rules between digital signals and analog voltages. Since digital circuits only recognize 0s and 1s, while analog circuits require specific voltage values, Connrules.vams ensures that digital high levels are correctly converted to the corresponding analog voltage values, thereby driving the analog circuits.

[0031] During simulation, the waveform loading module (Probe.vams) allows engineers to observe and analyze the circuit's response through a graphical interface. This module loads waveform data of the signals, providing engineers with a tool to gain a deeper understanding of circuit behavior and verify the accuracy of the design. Additionally, the circuit status monitoring module (Monitor_check.vams) plays a monitoring role throughout the simulation. It not only detects the flag signals of the circuit under test but also monitors the power control commands sent by St_driver.vams. Once a flag signal is detected, Monitor_check.vams transmits control signals to the controllable ideal voltage source, triggering it to operate according to a predetermined time and voltage value. If the circuit status is abnormal, Monitor_check.vams will detect it promptly and take appropriate measures, such as triggering a power-down process or stopping the simulation, to prevent the spread of errors.

[0032] The circuit condition monitoring module (Monitor_check.vams) can be implemented using the "analogbeginend" code block in the Verilog-Ams language. These code blocks are specifically designed to describe the behavior of analog circuits. They operate on a continuous-time basis and are able to respond to dynamic changes in the circuit.

[0033] It should be noted that the flag signals for different functional modules vary in different embodiments of the present invention. For example, in the attack module, the signal may be the attack signal output by the attack module; while in the voltage regulation module, it may be the output voltage value. These signals need to be connected to the "monitor_check.vams" monitoring module in the simulation environment according to the different functions being tested. The monitoring module will evaluate the input signals according to preset judgment criteria.

[0034] Taking power-on / off testing of a power supply as an example, when "monitor_check.vams" makes a judgment based on predetermined conditions, and the conditions are met, it sends a flag=1 signal to "st_driver.vams," indicating that the module under test has encountered an error state. This will cause the driver module to interrupt its current preset operating state and execute a new state flow, such as transitioning from a power-on state to a power-off state. At this time, "st_driver.vams" will activate the power-off driver of the "controllable ideal voltage source," input the preset power-off time and voltage value, and start the power-off process. Conversely, if the judgment conditions are not met, "monitor_check.vams" will maintain the output of a flag=0 signal to "st_driver.vams," indicating that the circuit under test is operating normally. In this case, the simulation will continue according to the normal preset drive mode, that is, after powering on, it remains stable and then performs a power-off.

[0035] The controllable ideal voltage source module is the core of the simulation environment. It can dynamically adjust the output voltage according to the instructions of Monitor_check.vams. This dynamic adjustment capability makes the simulation process more flexible and adaptable to different circuit states and operating conditions. After receiving the power-on signal, the controllable ideal voltage source module will operate according to the predetermined voltage value at a predetermined time, transmitting the voltage to the circuit under test and driving the circuit to work. If the circuit malfunctions, Monitor_check.vams will detect the change in the flag signal and take corresponding measures, such as triggering a power-down process or stopping the simulation.

[0036] Before the simulation begins, the Connrules.vams module first defines the digital-to-analog conversion rules to ensure that digital signals can be correctly converted into analog voltage values. Simultaneously, the Probe.vams module prepares to load waveform data for subsequent signal monitoring and analysis.

[0037] Next, the St_driver.vams module, acting as the simulation vector driver, begins sending control signals to activate the circuit under test (DUT) in etlist.vams. This includes enabling the circuit and providing initial conditions. The Monitor_check.vams module continuously monitors the state of the DUT during the simulation, including flag signals and power control commands sent by St_driver.vams. Once a flag signal is detected, Monitor_check.vams passes control signals to the controllable ideal voltage source module.

[0038] The controllable ideal voltage source module dynamically adjusts its output voltage according to the instructions of the Monitor_check.vams module. Upon receiving a power-on signal, the controllable ideal voltage source module operates according to a predetermined time and voltage value, transmitting voltage to the circuit under test and driving the circuit to operate normally. The Probe.vams module loads signal waveforms during simulation, allowing engineers to observe and analyze the circuit's response in a graphical interface. This helps verify whether the circuit design meets expectations.

[0039] After simulation, all functional modules collaboratively generate a simulation report, including circuit performance data and waveform analysis results. The entire simulation process is structured, starting with defining conversion rules and loading signals, then moving to the St_driver.vams module driving the circuit under test, and finally to the Monitor_check.vams module monitoring the circuit status and controlling the voltage source. This structured process ensures the accuracy and efficiency of the simulation, enabling engineers to precisely control and monitor the circuit simulation process, thereby improving the reliability and performance of the circuit design.

[0040] Based on the above simulation environment, the first embodiment of the present invention provides a simulation implementation method for a controllable ideal voltage source. For example... Figure 2 As shown, the method includes at least the following steps:

[0041] Step 1: Initialize voltage reference value

[0042] Before the circuit under test (RTL) can start operating normally, a reference voltage V needs to be input to the ideal voltage source model. REF In one embodiment of the present invention, V can be... REF It is set to 1V. This reference voltage is the basis for calculating the output voltage stability of the ideal voltage source model, providing a stable starting point for the entire simulation process.

[0043] Step 2: Select the number of power supply voltage sources

[0044] Next, the user needs to select the number of voltage sources that will be powered simultaneously. This step is determined based on the complexity of the circuit design and testing requirements, and can involve a single voltage source or multiple voltage sources.

[0045] Step 3: Configure power-on parameters for multiple power supplies

[0046] If the user selects multiple power supplies, detailed settings will be configured for each power supply (e.g., power supply A, power supply B, etc., up to five). Specifically, this includes setting the starting voltage, power-on completion voltage, and power-on time for each power supply, and enabling the corresponding power-on capability. This process involves processing the data as a continuous-time signal to simulate the power-on process of a real, ideal power supply, ensuring that the power supply gradually increases its voltage as expected until it reaches a stable state.

[0047] In one embodiment of the invention, the simulation environment is configured to simultaneously control two power supplies, namely power supply A and power supply B. For power supply A, the simulation parameters are set to an initial voltage of 0V, with the goal of gradually increasing to a power-on completion voltage of 3V, a process set to be completed within 10 microseconds (µs), and power-on enable of power supply A is activated. Similarly, the simulation parameters for power supply B are also set, with an initial voltage of 0V, but a slightly different power-on completion voltage of 3.3V, and a longer power-on time set to 20 microseconds. Like power supply A, power-on enable of power supply B is also activated. This setup allows the simulation environment to simulate the process of two power supplies powering on almost simultaneously but at different rates and with different final voltage values, thereby enabling the testing and verification of the circuit's performance and stability under this specific power management scenario.

[0048] Step 4: Verify that power-on is complete and voltage is stable.

[0049] After the power supply is set up, the detection circuit checks whether it has completed power-on within the preset time. Once power-on is complete, the steady-state enable will be turned on to ensure that the voltage source remains stable at the set voltage value, providing a continuous power supply for the normal operation of the circuit.

[0050] In one embodiment of the invention, real-time monitoring is performed during the power-on process of power supplies A and B to ensure that they reach their respective power-on completion voltage values, namely 3V and 3.3V, within set 10 microseconds and 20 microseconds, respectively. Once power supplies A and B have completed the power-on process, the system activates their steady-state enable. This means that power supplies A and B will be maintained at their respective final voltage values, namely 3V and 3.3V, to ensure that the circuit continues to operate under these stable voltage conditions. This design allows the circuit to enter a stable operating state immediately after power-on, providing a stable power environment for subsequent performance testing and verification.

[0051] Step 5: Selectively add noise

[0052] Users can choose whether to enable noise. If enabled, users can further select the type of noise, including sine wave, square wave, triangle wave, etc., and set the noise amplitude to ±10% of the current voltage source. This step simulates the noise interference that the circuit may encounter in a real working environment. If noise is not enabled, the voltage source will maintain the current voltage, ensuring a stable voltage input.

[0053] In one embodiment of the invention, for power supply A, the system provides a noise enable option, allowing the user to selectively add noise to power supply A. In this particular case, the user selects a sine wave as the noise type and sets the noise amplitude to ±10% of the current voltage value of power supply A. This means that once power supply A reaches its power-on completion voltage of 3V, the system will superimpose a sine wave noise with an amplitude of 3V ±10%, or ±0.3V, onto its voltage. This setting can simulate the voltage fluctuations that power supply A may encounter in a real-world operating environment. Conversely, for power supply B, the user selects not to add any noise, so power supply B will maintain a stable power-on completion voltage of 3.3V, ensuring that voltage source B provides a constant voltage input to facilitate testing circuit performance in the absence of noise interference. This differentiated noise handling approach allows engineers to evaluate the impact of noise on different power supplies and circuit sections separately.

[0054] Step Six: Test Circuit Stability

[0055] The circuit's stability is checked under stable conditions. If instability occurs, such as when the abnormal circuit flag signal goes high, the simulation will stop and display an instability message. This step ensures that potential stability issues can be identified and resolved promptly during circuit design.

[0056] In one embodiment of the invention, the key to stability detection lies in monitoring a specific flag signal that should remain low when the circuit is operating normally. If the flag signal is detected to abnormally go high, it indicates that the circuit may be experiencing a problem, such as voltage fluctuations, overload, or other erroneous conditions that prevent the circuit from functioning properly. Once the system recognizes this high-level state, it will automatically trigger a simulation stop mechanism and immediately alert the user, clearly indicating the circuit's instability. This automated detection and response mechanism is a crucial element in ensuring the reliability and safety of circuit design, allowing engineers to promptly identify and resolve potential design flaws.

[0057] Step 7: Set power-off parameters

[0058] After the circuit has been running stably for a period of time, power-down settings are configured, including setting the initial power-down voltage value, the power-down completion voltage value, the power-down time, and enabling the corresponding power-down function.

[0059] Step 8: Execute the power-down process

[0060] Select and enable power-down to begin simulating the circuit's power-down process. This step simulates a sudden power outage that the circuit might encounter in real-world applications.

[0061] In one embodiment of the invention, a series of operations are performed to simulate the power-down process of power supplies A and B. First, for power supply A, the initial power-down voltage is set to 3V, which is the voltage value of power supply A in a steady state. Then, the power-down completion voltage is set to 0V, meaning that power supply A will be completely shut down. The power-down time is set to 10 microseconds (µs), which is the time required for power supply A to drop from 3V to 0V. Simultaneously, the power-down enable of power supply A is activated to initiate this process.

[0062] For power supply B, similar procedures will be followed. The initial power-down voltage is set to 3.3V, which is the voltage of power supply B in a stable state. The power-down completion voltage is also set to 0V, indicating that power supply B will also be completely shut down. The power-down time for power supply B is also set to 10 microseconds, the same as for power supply A, to ensure that the two power supplies can power down synchronously. Finally, the power-down enable of power supply B will be turned on to begin the power-down process.

[0063] In this way, it is possible to simulate the power-down process of power supply A and power supply B linearly dropping from their respective stable voltage values ​​(3V and 3.3V) to 0V within 10 microseconds, which helps to test and verify the behavior and stability of the circuit under power-down conditions.

[0064] Step 9: Check the circuit status after power failure

[0065] During the power-down process, the circuit status is checked again, especially whether the flag signal is pulled high. If the flag signal is not pulled high, it indicates that no error occurred in the circuit during the power-down process, and the simulation stops after the power-down is completed, indicating that the simulation passed. If the flag signal is pulled high, the simulation will also stop, indicating that an instability message has appeared, indicating that a problem occurred in the circuit during the power-down process.

[0066] In one embodiment of the invention, a rigorous monitoring task is performed during the power-down process of power supplies A and B. The core of this monitoring process is the detection of a critical flag signal, which should normally remain low. After power supplies A and B drop from their respective initial voltage values ​​(3V and 3.3V) to 0V according to a predetermined power-down time (10 microseconds), the system checks the status of the flag signal. If the flag signal remains low after the power-down is complete, it indicates that the circuit encountered no problems during the power-down process, and the system stops the simulation and displays a "simulation failed" message. This effectively means the simulation was successful because the circuit exhibited the expected stability.

[0067] Conversely, if the flag signal is pulled high during a power-down, it indicates that the circuit may have encountered an unstable condition, such as a voltage drop or abnormal current. In this case, the system will not stop the simulation but will display "Instability Message Found," indicating that a problem occurred during the power-down and requires further inspection and adjustment. This automated detection and feedback mechanism is crucial for ensuring the reliability of circuit designs, allowing engineers to identify and resolve potential stability issues during the design phase.

[0068] By following the steps above, the power-on and power-off processes of an ideal voltage source can be fully simulated, ensuring the reliability and stability of the circuit design under various operating conditions.

[0069] In one embodiment of the invention, the objective is to determine the exact voltage value generated by the attack. Due to the attack delay in the internal attack circuitry, a too-fast power-up process may lead to inaccurate output voltage values. To address this issue, a binary search strategy can be employed, leveraging the advantage of a controllable ideal voltage source. First, the system is rapidly powered up to the "drive voltage" VDD to determine the approximate voltage range generated by the attack. Then, the voltage source is controlled to power down to VDD / 2, followed by a slower power-up. Once the attack occurs, the system is again powered down to 3 / 4 VDD. This method utilizes the binary search strategy to accurately locate the attack voltage value in a shorter time while conserving simulation resources.

[0070] The specific steps of the binary search strategy are as follows: First, set the initial voltage value to VDD 1, which is the complete supply voltage VDD. After the first power failure, the voltage value VDD2 for the second power-on is set to half of VDD, i.e., VDD / 2. Subsequently, the voltage value VDD3 for the third power-on is obtained by averaging VDD 1 and VDD2 and making slight adjustments. The calculation formula is (VDD - VDD / 2) / 2 + VDD / 2, resulting in 3 / 4 VDD. Next, the voltage value VDD4 for the fourth power-on is again obtained by averaging VDD3 and VDD2 and making slight adjustments. The calculation formula is (3 / 4 VDD - VDD / 2) / 2 + VDD / 2, resulting in 5 / 8 VDD. This process is repeated continuously, and the voltage value VDD5 for the fifth power-on is calculated as (3 / 4 VDD - 5 / 8 VDD) / 2 + 5 / 8 VDD, resulting in 11 / 16 VDD. This can be expressed by the following formula:

[0071] VDD 1: VDD

[0072] VDD2: VDD / 2;

[0073] VDD3: (VDD-VDD / 2) / 2+VDD / 2=3 / 4VDD;

[0074] VDD4: (3 / 4VDD-VDD / 2) / 2+VDD / 2=5 / 8VDD

[0075] VDD5: (3 / 4VDD-5 / 8VDD) / 2+5 / 8VDD=11 / 16VDD

[0076] ...

[0077] And so on.

[0078] In this way, the voltage value after each power-on is the midpoint of the previous voltage range, thus gradually approaching the attack voltage, improving the search efficiency and saving simulation resources.

[0079] In one embodiment of the invention, the voltage range is gradually narrowed down through a series of power-on and power-off processes to determine the attack voltage. The interaction between the driving voltage and the enable and flag signals is crucial to ensuring circuit stability and accuracy.

[0080] Figure 3 This describes the waveform logic diagram of the interactive process for finding the attack voltage value in a simulation implementation. It details how the attack voltage is determined by progressively adjusting the voltage value, using a binary search strategy. This is consistent with... Figure 2 Steps three and four are closely related, namely configuring power-on parameters and detecting power-on completion and stabilizing voltage. Figure 3 The voltage changes and decision points in this process are shown, illustrating how the voltage is dynamically adjusted based on the flag signal. The following are the detailed steps of this interactive process:

[0081] Step 1: First, set the initial power-on parameters for the circuit, including the power-on time (time 1) and the target voltage value (VDD 1). Then, activate the power-on enable signal to begin the power-on process.

[0082] Step 2: After power-on, wait for the flag signal to go high to indicate that the circuit has reached a stable state. Once the flag signal goes high, the stability enable signal is activated and will remain stable at the current voltage value for a duration of time 2 to ensure the stability of the flag signal.

[0083] Step 3: After maintaining a stable duration of time 2, activate the power-down enable signal and set the power-down parameters, including the power-down time and the target voltage value (VDD2). At this point, the power-down process begins, using the binary search strategy described above to determine the power-down threshold, saving time and accurately finding the attack voltage value.

[0084] Step 4: During the power-down process, continuously monitor the flag signal. When the flag signal goes low, it indicates a change in the circuit state. At this time, maintain the VDD2 voltage value for time 2 to determine the new stable state of the circuit.

[0085] Step 5: Set the parameters for the second power-on, including the power-on time (time 1) and the new voltage value (VDD3), and start powering on.

[0086] Step 6: After power-on, wait for the flag signal to go high again, then activate the stability enable signal and keep the current voltage value unchanged to ensure the stability of the flag signal.

[0087] Step 7: After maintaining a stable duration of time ime2, reactivate the power-down enable signal, set new power-down parameters, including power-down time and target voltage value (VDD4), and begin the power-down process.

[0088] Step 8: During the power failure process, monitor the flag signal. When the flag signal goes low, it indicates that the circuit state has changed again. At this time, maintain the VDD4 voltage value for time 2.

[0089] Step 9: Set the parameters for the third power-on, including the power-on time (time 1) and the new voltage value (VDD5), and start powering on.

[0090] Step 10: After power-on, wait for the flag signal to go high, activate the stabilization enable signal, and collect the voltage value at this time, which is considered to be a relatively accurate voltage value.

[0091] Step 11: After acquiring the accurate voltage value, perform the final power-down process to reduce the voltage to ground (GND), and output the voltage value acquired during the third attack as the final result.

[0092] The advantage of the above method is that it allows for dynamic adjustment of the voltage source during simulation to adapt to changes in circuit state. Compared to traditional simulation methods, which require stopping the simulation and modifying the control logic after an attack occurs, the method provided in this invention can significantly improve the efficiency and accuracy of simulation.

[0093] The following section provides further explanation on how to dynamically adjust the voltage source. Figure 4 A schematic diagram illustrating the interactive process of dynamically adjusting a voltage source is provided. It demonstrates how voltage parameters are adjusted based on signal states during simulation. This is consistent with... Figure 2 Steps five and six are related, namely, selectively adding noise and detecting circuit stability.

[0094] Figure 4This demonstrates how to adjust the voltage when instability is detected to ensure the accuracy and stability of the simulation. The process of powering down and then powering back on when a flag signal is encountered during power-on includes the following sub-steps:

[0095] (1) Set the expected power-on time x1, with the goal of raising the voltage to the voltage value y1;

[0096] (2) Start the power-on process, so that the voltage gradually rises to the voltage value y1 within the time x1; during the power-on process, continuously check whether the flag signal changes;

[0097] (3) When the voltage reaches the voltage value y2, if the flag signal is detected to be high, record the time point x2 at this time;

[0098] (4) At time x2, once the flag signal is detected to be high, the power-down enable is immediately activated;

[0099] (5) At time x2, record the current voltage value y2 to prepare for the power outage process;

[0100] (6) Start the power-down process according to the preset power-down time x3 and the target power-down voltage value y3;

[0101] (7) At time x3, complete the power-down process and ensure that the voltage drops to the target power-down voltage value y3;

[0102] (8) At time x3, after the power-down is completed, the power-on enable is reactivated to prepare for the next power-on cycle;

[0103] (9) Using voltage value y1 as the new target voltage value, restart the power-on process;

[0104] (10) Record the time point x4 when the power-on is completed, and ensure that the voltage reaches the voltage value y1 at time x4.

[0105] The power-on and power-off processes can be described by a linear function curve.

[0106] The power-on process function is y = (y1 / x1)x2;

[0107] The function for the power outage process is y = y2 - ((y2 - y3) / (x3 - x2))x3;

[0108] The function for the re-energization process is y = (y1 - y3) / (x4 - x3)x4 + y3

[0109] In this way, simulation testing can accurately simulate the dynamic response of a circuit when it encounters a specific signal, which is crucial for evaluating the stability and reliability of the circuit.

[0110] In another embodiment of the invention, a scenario was simulated where a flag signal was generated randomly to test the controllability of the voltage source. The specific simulation process is as follows: when the flag signal is detected, a power-down operation is immediately performed, reducing the voltage to ground (GND), and then the power-up process is restarted. After power-up, the rising edge of the flag signal is detected again to ensure that the circuit can function normally under the new voltage level. This continuous power-up and power-down process demonstrates the flexibility and responsiveness of the voltage source control.

[0111] Figure 5 The diagram details the waveform logic of the interaction process during steady state and after the detection of the flag signal during power-up. It elaborates on how to control the voltage source during multiple power-up and power-down cycles to test the circuit's stability and performance under different power management scenarios. This is consistent with... Figure 2 Steps seven and eight are closely related, namely setting the power-down parameters and executing the power-down process. The following are the detailed steps of this test procedure:

[0112] Step 1: First, configure the circuit for its first power-on, which includes specifying the power-on time (time 1) and the target voltage value (VDD). The power-on enable signal is activated, and the circuit begins to power on to VDD.

[0113] Step 2: After power-on, if no flag signal is detected at this stage, the stabilization enable will be turned on, allowing the circuit to stabilize at VDD voltage for the expected time (time2).

[0114] Step 3: If the flag signal is detected to be high at time3 (in this example, the flag signal is a pulse signal that will automatically clear to zero after being pulled high), this indicates that the circuit may have encountered a specific event or condition.

[0115] Step 4: Once the flag signal is detected, immediately begin the power-down process. This includes setting the power-down time (time4) and dropping the voltage to ground (GND).

[0116] Step 5: After the power failure is complete, the stabilization enable will be turned on to maintain the GND voltage for a period of time (time5) to ensure that the circuit is stable after the power failure.

[0117] Step 6: After maintaining the stable state for time5, set the power-on enable again to start a new power-on cycle, powering on to VDD for time6.

[0118] Step 7: During the new power-on process, if the flag signal is detected to be high again at time7, perform the power-down operation again to reduce the voltage to GND. After the power-down is complete, enable the stability enable to maintain the GND voltage and ensure that the circuit remains stable after the power-down.

[0119] Through this series of steps, the stability and response capability of the controllable ideal voltage source provided by the embodiments of the present invention in the face of sudden flag signals, as well as its adaptability to random events in practical applications, can be verified.

[0120] In one embodiment of the present invention, in order to ensure the stability and accuracy of Verilog-Ams simulations, a controllable ideal voltage source can be constructed and implemented according to the following steps:

[0121] First, define a Verilog-Ams module named voltage_control, which will encapsulate all the voltage source control logic. Within this module, all necessary parameters and variables can be declared, including the reference voltage VREF, the number of power sources, the starting voltage of each power source, the power-on completion voltage, the power-on time, and the power-down time.

[0122] During the initialization phase, the VREF voltage value is set to 1V using the Verilog-Ams initial block. This step ensures that the controllable ideal voltage source has a defined reference point when the simulation begins.

[0123] Next, conditional statements (such as if and case) are used to implement the power selection logic, allowing the user to select one or more power supplies for simulation as needed. In the Verilog-Ams analog block, analog operators (such as <+) are used to process continuous-time signals, simulating the power-on and power-off processes of the voltage source.

[0124] In Verilog-Ams, the analog block is the core of analog circuit design, providing designers with a behavioral-level approach to simulating continuous-time circuit characteristics. This block is fundamental to analog circuit simulation, allowing the use of specialized analog operators, such as <+ for simulating voltage sources, <- for simulating voltage sources, and analog functions like V() and I() to obtain voltage and current between nodes. The capabilities of the analog block extend beyond linear relationships; it also supports nonlinear equations, enabling accurate simulation of the complex behavior of analog circuit components. Furthermore, the analog block can handle time-dependent expressions, allowing for the realistic reproduction of the behavior of analog signals over time. Statements within the analog block can also be set to event-driven, meaning they can respond in real-time to any changes in the analog signal, ensuring the continuity and dynamism of the simulation process.

[0125] Within the analog block, designers can utilize the simulation functions provided by Verilog-Ams to precisely control the power-up process of a power supply. For example, the V() function can be used to set the initial voltage of the power supply and gradually adjust it to a predetermined power-up completion voltage within the power-up time, thus simulating the real power-up behavior of the power supply. Such simulation is not limited to a single power supply; it can be applied to multiple power supplies simultaneously. Each power supply can be independently controlled according to its specific parameters to test and verify the performance and stability of the circuit under different power management strategies. In this way, the analog block provides designers with a powerful tool for implementing and evaluating complex analog circuit designs within the Verilog-Ams environment.

[0126] Verilog-Ams has continuous-time signal processing capabilities, allowing for flexible parameter settings to control simulation accuracy at any time within the simulation environment. Specifically, the maximum time step of the simulation can be set to 200 picoseconds (ps). This setting helps reduce the voltage step effect during power-on, resulting in a smoother power-on curve and thus improving the realism and accuracy of the simulation results.

[0127] During simulation, the value of the flag signal is continuously monitored to evaluate the circuit's stability. If the flag signal goes high, it indicates a possible circuit malfunction; in this case, the Verilog-Ams $stop system task is used to stop the simulation. Additionally, noise can be added to the analog block by generating sine, square, or triangular waves using simulation functions and superimposing them onto the voltage source to simulate noise interference in a real-world operating environment.

[0128] After the circuit has been running stably for a period of time, a power-down process can be simulated using an analog block, gradually reducing the voltage of the voltage source to 0V. At the end of the power-down process, check the flag signal again. If the flag signal is not pulled high, it indicates that the circuit has remained stable during the power-down process. Use the Verilog-Ams $finish system task to end the simulation and output a simulation success message. If the flag signal is pulled high, use $stop to stop the simulation and report an instability message.

[0129] Finally, the constructed Verilog-Ams was compiled into the simulation environment and simulated along with other circuit modules to verify the performance and stability of the circuit design under different power management scenarios. This approach ensures the reliability and effectiveness of the circuit design in practical applications.

[0130] Second Embodiment

[0131] Based on the above method, the second embodiment of the present invention provides a simulation implementation system for a controllable ideal voltage source. For example... Figure 6As shown, the simulation implementation system includes a processor and a memory; wherein, the memory is coupled to the processor and is used to store computer programs. When the computer programs are executed by the processor, the processor implements the above-mentioned simulation implementation method for a controllable ideal voltage source.

[0132] The processor controls the overall operation of the simulation system to complete all or part of the steps described above. The processor can be a central processing unit (CPU), graphics processing unit (GPU), field-programmable gate array (FPGA), application-specific integrated circuit (ASIC), digital signal processing (DSP) chip, etc. The memory stores various types of data to support the operation of the simulation system. This data may include, for example, instructions for any application or method operating on the simulation system, as well as application-related data. The memory can be implemented using any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic storage, flash memory, etc.

[0133] In one exemplary embodiment, the simulation implementation system may be implemented by a computer or microprocessor, or by a product with certain functions, to perform the above-described methods and achieve the same technical effects as described above. Specifically, the computer may be, for example, a personal computer, a laptop computer, an in-vehicle human-machine interaction device, a cellular phone, a camera phone, a smartphone, a personal digital assistant, a media player, a navigation device, an email device, a game console, a tablet computer, a wearable device, or any combination of these devices.

[0134] In another exemplary embodiment, the present invention also provides a computer-readable storage medium including program instructions that, when executed by a processor, implement the steps of the method in any of the above embodiments. For example, the computer-readable storage medium may be the memory including the program instructions described above, which can be executed by a processor to complete the above method and achieve the same technical effects as the above method.

[0135] Compared to existing technologies, this invention utilizes Verilog-Ams for modeling, which allows for continuous-time signal processing of the input data. This reduces voltage steps during power-up with maximum accuracy, resulting in a smoother and more realistic power-up process. This continuous-time processing not only improves simulation accuracy but also, because this invention constructs an ideal voltage source at the code level, provides high-precision voltage output, theoretically reaching the accuracy range covered by floating-point numbers.

[0136] On the other hand, during simulation, the embodiments of the present invention can adjust the preset time and voltage values ​​in real time according to the signal state, realizing the re-presetting of signal time and voltage during simulation. This capability greatly improves the flexibility and efficiency of simulation, making circuit design and verification processes more efficient and accurate.

[0137] It should be noted that the above embodiments are merely illustrative examples. The technical solutions of each embodiment can be combined, and all are within the protection scope of this invention.

[0138] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0139] The simulation implementation method and system for a controllable ideal voltage source provided by this invention have been described in detail above. Any obvious modifications made by those skilled in the art without departing from the essence of this invention will constitute an infringement of the patent rights of this invention and will incur corresponding legal liability.

Claims

1. A simulation implementation method for a controllable ideal voltage source, characterized in that... Includes the following steps: Step 1: Initialize the voltage reference value; Step 2: Select the number of power supply voltage sources; Step 3: Configure the power-on parameters for multiple power supplies, including setting the starting voltage value, power-on completion voltage value, and power-on time for each power supply, and enabling the corresponding power-on function. Step 4: Check that the power-on is complete and the voltage is stable, turn on the stable state enable, and ensure that the voltage source remains stable at the set voltage value; Step 5: Selectively add noise; Step Six: Check circuit stability. If the flag signal indicating an abnormal circuit state is pulled high, the simulation will stop and an instability message will be displayed. Step 7: Set the power-down parameters, including setting the power supply's initial power-down voltage value, power-down completion voltage value, power-down time, and enabling the corresponding power-down function; Step 8: Execute the power-down process, select and enable power-down, and start simulating the power-down process of the circuit; Step 9: Check the circuit status after power failure. If the flag signal is not pulled high, it indicates that no error occurred in the circuit during the power failure process, and the simulation stops after the power failure is completed. The attack voltage is determined by gradually narrowing the voltage range through continuous power-on and power-off processes. The specific steps for determining the attack voltage include: Step a: Set the circuit's first power-on parameters, including power-on time and first voltage value; then, activate the power-on enable signal to start the power-on process; Step b: After power-on, wait for the flag signal to go high to indicate that the circuit has reached a stable state; once the flag signal goes high, the stability enable signal is activated and will remain stable at the current voltage value for a preset time to ensure the stability of the flag signal. Step c: After maintaining the preset time stably, activate the power-down enable signal and set the power-down parameters, including the power-down time and the second voltage value; start the power-down process and use a binary search strategy to determine the power-down threshold in order to save time and accurately find the attack voltage value. Step d: During the power failure process, continuously monitor the flag signal; when the flag signal goes low, it indicates that the circuit state has changed. At this time, maintain the preset time at the second voltage value to determine the new stable state of the circuit. Step e: Set the parameters for the second power-on, including the power-on time and the third voltage value, and start powering on; Step f: After power-on, wait for the flag signal to go high again, then activate the stability enable signal and keep the current voltage value unchanged to ensure the stability of the flag signal; Step g: After maintaining the preset time stably, reactivate the power-down enable signal, set new power-down parameters, including power-down time and fourth voltage value, and start the power-down process; Step h: During the power outage, monitor the flag signal; when the flag signal goes low, it indicates that the circuit state has changed again, and at this time, maintain the preset time at the fourth voltage value; Step i: Set the parameters for the third power-on, including the power-on time and the fifth voltage value, and start powering on; Step j: After power-on, wait for the flag signal to go high, activate the stability enable signal, and collect the voltage value at this time as the accurate voltage value; Step k: After acquiring an accurate voltage value, perform the final power-down process to reduce the voltage to ground, and output the voltage value acquired in step j as the final result.

2. The simulation implementation method of the controllable ideal voltage source as described in claim 1, characterized in that... The binary search strategy includes the following sub-steps: First, quickly power on to the drive voltage VDD to determine the approximate voltage range generated by the attack; then, control the voltage source to power down to VDD / 2, and then power on again at a slower speed; when the attack occurs, power down again to 3 / 4 VDD, and so on.

3. The simulation implementation method of the controllable ideal voltage source as described in claim 1, characterized in that... When a flag signal is encountered during power-on, a power-down operation is performed followed by a power-on restart, which includes the following sub-steps: (1) Set the expected power-on time x1, with the goal of raising the voltage to the voltage value y1; (2) Start the power-on process, so that the voltage gradually rises to the voltage value y1 within the time x1; During the power-on process, continuously check whether the flag signal changes; (3) When the voltage reaches the voltage value y2, if the flag signal is detected to be high, record the time point x2 at this time; (4) At time x2, once the flag signal is detected to be high, the power-down enable is immediately activated; (5) At time x2, record the current voltage value y2 to prepare for the power outage process; (6) Start the power-down process according to the preset power-down time x3 and the target power-down voltage value y3; (7) At time x3, complete the power-down process and ensure that the voltage drops to the target power-down voltage value y3; (8) At time x3, after the power-down is completed, the power-on enable is reactivated to prepare for the next power-on cycle; (9) Using voltage value y1 as the new target voltage value, restart the power-on process; (10) Record the time point x4 when the power-on is completed, and ensure that the voltage reaches the voltage value y1 at time x4.

4. The simulation implementation method of the controllable ideal voltage source as described in any one of claims 1 to 3, characterized in that: Modeling is performed using the Verilog-Ams language to perform continuous-time signal processing on the input data.

5. A simulation implementation system for a controllable ideal voltage source, characterized in that... The device includes a processor and a memory, which are coupled together; wherein the memory is used to store a computer program; and the processor is used to run the computer program stored in the memory to execute the simulation implementation method of the controllable ideal voltage source according to any one of claims 1 to 4.

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