Chip system and working state configuration method

Abstract

Embodiments of the present application provide a chip system and a working state configuration method. The chip system provided by the embodiments of the present application comprises: at least one layer of chips, each layer of chips being provided with at least one timing device, the timing device comprising a configurable timing device with a configurable working state; a connection structure, two ends of the connection structure being connected to one configurable timing device; when the chip system is working, if it is determined that the data transmission requirement of the chip system is data transmission, the working state of the configurable timing device is configured according to the timing requirement of the chip system, so as to change the effective transmission path of the chip system. The technical solution provided by the embodiments of the present application configures the working state of the configurable timing device, changes the effective transmission path of the chip system, makes the chip system meet the timing requirement of the chip system, avoids the incorrect timing in the chip system from affecting the performance of the chip system, and reduces the chip failure rate.

Description

Technical Field

[0001] This invention relates to the field of integrated circuits, specifically to a chip system and a method for configuring its operating state. Background Technology

[0002] With the development of semiconductor chips and the increasing complexity of integrated circuit design, the design of signal transmission paths in chip systems has become crucial. Due to the complexity of manufacturing processes, the delay characteristics of signals transmitted in some paths within a chip system are difficult to predict accurately. The actual delay may differ significantly from the simulation model, leading to incorrect timing in the chip system, affecting its performance, and in severe cases, even causing chip system failure or malfunction.

[0003] Against this backdrop, how to provide technical solutions to ensure the correct timing in chip systems and reduce chip system failure rates has become a technical problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0004] To address the above problems, embodiments of the present invention provide a chip system and a method for configuring its operating state.

[0005] In a first aspect, embodiments of the present invention provide a chip system, comprising:

[0006] At least one chip layer, each chip layer having at least one timing device, the timing device including configurable timing devices with configurable operating states;

[0007] The connection structure has one configurable timing device connected to each of its two ends;

[0008] When the chip system is working, if it is determined that the data transmission requirement of the chip system is that there is data transmission, the working state of the configurable timing device is configured according to the timing requirements of the chip system to change the effective transmission path of the chip system.

[0009] The effective transmission path is determined by timing devices in effective working state connected to both ends of the connection structure, and is adapted to the timing requirements.

[0010] In a second aspect, embodiments of the present invention provide a working state configuration method, applied to the chip system described in the first aspect, the working state configuration method comprising:

[0011] Determine the data transmission requirements of the chip system during operation;

[0012] If it is determined that the data transmission requirement is that data transmission is required, the operating state of the configurable timing devices in the chip system is configured based on the timing requirements of the chip system to change the effective transmission path of the chip system.

[0013] The effective transmission path is determined by timing devices in effective working state connected to both ends of the connection structure, and is adapted to the timing requirements of the chip system.

[0014] The chip system provided in this embodiment of the invention includes at least one layer of chips, each layer of chips having at least one timing device, the timing device including a configurable timing device with a configurable operating state; a connection structure with one of the configurable timing devices connected to each end; when the chip system is working, if it is determined that the data transmission requirement of the chip system is data transmission, the operating state of the configurable timing device is configured according to the timing requirement of the chip system to change the effective transmission path of the chip system; wherein, the effective transmission path is determined by the timing devices with effective operating states connected to both ends of the connection structure and is adapted to the timing requirement.

[0015] As can be seen, the technical solution provided by this embodiment of the invention connects a configurable timing device to each end of the connection structure. Therefore, when the chip system is operating, if the chip system requires data transmission, the operating state of the configurable timing device is configured according to the timing requirements of the chip system, thereby changing the effective transmission path of the chip system. Since the effective transmission path is adapted to the timing requirements, the effective transmission path via the cover plate ensures that the chip system can meet its timing requirements when transmitting data, preventing incorrect timing in the chip system from affecting its performance and reducing the chip failure rate. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0017] Figure 1 This is a schematic diagram of a chip system provided in an embodiment of the present invention.

[0018] Figure 2 This is another schematic diagram of a chip system provided in an embodiment of the present invention.

[0019] Figure 3This is another schematic diagram of a chip system provided in an embodiment of the present invention.

[0020] Figures 4 to 8 This is a flowchart of a working state configuration method provided in an embodiment of the present invention. Detailed Implementation

[0021] As described in the background section, the delay characteristics of signals transmitted in a chip system in some paths are difficult to predict accurately. The actual delay may differ significantly from the simulation model, resulting in incorrect timing in the chip system, affecting the chip system performance, and in severe cases, even causing chip system failure or malfunction.

[0022] Because existing chip systems operate at relatively high clock frequencies, the higher the clock frequency, the shorter the clock cycle. For example, when the clock frequency of a chip system is 4 GHz, the clock cycle is only 250 ps. This places higher timing requirements on the internal circuitry of the chip system.

[0023] However, in chip systems, the physical structures corresponding to some effective data transmission paths, such as long conductors and TSVs (Through-Silicon Vias), may differ between wafer manufacturers due to the complexity of manufacturing processes, interconnects, and packaging. This can lead to significant discrepancies between the electrical characteristics of some physical structures and the simulation models used in the chip design phase. Consequently, signal transmission delays in some physical structures may be too large or too small, or the signal delay distribution may be highly discrete. This problem can cause the internal circuitry of the chip system to fail to meet timing requirements, affecting chip performance, and in severe cases, even leading to chip malfunction or failure.

[0024] Therefore, the present invention provides a chip system and a method for configuring its operating state to ensure correct timing in the chip system and reduce the failure rate of the chip system.

[0025] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0026] Figure 1 This is a schematic diagram of a chip system provided in an embodiment of the present invention.

[0027] refer to Figure 1 The chip system 1 provided in this embodiment of the invention includes:

[0028] At least one chip layer, each chip layer having at least one timing device, the timing device including a configurable timing device 11 with configurable operating state;

[0029] The connection structure 10 has one of the configurable timing devices 11 connected to each end;

[0030] When the chip system 1 is working, if it is determined that the data transmission requirement of the chip system 1 is that there is data transmission, the working state of the configurable timing device 11 is configured according to the timing requirements of the chip system 1 to change the effective transmission path of the chip system 1.

[0031] The effective transmission path is determined by timing devices in effective working state connected to both ends of the connection structure 10, and is adapted to the timing requirements.

[0032] In the chip system 1 provided in this embodiment of the invention, when data transmission is required, the data will be transmitted through the connection structure 10 and the configurable timing device 11 connected to its two ends. Therefore, whether the configurable timing device 11 can transmit data according to the timing requirements of the chip system 1 determines whether the chip system 1 can work normally according to its timing requirements.

[0033] The timing device in the effective working state is a timing device that can transmit data normally.

[0034] The connection structure 10 is a physical structure for transmitting data. During the design phase of the chip system 1, the simulation model of the connection structure 10 has an expected delay, which is the time required for the data transmitted in the chip system 1 to pass through the connection structure 10.

[0035] When the timing device is in its effective operating state, its output at any given moment depends not only on the input at that moment but also on the inputs at previous moments. For example, the timing device can be a flip-flop. In the chip system 1, the timing device includes a configurable timing device 11 with configurable operating states, and one configurable timing device 11 is connected to each end of the connection structure 10. In some specific embodiments, the configurable timing device 11 includes at least one of a flip-flop, a register, or a counter.

[0036] Design documents that have passed testing during the chip system design phase may, due to the complexity of the manufacturing process, result in significant discrepancies between the electrical characteristics of the connection structure 10 in the actual product and the simulation model used in the design phase. This can lead to excessively large or small signal transmission delays in the connection structure 10, or highly discrete signal delay distributions, causing the chip system 1 to fail to operate normally according to its timing requirements.

[0037] Therefore, in the chip system provided by this embodiment of the invention, a configurable timing device 11 is connected to each end of the connection structure 10. When the chip system 1 is working, if the data transmission requirement of the chip system 1 is data transmission, the working state of the configurable timing device 11 is configured according to the timing requirements of the chip system 1 to change the effective transmission path of the chip system 1. When the chip system 1 uses the changed effective transmission path to transmit data, it can meet the timing requirements of the chip system 1, avoid the impact of incorrect timing in the chip system 1 on the chip system performance, and reduce the chip failure rate.

[0038] In some embodiments, the operating states of the configurable timing device 11 include: an enabled state and / or an disabled state.

[0039] Specifically, when it is determined that the data transmission requirement of the chip system 1 is data transmission, the configurable timing device 11 is configured to be in an enabled state, and the configurable timing device 11 is in an effective working state when the state of the configurable timing device 11 is configured to be in an disabled state, and the configurable timing device 11 is in an invalid working state, so as to transmit data according to the effective transmission path determined by the configurable timing device 11 after the working state is configured.

[0040] In some embodiments, the timing device further includes an original timing device 12 that maintains an active operating state. Unlike the configurable timing device 11, the original timing device always maintains an active operating state.

[0041] In some implementations, when the data transmission requirement is determined to be data transmission, the effective transmission path determined according to the configurable timing device 11 after configuring its working state is: the path between the configurable timing device 11 connected to one end of the connection structure 10 and configured to be in an effective working state, and the original timing device 12 connected to the other end of the connection structure 10; or, the path between the original timing devices 12 connected to both ends of the connection structure 10; or, the path between the configurable timing devices 11 connected to both ends of the connection structure 10 and configured to be in an effective working state.

[0042] For example, refer to Figure 1In some embodiments, the configurable timing device 11 includes a first configurable timing device 111 and a second configurable timing device 112, wherein the first configurable timing device 111 is connected to the front stage of the connection structure 10, and the second configurable timing device 112 is connected to the rear stage of the connection structure 10; the original timing device includes a first original timing device 121 and a second original timing device 122, wherein the first original timing device 121 is connected to the front stage of the connection structure 10, and the second original timing device 122 is connected to the rear stage of the connection structure 10.

[0043] In the above embodiment, the path between the configurable timing device 11, which is connected to one end of the connection structure 10 and whose working state is configured to be in an effective working state, and the original timing device connected to the other end of the connection structure 10, is specifically: the path of the first configurable timing device 111, whose working state is configured to be in an effective working state - connection structure 10 - second original timing device 122, or the path of the first original timing device 121 - connection structure 10 - second configurable timing device 112, whose working state is configured to be in an effective working state.

[0044] The specific path between the original timing devices 12 connected to both ends of the connection structure 10 is: the path of the first original timing device 121 - connection structure 10 - second original timing device 122.

[0045] The specific path between the configurable timing devices 11 connected to both ends of the connection structure 10 and configured to be in an effective working state is: the first configurable timing device 111 configured to be in an effective working state - connection structure 10 - the second configurable timing device 112 configured to be in an effective working state.

[0046] Figure 2 This is another schematic diagram of a chip system provided in an embodiment of the present invention, see reference. Figure 2 In some embodiments, the connection structure is a through-silicon via (TSV) structure 101; the chip system 1 includes an upper chip 102 and a lower chip 103 connected by the TSV structure; the configurable timing device 11 includes a first configurable timing device 111 located in the upper chip 102 and connected to one end of the TSV structure 101, and a second configurable timing device 112 located in the lower chip 103 and connected to the other end of the TSV structure 101.

[0047] Due to the complexity of the manufacturing process of the through-silicon via (TSV) structure 101, the electrical characteristics of the TSV may differ significantly from the TSV simulation model used in the chip design phase. This results in a higher probability of chip failure compared to conventional interconnect structures (such as vias). Therefore, connecting a configurable timing device 11 to each end of the TSV structure 101 allows for more effective utilization of the configuration of the operating state of the configurable timing device 11 to change the effective transmission path of the chip system 1, enabling the chip system 1 to meet its timing requirements.

[0048] In some embodiments, the operating state of the configurable timing device 11 further includes: a shutdown state; if it is determined that the data transmission requirement of the chip system 1 is no data transmission, the operating state of the configurable timing device 11 is configured to a shutdown state so that the effective transmission path has no data transmission.

[0049] It is understandable that, in cases like Figure 2 In the chip system 1 shown, when no data transmission is required under the current timing requirements, the chip system 1 can configure the operating state of either the first configurable timing device 111 or the second configurable timing device 112 to be off, so that the effective transmission path does not transmit data, thereby reducing the power consumption of the chip system 1 and avoiding interference with other signal processing in the downstream circuit of the configurable timing device 11.

[0050] Figure 3 This is another schematic diagram of the chip system provided in the embodiment of the present invention.

[0051] refer to Figure 3 In some embodiments, the connection structure is: a connection wire 104 on each chip layer; the configurable timing device 11 includes: a third configurable timing device 113 located on each chip layer and connected to one end of the connection wire 104, and a fourth configurable timing device 114 located on each chip layer and connected to the other end of the connection wire 104.

[0052] In some chip system 1 designs, certain connecting wires 104 have relatively long lengths (e.g., due to a large chip area and the need for long wires to connect multiple internal devices). In actual chip products, these longer connecting wires have higher resistance and parasitic inductance compared to other connecting wires. Because semiconductor chip manufacturers may use different processes, when the connecting wires 104 are long, their resistance and parasitic inductance may differ significantly from the simulation model used in the chip design phase. This can cause the chip system 1 to fail to meet its timing requirements, leading to chip failure. Therefore, connecting a configurable timing device 11 to each end of the connecting wire 104 allows for more effective use of the configurable timing logic device 11's operating state to change the effective transmission path of the chip system 1, enabling the chip system 1 to meet its timing requirements.

[0053] It is understood that in some embodiments, the connection structure may also be a cross-chip connection wire, and the chip system includes an upper-layer chip and a lower-layer chip connected by the cross-chip connection wire. Since some package structures require long cross-chip connection wires between chips of different layers, the cross-chip connection wires connecting the upper-layer chip and the lower-layer chip may face the same problem as the connection wires 104 on each layer of the chip. Therefore, it is necessary to connect a configurable timing device to each end of the cross-chip connection wire to more effectively utilize the configurable timing logic device to change the effective transmission path of the chip system 1, enabling the chip system to meet its timing requirements.

[0054] In some embodiments, the chip system 1 further includes a gating unit; the gating unit is connected to the clock input port and data input port of the configurable timing device 11 to configure the operating state of the configurable timing device 11 based on the gating unit.

[0055] It is understood that by applying a gating configuration signal to the gating unit, the operating state of the configurable timing device 11 can be configured to an enabled state, an disabled state, or a closed state, so as to change the effective transmission path of the chip system 1 according to the timing requirements of the chip system 1 under different data transmission requirements.

[0056] by Figure 2 Taking a chip system as an example, in some specific embodiments, the gating unit includes a first gating unit 151 and a second gating unit 152. The first gating unit 151 is used to configure the working state of the first configurable timing device 111, and the second gating unit 152 is used to configure the working state of the second configurable timing device 112, so that the effective transmission path of the chip system 1 can be changed according to the timing requirements of the chip system 1.

[0057] This invention also provides a working state configuration method, applied to the chip system described in the foregoing embodiments, to ensure correct timing in the chip system and reduce the chip system failure rate.

[0058] For ease of understanding, the working state configuration method provided by the present invention will be described in detail below with reference to the chip system provided in the embodiments of the present invention.

[0059] Figure 4 This is a flowchart of a working state configuration method provided in an embodiment of the present invention. (Reference) Figure 4 The present invention provides a working state configuration method including:

[0060] Step S100: Determine the data transmission requirements of the chip system during operation.

[0061] The data transmission requirement refers to whether the chip system needs to perform data transmission. In some cases, the chip system does not need to perform data transmission, and power consumption can be reduced by configuring the operating state of the configurable timing devices.

[0062] After executing step S100, continue to execute step S200.

[0063] Step S200: Determine whether the data transmission requirement is valid.

[0064] If it is determined that the data transmission requirement is to be met, proceed to step S300.

[0065] Step S300: Based on the timing requirements of the chip system, configure the operating state of the configurable timing devices in the chip system to change the effective transmission path of the chip system.

[0066] The effective transmission path is determined by timing devices in effective working state connected to both ends of the connection structure, and is adapted to the timing requirements of the chip system.

[0067] When the chip system needs to transmit data through the connection structure, the chip system must meet its timing requirements to ensure correct data transmission. Therefore, based on the timing requirements of the chip system, the operating state of the configurable timing devices in the chip system needs to be configured to change the effective transmission path of the chip system. This modified effective transmission path can meet the timing requirements of the chip system when transmitting data, ensuring that data can be transmitted correctly within the effective transmission path of the chip system.

[0068] To accurately configure the working status, in one implementation, step S300 may include:

[0069] Based on the determination conditions of the timing requirements of the chip system, obtain the corresponding defined working state configuration method under the determination conditions;

[0070] The operating states of configurable timing devices in the chip system are configured using the obtained operating state configuration method.

[0071] Timing requirements in a chip system can be determined based on different conditions. Therefore, the corresponding defined operating state configuration method can be selected according to the specific conditions to accurately configure the operating state of configurable timing devices.

[0072] In some implementations, reference Figure 5 The determining conditions may include: timing constraints; the determining conditions based on the timing requirements of the chip system, and obtaining the corresponding defined working state configuration method under the determining conditions, include:

[0073] Step S310: Based on the timing constraints, obtain the corresponding first working state configuration method, wherein the first working state configuration method is: configure the working state of the configurable timing device connected to one end of the connection structure of the chip system as an effective working state, and configure the working state of the configurable timing device connected to the other end of the connection structure as an invalid working state.

[0074] Timing requirements refer to the time constraints that a digital circuit, system, or device must meet during normal operation. For the chip system to function correctly, all timing devices at each stage of the chip system, including the configurable timing devices, must meet these timing requirements. Therefore, when timing requirements are determined based on timing constraints, the operating state of the configurable timing devices is configured using a correspondingly defined first operating state configuration method, thereby changing the effective transmission path to ensure that the chip system meets the timing constraints for normal operation.

[0075] In some specific implementations, the timing constraints may include: timing constraints based on setup time constraints and timing constraints based on hold time constraints.

[0076] After defining the first working state configuration method, continue to execute step S311.

[0077] Step S311: Configure the working state of the configurable timing device using the first working state configuration method.

[0078] The effective transmission path in the chip system is changed according to the configuration in step S311, thereby enabling the chip system to meet the timing requirements determined based on timing constraints.

[0079] The following is combined with, for example Figure 2 The chip system shown here will be described in detail in the step S300 of the working state configuration method provided in the embodiment of the present invention.

[0080] refer to Figure 2 Let the clock period of the chip system 1 be T_Cyc. The timing constraints of the first timing requirement include the timing constraints formed based on the setup time constraint: T_Setup>0.3*T_Cyc.

[0081] Setup time requirement refers to the shortest time that the input signal of a sequential device must remain stable before the valid edge of the clock signal. In other words, the input signal must remain stable before the valid edge of the clock signal arrives so that the sequential element (such as a flip-flop) can correctly sample the input signal.

[0082] In such Figure 2 In the chip system shown, the original timing device 12 includes a first original timing device 121 and a second original timing device 122. For the data transmitted by the chip system 1 under the current data transmission requirements, the total transmission delay of the through-silicon via structure 101, combinational logic Logic2, and combinational logic Logic3 is T_tsv = 0.6 * T_cyc, the delay of combinational logic Logic1 is T_1 = 0.2 * T_cyc, and the delay of combinational logic Logic4 is T_4 = 0.5 * T_cyc. The first original timing device 121, the second original timing device 122, the first configurable timing device 111, and the second configurable timing device 112 are all D flip-flops (DFFs), and the transmission delays of the first original timing device 121, the second original timing device 122, the first configurable timing device 111, and the second configurable timing device 112 are negligible.

[0083] Step S310 is executed, that is, based on the timing constraints, using the corresponding defined first working state configuration method, the working state of the configurable timing device 11 connected to one end of the through-silicon via structure 101 is configured as an effective working state, and the working state of the configurable timing device 11 connected to the other end of the through-silicon via structure 101 is configured as an invalid working state.

[0084] For example, the original operating state of the configurable sequential logic device 11 (i.e., the operating state in which the chip system 1 does not meet the setup time requirement) is as follows: the first configurable sequential device 111 is in an enabled state, and the second configurable sequential device 112 is in a disabled state. When the chip system 1 does not meet the setup time requirement, step S311 is executed: the operating state of the configurable sequential device 11 is configured according to the first operating state configuration method, thereby changing the effective transmission path of the chip system 1 so that the effective transmission path is adapted to the timing constraints of the chip system 1.

[0085] Specifically, since the first configurable timing device 111 is in an enabled state in the original working state, according to the configuration method of the first working state, the working state of the second configurable timing device 112 connected to one end of the through-silicon via structure 101 needs to be configured to an active working state, and the working state of the second configurable timing device 111 connected to the other end of the connection structure needs to be configured to an inactive working state, thereby changing the effective transmission path of the chip system 1 and making the effective transmission path adapt to the timing constraints of the chip system 1.

[0086] In its original operating state, the effective transmission path in the chip system 1 is: first original timing device 121 - first configurable timing device 111 - through-silicon via structure 101 - second original timing device 122. The signal output by the first configurable timing device 111 is received and sampled by the second original timing device 122 after passing through T_tsv + T_4 = 1.1 * Tcyc. However, for the timing device connected to the through-silicon via structure 101, the setup time requirement is T_Setup > 0.3 * T_Cyc. The T_Setup of the second original timing device 122 is the portion of T_real + T_4 that exceeds an integer multiple of the clock cycle, i.e., T_Setup = (T_real + T_4) mod T_cyc = 0.1 * T_Cyc < 0.3 * T_Cyc.

[0087] The reason for the above problem is that in the simulation model used in the design phase of the chip system 1, the expected total transmission delay of the through-silicon via structure 101, combinational logic Logic2 and combinational logic Logic3 is T_design = 0.2 * T_cyc. However, in the actual product, the transmission delay of the through-silicon via structure 101 increases, resulting in the total transmission delay T_tsv of the through-silicon via structure 101, combinational logic Logic2 and combinational logic Logic3 being greater than T_design. Ultimately, this causes the second original timing device 122 in the chip system 1 to fail to meet the setup time requirements.

[0088] According to the first working state configuration method, after configuring the working state of the configurable timing device 11 through the first gating unit 151 and the second gating unit 152, the effective transmission path in the chip system 1 changes. The changed effective transmission path is: first original timing device 121 - through-silicon via structure 101 - second configurable timing device 112 - second original timing device 122. It can be seen that for the timing devices in the effective working state connected by the through-silicon via structure 101, the setup time T_Setup=T_1+T_tsv=0.8T_Cyc>0.3*T_Cyc, which meets the setup time requirement. Furthermore, the number of pipeline stages in the effective transmission path does not change before and after the change, thereby enabling the chip system 1 to meet the timing constraints formed by its setup time constraints without introducing additional pipeline stages and avoiding an increase in the latency of the chip system 1, ensuring the normal operation of the chip system and reducing the chip system failure rate.

[0089] In other embodiments, the timing constraints include timing constraints based on hold-time constraints: T_Setup>0.3*T_Cyc.

[0090] The hold time requirement refers to the minimum time that an input signal must remain stable after the effective edge of a clock signal. In other words, for a sequential logic element, the input signal cannot change immediately after the clock edge arrives; it must remain in its current state for a certain period of time to ensure that the sequential logic element can correctly sample the input signal.

[0091] Continue to refer to Figure 2 For the signals transmitted by the chip system 1 under the current data transmission requirements, the total transmission delay of the through-silicon via structure 101, combinational logic Logic2, and combinational logic Logic3 is T_tsv = 0.1 * T_cyc, the delay of combinational logic Logic1 is T_1 = 0.5 * T_cyc, and the delay of combinational logic Logic4 is T_4 = 0.1 * T_cyc; the first original timing device 121, the second original timing device 122, the first configurable timing device 111, and the second configurable timing device 112 are all D flip-flops, and the transmission delays of the first original timing device 121, the second original timing device 122, the first configurable timing device 111, and the second configurable timing device 112 are negligible.

[0092] Execute step S310, that is, based on the timing constraints, define the first working state configuration method as follows: configure the working state of the configurable timing device 11 connected to one end of the through-silicon via structure 101 as an effective working state, and configure the working state of the configurable timing device 11 connected to the other end of the through-silicon via structure 101 as an invalid working state.

[0093] For example, the original operating state of the configurable sequential logic device 11 (i.e., the operating state in which the chip system 1 does not meet the hold time requirement) is as follows: the first configurable sequential device 111 is in an enabled state, and the second configurable sequential device 112 is in an disabled state. When the chip system 1 does not meet the timing constraints formed by the hold time constraint, step S311 is executed: the operating state of the configurable sequential device 11 is configured according to the first operating state configuration method, thereby changing the effective transmission path of the chip system 1 so that the effective transmission path is adapted to the timing requirements of the chip system 1 (i.e., the timing constraints established by the hold time constraint).

[0094] Specifically, since the first configurable timing device 111 is enabled in the original working state, according to the configuration method of the first working state, the working state of the second configurable timing device 112 connected to one end of the through-silicon via structure 101 needs to be configured to an active working state, and the working state of the second configurable timing device 111 connected to the other end of the connection structure needs to be configured to an inactive working state, thereby changing the effective transmission path of the chip system 1 so that the effective transmission path meets the timing requirements of the chip system 1.

[0095] In its original operating state, the effective transmission path in the chip system 1 is: first original timing device 121 - first configurable timing device 111 - through silicon via structure 101 - second original timing device 122.

[0096] Among them, the data output by the first configurable timing device 111 is received and sampled by the second original timing device 122 after T_tsv + T_4 = 0.2 * Tcyc; however, for the timing devices in the effective working state connected by the through-silicon via structure 101, the hold time requirement is T_Hold > 0.3 * T_Cyc, and the hold time T_Hold of the second original timing device 122 is 0.2 * T_Cyc < 0.3 * T_Cyc. The reason for the problem is that in the simulation model used in the design stage of the chip system 1, the expected total transmission delay of the through-silicon via structure 101, combinational logic Logic2, and combinational logic Logic3 is T_design = 0.5 * T_cyc. However, in the actual product, the transmission delay of the through-silicon via structure 101 is reduced, resulting in the total transmission delay T_tsv of the through-silicon via structure 101, combinational logic Logic2, and combinational logic Logic3 < T_design. Finally, in the chip system 1, the second original timing device 122 does not meet the timing constraint conditions formed by the hold time constraint.

[0097] According to the first working state configuration method, after configuring the working state of the configurable timing device 11 through the first gating unit 151 and the second gating unit 152, the effective transmission path in the chip system 1 changes. The changed effective transmission path is: the first original timing device 121 - through-silicon via structure 101 - second configurable timing device 112 - second original timing device 122; it can be seen that for the timing devices in the effective working state connected by the through-silicon via structure 101, the hold time of the second configurable timing logic device 112 is: T_Hold = T_1 + T_tsv = 0.8T_Cyc > 0.3 * T_Cyc, meeting the timing constraint conditions formed based on the hold time constraint. Moreover, the number of pipeline stages of the effective transmission path does not change before and after the change, so that the chip system 1 can meet its timing requirements without introducing additional pipeline stages and avoiding an increase in the delay of the chip system 1, ensuring the normal operation of the chip system and reducing the failure rate of the chip system.

[0098] According to the above embodiments, the working state configuration method provided by the present invention determines that the data transmission requirement of the chip system during operation is when data transmission is required. Based on the timing requirements of the chip system determined by timing constraints, a first working state configuration method is defined as follows: the working state of the configurable timing device connected to one end of the connection structure of the chip system is configured as an effective working state, the working state of the configurable timing device connected to the other end of the connection structure is configured as an ineffective working state, and the working state of the configurable timing device is configured according to the first working state configuration method to change the effective transmission path of the chip system; wherein, the effective transmission path is determined by the timing devices in the effective working state connected to both ends of the connection structure and is adapted to the timing requirements of the chip system.

[0099] As can be seen, the working state configuration method provided in this embodiment of the invention, when the chip system does not meet the timing constraints formed by setup time constraints and hold time constraints, changes the effective transmission path of the chip system by configuring the working state of the configurable timing device connected to one end of the connection structure of the chip system as an effective working state and configuring the working state of the configurable timing device connected to the other end of the connection structure as an invalid working state. This first working state configuration method changes the effective transmission path of the chip system, and enables the chip system to meet its timing requirements without introducing additional pipeline stages or increasing the latency of the chip system, thereby ensuring the normal operation of the chip system and reducing the failure rate of the chip system.

[0100] In some implementations, reference Figure 6 and Figure 7 The determining conditions include: design clock frequency conditions; the determining conditions based on the timing requirements of the chip system, and obtaining the corresponding defined working state configuration method under the determining conditions, include:

[0101] Step S320: Based on the design clock frequency condition, obtain the corresponding defined second working state configuration method. The second working state configuration method is: configure the working state of the configurable timing device connected to one end of the connection structure of the chip system as an effective working state, and configure the working state of the configurable timing device connected to the other end of the connection structure as an invalid working state.

[0102] Or, such as Figure 7 Step S321 shown: Based on the design clock frequency of the second timing requirement, the second working state configuration method is defined as: the working state of the configurable timing device connected to both ends of the connection structure of the chip system is configured as an effective working state.

[0103] In some implementations, it is necessary to increase or temporarily increase the clock frequency of the chip system 1 to the design clock frequency to optimize the performance of the chip system 1, for example, to increase the data throughput or the response speed of the chip system 1. The design clock frequency is the clock frequency at which the chip system 1 operates according to its design. Therefore, under the timing requirements determined based on the design clock frequency, the chip system is able to operate according to the timing requirements of its design.

[0104] After obtaining the defined second working state configuration method, continue to execute step S322.

[0105] Step S322: Configure the working state of the configurable timing device using the second working state configuration method.

[0106] The effective transmission path in the chip system is changed according to the configuration in step S322, thereby enabling the chip system to meet the design clock frequency requirements.

[0107] The following is combined with, for example Figure 2 The chip system shown here will be described in detail in the step S300 of the working state configuration method provided in the embodiment of the present invention.

[0108] refer to Figure 2 Let the clock period of the chip system 1 be T_Cyc = 600ps, that is, the clock frequency of the current state of the timing circuit is f_0 = 1.67GHz. For the data transmitted by the chip system 1 under the current data transmission requirements, the total transmission delay of the through-silicon via structure 101, combinational logic Logic2 and combinational logic Logic3 is T_tsv = 200ps, the delay of combinational logic Logic1 is T_1 = 200ps, and the delay of combinational logic Logic4 is T_4 = 200ps; the first original timing device 121, the second original timing device 122, the first configurable timing device 111 and the second configurable timing device 112 are all D flip-flops (DFFs), and the transmission delay of the first original timing device 121, the second original timing device 122, the first configurable timing device 111 and the second configurable timing device 112 is negligible.

[0109] Execute step S320, that is, based on the design clock frequency condition, obtain the corresponding defined second working state configuration mode, configure the working state of the configurable timing device 11 connected to one end of the through silicon via structure 101 as an effective working state, and configure the working state of the configurable timing device 11 connected to the other end of the through silicon via structure 101 as an invalid working state.

[0110] For example, the original operating state of the configurable sequential logic device 11 (i.e., the operating state in which the chip system 1 does not meet the design clock frequency requirement) is as follows: both the first configurable sequential logic device 111 and the second configurable sequential logic device 112 are in an disabled state. When the chip system 1 does not meet the design clock frequency condition, step S322 is executed: the operating state of the configurable sequential logic device 11 is configured according to the second operating state configuration method, thereby changing the effective transmission path of the chip system 1 so that the effective transmission path is adapted to the timing requirements of the chip system 1 (i.e., the second timing requirements).

[0111] Specifically, since both the first configurable timing device 111 and the second configurable timing logic device 112 are disabled in their original working state, according to the second working state configuration method, the working state of the first configurable timing device 111 connected to one end of the through-silicon via structure 101 needs to be configured as an active working state, and the working state of the second configurable timing device 112 connected to the other end of the connection structure needs to be configured as an inactive working state. This changes the effective transmission path of the chip system 1, making the effective transmission path compatible with the design clock frequency conditions of the chip system 1.

[0112] In its original operating state, the effective transmission path in the chip system 1 is: first original timing device 121 - through-silicon via structure 101 - second original timing device 122, wherein the signal output by the first original timing device 121 is received and sampled by the second original timing device 122 after passing through T_1 + T_tsv + T_4 = 600ps; however, in one embodiment, the design clock frequency condition is f ≥ 2GHz, that is, the transmission delay T between any two stages of timing devices in the chip system 1 is ≤ 500ps.

[0113] According to the second working state configuration method defined in step S320, after configuring the working state of the configurable timing device 11 through the first gate unit 151 and the second gate unit 152, the effective transmission path in the chip system 1 changes. The changed effective transmission path is: first original timing device 121 - first configurable timing device 111 - through-silicon via structure 101 - second original timing device 122. It can be seen that for the timing devices in the effective working state connected by the through-silicon via structure 101, the maximum transmission delay between any two stages of timing devices is T_tsv + T_4 = 400ps ≤ 500ps, which can meet the design clock frequency condition.

[0114] In another implementation, the design clock frequency condition is f ≥ 4GHz, meaning the transmission delay T between any two timing devices in the chip system 1 is ≤ 250ps. The second operating state configuration method defined in step S320 cannot meet the design clock frequency requirement. Therefore, according to step S321, the second operating state configuration method needs to be defined as follows: configuring the operating state of the configurable timing devices connected to both ends of the connection structure of the chip system as an effective operating state.

[0115] The modified effective transmission path is: first original timing device 121 - first configurable timing device 111 - through-silicon via structure 101 - second configurable timing device 112 - second original timing device 122; it can be seen that for the timing devices connected by the through-silicon via structure 101, the maximum transmission delay between any two stages of timing devices is T_1=T_tsv=T_4=200ps≤250ps, which can meet the design clock frequency condition.

[0116] According to the above embodiments, the working state configuration method provided by the present invention determines that when the data transmission requirement of the chip system is in operation, and the timing requirements are determined based on the clock frequency conditions of the chip system, a second working state configuration method is defined as follows: the working state of the configurable timing device connected to one end of the connection structure of the chip system is configured as an effective working state, and the working state of the configurable timing device connected to the other end of the connection structure is configured as an ineffective working state; or, the second working state configuration method is defined as follows: the working state of the configurable timing device connected to both ends of the connection structure of the chip system is configured as an effective working state; and the working state of the configurable timing device is configured according to the first working state configuration method to change the effective transmission path of the chip system; wherein, the effective transmission path is determined by the timing devices in the effective working state connected to both ends of the connection structure and is adapted to the timing requirements of the chip system.

[0117] As can be seen, the working state configuration method provided in this embodiment of the invention, when the chip system does not meet the design clock frequency requirement, changes the effective transmission path of the chip system by configuring the working state of the configurable timing device connected to one end of the connection structure of the chip system to an effective working state and configuring the working state of the configurable timing device connected to the other end of the connection structure to an invalid working state, or by configuring the working state of the configurable timing devices connected to both ends of the connection structure of the chip system to an effective working state, thereby increasing the clock frequency of the chip system to the design clock frequency and satisfying the design clock frequency, thereby optimizing the performance of the chip system.

[0118] Continue to refer to Figure 4 If it is determined that there is no data transmission requirement, step S400 is executed.

[0119] Step S400: Based on the timing requirements of the chip system, configure the operating state of the configurable timing devices in the chip system so that there is no data transmission on the effective transmission path of the chip system.

[0120] When the chip system does not require data transmission through the connection structure, i.e., when there is no data transmission requirement, the operating state of the configurable timing devices in the chip system is configured based on the timing requirements of the chip system, so that the effective transmission path of the chip system does not transmit data, thereby reducing the power consumption of the chip system.

[0121] refer to Figure 8 When the data transmission requirement is no data transmission, the determining condition further includes: low-power data transmission condition; the determining condition based on the timing requirements of the chip system, obtaining the corresponding defined working state configuration method under the determining condition, includes:

[0122] Step S410: Based on the low-power data transmission conditions, obtain the corresponding defined third working state configuration mode, wherein the third working state configuration mode is: configure the working state of any configurable timing device connected to both ends of the connection structure of the chip system to the off working state.

[0123] In some implementations, it is necessary to reduce the power consumption of the chip system 1 to avoid additional energy consumption. Therefore, by configuring the operating state of the configurable timing devices based on the timing requirements determined by the low-power data transmission conditions, the chip system can meet the low-power data transmission conditions.

[0124] After obtaining the corresponding defined third working state configuration method, continue to execute step S411.

[0125] Step S411: Configure the working state of the configurable timing device using the third working state configuration method.

[0126] The effective transmission path in the chip system is changed according to the configuration in step S411, thereby enabling the chip system to meet the low-power data transmission conditions.

[0127] Step S411 may include: using the third working state configuration method, configuring the working state of the configurable timing device connected to any end of the connection structure to a closed state; wherein, in the closed state, the output port of the configurable timing device outputs a fixed value.

[0128] The fixed value (Sig_1) can be 0, which saves power consumption by reducing the Toggle (switching) method of useless data transmission.

[0129] By configuring the operating state of configurable timing devices to be off, no data is transmitted, reducing the power consumption of the chip system and meeting the requirements for low-power data transmission.

[0130] The following is combined with, for example Figure 2 The chip system shown here will be described in detail in the step S400 of the working state configuration method provided in the embodiment of the present invention.

[0131] refer to Figure 2 When the data transmission requirement is no data transmission, step S410 is executed, that is, the working state of the configurable timing device is configured based on the third working state configuration method obtained according to the low power data transmission condition. The third working state configuration method is: the working state of the configurable timing device 11 connected to one end of the through silicon via structure 101 is configured to be in the off working state.

[0132] For example, the original operating state of the configurable sequential logic device 11 (i.e., the operating state in which the chip system 1 does not meet the design clock frequency requirements) is as follows: the first configurable sequential logic device 111 is in an enabled state, and the second configurable sequential logic device 112 is in an disabled state. When the chip system 1 does not need to transmit data through the through-silicon via structure 101, step S411 is executed: the operating state of the configurable sequential device 11 is configured using the third operating state configuration method, thereby changing the effective transmission path of the chip system 1 so that the effective transmission path is adapted to the low-power data transmission conditions of the chip system 1.

[0133] Specifically, according to the third working state configuration method, the working state of the second configurable timing device 112 connected to one end of the through-silicon via structure 101 is configured to be in a closed working state, thereby changing the effective transmission path of the chip system 1 and adapting the effective transmission path to low-power data transmission conditions.

[0134] According to the third working state configuration method defined in step S410, after configuring the working state of the configurable timing device 11 through the second gate unit 152, the effective transmission path in the chip system 1 changes. The changed effective transmission path is: first original timing device 121 - first configurable timing device 111 - through-silicon via structure 101 - second configurable timing device 112. It can be seen that the second original timing device 122 and other downstream timing devices do not perform data transmission, thereby satisfying the low-power data transmission condition.

[0135] According to the above embodiments, the working state configuration method provided by the present invention determines that when the data transmission requirement of the chip system during operation is no data transmission, it obtains a corresponding defined third working state configuration method based on the low-power data transmission conditions of the chip system. The third working state configuration method is: configuring the working state of the configurable timing device connected to one end of the connection structure of the chip system as an effective working state, and configuring the working state of the configurable timing device connected to the other end of the connection structure as an ineffective working state; or, defining a second working state configuration method is: configuring the working state of any configurable timing device connected to both ends of the connection structure of the chip system as a closed working state; wherein, the effective transmission path is determined by the timing devices in the effective working state connected to both ends of the connection structure, and is adapted to the low-power data transmission conditions.

[0136] As can be seen, the working state configuration method provided in this embodiment of the invention, when the chip system does not meet the low-power data transmission conditions, changes the effective transmission path of the chip system by configuring the working state of the configurable timing device connected to one end of the connection structure of the chip system to the off working state, thereby reducing the power consumption of the chip system.

[0137] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A chip system, characterized in that, include: At least one chip layer, each chip layer having at least one timing device, the timing device including a configurable timing device with a configurable operating state; the operating state of the configurable timing device is configured to any one of an enabled state, a disabled state, or a disabled state; the timing device also includes an original timing device whose operating state is maintained in an active operating state; the operating state of the configurable timing device includes an enabled state and / or a disabled state. A connection structure is provided, with one configurable timing device connected to each of its two ends; wherein the connection structure is a through-silicon via (TSV) structure; the chip system includes an upper-layer chip and a lower-layer chip connected by the TSV structure; the configurable timing device includes: a first configurable timing device located in the upper-layer chip and connected to one end of the TSV structure, and a second configurable timing device located in the lower-layer chip and connected to the other end of the TSV structure; When the chip system is operating, if it is determined that the data transmission requirement of the chip system is data transmission, the operating state of the configurable timing device is configured according to the timing requirements of the chip system to change the effective transmission path of the chip system; the operating state of the configurable timing device also includes: a closed state; if it is determined that the data transmission requirement of the chip system is no data transmission, the operating state of the configurable timing device is configured to a closed state so that there is no data transmission on the effective transmission path; when it is determined that the data transmission requirement of the chip system is data transmission, the state of the configurable timing device is configured to an enabled state, and the configurable timing device is a timing device in an effective operating state; when the state of the configurable timing device is configured to a disabled state, the configurable timing device is a timing device in an invalid operating state, so that data is transmitted according to the effective transmission path determined corresponding to the configurable timing device after the configuration of the operating state; the effective transmission path determined corresponding to the configurable timing device after the configuration of the operating state is: The path between the configurable timing device, configured to be in an active state and connected to one end of the connection structure, and the original timing device connected to the other end of the connection structure; Alternatively, the path between the original timing devices connected to both ends of the connection structure; Alternatively, the path between configurable timing devices connected to both ends of the connection structure, whose operating states are configured to be in an effective operating state; The effective transmission path is determined by timing devices in effective working state connected to both ends of the connection structure, and is adapted to the timing requirements.

2. The chip system as described in claim 1, characterized in that, The connection structure is: a connection wire on each chip layer; the configurable timing device includes: a third configurable timing device located on each chip layer and connected to one end of the connection wire, and a fourth configurable timing device located on each chip layer and connected to the other end of the connection wire.

3. The chip system as described in claim 1, characterized in that, The configurable timing device includes at least one of the following: a flip-flop, a register, or a counter.

4. The chip system as described in claim 1, characterized in that, Also includes: Gating unit; The gating unit is connected to the clock input port and data input port of the configurable timing device to configure the operating state of the configurable timing device based on the gating unit.

5. A method for configuring working states, characterized in that, Applied to the chip system as described in any one of claims 1-4, the method comprises: Determine the data transmission requirements of the chip system during operation; If it is determined that the data transmission requirement is that data transmission is required, the operating state of the configurable timing devices in the chip system is configured based on the timing requirements of the chip system to change the effective transmission path of the chip system; if it is determined that the data transmission requirement is that data transmission is not required, the operating state of the configurable timing devices in the chip system is configured based on the timing requirements of the chip system to ensure that there is no data transmission on the effective transmission path of the chip system. The effective transmission path is determined by timing devices in effective working state connected to both ends of the connection structure, and is adapted to the timing requirements of the chip system.

6. The working state configuration method as described in claim 5, characterized in that, The configuration of the operating states of configurable timing devices in the chip system based on the timing requirements of the chip system includes: Based on the determination conditions of the timing requirements of the chip system, obtain the corresponding defined working state configuration method under the determination conditions; The operating states of configurable timing devices in the chip system are configured using the obtained operating state configuration method.

7. The working state configuration method as described in claim 6, characterized in that, The determining conditions include: timing constraints; the determining conditions based on the timing requirements of the chip system, and obtaining the corresponding defined working state configuration method under the determining conditions, include: Based on the timing constraints, a first working state configuration method is defined, wherein the first working state configuration method is: the working state of the configurable timing device connected to one end of the connection structure of the chip system is configured as an effective working state, and the working state of the configurable timing device connected to the other end of the connection structure is configured as an invalid working state. The step of configuring the operating state of the configurable timing devices in the chip system using the acquired operating state configuration method includes: The operating state of the configurable timing device is configured using the first operating state configuration method.

8. The working state configuration method as described in claim 7, characterized in that, The step of configuring the operating state of the configurable timing device using the first operating state configuration method includes: Using the first working state configuration method, the working state of the configurable timing device connected to one end of the connection structure is configured to be enabled, so that the working state of the configurable timing device is an effective working state. The operating state of the configurable timing device connected to the other end of the connection structure is configured to be disabled, so that the operating state of the configurable timing device is invalid.

9. The working state configuration method as described in claim 8, characterized in that, The timing constraints include: timing constraints based on setup time constraints and timing constraints based on hold time constraints.

10. The working state configuration method as described in claim 6, characterized in that, The determining conditions include: design clock frequency conditions; the determining conditions based on the timing requirements of the chip system, and obtaining the corresponding defined working state configuration method under the determining conditions, include: Based on the design clock frequency conditions, a corresponding second working state configuration method is obtained. The second working state configuration method is: the working state of the configurable timing device connected to one end of the connection structure of the chip system is configured as an effective working state, and the working state of the configurable timing device connected to the other end of the connection structure is configured as an invalid working state. Alternatively, the second working state configuration method can be defined as: configuring the working state of the configurable timing device connected to both ends of the connection structure of the chip system as an effective working state; The step of configuring the operating state of the configurable timing devices in the chip system using the acquired operating state configuration method includes: The operating state of the configurable timing device is configured using the second operating state configuration method.

11. The working state configuration method as described in claim 10, characterized in that, The step of configuring the operating state of the configurable timing device using the second operating state configuration method includes: Using the second working state configuration method, the working state of the configurable timing device connected to one end of the connection structure is configured to be enabled, so that the working state of the configurable timing device is an effective working state. The operating state of the configurable timing device connected to the other end of the connection structure is configured to be disabled, so that the operating state of the configurable timing device is invalid. Alternatively, using the second working state configuration method, the working states of all configurable timing devices connected to both ends of the connection structure are configured to be enabled, so that the working states of the configurable timing devices are in an effective working state.

12. The working state configuration method as described in claim 11, characterized in that, The determining conditions also include: low-power data transmission conditions; the determining conditions based on the timing requirements of the chip system, obtaining the corresponding defined working state configuration method under the determining conditions, includes: Based on the low-power data transmission conditions, a corresponding third working state configuration method is obtained. The third working state configuration method is: to configure the working state of any configurable timing device connected to both ends of the connection structure of the chip system to the off working state. The step of configuring the operating state of the configurable timing devices in the chip system using the acquired operating state configuration method includes: The operating state of the configurable timing device is configured using the third operating state configuration method.

13. The working state configuration method as described in claim 12, characterized in that, The configuration of the operating state of the configurable timing device using the third operating state configuration method includes: Using the third working state configuration method, the working state of the configurable timing device connected to any end of the connection structure is configured to be in the off state; In the off state, the output port of the configurable timing device outputs a fixed value.

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