Memory device with vertical transistor and method of forming the same

Abstract

A memory device includes an array of memory cells. Each memory cell includes a vertical transistor having a semiconductor body extending vertically in a first direction. Each memory cell includes a storage element coupled to a first end of the semiconductor body and a bit line extending in a second direction perpendicular to the first direction. The bit line is connected to second ends of the semiconductor bodies of a row of the vertical transistors. The bit line includes a semiconductor epitaxial layer extending in the second direction and connected at a top surface of the semiconductor epitaxial layer to the second ends of the semiconductor bodies of the row of the vertical transistors.

Description

Technical Field

[0001] This disclosure relates to storage devices and methods of manufacturing them. Background Technology

[0002] Planar memory cells can be miniaturized to smaller sizes through improvements in process technology, circuit design, programming algorithms, and manufacturing processes. However, as the feature size of memory cells approaches its lower limit, planar processes and manufacturing technologies become challenging and costly. As a result, the storage density of planar memory cells is approaching its upper limit.

[0003] Three-dimensional (3D) memory architectures can address the density limitations of planar memory cells. A 3D memory architecture includes a memory array and peripheral circuitry to facilitate the operation of the memory array. Summary of the Invention

[0004] This disclosure provides a method for manufacturing a memory device. A stack comprising a first semiconductor layer is formed. The stack includes a second semiconductor layer above the first semiconductor layer, a third semiconductor layer above the second semiconductor layer, and a fourth semiconductor layer above the third semiconductor layer. The stack is etched through the fourth, third, and second semiconductor layers to form a first trench along a first direction and on the first semiconductor layer. The first trench is filled with an insulating material to form trench isolation. Remaining portions of the fourth, third, and second semiconductor layers are sandwiched between adjacent trench isolations. The remaining portions of the fourth semiconductor layer and the trench isolations are etched to form a second trench on the third semiconductor layer and along a second direction perpendicular to the first direction, and a semiconductor body of a vertical transistor extending upward in a third direction and surrounded by the second trench and the trench isolations. The third direction is perpendicular to the first and second directions. The vertical transistor is located on top of the remaining portions of the third semiconductor layer. A gate structure of the vertical transistor is formed, the gate structure being along the second direction and coupled to at least one side of the semiconductor body.

[0005] In one aspect, a memory device includes an array of memory cells. Each memory cell includes a vertical transistor having a semiconductor body extending vertically in a first direction. Each memory cell includes a memory element coupled to a first end of the semiconductor body and a bit line extending in a second direction perpendicular to the first direction. The bit line is connected to a second end of the semiconductor body of the row of vertical transistors. The bit line includes a semiconductor epitaxial layer extending in the second direction and connected at its top surface to the second end of the semiconductor body of the row of vertical transistors.

[0006] In one aspect, a memory system includes a memory controller and a memory device coupled to the memory controller. The memory device includes an array of memory cells. Each memory cell includes a vertical transistor having a semiconductor body extending vertically in a first direction. Each memory cell includes a storage element coupled to a first end of the semiconductor body and a bit line extending in a second direction perpendicular to the first direction. The bit line is connected to a second end of the semiconductor body of the row of vertical transistors. The bit line includes a semiconductor epitaxial layer extending in the second direction and connected at its top surface to the second end of the semiconductor body of the row of vertical transistors. Attached Figure Description

[0007] When read in conjunction with the accompanying drawings, various aspects of this disclosure can be understood from the following detailed description. It should be noted that, in accordance with industry standard practice, the various features are not drawn to scale. In fact, the dimensions of the various features may be increased or decreased for clarity of discussion.

[0008] Figure 1 A block diagram of an exemplary system having a storage device is shown, according to some aspects of this disclosure.

[0009] Figure 2 A schematic diagram of a memory device including peripheral circuitry and an array of memory cells, each having a vertical transistor, is shown, according to some aspects of this disclosure.

[0010] Figure 3 A schematic circuit diagram of a storage device including peripheral circuitry and an array of dynamic random access memory (DRAM) cells, according to some aspects of this disclosure, is shown.

[0011] Figure 4 A schematic circuit diagram of a storage device including an array of peripheral circuitry and phase-change memory (PCM) cells, according to some aspects of this disclosure, is shown.

[0012] Figures 5A-5B The process for manufacturing a memory device is illustrated, in which a semiconductor body 502 of a vertical transistor is formed without employing an etch stop layer.

[0013] Figure 6A , Figure 6B and Figure 6C The invention illustrates a memory device manufacturing process in which an etch stop layer is used to improve the uniformity of the bottom profile and etch depth of isolation trenches, word line trenches, and back-side bit line silicon recesses.

[0014] Figure 7 A plan view is shown of an array of memory cells 702, each including a vertical transistor, in a memory device 700 according to some aspects of the present disclosure.

[0015] Figure 8 A side view of a cross-section of a storage device 800 made using an etch stop layer, according to some aspects of this disclosure, is shown.

[0016] Figure 9A-1 / Figure 9A-2 Image / 9B-1 / Figure 9B-2 / Figure 9C-1 / Figure 9C-2 and Figure 9D-9J The present disclosure illustrates a manufacturing process for forming a memory device (such as memory device 700 or 800) by using several etch stop layers.

[0017] Figure 10 A flowchart is shown of a manufacturing process 1000 for forming a 3D memory device including vertical transistors, according to some aspects of this disclosure. Detailed Implementation

[0018] Although specific configurations and arrangements have been discussed, it should be understood that this is for illustrative purposes only. Therefore, other configurations and arrangements may be used without departing from the scope of this disclosure. Furthermore, this disclosure can be used in a variety of other applications. The functional and structural features described in this disclosure may be combined, adjusted, and modified with each other and in ways not specifically shown in the accompanying drawings, such combinations, adjustments, and modifications being within the scope of this disclosure.

[0019] Generally, terms can be understood at least partly from their usage in context. For example, depending at least partly on the context, the term "one or more" as used herein can be used to describe any feature, structure, or characteristic in a singular sense, or it can be used to describe a combination of features, structures, or characteristics in a plural sense. Similarly, depending at least partly on the context, terms such as "a" or "described" can also be understood to express either a singular or a plural usage. Furthermore, the term "based on" can be understood not necessarily to express an exclusive set of elements, but rather to allow for the presence of other elements that are not necessarily explicitly described, which also depends at least partly on the context.

[0020] It should be readily understood that the meanings of “on,” “above,” and “on top of” in this disclosure should be interpreted in the broadest possible sense, such that “on” means not only “directly on” but also includes “on” with an intermediate feature or layer, and “above” or “on top of” means not only “above” or “on top of” but also includes “on” or “on top of” without an intermediate feature or layer (i.e., directly on).

[0021] Furthermore, for ease of description, spatially relative terms such as “below,” “under,” “lower,” “above,” and “upper” may be used herein to describe the relationship between one element or feature and another (or more) shown in the figures. In addition to the orientations shown in the figures, the spatially relative terms are intended to cover different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations) and the spatially related descriptive terms used herein may be interpreted accordingly.

[0022] As used herein, the term "substrate" refers to the material on which subsequent material layers are added. The substrate itself may be patterned. The material added on top of the substrate may be patterned or may remain unpatterned. Furthermore, the substrate may include a variety of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of a non-conductive material, such as glass, plastic, or sapphire wafers.

[0023] As used herein, the term "layer" refers to a portion of material comprising a region having thickness. A layer may extend over the entire lower or upper layer structure, or may have a range smaller than that of the lower or upper layer structure. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure having a thickness less than that of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure or between any pair of horizontal planes at the top and bottom surfaces. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer, which may include one or more layers, and / or may have one or more layers on, above, and / or below it. A layer may include multiple layers. For example, an interconnect layer may include one or more conductor and contact layers (where interconnect lines and / or vertical interconnect vias are formed) and one or more dielectric layers.

[0024] I. Storage devices with vertical transistors

[0025] Transistors serve as switches or selection devices in memory cells of some memory devices, such as Dynamic Random Access Memory (DRAM), Phase-Change Memory (PCM), and Ferroelectric DRAM (FRAM). However, planar transistors, typically used in existing memory cells, generally have a horizontal structure, with buried word lines in the substrate and bit lines above the substrate. This increases the area occupied by the transistor because the source and drain of the planar transistor are laterally positioned in different locations. The design of planar transistors also complicates the arrangement of interconnect structures coupled to the memory cell, such as word lines and bit lines, for example, by limiting the spacing of word lines and / or bit lines, thereby increasing manufacturing complexity and reducing yield. Furthermore, because the bit lines and memory devices (e.g., capacitors or PCM elements) are arranged on the same side of the planar transistor (above the transistor and substrate), the bit line process margin is limited by the memory devices, and the coupling capacitance between the bit lines and memory devices (such as capacitors) increases. Planar transistors may also suffer from high leakage currents as the saturation drain current continues to increase, which is undesirable for the performance of the memory device.

[0026] On the other hand, the memory cell array and the peripheral circuitry used to control the memory cell array are typically arranged side-by-side in the same plane. As the number of memory cells increases, in order to maintain the same chip size, the size of the components in the memory cell array (such as transistors, word lines, and / or bit lines) needs to be continuously reduced so as not to significantly reduce the efficiency of the memory cell array.

[0027] To address one or more of the aforementioned problems, vertical transistors can replace planar transistors as switching and selection devices in the cell arrays of memory devices (e.g., DRAM, PCM, and FRAM). Compared to planar transistors, vertically arranged transistors (e.g., with drains and sources overlapping in a planar diagram) can reduce transistor area and simplify the layout of interconnect structures (e.g., metal wiring for word lines and bit lines), which can reduce manufacturing complexity and increase yield. For example, the spacing between word lines and / or bit lines can be reduced to facilitate manufacturing. The vertical structure of transistors also allows bit lines and memory devices (such as capacitors) to be arranged vertically on opposite sides of the transistor (e.g., one above the transistor and one below), which can increase the process margin of the bit lines and reduce the coupling capacitance between the bit lines and the memory devices.

[0028] Furthermore, the memory cell array with vertically arranged transistors and its peripheral circuitry can be formed on different wafers and bonded together face-to-face. Therefore, the thermal budget for manufacturing the memory cell array does not affect the fabrication of the peripheral circuitry. Compared to side-by-side arrangements, stacked memory cell arrays and peripheral circuitry can also reduce chip size, thereby improving array efficiency. In some embodiments, bonding techniques are used to stack more than one memory cell array on top of each other to further improve array efficiency. In some embodiments, due to the vertically arranged transistors, word lines, and bit lines are positioned close to the bonding interface, they can be coupled to the peripheral circuitry via a large number (e.g., millions) of parallel bonding contacts across the bonding interface. This allows for direct, short-distance (e.g., micrometer-scale) electrical connections between the memory cell array and the peripheral circuitry, increasing the throughput and input / output (I / O) speed of the memory device.

[0029] In some embodiments, the vertical transistors disclosed herein include multi-gate transistors (e.g., gate-all-around (GAA) transistors, tri-gate transistors, or dual-gate transistors), which may have a larger gate control region to achieve better channel control with a smaller subthreshold swing. Since the channel is fully depleted, the leakage current of multi-gate transistors can also be significantly reduced. Therefore, using multi-gate transistors instead of planar transistors can achieve better speed (saturation drain current) / leakage current performance.

[0030] In some implementations, the vertical transistors disclosed herein include single-gate transistors (also referred to as single-sided gate transistors) arranged in a mirror-symmetric manner with respect to adjacent transistors in the bit-line direction, due to the use of trench isolation extending along the word line direction to divide multi-gate transistors (e.g., dual-gate transistors). Therefore, the memory cell density in the bit-line direction can be significantly increased (e.g., doubled) without overcomplicating the fabrication process compared to processes such as self-aligned double patterning (SADP). Furthermore, the mirror-symmetric single-gate transistor has a larger process window for word line, bit line, and transistor pitch reduction compared to planar transistors or multi-gate vertical transistors (e.g., those with dual-sided or full-ring gates).

[0031] Figure 1 A block diagram of a system 100 having a storage device according to some aspects of this disclosure is shown. System 100 may be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having storage therein. Figure 1As shown, system 100 may include a host 108 and a memory system 102 having one or more storage devices 104 and a memory controller 106. The host 108 may be a processor of an electronic device, such as a central processing unit (CPU), or a system-on-a-chip (SoC), such as an application processor (AP). The host 108 may be configured to send or receive data to or from the storage device 104.

[0032] Storage device 104 can be any storage device disclosed herein. In some embodiments, storage device 104 includes an array of storage cells, each storage cell including a vertical transistor, as described herein.

[0033] According to some embodiments, a memory controller 106 is coupled to the storage device 104 and the host 108 and is configured to control the storage device 104. The memory controller 106 can manage data stored in the storage device 104 and communicate with the host 108. The memory controller 106 can be configured to control operations of the storage device 104, such as read, write, and refresh operations. The memory controller 106 can also be configured to manage various functions regarding data stored or to be stored in the storage device 104, including but not limited to refresh and timing control, command / request translation, buffering and scheduling, and power management. In some embodiments, the memory controller 106 is also configured to determine the maximum memory capacity that the computer system can use, the number of memory groups, the memory type and speed, the memory particle data depth and data width, and other important parameters.

[0034] The memory controller 106 may also perform any other suitable functions. The memory controller 106 may communicate with external devices (e.g., host 108) according to a specific communication protocol. For example, the memory controller 106 may communicate with external devices via at least one of various interface protocols, such as USB, MMC, Peripheral Component Interconnect (PCI), Fast PCI (PCI-E), Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer Small Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), Firewire, etc.

[0035] Figure 2A schematic diagram of a storage device 200, including peripheral circuitry and arrays of memory cells, each having a vertical transistor, according to some aspects of this disclosure, is shown. The storage device 200 may include a memory cell array 201 and peripheral circuitry 202 coupled to the memory cell array 201. The memory cell array 201 may be any suitable memory cell array, wherein each memory cell 208 includes a vertical transistor 210 and a storage element 212 coupled to the vertical transistor 210. In some embodiments, the memory cell array 201 is a DRAM cell array, and the storage element 212 is a capacitor for storing charge as binary information stored by the respective DRAM cell. In some embodiments, the memory cell array 201 is a PCM cell array, and the storage element 212 is a PCM element (e.g., including a chalcogenide alloy) for storing binary information of the respective PCM cell based on the different resistivities of the PCM elements in the amorphous and crystalline phases. In some implementations, the memory cell array 201 is an FRAM cell array, and the storage device 212 is a ferroelectric capacitor for storing binary information of the corresponding FRAM cell based on the switching between two polarization states of the ferroelectric material under an external electric field.

[0036] like Figure 2 As shown, the memory cells 208 can be arranged as a two-dimensional (2D) array with rows and columns. The memory device 200 may include word lines 204 coupling peripheral circuitry 202 and the memory cell array 201 for controlling the switching of vertical transistors 210 in the memory cells 208 located in a row, and bit lines 206 coupling peripheral circuitry 202 and the memory cell array 201 for sending data to and / or receiving data from the memory cells 208 located in a column. That is, each word line 204 is coupled to a corresponding row of memory cells 208, and each bit line is coupled to a corresponding column of memory cells 208.

[0037] A vertical transistor 210 (such as a vertical metal-oxide-semiconductor field-effect transistor (MOSFET)) can replace the planar transistor as the transfer transistor for the memory cell 208, thereby reducing the area occupied by the transfer transistor, coupling capacitance, and interconnect wiring complexity. Figure 2 As shown, in some embodiments, unlike planar transistors where the active region is formed in the substrate, the vertical transistor 210 includes a semiconductor body 214 extending vertically (in the z-direction) above a substrate (not shown). That is, the semiconductor body 214 may extend above the top surface of the substrate to allow channels to be formed not only at the top surface of the semiconductor body 214 but also at one or more of its side surfaces.

[0038] like Figure 2As shown, for example, the semiconductor body 214 may have a cuboid shape to expose its four sides. It should be understood that the semiconductor body 214 may have any suitable 3D shape, such as a polyhedral shape or a cylindrical shape. That is, the cross-section of the semiconductor body 214 in a planar view (e.g., in the xy plane) may have a square shape, a rectangular shape (or a trapezoidal shape), a circular (or elliptical) shape, or any other suitable shape. It should be understood that for a semiconductor body whose cross-section in a planar view has a circular or elliptical shape, the semiconductor body can still be considered to have multiple sides, such that the gate structure contacts more than one side of the semiconductor body. As described below regarding the manufacturing process, in some cases, the semiconductor body 214 may be formed from a substrate (e.g., by etching or epitaxy) and therefore have the same semiconductor material as the substrate (e.g., a silicon substrate) (e.g., crystalline silicon).

[0039] like Figure 2 As shown in the example, the vertical transistor 210 may further include a gate structure 216, for example, contacting one or more sides of the semiconductor body 214 in one or more planes on one or more side surfaces of the active region(s). That is, the active region of the vertical transistor 210 (e.g., the semiconductor body 214) may be at least partially surrounded by the gate structure 216. The gate structure 216 may include a gate dielectric 218 on one or more sides of the semiconductor body 214, for example, contacting four side surfaces of the semiconductor body 214, such as... Figure 2 As shown. Gate structure 216 may also include a gate electrode 220 on and in contact with gate dielectric 218. Gate dielectric 218 may include any suitable dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or a high-k dielectric. For example, gate dielectric 218 may include silicon oxide, a form of gate oxide. Gate electrode 220 may include any suitable conductive material, such as polysilicon, metals (e.g., tungsten (W), copper (Cu), aluminum (Al), etc.), metal compounds (e.g., titanium nitride (TiN), tantalum nitride (TaN), etc.), or silicides. For example, gate electrode 220 may include doped polysilicon, a form of gate polysilicon. In some embodiments, gate electrode 220 includes multiple conductive layers, such as a W layer over a TiN layer. It should be understood that in some examples, gate electrode 220 and word line 204 may be a continuous conductive structure. That is, the gate electrode 220 can be regarded as part of the word line 204 forming the gate structure 216, or the word line 204 can be regarded as an extension of the gate electrode 220 to be coupled to the peripheral circuit 202.

[0040] like Figure 2As shown, the vertical transistor 210 may further include a pair of source and drain electrodes (S / D, doped regions, also referred to as source and drain electrodes) formed respectively at both ends of the semiconductor body 214 in the vertical direction (z-direction). The source and drain electrodes may be doped with any suitable P-type dopant, such as boron (B) or gallium (Ga), or any suitable N-type dopant, such as phosphorus (P) or arsenic (As). The source and drain electrodes may be separated in the vertical direction (z-direction) by a gate structure 216. That is, the gate structure 216 is formed vertically between the source and drain electrodes. As a result, when the gate voltage applied to the gate electrode 220 of the gate structure 216 is higher than the threshold voltage of the vertical transistor 210, one or more channels (not shown) of the vertical transistor 210 may be formed vertically in the semiconductor body 214 between the source and drain electrodes. That is, according to some embodiments, each channel of the vertical transistor 210 is also formed in the vertical direction along which the semiconductor body 214 extends.

[0041] In some implementations, such as Figure 2 As shown, the vertical transistor 210 is a multi-gate transistor. That is, the gate structure 216 can be connected to more than one side of the semiconductor body 214 (e.g., Figure 2 The four sides of the transistor are contacted to form more than one gate, allowing more than one channel to be formed between the source and drain during operation. That is, unlike planar transistors which only include a single planar gate (and create a single planar channel), Figure 2 The vertical transistor 210 shown can include multiple vertical gates on multiple sides of the semiconductor body 214 due to the 3D structure of the semiconductor body 214 and the gate structure 216 surrounding multiple sides of the semiconductor body 214. As a result, compared to planar transistors, Figure 2 The vertical transistor 210 shown can have a larger gate control region to achieve better channel control with a smaller subthreshold swing. Since the channel is fully depleted, the leakage current (Ioff) of the vertical transistor 210 can be significantly reduced in the well. In various examples, multi-gate vertical transistors can include dual-gate vertical transistors (e.g., dual-side-gate vertical transistors), tri-gate vertical transistors (e.g., tri-side-gate vertical transistors), and GAA vertical transistors.

[0042] It should be understood that, although the vertical transistor 210 in Figure 2While shown as a multi-gate transistor, the vertical transistor disclosed herein may also include a single-gate transistor. That is, the gate structure 216 may contact a single side of the semiconductor body 214, for example, for the purpose of increasing transistor and memory cell density. It should also be understood that although the gate dielectric 218 is shown as separate from other gate dielectrics of adjacent vertical transistors (not shown) (separate structure), the gate dielectric 218 may be part of a continuous dielectric layer of multiple gate dielectrics having vertical transistors.

[0043] In planar transistors and some lateral multi-gate transistors (e.g., FinFETs), the active region, such as the semiconductor body (e.g., a fin), extends laterally (in the xy plane), and the source and drain are located at different positions in the same lateral plane (xy plane). In contrast, according to some embodiments, in the vertical transistor 210, the semiconductor body 214 extends vertically (in the z-direction), and the source and drain are located in different lateral planes. In some embodiments, the source and drain are formed at opposite ends of the semiconductor body 214 in the vertical direction (z-direction), thus overlapping in a planar view. As a result, the area occupied by the vertical transistor 210 (in the xy plane) can be reduced compared to planar transistors and lateral multi-gate transistors. Furthermore, the metal wiring coupled to the vertical transistor 210 can be simplified because the interconnects can be wired in different planes. For example, bit line 206 and memory device 212 can be formed on opposite sides of the vertical transistor 210. In one example, bit line 206 may be coupled to a source or drain at the upper end of semiconductor body 214, while memory device 212 may be coupled to another source or drain at the lower end of semiconductor body 214.

[0044] like Figure 2 As shown, storage device 212 can be coupled to the source or drain of vertical transistor 210. Storage device 212 can include any means capable of storing binary data (e.g., 0s and 1s), including but not limited to capacitors for DRAM and FRAM cells and PCM elements for PCM cells. In some embodiments, vertical transistor 210 controls the selection and / or state switching of a corresponding storage device 212 coupled to vertical transistor 210. In some embodiments, such as... Figure 3 As shown, each memory cell 208 is a DRAM cell 302, which includes a transistor 304 (e.g., using...). Figure 2 The vertical transistor 210 is implemented in the middle) and the capacitor 306 (e.g., Figure 2(Example of storage device 212 in the example). The gate of transistor 304 (e.g., corresponding to gate electrode 220) can be coupled to word line 204, one of the source and drain of transistor 304 can be coupled to bit line 206, the other of the source and drain of transistor 304 can be coupled to one electrode of capacitor 306, and the other electrode of capacitor 306 can be coupled to ground.

[0045] In some implementations, such as Figure 4 As shown, each memory cell 208 is a PCM cell 402, which includes a transistor 404 (e.g., using...). Figure 2 The vertical transistor 210 is implemented in the middle) and the PCM element 406 (e.g., Figure 2 (Example of storage device 212 in the example). The gate of transistor 404 (e.g., corresponding to gate electrode 220) can be coupled to word line 204, one of the source and drain of transistor 404 can be coupled to ground, the other of the source and drain of transistor 404 can be coupled to one electrode of PCM element 406, and the other electrode of PCM element 406 can be coupled to bit line 206.

[0046] Peripheral circuitry 202 can be coupled to memory cell array 201 via bit lines 206, word lines 204, and any other suitable metal wiring. As described above, peripheral circuitry 202 may include any suitable circuitry for facilitating operation of memory cell array 201 by applying voltage and / or current signals to and from each memory cell 208 via word lines 204 and bit lines 206. For example, peripheral circuitry 202 may include various types of peripheral circuitry formed using CMOS technology.

[0047] II. Forming a storage device by employing an etch stop layer

[0048] Figures 5A-5B A memory device manufacturing process is illustrated, in which a semiconductor body 502 of a vertical transistor is formed without employing an etch stop layer. Figure 5A In this process, multiple first trenches (isolation trenches) 501 can be formed in a silicon substrate along the bit line direction (y-direction). For example, a first photolithography process and a first etching process can be performed in the substrate to form the isolation trenches 501. An insulating material such as silicon oxide can be filled in the isolation trenches to form trench isolation. Figure 5B In this process, multiple second trenches (referred to as word line trenches or gate trenches) 503 can be formed along the word line direction (x-direction) through the trench isolation. For example, a second photolithographic patterning process and a second etching process can be performed for the word line trenches 503. As a result, multiple semiconductor bodies 502 surrounded by trench isolation and word line trenches 503 can be formed.

[0049] exist Figures 5A-5B In the manufacturing process, no etch stop layer is formed and used for the first etch process in the y-direction and the second etch process in the x-direction. Due to the high aspect ratio of the first and second trenches, it is difficult to control the bottom profile and etch depth uniformity of these trenches. Furthermore, in some embodiments, a backside silicon recess process is performed in a later manufacturing stage to remove silicon and form a recess along the bit line direction below the semiconductor body 502 and between the trench isolations. Source / drain region doping and bit line deposition can be performed in the recess. Similarly, to form these recesses, it is difficult to control the recess uniformity without an etch stop layer.

[0050] Figure 6A , Figure 6B and Figure 6C The invention illustrates a memory device manufacturing process in which an etch stop layer is used to improve the uniformity of the bottom profile and etch depth of isolation trenches, word line trenches, and back-side bit line silicon recesses.

[0051] exist Figure 6A In this process, the layer stack 600 can be formed in various ways. As an example, a semiconductor substrate 601 can be provided first. Subsequently, a first semiconductor layer 602, a second semiconductor layer 603, a third semiconductor layer 604, and a fourth semiconductor layer 605 can be formed sequentially. In some embodiments, the semiconductor substrate 601 can be a crystalline silicon substrate, and multiple layers 602-605 can be epitaxially grown. In some embodiments, other formation methods can be used to form the layer stack 600. In some embodiments, the two etch stop layers are silicon-germanium (SiGe) epitaxial layers, and the two semiconductor layers 603 and 605 are silicon epitaxial layers.

[0052] exist Figure 6B In this process, an isolation trench 611 can be formed along the bit line direction. As shown, the first semiconductor layer 602 can be used as an etch stop layer for etching the isolation trench 611. The resulting isolation trench 611 extends downward through the fourth semiconductor layer 605, the third semiconductor layer 604, and the second semiconductor layer 603, and reaches or enters the first semiconductor layer 602. The isolation trench 611 can then be filled with an insulating material such as silicon dioxide to form trench isolation.

[0053] exist Figure 6C In this process, word line trenches 621 can be formed along the word line direction. As shown, the third semiconductor layer 604 can be used as an etch stop layer for etching the word line trenches 621. The resulting word line trenches 621 extend downward through the fourth semiconductor layer 605 (the remaining portion sandwiched between adjacent trench isolations) and the trench isolations, and reach or enter the third semiconductor layer 604. Accordingly, a vertically positioned semiconductor body 622 is formed.

[0054] For example Figure 6C As shown, the remaining portion 623 of the third semiconductor layer 604 lies below the semiconductor body 622, sandwiched between adjacent trench isolations, and above the second semiconductor layer 603. In later stages of the manufacturing process, the remaining portion 623 can be used as part of a bitline structure. Therefore, when SiGe is used in the third semiconductor layer 604, the remaining portion 623 (possibly with additional doping) can be referred to as a bitline SiGe structure.

[0055] The remaining portion 624 of the second semiconductor layer 603 lies between the remaining portion 623 and the first semiconductor layer 602, and is sandwiched between adjacent trench isolations. In a later stage of the manufacturing process, the substrate 601 and the first semiconductor layer 602 can be removed. Subsequently, the remaining portion 624 can be removed (silicon recess process), forming a recess (referred to as a bit line recess) in the space of the remaining portion 624. Bit line metal can be deposited in the bit line recess and adjacent to the bottom surface of the bit line SiGe structure 623. In the silicon recess process, the third semiconductor layer 604 (bit line SiGe structure 623) can be used as an etch stop layer for etching the remaining portion 624.

[0056] For reference Figures 6A-6C The aforementioned method can introduce a stack of Si-SiGe layers epitaxially grown on a silicon substrate. The SiGe epitaxial layer can be used as an etch stop layer for forming isolation trenches, word line trenches, and bit line silicon recesses, thereby improving the uniformity of etch profile and etch depth.

[0057] refer to Figure 7-8 A memory device manufactured using the etch stop layer described above is described. Figure 7 A plan view of an array of memory cells 702, each including a vertical transistor, in a memory device 700 according to some aspects of this disclosure is shown. Figure 7 As shown, the storage device 700 may include multiple word lines 704, each word line 704 extending in a first lateral direction (x-direction, referred to as the word line direction). The storage device 700 may also include multiple bit lines 706, each bit line 706 extending in a second lateral direction (y-direction, referred to as the bit line direction) perpendicular to the first lateral direction. Figures 6A-6C In the example, bit line 706 may include the remainder 623 of the third semiconductor layer 604 (bit line SiGe structure 623). It should be understood that... Figure 7 The storage device 700 is not shown in a cross-section in the same horizontal plane, and the word line 704 and bit line 706 may be formed in different horizontal planes to facilitate wiring.

[0058] Memory cell 702 may be formed at the intersection of word line 704 and bit line 706. In some embodiments, each memory cell 702 includes a vertical transistor having a semiconductor body 708 and a gate structure 710 (e.g., Figure 2 The vertical transistor 210 in the semiconductor body 708 may extend in the substrate in a vertical direction (z-direction, not shown) perpendicular to the first and second lateral directions. The vertical transistor may be a dual-gate transistor, wherein the two gate structures 710 are opposite to the sides of the semiconductor body 708 (where the active region forming the channel is located) (e.g., Figure 7 Two of the four sides of the object are in contact. For example... Figure 7 As shown, each of the two gate structures 710 is adjacent to one side of the semiconductor body 708 (having a rectangular or square cross-section) in the bit line direction (y-direction) in the plan view. According to some embodiments, the gate structure 710 does not surround or contact the other two sides of the semiconductor body 708 in the word line direction.

[0059] The gate structure 710 may include a gate dielectric 712 adjacent to one side of the semiconductor body 708 in a plan view, and a gate electrode 714 in contact with the gate dielectric 712. In some embodiments, the gate dielectric 712 is laterally located between the gate electrode 714 and the semiconductor body 708 in the bit line direction (y direction). The gate electrode 714 may be a portion of a word line 704, and the word line 704 may be an extension of the gate electrode 714. That is, the gate electrodes 714 of adjacent vertical transistors in the word line direction (x direction) are continuous, for example, a portion of a continuous conductive layer having gate electrodes 714. In some embodiments, the gate structure 710 of a row of vertical transistors is continuous in the x direction, such as... Figure 7 As shown.

[0060] In some other embodiments, the semiconductor body 708 can be divided into two segments using trench isolation extending in the word line direction (x-direction) and parallel to the word line 704. The trench isolation and word line 704 can be arranged in an interleaved manner in the bit line direction. For example, a trench isolation can be formed in the middle of a semiconductor pillar (not shown). As a result, the pair of semiconductor bodies are mirror-symmetrical with respect to the trench isolation. A pair of single-gate vertical transistors corresponding to the pair of semiconductor bodies are mirror-symmetrical with respect to the trench isolation. The corresponding gate structure 710 is also mirror-symmetrical with respect to the trench isolation.

[0061] By using trench isolation to split dual-gate vertical transistors into single-gate vertical transistors, the number of memory cells (and cell density) in the bit line direction can be doubled compared to dual-gate vertical transistors without overcomplicating the manufacturing process (e.g., compared to using SADP process).

[0062] Figure 8 A side view of a cross-section of a memory device 800 made using an etch stop layer described above, according to some aspects of this disclosure, is shown. The memory device 800 may be an example of a memory device 700 including dual-gate vertical transistors. It should be understood that... Figure 8 For illustrative purposes only, and may not necessarily reflect the actual device structure dimensions or scale in practice. Storage device 800 may include an array of storage cells (e.g., DRAM cells). A cross-section of storage device 800 can be obtained by cutting through a yz plane passing through a row of storage cells and the bit line below it. As shown, each storage cell in a row may include a vertical transistor 816 and a storage element 803 (e.g., including a capacitor) coupled to the vertical transistor 816. The row of storage cells is located on bit line 820.

[0063] In some implementations, bit line 820 includes semiconductor line 821 (or semiconductor layer 821), contact line 822 (first interconnect layer 822), and metal line 823 (second interconnect layer 823). Semiconductor line 821 may be similar to that generated by an etch stop layer in a stack of Si-SiGe layers. Figure 6C The remaining portion (or bit line SiGe structure) 623. For example, semiconductor line 821 may include SiGe. Semiconductor line 821 may be an epitaxially grown semiconductor layer (or semiconductor epitaxial layer). For example, semiconductor line 821 may be an epitaxially grown SiGe layer (or SiGe epitaxial layer), the opposite of a SiGe layer formed by implanting Ge into a silicon layer. Various growth techniques can be used to form SiGe semiconductor line 821, such as molecular beam epitaxy (MBE), low-pressure chemical vapor deposition (LPCVD), and ultra-high vacuum chemical vapor deposition (UHV-CVD).

[0064] In some implementations, the Ge concentration in the SiGe semiconductor line 821 is optimized to obtain a specific concentration distribution in the vertical direction. For example, the Ge concentration can be controlled at a lower level near the interface between the SiGe layer and the adjacent lower or upper silicon layer compared to locations farther from the interface. In this way, the SiGe lattice can be closely matched to the lattice constant of the silicon layer, reducing strain and defects, as well as contact resistance at the Si-SiGe interface, thereby improving the electrical and structural properties of the device. At locations farther from the interface, the Ge concentration can be controlled at a desired level to achieve the desired electrical and structural properties.

[0065] Therefore, in some embodiments, the concentration of Ge decreases vertically upwards above the SiGe semiconductor line 821. In some embodiments, the first Ge concentration at the first location is greater than the second Ge concentration at the second location, and the first location is vertically below the second location above the SiGe semiconductor line 821. In some embodiments, the concentration of Ge decreases vertically upwards from 20% to 5% above the SiGe semiconductor line 821. In some embodiments, the first Ge concentration at the first location is in the range of 25%-15%, and the second Ge concentration at the second location is in the range of 10%-2%, and the first location is vertically below the second location above the SiGe semiconductor line 821.

[0066] In some embodiments, the Ge concentration is lower near the upper and lower surfaces of the SiGe semiconductor line 821, while the Ge concentration is higher in the middle of the SiGe semiconductor line 821. Therefore, the Ge concentration initially increases and then decreases in the SiGe semiconductor line 821 from top to bottom. In some embodiments, the Ge concentration initially increases in the SiGe semiconductor line 821 from top to bottom and then remains at a certain level. In some embodiments, the Ge concentration increases continuously from top to bottom until it reaches the lower surface of the SiGe semiconductor line 821.

[0067] In some implementations, silicon and germanium are miscible across the entire composition range and can therefore be combined to form Si. 1-x Ge x An alloy in which the germanium content x is in the range of 0 to 1 (0-100%). Si 1-x Ge x It possesses a diamond-like lattice structure. When Si is grown on a silicon substrate... 1-x Ge x When layered, adapt to Si 1-x Ge x Lattice mismatch at the interface with silicon. This can be addressed by compressing Si. 1-x Ge x Layers are created to fit the silicon lattice or by generating mismatched dislocations at the interface. In the former case, Si 1-x Ge x The layers employ silicon lattice spacing in a growth plane, thus typically cubic Si 1-x Ge x The crystal undergoes deformation. When Si... 1- x Ge x When growth occurs in this manner, Si 1-x Ge x The layer is under compressive strain and is described as pseudocrystalline. In the second case, Si1-x Ge x The layers are unstrained or relaxed, and lattice mismatches at the interfaces are accommodated by the formation of misfit dislocations. These misfit dislocations are typically located in the plane of the interface, but dislocations can also penetrate perpendicularly through Si. 1-x Ge x layer.

[0068] In some embodiments, semiconductor line 821 may be doped with an N-type dopant (e.g., P or As) or a P-type dopant (e.g., B or Ga) at a desired doping level or doping distribution. For example, semiconductor line 821 may be a doped SiGe line. Doped semiconductor line 821 may be used as the source / drain region of a vertical transistor above it. In some embodiments, a SiGe layer formed by implanting Ge into a silicon layer (optionally followed by annealing) may be used instead of a SiGe epitaxial layer in semiconductor line 821.

[0069] In some embodiments, contact line 822 covers semiconductor line 821. Contact line 822 (or connection layer 822) may be an ohmic contact, such as a metal silicide contact, rather than a Schottky contact. For example, contact line 822 may include a metal silicide, such as NiSi, TiSi, WSi, CoSi, CuSi, AlSi, or any other suitable metal silicide having a higher conductivity than doped silicon. In some embodiments, metal line 823 may include W, Co, Cu, Al, or any other suitable metal having a higher conductivity than doped silicon. In some embodiments, contact line 822 may be omitted, and metal line 823 may be in direct contact with semiconductor line 821. In some embodiments, contact line 822 and metal line 823 are absent and not configured for memory device 800. Semiconductor line 821 serves as a bit line connecting the aforementioned vertical transistor. In some embodiments, an additional semiconductor is positioned below and in contact with semiconductor line 821. The two semiconductor lines together serve as a bit line.

[0070] The vertical transistor 816 may be a MOSFET for switching a corresponding memory cell. In some embodiments, the vertical transistor 816 includes a vertically (in the z-direction) extending semiconductor body 815 (in which an active region may form a channel) and two gate structures 810 contacting each opposite side of the semiconductor body 815 in the bit line direction (y-direction). The semiconductor body 815 may have a cuboid or cylindrical shape, and the gate structures 810 may be adjacent to one side of the semiconductor body 815 in a plan view, for example, as shown in the figure. Figure 8As shown. According to some embodiments, the gate structure 810 includes a gate electrode 814 and a gate dielectric 812 laterally located between the gate electrode 814 and the semiconductor body 815 in the bit line direction. In some embodiments, the gate dielectric 812 is adjacent to one side of the semiconductor body 815, and the gate electrode 814 is adjacent to the gate dielectric 812.

[0071] like Figure 8 As shown, in some embodiments, the semiconductor body 815 has two ends (upper end and lower end) in the vertical direction (z direction), and at least one end (e.g., Figure 8 The lower end of the semiconductor body 815 extends beyond the gate dielectric 812 in the vertical direction (z-direction). In some embodiments, one end of the semiconductor body 815 (e.g., Figure 8 The upper end of the gate dielectric 812 and the corresponding end of the gate dielectric 812 (e.g., Figure 8 The upper end of the semiconductor body 815 is flush with the gate electrode 814. In some embodiments, the two ends (upper and lower) of the semiconductor body 815 extend beyond the gate electrode 814 in the vertical direction (z-direction). That is, the semiconductor body 815 (e.g., in the z-direction) may have a larger vertical dimension (e.g., depth) than the vertical dimension of the gate electrode 814, and neither the upper nor lower end of the semiconductor body 815 is flush with the corresponding end of the gate electrode 814. Therefore, short circuits between the bit line 820 and the word line / gate electrode 814 or between the word line / gate electrode 814 and the memory device 803 can be avoided.

[0072] The vertical transistor 816 may also include a source and a drain (their positions may be interchanged) respectively disposed at two ends (upper and lower ends) of the semiconductor body 815 in the vertical direction (z-direction). In some embodiments, one of the source and drain (e.g., in...) Figure 8 At the upper end of the middle) it is coupled to the storage device 803, and the other of the source and drain (e.g., in Figure 8 At the lower end of the transistor 816, the line 820 is coupled to the vertical transistor 816. That is, the vertical transistor 816 can have a first terminal in the positive z-direction and a second terminal opposite to the first terminal in the negative z-direction, such as... Figure 8 As shown. In some embodiments, bit line 820 is coupled to the second terminal of vertical transistor 816.

[0073] In some embodiments, the semiconductor body 815 includes a semiconductor material, such as monocrystalline silicon, polycrystalline silicon, amorphous silicon, Ge, any other semiconductor material, or any combination thereof. In one example, the semiconductor body 815 may include monocrystalline silicon. The source and drain may be doped with an N-type dopant (e.g., P or As) or a P-type dopant (e.g., B or Ga) at a desired doping level or doping distribution. In some embodiments, a silicide layer (e.g., a metal silicide layer) is formed between the source / drain of the vertical transistor 816 and the bit line 820 (if implemented as a metal line) as a bit line contact, or is formed between the source / drain of the vertical transistor 816 and the first electrode of the memory device 803 to reduce contact resistance.

[0074] In some embodiments, the gate dielectric 812 comprises a dielectric material, such as silicon oxide, silicon nitride, or a high-k dielectric, including but not limited to Al₂O₃, HfO₂, Ta₂O₅, ZrO₂, TiO₂, or any combination thereof. In some embodiments, the gate electrode 814 comprises a conductive material, including but not limited to W, Co, Cu, Al, TiN, TaN, polysilicon, silicide, or any combination thereof. In some embodiments, the gate electrode 814 comprises multiple conductive layers, such as a W layer over a TiN layer. In one example, the gate structure 810 may be a “gate oxide / gate polysilicon” gate, wherein the gate dielectric 812 comprises silicon oxide and the gate electrode 814 comprises doped polysilicon. In another example, the gate structure 810 may be an HKMG, wherein the gate dielectric 812 comprises a high-k dielectric and the gate electrode 814 comprises a metal.

[0075] As described above, since the gate electrode 814 can be a portion of the word line or in the word line direction (e.g., Figure 8 In the x-direction, it extends as a letter line, such as Figure 8 As shown, the memory device 800 may further include multiple word lines (referred to as 814), each extending in a word line direction (x-direction). Each word line 814 may be coupled to a row of memory cells. That is, the bit line 820 and the word line 814 may extend in two perpendicular lateral directions, and the semiconductor body 815 of the vertical transistor 816 may extend in a direction perpendicular to the two lateral directions in which the bit line 820 and the word line 814 extend. According to some embodiments, the word line 814 is in contact with word line contacts (not shown). In some embodiments, the word line 814 comprises a conductive material, including but not limited to W, Co, Cu, Al, TiN, TaN, polysilicon, silicide, or any combination thereof. In some embodiments, the word line 814 comprises multiple conductive layers, such as a W layer over a TiN layer.

[0076] like Figure 8As shown, in some embodiments, memory device 803 includes a first electrode above the source or drain of vertical transistor 816 and coupled to the source or drain of vertical transistor 816 (e.g., the upper end of semiconductor body 815) via memory device contact 802. In some embodiments, memory device contact 802 is an ohmic contact, such as a metal silicide contact, rather than a Schottky contact. For example, memory device 803 may be a capacitor having a capacitor dielectric above and in contact with the first electrode, and a second electrode above and in contact with the capacitor dielectric. That is, memory device 803 may be a vertical capacitor in which the electrodes and capacitor dielectric are stacked vertically (in the z-direction), and the capacitor dielectric may be sandwiched between the electrodes. In some embodiments, each first electrode is coupled to the source or drain of a corresponding vertical transistor 816 in the same memory cell, while all second electrodes are coupled to a common plate coupled to ground (e.g., common ground). Memory device 803 may have a first end in the negative z-direction and a second end in the positive z-direction opposite to the first end, such as... Figure 8 As shown.

[0077] It should be understood that the structure and configuration of storage device 803 are not limited to Figure 8 Examples are provided, and any suitable structure and configuration may be included, such as planar capacitors, stacked capacitors, multi-fin capacitors, cylindrical capacitors, trench capacitors, or substrate-plate capacitors. In some embodiments, the capacitor dielectric includes a dielectric material, such as silicon oxide, silicon nitride, or a high-k dielectric, including but not limited to Al2O3, HfO2, Ta2O5, ZrO2, TiO2, or any combination thereof. It should be understood that in some examples, the storage device 803 may be a ferroelectric capacitor for use in an FRAM cell, and the capacitor dielectric may be replaced by a ferroelectric layer having a ferroelectric material (e.g., PZT or SBT). In some embodiments, the electrodes include conductive materials, including but not limited to W, Co, Cu, Al, TiN, TaN, polycrystalline silicon, silicides, or any combination thereof.

[0078] like Figure 8As shown, according to some embodiments, a vertical transistor 816 extends vertically through and contacts the word line 814. The source or drain of the vertical transistor 816 at its lower end contacts the bit line 820, and the source or drain of the vertical transistor 816 at its upper end is coupled to the memory cell 803. That is, due to the vertical arrangement of the vertical transistor 816, the bit line 820 and the memory cell 803 can be arranged in different planes in the vertical direction, and the vertical transistors 816 coupled to the memory cells are at opposite ends in the vertical direction. In some embodiments, the bit line 820 and the memory cell 803 are arranged on opposite sides of the vertical transistor 816 in the vertical direction. This simplifies the wiring of the bit line 820 and reduces the coupling capacitance between the bit line 820 and the memory cell 803 compared to a memory cell where the bit line and capacitor are arranged on the same side of a planar transistor.

[0079] III. Manufacturing process of memory devices employing etch stop layers

[0080] Figure 9A-1 / Figure 9A-2 / Figure 9B-1 / Figure 9B-2 / Figure 9C-1 / Figure 9C-2 and Figure 9D-9J The present disclosure illustrates a manufacturing process for forming a memory device (such as memory device 700 or 800) using several etch stop layers. The memory device may include an array of memory cells, each memory cell including a vertical transistor and a memory element coupled to the vertical transistor.

[0081] exist Figure 9A-1 and Figure 9A-2 In the process, multiple parallel trenches 904 are formed in the y-direction (e.g., bit line direction) to form a stack of semiconductor layers (films) (such as... Figure 6A In the stacked body 600, multiple parallel semiconductor walls 905 are formed in the y direction.

[0082] exist Figure 9A-1 and Figure 9A-2Prior to the processing steps, a stack 600 may be formed first. As shown, the stack 600 includes a semiconductor substrate 601, a first semiconductor layer 602, a second semiconductor layer 603, a third semiconductor layer 604, and a fourth semiconductor layer 605. For example, the process of forming the stack 600 may include epitaxially growing the first semiconductor layer 602 on the semiconductor substrate 601, epitaxially growing the second semiconductor layer 603 on the first semiconductor layer 602, epitaxially growing the third semiconductor layer 604 on the second semiconductor layer 603, and epitaxially growing the fourth semiconductor layer 605 on the third semiconductor layer 604. The semiconductor substrate 601 may include silicon (e.g., single-crystal silicon, c-Si), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), or any other suitable material.

[0083] In some embodiments, the first semiconductor layer 602 and / or the third semiconductor layer 604 comprises SiGe epitaxially grown on a lower layer (semiconductor substrate 601 or second semiconductor layer 603). Various growth techniques can be used to form the SiGe epitaxial layer, such as molecular beam epitaxy (MBE), low-pressure chemical vapor deposition (LPCVD), and ultra-high vacuum chemical vapor deposition (UHV-CVD). In some embodiments, the first semiconductor layer 602 and / or the third semiconductor layer 604 comprises SiGe formed by implanting Ge into a silicon layer. For example, Ge pre-amorphization implantation (PAI) utilizing Ge ions with certain energies can be performed to form SiGe. An annealing process can be performed after Ge implantation.

[0084] In some embodiments, the Ge concentration in the SiGe layer (first semiconductor layer 602 and / or third semiconductor layer 604) decreases upward on the upper side of the SiGe layer adjacent to the upper semiconductor layer 603 or 605. For example, the Ge concentration decreases upward from 20% to 5%.

[0085] In some embodiments, the Ge concentration is lower near the upper and lower surfaces of the SiGe layers 602 and / or 604, while the Ge concentration is higher in the middle of the SiGe layers 602 and / or 604. Therefore, the Ge concentration initially increases and then decreases in the SiGe layers 602 and / or 604 from top to bottom. In some embodiments, the Ge concentration initially increases and then remains at a certain level in the SiGe layers 602 and / or 604 from top to bottom. In some embodiments, the Ge concentration increases continuously from top to bottom until it reaches the lower surface of the SiGe layers 602 and / or 604.

[0086] In some embodiments, the first semiconductor layer 602 and / or the third semiconductor layer 604 are doped with an N-type dopant (e.g., P or As) or a P-type dopant (e.g., B or Ga) at a desired doping level or doping distribution. For example, the first semiconductor layer 602 and / or the third semiconductor layer 604 can be grown epitaxially using in-situ doping. For example, the first semiconductor layer 602 and / or the third semiconductor layer 604 can be doped by performing an implantation process and / or a thermal diffusion process.

[0087] In some embodiments, semiconductor layers 603 and / or 605 may comprise epitaxially grown silicon or other epitaxially grown semiconductor materials. Typically, high etch selectivity is desired between layers 602 and 603, between layers 605 and 604, and between layers 603 and 604.

[0088] To form trench 904, for example, in a bit-line based design, a photolithography process is performed to pattern trench 904 and semiconductor wall 905 using an etch mask (e.g., a photoresist mask and / or a hard mask). One or more dry and / or wet etch processes, such as reactive ion etching (RIE), are performed to etch trench 904 in stack 600. A first semiconductor layer 602 is used to ensure uniformity of the etch depth and bottom profile of trench 904. Semiconductor wall 905 extends vertically through a second etch stop layer 604 in stack 600 and is located on top of the first semiconductor layer 602. The upper surface of the first semiconductor layer 602 forms the bottom of trench 904.

[0089] Figure 9A-1 It shows the direction along the x-axis (the direction of the word line, for example, in...) Figure 9A-2 The side view of the cross section in the BB plane shown. Figure 9A-2 This is shown in the xy plane (e.g., in...). Figure 9A-1 The diagram shows a plan view of the cross-section (in plane AA) passing through semiconductor wall 905. Figure 9B-1 and Figure 9B-2 The same drawing layout was also used in the middle.

[0090] exist Figure 9B-1 and Figure 9B-2 In this embodiment, trench isolation 908 (e.g., STI) is formed in trench 904. In some embodiments, one or more thin-film deposition processes (including, but not limited to, CVD, PVD, ALD, or any combination thereof) are used to deposit a dielectric such as silicon oxide to completely fill trench 904. In some embodiments, a planarization process (such as CMP) is performed to remove excess dielectric deposited beyond the top surface of the stack 600. As a result, parallel semiconductor walls 905 can be separated by trench isolation 908.

[0091] exist Figure 9C-1 and Figure 9C-2 In the stack 600, a plurality of parallel trenches 910 are formed in the x-direction (e.g., word line direction) to form an array of semiconductor pillars 906 that extend vertically in the stack 600.

[0092] In some implementations, for example, based on word line design, a photolithography process is performed to pattern trench 910 perpendicular to trench isolation 908 using an etch mask (e.g., a photoresist mask and / or a hard mask). One or more dry and / or wet etch processes (such as RIE) are performed on semiconductor wall 905 and trench isolation 908 to etch trench 910 in stack 600. As a result, semiconductor wall 905 ( Figure 9B-1 and Figure 9B-2 (As shown) can be cut by trench 910 to form an array of semiconductor pillars 906, each extending vertically within the stack 600. A third semiconductor layer 604 is used to etch semiconductor walls 905 to ensure uniformity of the etch depth and bottom profile of the trench 910 between two adjacent semiconductor pillars 906. The array of semiconductor pillars 906 is located on the third semiconductor layer 604.

[0093] Figure 9C-1 This shows the direction along the y-axis (bit line direction, for example, in...) Figure 9C-2 A side view of the cross section in the CC plane shown. Figure 9C-2 This is shown in the xy plane (e.g., in...). Figure 9C-1 The plan view of the cross section (in the plane AA passing through semiconductor pillar 906) shown.

[0094] As shown in the plan view, the two opposite sides of the semiconductor pillar 906 in the y-direction are exposed by the trench 910, and the other two opposite sides of the semiconductor pillar 906 in the x-direction are in contact with the trench isolation 908. That is, the semiconductor pillar 906 is surrounded by the trench 910 and the trench isolation 908.

[0095] exist Figure 9D In this process, multiple vertical transistors 936 and corresponding memory devices 923 are formed. Figure 9D A side view of a cross-section along the bit line direction in the yz plane is shown.

[0096] A gate structure is formed that contacts the opposite side of the semiconductor pillar. In some embodiments, to form the gate structure, a gate dielectric is formed on the opposite side of the semiconductor pillar, and a gate electrode is formed on the gate dielectric. In some embodiments, to form the gate electrode, a conductive layer is deposited on the gate dielectric, and the conductive layer is etched back.

[0097] exist Figure 9DIn this embodiment, a gate dielectric 932 is formed over two opposite sides of a semiconductor pillar 906 (shown as semiconductor body 935) exposed from trench 910. In some embodiments, the gate dielectric 932 is formed by depositing a dielectric layer, such as silicon oxide, over the sidewalls of trench 910 but not completely filling trench 910 using one or more thin-film deposition processes (including, but not limited to, CVD, PVD, ALD, or any combination thereof). It should be understood that in some examples, the gate dielectric 932 may not be part of a continuous dielectric layer. For example, wet oxidation and / or dry oxidation processes (e.g., in-situ vapor generation (ISSG) oxidation) are performed to form a native oxide (e.g., silicon oxide) on the semiconductor pillar 906 (e.g., single-crystal silicon) as the gate dielectric 932.

[0098] A conductive layer 934 is formed over the gate dielectric 932 in the trench 910. In some embodiments, the conductive layer 934 is formed by depositing one or more conductive materials (such as metals and / or metal compounds (e.g., W and TiN)) over the gate dielectric 932 using one or more thin-film deposition processes (including, but not limited to, CVD, PVD, ALD, or any combination thereof) to partially fill the trench 910. For example, TiN and W layers may be deposited sequentially to form the conductive layer 934. A planarization process (e.g., CMP) may be performed to remove excess conductive material over the top surface of the stack 600.

[0099] In some embodiments, the conductive layer 934 is etched back using, for example, dry etching and / or wet etching (e.g., RIE) to form a recess, such that the upper end of the conductive layer 934 is below the top surface of the semiconductor pillar 906. In some embodiments, since there is no etch-back of the gate dielectric 932 (not shown), the upper end of the conductive layer 934 is also below the upper end of the gate dielectric 932, which is flush with the top surface of the semiconductor pillar 906. As a result, the etched-back conductive layer 934 can become respective word lines extending in the word line direction (x direction), and the portion of the etched-back conductive layer 934 facing the semiconductor pillar 906 can become the gate electrode. This allows the formation of gate structures, each including a corresponding gate dielectric 932 on the exposed side surface of the semiconductor pillar 906 and a corresponding gate electrode (a portion of the conductive layer 934) on the gate dielectric 932. In some embodiments, a dielectric layer is formed, for example, by depositing a dielectric (such as silicon oxide) using one or more thin-film deposition processes (including but not limited to CVD, PVD, ALD, or any combination thereof), in the remaining space of trench 910 and in the recesses (not shown) created by the back etching of conductive layer 934. It should be understood that air gaps may be formed in the dielectric layer depending on the word line spacing (the size of trench 910).

[0100] The upper portion of the semiconductor body 935, away from the substrate, is doped. The exposed upper portion of each semiconductor body 935 is doped to form a source / drain (e.g., the source terminal of a vertical transistor). In some embodiments, implantation and / or thermal diffusion processes are performed to dope P-type or N-type dopant onto the exposed upper portion of the semiconductor body 935 to form a source / drain. In some embodiments, a silicide layer is formed on the source / drain by performing a silicide process at the exposed upper portion of the semiconductor body 935.

[0101] A storage device is formed in contact with a semiconductor body (e.g., its doped first end). The storage device may include a capacitor or a PCM element. In some embodiments, to form a storage device as a capacitor, a first electrode is formed on the doped upper end of the semiconductor body, a capacitor dielectric is formed on the first electrode, and a second electrode is formed on the capacitor dielectric.

[0102] For example, one or more interlayer dielectric (ILD) layers are formed on the top surface of the stack 600 by depositing dielectrics using one or more thin-film deposition processes (including but not limited to CVD, PVD, ALD, or any combination thereof). Subsequently, memory device contacts (capacitor contacts) 922, a first electrode of memory device (capacitor) 923, a capacitor dielectric, a second electrode, and a common plate 924, which will be coupled to the semiconductor body 935, are formed in the ILD layer. In some embodiments, capacitor contacts 922 are formed on the corresponding source / drain electrodes (e.g., the doped upper ends of the corresponding semiconductor body 935) by patterning and etching electrode holes aligned with the corresponding source / drain electrodes using photolithography and etching processes and depositing conductive material to fill the electrode holes using thin-film deposition processes. In some embodiments, a common plate 924 is formed on the second electrode of the capacitor 923 by patterning and etching electrode trenches aligned with the capacitor 923 using photolithography and etching processes and depositing conductive material to fill the electrode trenches using thin-film deposition processes.

[0103] Figure 9E-9J It shows the use of in Figure 9A-1 / Figure 9A-2 / Figure 9B-1 / Figure 9B-2 / Figure 9C-1 / Figure 9C-2 and Figure 9D Following the manufacturing steps in the process, a back-side fabrication process is used to form bit lines from the back side of the semiconductor substrate 602. Figure 9E-9J Each of these figures shows a side view of a cross-section in the xz plane along the word line direction (x-direction). The cross-section cuts through a row of vertical semiconductor bodies 935 of corresponding vertical transistors 936 arranged in the x-direction. Figure 9A-1 / Figure 9A-2 / Figure 9B-1 / Figure 9B-2 / Figure 9C-1 / Figure 9C-2 and Figure 9D compared to, Figure 9E-9J The side view is flipped, and substrate 601 becomes the top layer in stack 600. Furthermore, Figure 9E-9J Only a partial cross-sectional view of the storage device is shown, and the storage components are not shown.

[0104] Figure 9E It shows the corresponding Figure 9D The diagram shows a partial cross-sectional view along cut line A-A', and for simplicity, only two semiconductor bodies 935 are shown. The remaining portion 623 of the third semiconductor layer 604 is on top of the respective semiconductor body 935. The remaining portion 624 of the second semiconductor layer 603 is on top of the respective remaining portion 623. Structures 623 and 624 extend in the bit line direction (y-direction). The semiconductor bodies 935 and the structures 623 and 624 on top of them are sandwiched between two adjacent trench isolations 908 extending in the bit line direction.

[0105] exist Figure 9F In this process, the semiconductor substrate 601 and the first semiconductor layer 602 are removed, for example, by performing a planarization process (e.g., CMP), an etching process, or any suitable process. This exposes the top surface of the trench isolation 908 and the remaining portion 624 of the second semiconductor layer 603.

[0106] exist Figure 9G In the process of removing the remaining portion 624 of the second semiconductor layer 603 during the recess process, the top surface of the remaining portion 623 of the third semiconductor layer 604 is exposed. As a result of the recess process, a bit line recess 930 is formed. The recess process can be a dry or wet etching process or any suitable process for removing the remaining portion 624. The remaining portion 623 of the third semiconductor layer 604 serves as an etch stop layer during the recess process. Therefore, the uniformity of the etch depth and bottom etch profile of the bit line recess 930 can be ensured.

[0107] The remaining portion 623 of the third semiconductor layer 604 can be used together with the subsequently formed metal lines to form bit lines, and is therefore referred to as semiconductor line 623 in the following description, in contrast to the subsequently formed metal lines. After forming the bit line recess 930, semiconductor line 623 can be doped with an N-type dopant (e.g., P or As) or a P-type dopant (e.g., B or Ga) at a desired doping level by performing an implantation process, a thermal diffusion process, a combination thereof, or any suitable process. In some embodiments, the third semiconductor layer 604 is doped when forming the Si-SiGe layer stack 600. Figure 9G The doping in the semiconductor line 623 can be used to further adjust the doping level. In some implementations, this can be skipped. Figure 9G The doping operation in.

[0108] Figure 9H-9J The process for forming a metal line on top of a semiconductor line 623 within a bit line recess 930 is shown.

[0109] exist Figure 9H In this process, a silicide layer 931, such as a metal silicide layer, is formed on the top surface of semiconductor line 623 by performing a silicide process. The silicide layer may include metal silicides such as NiSi, TiSi, WSi, CoSi, CuSi, AlSi, or any other suitable metal silicide having a higher conductivity than doped silicon. Figure 9I In this process, a metal layer 938 can be deposited on top of the silicide layer 931 to fill the bit line recess 930. The metal layer 938 may include W, Co, Cu, Al, or any other suitable metal having a higher conductivity than doped silicon. Figure 9J In this process, excess portions of the metal layer 938 extending beyond the top surface of the trench isolation 908 can be removed by performing a planarization process (e.g., CMP). The remaining portion of the metal layer 938 within the bit line recess 930 can be further recessed using a dry / wet etching process to form a metal line 933 on top of the silicide layer 931. In some embodiments, an insulating layer is further formed on top of the metal line 933 to surround the metal line 933.

[0110] In some embodiments, semiconductor line 623, silicide layer 931, and metal line 933 are formed together to form a bit line extending in the y direction. The bit line is located on top of semiconductor body 935 and sandwiched between two adjacent trench isolations 908.

[0111] IV. Flowchart of the manufacturing process using an etch stop layer

[0112] Figure 10 A flowchart of a manufacturing process 1000 for forming a 3D memory device including vertical transistors, according to some aspects of this disclosure, is shown. Manufacturing process 1000 may employ an etch stop layer as described herein. Manufacturing process 1000 begins at S1001 and proceeds to S1010.

[0113] At S1010, a stack of semiconductor layers can be formed on the substrate. The stack may include a first semiconductor layer, a second semiconductor layer on the first semiconductor layer, a third semiconductor layer on the second semiconductor layer, and a fourth semiconductor layer on the third semiconductor layer.

[0114] At S1012, the stack is etched through the fourth semiconductor layer, the third semiconductor layer, and the second semiconductor layer to form a first trench along a first direction and on the first semiconductor layer. The second semiconductor layer and the first semiconductor layer can have different etch rates during the etching process, such that the first semiconductor layer can be used as an etch stop layer during the etching process. High etch selectivity between the second semiconductor layer and the first semiconductor layer is desired.

[0115] At S1014, the first trench is filled with insulating material to form trench isolation. The remaining portions of the fourth semiconductor layer, the third semiconductor layer, and the second semiconductor layer are sandwiched between adjacent trench isolations.

[0116] At S1016, the remaining portion of the fourth semiconductor layer and the trench isolation are etched to form a second trench on the third semiconductor layer along a second direction perpendicular to the first direction. Furthermore, a semiconductor body for a vertical transistor is formed, extending upwards in the third direction and surrounded by the second trench and the trench isolation. The third direction is perpendicular to both the first and second directions. The vertical transistor is located on top of the remaining portion of the third semiconductor layer.

[0117] During the etching process in S1016, the fourth semiconductor layer and the third semiconductor layer can have different etching rates, allowing the third semiconductor layer to be used as an etch stop layer during the S1016 etching process. High etch selectivity between the fourth and third semiconductor layers is desired.

[0118] At S1018, a gate structure is formed that is coupled to at least one side of the semiconductor body along the second direction of a vertical transistor. The gate structure may each include a dielectric layer and a gate electrode.

[0119] At S1020, the substrate and the first semiconductor layer are removed to expose the remaining portion of the trench isolation and the second semiconductor layer.

[0120] At S1022, for example, by performing an etching process, the remaining portion of the second semiconductor layer is removed to expose the remaining portion of the third semiconductor layer at the bottom of the recess between adjacent trench isolations. During the etching process in S1022, the second and third semiconductor layers can have different etching rates, such that the third semiconductor layer can be used as an etch stop layer during the etching process in S1022. High etch selectivity between the second and third semiconductor layers is desirable.

[0121] At S1024, the remaining portion of the third semiconductor layer is doped to form the source-drain region of the vertical transistor.

[0122] At S1026, a first interconnect layer, such as a silicide layer, is formed on the surface of a third semiconductor layer at the bottom of a recess between adjacent trench isolations.

[0123] At S1028, a second layer, such as bit line metal, is formed on the first connecting layer within the recess between adjacent trench isolations. The process proceeds to S1099 and terminates at S1099.

[0124] While various aspects of this disclosure have been described in conjunction with specific embodiments presented as examples, substitutions, modifications, and variations are possible with respect to these examples. Therefore, the embodiments set forth herein are intended to be illustrative rather than restrictive. Changes may be made without departing from the scope of the claims set forth below.

Claims

1. A method for manufacturing a storage device, comprising: Forming a stack, the stack comprising: First semiconductor layer, A second semiconductor layer above the first semiconductor layer A third semiconductor layer above the second semiconductor layer, and A fourth semiconductor layer above the third semiconductor layer; The stack is etched through the fourth semiconductor layer, the third semiconductor layer and the second semiconductor layer to form a first trench along a first direction and on the first semiconductor layer; The first trench is filled with insulating material to form trench isolation, and the remaining portions of the fourth semiconductor layer, the third semiconductor layer and the second semiconductor layer are sandwiched between adjacent trench isolations; The remaining portion of the fourth semiconductor layer and the trench isolation are etched to form a second trench on the third semiconductor layer and along a second direction perpendicular to the first direction, and a semiconductor body of a vertical transistor extending upward in a third direction and surrounded by the second trench and the trench isolation, the third direction being perpendicular to the first and second directions, the vertical transistor being located on top of the remaining portion of the third semiconductor layer; and A gate structure is formed for the vertical transistor, the gate structure being along the second direction and coupled to at least one side of the semiconductor body.

2. The method according to claim 1, further comprising: Remove the first semiconductor layer to expose the second semiconductor layer; Remove the second semiconductor layer to expose the third semiconductor layer at the bottom of the recess between the adjacent trench isolations; as well as The third semiconductor layer is doped to form the source-drain region of the vertical transistor.

3. The method according to claim 2, further comprising: A silicide layer is formed on the surface of the third semiconductor layer at the bottom of the recess between the adjacent trench isolations; as well as A bit line metal layer is formed on the silicide layer within the recess between the adjacent trench isolations.

4. The method according to claim 1, wherein, Forming the stack includes: The first semiconductor layer, the second semiconductor layer above the first semiconductor layer, the third semiconductor layer above the second semiconductor layer, and the fourth semiconductor layer above the third semiconductor layer are epitaxially grown.

5. The method according to claim 1, wherein, Forming the stack includes: An epitaxial silicon-germanium (SiGe) layer is grown as the third semiconductor layer.

6. The method according to claim 1, wherein, Forming the stack includes: An epitaxial silicon-germanium (SiGe) layer is grown as the third semiconductor layer, such that the concentration of germanium (Ge) decreases upward on the upper side of the silicon-germanium (SiGe) layer adjacent to the fourth semiconductor layer.

7. The method according to claim 1, wherein, Forming the stack includes: An epitaxial silicon-germanium (SiGe) layer is grown as the third semiconductor layer, such that the concentration of germanium (Ge) decreases from 20% to 5% upwards on the upper side of the silicon-germanium (SiGe) layer adjacent to the fourth semiconductor layer.

8. The method according to claim 1, wherein, Forming the stack includes: The third semiconductor layer is grown epitaxially using in-situ doped silicon-germanium (SiGe) layer.

9. The method according to claim 1, wherein, Forming the stack includes: An epitaxial silicon-germanium (SiGe) layer is grown as the first semiconductor layer.

10. A storage device, comprising: An array of memory cells, each memory cell including a vertical transistor having a semiconductor body extending vertically in a first direction, each memory cell including a storage element coupled to a first end of the semiconductor body; as well as Bit lines extending in a second direction perpendicular to the first direction are connected to a second end of the semiconductor body of a row of vertical transistors. The bit lines include a semiconductor epitaxial layer extending in the second direction and connected at the top surface of the semiconductor epitaxial layer to the second end of the semiconductor body of the row of vertical transistors.

11. The storage device according to claim 10, wherein, The bit line also includes: A first interconnect layer extends in the second direction and covers the bottom surface of the semiconductor epitaxial layer, and A third connecting layer is located below and adjacent to the first connecting layer, and extends in the second direction.

12. The storage device according to claim 10, wherein, The bit line also includes: A silicide layer extending in the second direction and covering the bottom surface of the semiconductor epitaxial layer, and A metal layer, which is below and adjacent to the silicide layer and extends in the second direction.

13. The storage device according to claim 10, wherein, The semiconductor epitaxial layer is a silicon-germanium (SiGe) epitaxial layer.

14. The storage device according to claim 10, wherein, The concentration of germanium (Ge) decreases upward in the first direction on the upper side of the semiconductor epitaxial layer.

15. The storage device according to claim 10, wherein, The first concentration of germanium (Ge) at the first position is greater than the second concentration of germanium (Ge) at the second position, wherein the first position is located above the semiconductor epitaxial layer and below the second position along the first direction.

16. The storage device according to claim 10, wherein, The concentration of germanium (Ge) decreases from 20% to 5% upward in the first direction on the upper side of the semiconductor epitaxial layer.

17. The storage device according to claim 10, wherein, The first concentration of germanium (Ge) at the first position is in the range of 25%-15%, and the second concentration of germanium (Ge) at the second position is in the range of 10%-2%, wherein the first position is located on the upper side of the semiconductor epitaxial layer and below the second position in the first direction.

18. The storage device according to claim 10, wherein, The semiconductor epitaxial layer is doped with n-type or p-type dopants.

19. The storage device according to claim 10, further comprising: Multiple word lines, each word line extending upward in a third direction perpendicular to the first direction and the second direction, each word line being coupled to the gate structure of the corresponding vertical transistor.

20. A memory system, comprising: Memory controller; as well as Storage device, coupled to the memory controller, the storage device comprising: An array of memory cells, each memory cell including a vertical transistor having a semiconductor body extending vertically in a first direction, each memory cell including a storage element coupled to a first end of the semiconductor body; as well as Bit lines extending in a second direction perpendicular to the first direction are connected to a second end of the semiconductor body of a row of vertical transistors. The bit lines include a semiconductor epitaxial layer extending in the second direction and connected at the top surface of the semiconductor epitaxial layer to the second end of the semiconductor body of the row of vertical transistors.

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