Semiconductor device and method of manufacturing the same

Abstract

Three-dimensional (3D) semiconductor devices and methods of fabrication are provided. In some embodiments, the disclosed semiconductor devices include a plurality of vertical transistors, each vertical transistor including a semiconductor layer having a leakage value below a picoampere and including a vertical semiconductor portion and at least one lateral semiconductor portion, a gate dielectric layer including a vertical gate dielectric portion on the vertical semiconductor portion and extending in a vertical direction, and a gate electrode on the gate dielectric layer and separated from the semiconductor layer by the gate dielectric layer. The disclosed semiconductor devices also include a plurality of capacitors, each capacitor coupled with the semiconductor layer of a corresponding one of the plurality of vertical transistors.

Description

Technical Field

[0001] This disclosure relates generally to the field of semiconductor technology, and more specifically to semiconductor devices and methods of manufacturing thereof. Background Technology

[0002] Planar memory cells can be scaled to smaller sizes by improving process technology, circuit design, programming algorithms, and manufacturing processes. However, as the feature size of memory cells approaches its lower limit, planar processes and manufacturing technologies become challenging and costly. As a result, the storage density of planar memory cells is approaching its upper limit.

[0003] Three-dimensional (3D) memory architectures can address the density limitations of planar memory cells. A 3D memory architecture includes a memory array and peripheral circuitry to facilitate the operation of the memory array. Summary of the Invention

[0004] One aspect of this disclosure provides a semiconductor device comprising: a plurality of vertical transistors, each vertical transistor comprising: a semiconductor layer having a leakage value of less than picoampere and including a vertical semiconductor portion and at least one lateral semiconductor portion; a gate dielectric layer including a vertical gate dielectric portion extending in a vertical direction on the vertical semiconductor portion; a gate electrode on the gate dielectric layer and separated from the semiconductor layer by the gate dielectric layer; and a plurality of capacitors, each capacitor being coupled to the semiconductor layer of a corresponding vertical transistor among the plurality of vertical transistors.

[0005] In some implementations, the gate electrode extends vertically and is laterally surrounded by a vertical gate dielectric portion.

[0006] In some implementations, the vertical gate dielectric portion is laterally surrounded by the vertical semiconductor portion.

[0007] In some embodiments, the gate dielectric layer further includes a lateral gate dielectric portion that contacts a first end of the gate electrode.

[0008] In some embodiments, the first lateral semiconductor portion is located between the lateral gate dielectric portion and a corresponding capacitor.

[0009] In some embodiments, the semiconductor device further includes word lines, each word line extending along a first lateral direction and connected to a second end of the gate electrode.

[0010] In some embodiments, the semiconductor device further includes bit lines, each bit line extending along a second lateral direction and in direct contact with a vertical semiconductor portion.

[0011] In some implementations, the bit line completely surrounds the sidewall of the vertical semiconductor portion and contacts the second lateral semiconductor portion.

[0012] In some implementations, the bit line partially surrounds the sidewall of the vertical semiconductor portion and contacts the second lateral semiconductor portion.

[0013] In some embodiments, the semiconductor device further includes a conductive plug that is laterally surrounded by the vertical semiconductor portion and connected to a bit line extending along a second lateral direction.

[0014] In some implementations, the vertical semiconductor portion is laterally surrounded by the vertical gate dielectric portion.

[0015] In some implementations, word lines include gate electrodes that are connected to each other in a first lateral direction.

[0016] In some implementations, the word line at least partially surrounds the vertical gate dielectric portion of a row of vertical transistors.

[0017] In some implementations, the leakage value of the semiconductor layer is lower than the intrinsic leakage value of monocrystalline silicon.

[0018] In some implementations, the semiconductor layer is a metal oxide semiconductor layer.

[0019] Another aspect of this disclosure provides a semiconductor device comprising: a plurality of vertical transistors, each vertical transistor including: a gate electrode extending in a vertical direction; a gate dielectric layer laterally surrounding the gate electrode and covering a first end of the gate electrode; a semiconductor layer laterally surrounding the gate dielectric layer and covering the first end of the gate dielectric layer; a plurality of capacitors, each capacitor being coupled to the semiconductor layer of a corresponding vertical transistor; a plurality of word lines, each word line extending along a first lateral direction and coupled to the gate electrode; and a plurality of bit lines, each bit line extending along a second lateral direction and coupled to the semiconductor layer.

[0020] In some implementations, the bit lines at least partially surround the semiconductor layer of each vertical transistor in the lateral plane.

[0021] In some implementations, the leakage value of the semiconductor layer is lower than the intrinsic leakage value of monocrystalline silicon.

[0022] In some implementations, the semiconductor layer is a metal oxide semiconductor layer.

[0023] Another aspect of this disclosure provides a method for forming a semiconductor device, comprising: forming a plurality of capacitors; forming a dielectric layer on the plurality of capacitors; forming a conductive layer on the dielectric layer; forming a plurality of vias, each via penetrating the conductive layer and the dielectric layer to expose a corresponding capacitor among the plurality of capacitors; forming a semiconductor layer to cover the bottom and sidewalls of each via; forming a gate dielectric layer to cover the semiconductor layer; and forming a gate electrode on the gate dielectric layer in each via.

[0024] In some embodiments, the method further includes cutting the conductive layer to form a plurality of bit lines, each bit line extending along a second lateral direction, prior to forming the plurality of vias.

[0025] In some embodiments, the method further includes forming a plurality of word lines, each word line extending along a first lateral direction and coupled to the gate electrode. Attached Figure Description

[0026] The accompanying drawings, which are incorporated herein and form part of this specification, illustrate embodiments of the present disclosure, and together with the description, serve to explain the principles of the present disclosure and enable those skilled in the art to make and use the present disclosure.

[0027] Figure 1 A schematic circuit diagram of a memory device comprising an array of memory cells, each having a vertical transistor, according to some embodiments of the present disclosure is shown.

[0028] Figure 2A A schematic plan view is shown of an array of memory cells, each including a vertical transistor, in a memory device according to some embodiments of the present disclosure.

[0029] Figure 2B A schematic plan view is shown of an array of memory cells, each including a vertical transistor, in a memory device according to some embodiments of the present disclosure.

[0030] Figure 2C A schematic side view of a cross-section of a memory cell in a 3D memory device according to some embodiments of the present disclosure is shown.

[0031] Figure 2D A schematic side view of a cross-section of a memory cell in a 3D memory device according to some embodiments of the present disclosure is shown.

[0032] Figure 3A A schematic plan view is shown of an array of memory cells, each including a vertical transistor, in a memory device according to some embodiments of the present disclosure.

[0033] Figure 3B A schematic plan view is shown of an array of memory cells, each including a vertical transistor, in a memory device according to some embodiments of the present disclosure.

[0034] Figure 3C A schematic side view of a cross-section of a memory cell in a 3D memory device according to some embodiments of the present disclosure is shown.

[0035] Figure 3D A schematic side view of a cross-section of a memory cell in a 3D memory device according to some embodiments of the present disclosure is shown.

[0036] Figure 4 A block diagram of a system having a memory device according to some embodiments of the present disclosure is shown.

[0037] Figure 5 A flowchart illustrating a manufacturing method for forming a 3D memory device according to some embodiments of the present disclosure is shown.

[0038] Figures 6A-6E Various embodiments according to this disclosure are shown in [the document / ... Figure 5 A schematic side cross-sectional view of a 3D memory device at a certain manufacturing stage of the method shown.

[0039] Figure 7 A flowchart illustrating a manufacturing method for forming a 3D memory device according to some embodiments of the present disclosure is shown.

[0040] Figures 8A-8E Various embodiments according to this disclosure are shown in [the document / ... Figure 5 A schematic side cross-sectional view of a 3D memory device at a certain manufacturing stage of the method shown.

[0041] The contents of this disclosure will be described with reference to the accompanying drawings. Detailed Implementation

[0042] Although specific configurations and arrangements have been discussed, it should be understood that this is for illustrative purposes only. Therefore, other configurations and arrangements may be used without departing from the scope of this disclosure. Furthermore, this disclosure can be used in a variety of other applications. The functional and structural features described in this disclosure may be combined, adjusted, and modified with each other and in ways not specifically shown in the accompanying drawings, such combinations, adjustments, and modifications being within the scope of this disclosure.

[0043] Generally, terms can be understood at least partly from their usage in context. For example, depending at least partly on the context, the term "one or more" as used herein can be used to describe any feature, structure, or characteristic in a singular sense, or to describe a combination of features, structures, or characteristics in a plural sense. Similarly, depending at least partly on the context, terms such as "a," "an," or "the" can also be understood to express either a singular or a plural usage. Furthermore, the term "based on" can be understood not necessarily to express an exclusive set of factors, but rather to allow for the presence of other factors that are not necessarily explicitly described, which also depends at least partly on the context.

[0044] It should be readily understood that the meanings of “on,” “above,” and “on top of” in this disclosure should be interpreted in the broadest possible sense, such that “on” means not only “directly on” but also includes “on” with an intermediate feature or layer, and “above” or “on top of” means not only “above” or “on top of” but also includes “on” or “on top of” without an intermediate feature or layer (i.e., directly on).

[0045] Furthermore, for ease of description, spatially relative terms such as “below,” “under,” “down,” “above,” and “above” may be used herein to describe the relationship between one element or feature as shown in the figures and one or more other elements or features. In addition to the orientations shown in the figures, the spatially relative terms are intended to cover different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially related descriptive terms used herein may be interpreted accordingly.

[0046] As used herein, the term "substrate" refers to the material on which subsequent material layers are added. The substrate itself may be patterned. The material added on top of the substrate may be patterned or may remain unpatterned. Furthermore, the substrate may include a variety of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of a non-conductive material, such as glass, plastic, or sapphire wafer.

[0047] As used herein, the term "layer" refers to a portion of material comprising a region having thickness. A layer may extend over the entire lower or upper layer structure, or may have a range smaller than that of the lower or upper layer structure. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure having a thickness less than that of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure or between any pair of horizontal planes at the top and bottom surfaces. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer, which may include one or more layers, and / or may have one or more layers on, above, and / or below it. A layer may include multiple layers. For example, an interconnect layer may include one or more conductor and contact layers (where interconnect lines and / or vertical interconnect vias are formed) and one or more dielectric layers.

[0048] Transistors are used as switches or selection devices in memory cells of some memory devices, such as Dynamic Random Access Memory (DRAM). In a one-transistor-one-capacitor (1T1C) DRAM structure, data is stored in a capacitor. High demands are placed on the leakage of the selection transistor. Therefore, it is necessary to identify alternative channel materials with lower leakage compared to using monocrystalline silicon as the channel material. Furthermore, as DRAM continues to scale, the unit size of the 1T1C cell continues to decrease, thus increasing the impact of leakage issues in the selection transistor. In addition, the increased etching aspect ratio of the capacitor leads to significant challenges in the manufacturing process and increased product costs.

[0049] To address one or more of the aforementioned problems, this disclosure describes a solution in which vertical transistors are included in an array of memory cells in a memory device (e.g., DRAM). In the disclosed memory device, a low-leakage material, such as a metal-oxide-semiconductor (MODS) material, is selected as the channel for the select transistor to address leakage issues during DRAM scaling. The disclosed memory device includes two device architectures: a channel-all-around (CAA) type vertical channel transistor and a gate-all-around (GAA) type vertical channel transistor. Corresponding fabrication processes for the two device architectures are described, wherein the vertical channel transistor can be formed on the front or back side of a capacitor. By using a novel channel material for the select transistor in the DRAM, the disclosed memory device can achieve high storage density and further reduced cell size. The disclosed fabrication process can have a simplified source node (SN) contact process, thereby reducing product costs.

[0050] Consistent with the scope of this disclosure, according to some embodiments of this disclosure, a memory cell array has vertical transistors, each vertical transistor including a semiconductor layer extending in a vertical direction and a gate structure adjacent to or surrounded by the semiconductor layer. In some embodiments, word lines and bit lines connected to the vertical transistors are arranged along a first lateral direction and a second lateral direction, respectively. Each semiconductor body of the vertical transistor array extends in a vertical direction. By using such an arrangement, memory area efficiency can be improved. Furthermore, the memory cell array and peripheral circuitry can be formed on different wafers separately, so that the fabrication processes of the memory cell array and peripheral circuitry do not interfere with each other, and memory area efficiency can be further improved.

[0051] Figure 1 A schematic diagram of a memory device 100 having an array of memory cells, each having a vertical transistor, according to some embodiments of the present disclosure is shown. The memory device 100 may include an array of memory cells, wherein each memory cell 110 includes a vertical transistor 120 and memory cells coupled to the vertical transistor 120. In such a way... Figure 1 In some embodiments shown, the memory cell array is a DRAM cell array, and the storage cell is a capacitor 130 for storing charge as binary information stored by the respective DRAM cell. In some other embodiments not shown in the figures, the memory cell array is a PCM cell array, and the storage cell may be a PCM element (e.g., including a chalcogenide alloy) for storing the binary information of the respective PCM cell based on the different resistivities of the PCM elements in the amorphous and crystalline phases.

[0052] like Figure 1 As shown, memory cells 110 can be arranged as a two-dimensional (2D) array with rows and columns. Memory device 100 may include word lines 150 and bit lines 160. The word lines 150 couple the memory cell array to peripheral circuitry for controlling the switching of vertical transistors 120 in the memory cells 110 located in a row, and the bit lines 160 couple the memory cell array to peripheral circuitry for sending data to and / or receiving data from the memory cells 110 located in a column. That is, each word line 150 is coupled to a corresponding row of memory cells 110, and each bit line 160 is coupled to one or more corresponding logical columns of memory cells 110. In some embodiments, the gate of a vertical transistor 120 is coupled to word line 150, one of the source and drain of vertical transistor 120 is coupled to bit line 160, the other of the source and drain of vertical transistor 120 is coupled to one electrode of capacitor 130, and the other electrode of capacitor 130 is coupled to ground.

[0053] Consistent with the scope of this disclosure, a vertical transistor 120 (such as a vertical metal-oxide-semiconductor field-effect transistor (MOSFET)) can replace a conventional planar transistor as a transfer transistor for memory cell 110 to reduce the area occupied by the transfer transistor, coupling capacitance, and interconnect wiring complexity, as described in detail below.

[0054] Figure 2A and Figure 2B Each of the above presents a schematic plan view of an array of memory cells comprising full-ring channel (CAA) type vertical transistors in a 3D memory device according to some embodiments of the present disclosure. Figure 2C and Figure 2D Each of the embodiments according to this disclosure is shown separately. Figure 2A and Figure 2B A schematic cross-sectional side view of a memory cell in a 3D memory device. It should be noted that... Figure 2C A cross-sectional side view of a memory cell 200C of a memory cell array 200A along a bit line 260 in the yz plane is shown, while Figure 2D A cross-sectional side view of a memory cell 200D of a memory cell array 200B along a word line 250 in the xz plane is shown.

[0055] like Figure 2A As shown, the disclosed memory device may include a memory cell array 200A, which includes multiple word lines 25 extending in a first lateral direction (x-direction, referred to as the word line direction) and multiple bit lines 260 extending in a second lateral direction (y-direction, referred to as the bit line direction) perpendicular to the first lateral direction. Each bit line 260 laterally surrounds a corresponding column of vertical transistors 210 along the second lateral direction (i.e., the y-direction). It should be understood that... Figure 2A A cross-sectional view of the memory device in the same transverse plane is not shown, and word lines 250 and bit lines 260 may be formed in different transverse planes to facilitate wiring, as described in detail below.

[0056] like Figure 2CAs shown, in some embodiments, each memory cell 200C of the memory cell array 200A includes a memory cell 280 and a CAA-type vertical transistor 210 having a semiconductor layer 220 and a gate electrode 230 surrounded by the semiconductor layer 200. The vertical transistor 210 may include a semiconductor layer 220 having a leakage value below picoamperes. In some embodiments, the leakage value of the semiconductor layer 220 is lower than the intrinsic leakage value of single-crystal silicon. In some embodiments, the material of the semiconductor layer 220 may be a metal oxide semiconductor material, such as indium gallium zinc oxide (IGZO). In the CAA-type vertical channel transistor 210, the semiconductor layer 220 may include a first lateral semiconductor portion 222 serving as a source, a vertical semiconductor portion 224 serving as a channel, and a second lateral semiconductor portion 226 serving as a drain.

[0057] The vertical semiconductor portion 224 may extend in a direction perpendicular to both the first and second lateral directions (i.e., the z-direction). The first lateral semiconductor portion 222 may extend in a lateral plane (i.e., the xy-plane) and contact the memory cell 280. It should be understood that the first lateral semiconductor portion 222 may have any suitable shape, such as a square, rectangular (or trapezoidal), circular, partially circular, elliptical, partially elliptical, or any other suitable shape. The bit line 260 laterally surrounds the lower sidewall of the vertical semiconductor portion 224 and contacts the second lateral semiconductor portion 226.

[0058] The vertical transistor 210 also includes a gate electrode 230 extending along the vertical direction (i.e., the z-direction) and laterally surrounded by the vertical semiconductor portion 224. The gate electrode 230 may comprise any suitable conductive material, such as polysilicon, metals (e.g., tungsten (W), copper (Cu), aluminum (Al), etc.), metal compounds (e.g., titanium nitride (TiN), tantalum nitride (TaN), etc.), or silicides. For example, the gate electrode 230 may comprise doped polysilicon, i.e., gate polysilicon. In some embodiments, the gate electrode 230 comprises multiple conductive layers, such as a W layer over a TiN layer.

[0059] In some embodiments, the gate dielectric layer 235 is located between the semiconductor layer 220 and the gate electrode 230. The word line 250 may contact the gate electrode 230 of a row of vertical transistors 210 along a first lateral direction (i.e., the x-direction). The gate dielectric layer 235 may comprise any suitable dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or a high-k dielectric. For example, the gate dielectric layer 235 may comprise silicon oxide, i.e., a gate oxide.

[0060] In some embodiments, memory cell 280 may include any means for storing binary data (e.g., 0s and 1s), including but not limited to capacitors for DRAM cells and PCM elements for PCM cells. In some embodiments, each vertical transistor 210 controls the selection and / or state switching of a corresponding memory cell 280 coupled to the vertical transistor 210. In some embodiments, memory cell 280 includes capacitor 290. It should be understood that capacitor 290 may include any suitable structure and configuration, such as planar capacitors, stacked capacitors, multi-fin capacitors, cylindrical capacitors, trench capacitors, or substrate capacitors.

[0061] like Figure 2C As shown, capacitor 290 includes a first electrode 291 coupled to the source / drain of vertical transistor 210. The capacitor may also include a second electrode 293 separated from vertical transistor 210 and a capacitor dielectric 295 between the first electrode 291 and the second electrode 293. As shown, capacitor 290 may be a vertical capacitor in which the two electrodes 291, 293 and the capacitor dielectric 295 between them are stacked vertically (in the z-direction). In some embodiments, each first electrode 291 may be coupled to the source of a corresponding vertical transistor 210 in the same DRAM cell (i.e., the first lateral semiconductor portion 222 of semiconductor layer 220), while all second electrodes 293 may be portions of a common plate coupled to ground (e.g., common ground). In some embodiments, capacitor dielectric 295 includes a dielectric material such as silicon oxide, silicon nitride, or a high-k dielectric, including but not limited to Al2O3, HfO2, Ta2O5, ZrO2, TiO2, or any combination thereof. In some embodiments, the two electrodes 291, 293 may include conductive materials, including but not limited to W, Co, Cu, Al, TiN, TaN, polycrystalline silicon, silicides, or any combination thereof.

[0062] like Figure 2B As shown, the disclosed memory device may include a memory cell array 200B, which includes multiple word lines 250 extending in a first lateral direction (x-direction, referred to as the word line direction) and multiple bit lines 265 extending in a second lateral direction (y-direction, referred to as the bit line direction) perpendicular to the first lateral direction. Each bit line 265 is located on one side of a corresponding column of vertical transistors 210 along the second lateral direction. It should be understood that... Figure 2B A cross-sectional view of the memory device in the same transverse plane is not shown, and word line 250 and bit line 265 may be formed in different transverse planes to facilitate wiring, as described in detail below.

[0063] like Figure 2DAs shown, in some embodiments, each memory cell 200D of the memory cell array 200B includes a memory cell 280 and a CAA-type vertical transistor 210 having a semiconductor layer 220 and a gate electrode 230 surrounded by the semiconductor layer 220. The vertical transistor 210 may include a semiconductor layer 220 having a leakage value below picoamperes. In some embodiments, the leakage value of the semiconductor layer 220 is lower than the intrinsic leakage value of single-crystal silicon. In some embodiments, the material of the semiconductor layer 220 may be a metal oxide semiconductor material, such as IGZO. In the CAA-type vertical channel transistor 210, the semiconductor layer 220 may include a first lateral semiconductor portion 222 serving as a source, a vertical semiconductor portion 224 serving as a channel, and a second lateral semiconductor portion 226 serving as a drain.

[0064] The vertical semiconductor portion 224 may extend in a direction perpendicular to both the first and second lateral directions (i.e., the z-direction). The first lateral semiconductor portion 222 may extend in a lateral plane (i.e., the xy-plane) and contact the memory cell 280. It should be understood that the first lateral semiconductor portion 222 may have any suitable shape, such as a square, rectangular (or trapezoidal), circular, partially circular, elliptical, partially elliptical, or any other suitable shape. The bit line 265 partially surrounds the lower sidewall of the vertical semiconductor portion 224 and contacts a portion of the second lateral semiconductor portion 226.

[0065] The vertical transistor 210 also includes a gate electrode 230 extending along the vertical direction (i.e., the z-direction) and laterally surrounded by the vertical semiconductor portion 224. The gate electrode 230 may comprise any suitable conductive material, such as polysilicon, a metal (e.g., W, Cu, Al, etc.), a metal compound (e.g., TiN, TaN, etc.), or a silicide. For example, the gate electrode 230 may comprise doped polysilicon, i.e., gate polysilicon. In some embodiments, the gate electrode 230 comprises multiple conductive layers, such as a W layer over a TiN layer.

[0066] In some embodiments, the gate dielectric layer 235 is located between the semiconductor layer 220 and the gate electrode 230. The word line 250 may contact the gate electrode 230 of a row of vertical transistors 210 along a first lateral direction (i.e., the x-direction). The gate dielectric layer 235 may comprise any suitable dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or a high-k dielectric. For example, the gate dielectric layer 235 may comprise silicon oxide, i.e., a gate oxide.

[0067] In some embodiments, memory cell 280 may include any means for storing binary data (e.g., 0s and 1s), including but not limited to capacitors for DRAM cells and PCM elements for PCM cells. In some embodiments, each vertical transistor 210 controls the selection and / or state switching of a corresponding memory cell 280 coupled to the vertical transistor 210. In some embodiments, memory cell 280 includes capacitor 290. It should be understood that capacitor 290 may include any suitable structure and configuration, such as planar capacitors, stacked capacitors, multi-fin capacitors, cylindrical capacitors, trench capacitors, or substrate capacitors.

[0068] like Figure 2D As shown, capacitor 290 includes a first electrode 291 coupled to the source / drain of vertical transistor 210. The capacitor may also include a second electrode 293 separated from vertical transistor 210 and a capacitor dielectric 295 between the first electrode 291 and the second electrode 293. As shown, capacitor 290 may be a vertical capacitor in which two electrodes 291, 293 and the capacitor dielectric 295 between them are stacked vertically (in the z-direction). In some embodiments, each first electrode 291 may be coupled to the source of a corresponding vertical transistor 210 in the same DRAM cell (i.e., the first lateral semiconductor portion 222 of semiconductor layer 220), while all second electrodes 293 may be portions of a common plate coupled to ground (e.g., common ground). In some embodiments, capacitor dielectric 295 includes a dielectric material such as silicon oxide, silicon nitride, or a high-k dielectric, including but not limited to Al2O3, HfO2, Ta2O5, ZrO2, TiO2, or any combination thereof. In some embodiments, the two electrodes 291, 293 may include conductive materials, including but not limited to W, Co, Cu, Al, TiN, TaN, polycrystalline silicon, silicides, or any combination thereof.

[0069] In some embodiments, one or more peripheral circuits (not shown) may be coupled to the memory cell array 200A / 200B via bit lines 260 / 265, word lines 250, and any other suitable metal wiring. It should be noted that the one or more peripheral circuits may include any suitable circuitry for facilitating the operation of the memory cell array 200A / 200B by applying and sensing voltage and / or current signals to and from each vertical transistor 210 via word lines 250 and bit lines 260 / 265. The one or more peripheral circuits may include various types of peripheral circuitry formed using CMOS technology.

[0070] Figure 3AA schematic plan view of an array of memory cells in a 3D memory device according to some embodiments of the present disclosure is shown, each memory cell including a gate-all-around (GAA) type vertical transistor. Figure 3C Some embodiments according to this disclosure are shown. Figure 3A A schematic cross-sectional side view of a memory cell in a 3D memory device shown. Figure 3B A schematic plan view of an array of memory cells in a 3D memory device according to some embodiments of the present disclosure is shown, each memory cell including a partially gate-around-the-aperture (GPA) type vertical transistor. Figure 3D Some embodiments according to this disclosure are shown. Figure 3B A schematic cross-sectional side view of a memory cell in a 3D memory device. It should be noted that... Figure 3C and Figure 3D Each of the memory cells 300C / 300D of the memory cell arrays 300A / 300B is shown as a cross-sectional side view along a bit line 360 ​​in the yz plane.

[0071] like Figure 3A As shown, the disclosed memory device may include a memory array 300A, which includes multiple word lines 350 extending in a first lateral direction (x-direction, referred to as the word line direction) and multiple bit lines 360 extending in a second lateral direction (y-direction, referred to as the bit line direction) perpendicular to the first lateral direction. Each word line 350 laterally surrounds a corresponding row of vertical transistors 310 along the first lateral direction (i.e., the x-direction). It should be understood that... Figure 3A A cross-sectional view of the memory device in the same transverse plane is not shown, and word lines 350 and bit lines 360 may be formed in different transverse planes to facilitate wiring, as described in detail below.

[0072] like Figure 3C As shown, in some embodiments, each memory cell 300C of the memory array 300A includes a memory cell 380 and a GAA-type vertical transistor 310 having a semiconductor layer 320 and a gate structure laterally surrounding the semiconductor layer 320. The vertical transistor 310 may include a semiconductor layer 320 having a leakage value below picoamperes. In some embodiments, the leakage value of the semiconductor layer 320 is lower than the intrinsic leakage value of single-crystal silicon. In some embodiments, the material of the semiconductor layer 320 may be a metal-oxide-semiconductor material, such as IGZO. In the GAA-type vertical channel transistor 310, the semiconductor layer 320 may include a first lateral semiconductor portion 322 serving as a source, a vertical semiconductor portion 324 serving as a channel, and a second lateral semiconductor portion 326 serving as a drain.

[0073] The vertical semiconductor portion 324 may extend in a direction perpendicular to both the first and second lateral directions (i.e., the z-direction). The first lateral semiconductor portion 322 may extend in a lateral plane (i.e., the xy-plane) and contact the memory cell 380. It should be understood that the first lateral semiconductor portion 322 may have any suitable shape, such as a square, rectangular (or trapezoidal), circular, partially circular, elliptical, partially elliptical, or any other suitable shape.

[0074] The GAA vertical transistor 310 also includes a gate electrode 352 laterally surrounding the middle portion of the vertical semiconductor portion 324 of the semiconductor layer 320. The gate electrode 352 may comprise any suitable conductive material, such as polysilicon, a metal (e.g., W, Cu, Al, etc.), a metal compound (e.g., TiN, TaN, etc.), or a silicide. For example, the gate electrode 352 may comprise doped polysilicon, i.e., gate polysilicon. In some embodiments, the gate electrode 352 comprises multiple conductive layers, such as a W layer over a TiN layer. Figure 3A As shown, the gate electrodes 352 of adjacent vertical transistors 310 along the first lateral direction (i.e., the x-direction) are continuous, for example, a portion of a continuous conductive layer having gate electrodes 352. That is, multiple gate electrodes 352 of a row of vertical transistors 310 can be connected to each other and extend along the first lateral direction to form word lines 350 of that row of vertical transistors 310. In some embodiments, a gate dielectric layer 370 is located between the semiconductor layer 320 and the gate electrodes 352. The gate dielectric layer 370 can include any suitable dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or a high-k dielectric. For example, the gate dielectric layer 370 can include silicon oxide, i.e., a gate oxide.

[0075] like Figure 3C As shown, bit line contact 365 contacts and is surrounded by the lower portion of the vertical semiconductor portion 324. Bit line contact 365 can be a heavily doped semiconductor material having any suitable P-type dopant (such as boron (B) or gallium (Ga)) or any suitable N-type dopant (such as phosphorus (P) or arsenic (As)). Figure 3A and Figure 3C In some embodiments shown, each bit line 360 ​​may extend along a second lateral direction (i.e., the y-direction) and contact a bit line contact 365 of a column of vertical transistors 310 along the second lateral direction (i.e., the y-direction). In some embodiments, the bit line 360 ​​may include a silicide line (not shown) and a metal line (not shown), the silicide line comprising any suitable metal silicide material and the metal line comprising any suitable metal material, such as W, Cu, Al, etc.

[0076] In some embodiments, memory cell 380 may include any means for storing binary data (e.g., 0s and 1s), including but not limited to capacitors for DRAM cells and PCM elements for PCM cells. In some embodiments, each vertical transistor 310 controls the selection and / or state switching of a corresponding memory cell 380 coupled to the vertical transistor 310. In some embodiments, memory cell 380 includes capacitor 390. It should be understood that capacitor 390 may include any suitable structure and configuration, such as planar capacitor, stacked capacitor, multi-fin capacitor, cylindrical capacitor, trench capacitor, or substrate capacitor.

[0077] like Figure 3C As shown, capacitor 390 includes a first electrode 391 coupled to the source / drain of vertical transistor 310. The capacitor may also include a second electrode 393 separated from vertical transistor 310 and a capacitor dielectric 395 between the first electrode 391 and the second electrode 393. As shown, capacitor 390 may be a vertical capacitor in which the two electrodes 391, 393 and the capacitor dielectric 395 between them are stacked vertically (in the z-direction). In some embodiments, each first electrode 391 may be coupled to the source of a corresponding vertical transistor 310 in the same DRAM cell (i.e., the first lateral semiconductor portion 322 of semiconductor layer 320), while all second electrodes 393 may be portions of a common plate coupled to ground (e.g., common ground). In some embodiments, capacitor dielectric 395 includes a dielectric material such as silicon oxide, silicon nitride, or a high-k dielectric, including but not limited to Al2O3, HfO2, Ta2O5, ZrO2, TiO2, or any combination thereof. In some embodiments, the two electrodes 291, 293 may include conductive materials, including but not limited to W, Co, Cu, Al, TiN, TaN, polycrystalline silicon, silicides, or any combination thereof.

[0078] Note that the disclosed memory devices may include, for example: Figure 3B and Figure 3D The single-gate transistor 315 is shown. That is, the word line 335 or gate electrode 354 can be in contact with one side of the semiconductor layer 320. In some other embodiments not shown, the disclosed memory device may include multi-gate vertical transistors, such as dual-gate vertical transistors (i.e., dual-side gate vertical transistors), tri-gate vertical transistors (i.e., tri-side gate vertical transistors), etc.

[0079] like Figure 3BAs shown, the disclosed memory device may include a memory array 300B, which includes multiple word lines 355 extending in a first lateral direction (x-direction, referred to as the word line direction) and multiple bit lines 360 extending in a second lateral direction (y-direction, referred to as the bit line direction) perpendicular to the first lateral direction. Each word line 355 is located on one side of a corresponding row of vertical transistors 315 along the first lateral direction (i.e., the x-direction). It should be understood that... Figure 3B A cross-sectional view of the memory device in the same transverse plane is not shown, and word line 355 and bit line 360 ​​may be formed in different transverse planes to facilitate wiring, as described in detail below.

[0080] like Figure 3D As shown, in some embodiments, each memory cell 300D of the memory array 300B includes a memory cell 380 and a single-gate vertical transistor 315 having a semiconductor layer 320 and a gate electrode 354 partially surrounding the semiconductor layer 320. The vertical transistor 315 may include the semiconductor layer 320 having a leakage value below picoamperes. In some embodiments, the leakage value of the semiconductor layer 320 is lower than the intrinsic leakage value of monocrystalline silicon. In some embodiments, the material of the semiconductor layer 320 may be a metal-oxide-semiconductor material, such as IGZO. In the vertical-channel transistor 315, the semiconductor layer 320 may include a first lateral semiconductor portion 322 serving as a source, a vertical semiconductor portion 324 serving as a channel, and a second lateral semiconductor portion 326 serving as a drain.

[0081] The vertical semiconductor portion 324 may extend in a direction perpendicular to both the first and second lateral directions (i.e., the z-direction). The first lateral semiconductor portion 322 may extend in a lateral plane (i.e., the xy-plane) and contact the memory cell 380. It should be understood that the first lateral semiconductor portion 322 may have any suitable shape, such as a square, rectangular (or trapezoidal), circular, partially circular, elliptical, partially elliptical, or any other suitable shape.

[0082] The single-gate vertical transistor 315 also includes a gate electrode 354 located on one side of the middle portion of the vertical semiconductor portion 324 of the semiconductor layer 320. The gate electrode 354 may comprise any suitable conductive material, such as polysilicon, a metal (e.g., W, Cu, Al, etc.), a metal compound (e.g., TiN, TaN, etc.), or a silicide. For example, the gate electrode 354 may comprise doped polysilicon, i.e., gate polysilicon. In some embodiments, the gate electrode 354 comprises multiple conductive layers, such as a W layer over a TiN layer. Figure 3BAs shown, the gate electrodes 354 of adjacent vertical transistors 315 along the first lateral direction (i.e., the x-direction) are continuous, for example, a portion of a continuous conductive layer having gate electrodes 354. That is, multiple gate electrodes 354 of a row of vertical transistors 315 can be connected to each other and extend along the first lateral direction to form word lines 355 of that row of vertical transistors 315. In some embodiments, a gate dielectric layer 370 is located between the semiconductor layer 320 and the gate electrodes 354. The gate dielectric layer 370 can include any suitable dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or a high-k dielectric. For example, the gate dielectric layer 370 can include silicon oxide, i.e., a gate oxide.

[0083] like Figure 3D As shown, bit line contact 365 contacts and is surrounded by the lower portion of the vertical semiconductor portion 324. Bit line contact 365 can be a heavily doped semiconductor material having any suitable P-type dopant (such as boron (B) or gallium (Ga)) or any suitable N-type dopant (such as phosphorus (P) or arsenic (As)). Figure 3B and Figure 3D In some embodiments shown, each bit line 360 ​​may extend along a second lateral direction (i.e., the y-direction) and contact a bit line contact 365 of a column of vertical transistors 315 along the second lateral direction (i.e., the y-direction). In some embodiments, the bit line 360 ​​may include a silicide line (not shown) and a metal line (not shown), the silicide line comprising any suitable metal silicide material and the metal line comprising any suitable metal material, such as W, Cu, Al, etc.

[0084] In some embodiments, memory cell 380 may include any means for storing binary data (e.g., 0s and 1s), including but not limited to capacitors for DRAM cells and PCM elements for PCM cells. In some embodiments, each vertical transistor 315 controls the selection and / or state switching of the corresponding memory cell 380 coupled to the vertical transistor 315. In some embodiments, memory cell 380 includes capacitor 390. It should be understood that capacitor 390 may include any suitable structure and configuration, such as planar capacitor, stacked capacitor, multi-fin capacitor, cylindrical capacitor, trench capacitor, or substrate capacitor.

[0085] like Figure 3DAs shown, capacitor 390 includes a first electrode 391 coupled to the source / drain of vertical transistor 315. The capacitor may also include a second electrode 393 separated from vertical transistor 315 and a capacitor dielectric 395 between the first electrode 391 and the second electrode 393. As shown, capacitor 390 may be a vertical capacitor in which the two electrodes 391, 393 and the capacitor dielectric 395 between them are stacked vertically (in the z-direction). In some embodiments, each first electrode 391 may be coupled to the source of a corresponding vertical transistor 315 in the same DRAM cell (i.e., the first lateral semiconductor portion 322 of semiconductor layer 320), while all second electrodes 393 may be portions of a common plate coupled to ground (e.g., common ground). In some embodiments, capacitor dielectric 395 includes a dielectric material such as silicon oxide, silicon nitride, or a high-k dielectric, including but not limited to Al2O3, HfO2, Ta2O5, ZrO2, TiO2, or any combination thereof. In some embodiments, the two electrodes 291, 293 may include conductive materials, including but not limited to W, Co, Cu, Al, TiN, TaN, polycrystalline silicon, silicides, or any combination thereof.

[0086] In some embodiments, one or more peripheral circuits (not shown) may be coupled to the memory cell array 300A / 300B via bit line 360, word line 350 / 355, and any other suitable metal wiring. It should be noted that the one or more peripheral circuits may include any suitable circuitry for facilitating the operation of the memory cell array 300A / 300B by applying and sensing voltage and / or current signals to and from each memory cell 310 / 315 via word line 350 / 355 and bit line 360. The one or more peripheral circuits may include various types of peripheral circuitry formed using CMOS technology.

[0087] Figure 4 A block diagram of a system 400 having a memory device according to some embodiments of this disclosure is shown. System 400 may be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having storage therein. Figure 5As shown, system 400 may include a host 408 and a memory system 402 having one or more memory devices 404 and a memory controller 406. Host 408 may be a processor of an electronic device, such as a central processing unit (CPU), or a system-on-a-chip (SoC), such as an application processor (AP). Host 408 may be configured to send or receive data to or from memory device 404. Memory device 404 may be any memory device disclosed herein, such as memory device 100. In some embodiments, memory device 404 includes an array of memory cells as shown in 200A / 200B / 300A / 300B, each memory cell including a vertical transistor, as described in detail above.

[0088] According to some embodiments, a memory controller 406 is coupled to a memory device 404 and a host 408 and is configured to control the memory device 404. The memory controller 406 manages data stored in the memory device 404 and communicates with the host 408. The memory controller 406 can be configured to control operations of the memory device 404, such as read, write, and refresh operations. The memory controller 406 can also be configured to manage various functions regarding data stored or to be stored in the memory device 404, including but not limited to refresh and timing control, command / request translation, buffering and scheduling, and power management. In some embodiments, the memory controller 406 is also configured to determine the maximum memory capacity that the computer system can use, the number of memory groups, the memory type and speed, the memory particle data depth and data width, and other important parameters. Any other suitable functions may also be performed by the memory controller 406. The memory controller 406 may communicate with external devices (e.g., the host 408) according to a specific communication protocol. For example, the memory controller 406 can communicate with external devices through at least one of various interface protocols, such as USB protocol, MMC protocol, Peripheral Component Interconnect (PCI) protocol, Fast PCI (PCI-E) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer Small Interface (SCSI) protocol, Enhanced Small Disk Interface (ESDI) protocol, Integrated Drive Electronics (IDE) protocol, Firewire protocol, etc.

[0089] Figure 5 The following are some embodiments of a 3D memory device (such as those described above) for forming vertical transistors, according to the present disclosure. Figure 2A A flowchart of a manufacturing method 500 for a memory cell array 200A described herein. Figures 6A-6E Various embodiments according to this disclosure are shown in Figure 5The diagram shows a schematic side cross-sectional view of a 3D memory device at certain manufacturing stages of method 500. It should be understood that the operations shown in method 500 are not exhaustive, and other operations may be performed before, after, or between any of the operations shown. Furthermore, some operations may be performed simultaneously or in conjunction with... Figure 5 The different execution sequences are shown.

[0090] like Figure 5 As shown, method 500 can begin at operation 510, where a capacitor array can be formed on the substrate. Figure 6A A schematic side cross-sectional view of a 3D memory device in the yz plane is shown after operation 510 of method 500.

[0091] like Figure 6A As shown, an array of capacitors 680 can be formed on a substrate 610. In some embodiments, the substrate 610 can be a semiconductor substrate, which may include silicon (e.g., single-crystal silicon, c-Si), silicon-germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), or any other suitable material. In such embodiments, the array of capacitors 680 can be formed directly on the semiconductor substrate 610, and transistors can be formed on the front side of the array of capacitors 680 in subsequent processes. In some other embodiments, the substrate 610 can be a carrier substrate, which may include any suitable semiconductor material or a non-conductive material (e.g., glass, plastic, or sapphire wafer). In such embodiments, the array of capacitors 680 can be formed directly on another semiconductor substrate, and the carrier substrate 610 can be formed on the front side of the array of capacitors 680. After flipping the structure and removing the semiconductor substrate, transistors can be formed on the back side of the array of capacitors 680 in subsequent processes.

[0092] The array of capacitors 680 may include a common second electrode 683, a plurality of first electrodes 681, and a capacitor dielectric layer 685 between the first electrodes 681 and the common second electrode 683. As shown, the array of capacitors 680 may be an array. In some embodiments, the first electrode 681 and / or the common second electrode 683 may include a conductive material, including but not limited to W, Co, Cu, Al, TiN, TaN, polycrystalline silicon, silicides, or any combination thereof. In some embodiments, the capacitor dielectric layer 685 includes a dielectric material such as silicon oxide, silicon nitride, or a high-k dielectric, including but not limited to Al2O3, HfO2, Ta2O5, ZrO2, TiO2, or any combination thereof.

[0093] In some embodiments, the array of capacitors 680 can be formed by a series of manufacturing processes, including thin film deposition processes (e.g., chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), etc.) and patterning processes (e.g., photolithography, dry etching, wet etching, cleaning, chemical mechanical polishing (CMP), etc.). It should be noted that the manufacturing processes and / or sequence for forming the first electrode 681, the common second electrode 683, and the capacitor dielectric layer 685 can vary depending on whether the process is front-side or back-side.

[0094] like Figure 5 As shown, method 500 can proceed to operation 520, in which multiple bit lines can be formed on the array of capacitors. Figure 6B A schematic side cross-sectional view of a 3D memory device in the yz plane is shown after operation 520 of method 500.

[0095] In such Figure 6B In some embodiments shown, a first dielectric layer 625 may be formed on an array of capacitors 680, and a conductive layer may be formed on the first dielectric layer 626. The conductive layer may be patterned to form a plurality of bit lines 620 arranged in parallel in a first lateral direction (x-direction), each bit line extending along a second lateral direction (y-direction).

[0096] like Figure 5 As shown, method 500 can proceed to operation 530, in which multiple vias can be formed, each via penetrating a corresponding bit line and dielectric layer to expose a corresponding capacitor among a plurality of capacitors. Figure 6C A schematic side cross-sectional view of a 3D memory device in the yz plane is shown after operation 530 of method 500.

[0097] like Figure 6C As shown, a plurality of vias 670 can be formed along each bit line 620 by using any suitable etching process. Each via 670 can penetrate the bit line 620 and the first dielectric layer 625 beneath the bit line, and expose the first electrode 681 of the corresponding capacitor 680.

[0098] like Figure 5 As shown, method 500 can proceed to operation 540, in which a semiconductor layer, a gate dielectric layer, and a gate electrode can be formed in each via. Figure 6D A schematic side cross-sectional view of a 3D memory device in the yz plane is shown after operation 540 of method 500. The semiconductor layer 660, the gate dielectric layer 655, and the gate electrode 650 can be formed by a variety of thin film deposition processes (e.g., CVD, PVD, ALD, etc.) and one or more CMP processes.

[0099] like Figure 6D As shown, the semiconductor layer 660 can be formed to cover the sidewalls and bottom of each via 670. The semiconductor layer 660 can have a leakage value below picoamperes. In some embodiments, the leakage value of the semiconductor layer 660 is lower than the intrinsic leakage value of single-crystal silicon. In some embodiments, the material of the semiconductor layer 660 can be a metal oxide semiconductor material, such as IGZO. In some embodiments, the semiconductor layer 660 may include a first lateral semiconductor portion 662 located at the bottom of the via 670 and in contact with the first electrode 681 of the corresponding capacitor 680, a vertical semiconductor portion 664 on the sidewall of the via 670, and a second lateral semiconductor portion 666 located outside the via 670.

[0100] The gate dielectric layer 655 may be formed to cover the semiconductor layer 660. The gate dielectric layer 655 may include any suitable dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or a high-k dielectric. For example, the gate dielectric layer 655 may include silicon oxide, i.e., a gate oxide. The gate electrode 650 may be formed to fill the via 670. The gate electrode 650 may include any suitable conductive material, such as polysilicon, a metal (e.g., W, Cu, Al, etc.), a metal compound (e.g., TiN, TaN, etc.), or a silicide. For example, the gate electrode 650 may include doped polysilicon, i.e., gate polysilicon. In some embodiments, the gate electrode 650 includes multiple conductive layers, such as a W layer over a TiN layer.

[0101] like Figure 5 As shown, method 500 can proceed to operation 550, in which multiple word lines can be formed. The word lines can extend parallel along a first lateral direction, and each word line contacts the gate electrode of a row of vertical transistors. Figure 6E A schematic side cross-sectional view of a 3D memory device in the yz plane is shown after operation 550 of method 500.

[0102] like Figure 6E As shown, forming word lines 640 may include forming a second dielectric layer 630 to cover the gate dielectric layer 655 and the gate electrode 650, patterning the second dielectric layer 630 to form a plurality of trenches (not shown), and depositing conductive material in the trenches to form word lines 640. The plurality of word lines 640 are arranged in parallel along a second lateral direction (y-direction), and each word line 640 extends along a first lateral direction (x-direction) and is coupled to the gate electrode of a row of vertical transistors in the first lateral direction.

[0103] Figure 7 The following are some embodiments of a 3D memory device (such as those described above) for forming vertical transistors, according to the present disclosure. Figure 3AA flowchart of the manufacturing method 700 of the described memory array 300A. Figures 8A-8E Various embodiments according to this disclosure are shown in Figure 7 The diagram shows a schematic side cross-sectional view of a 3D memory device at certain manufacturing stages of method 700. It should be understood that the operations shown in method 700 are not exhaustive, and other operations may be performed before, after, or between any of the operations shown. Furthermore, some operations may be performed simultaneously or in conjunction with... Figure 7 The different execution sequences are shown.

[0104] like Figure 7 As shown, method 700 can begin at operation 710, where an array of capacitors can be formed on the substrate. Figure 8A A schematic side cross-sectional view of a 3D memory device in the xz plane is shown after operation 710 of method 700.

[0105] like Figure 8A As shown, an array of capacitors 880 can be formed on a substrate 810. In some embodiments, the substrate 810 can be a semiconductor substrate, which may include silicon (e.g., single-crystal silicon, c-Si), silicon-germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), or any other suitable material. In such embodiments, the array of capacitors 880 can be formed directly on the semiconductor substrate 810, and transistors can be formed on the front side of the array of capacitors 880 in subsequent processes. In some other embodiments, the substrate 810 can be a carrier substrate, which may include any suitable semiconductor material or a non-conductive material (e.g., glass, plastic, or sapphire wafer). In such embodiments, the array of capacitors 880 can be formed directly on another semiconductor substrate, and the carrier substrate 810 can be formed on the front side of the array of capacitors 880. After flipping the structure and removing the semiconductor substrate, transistors can be formed on the back side of the array of capacitors 880 in subsequent processes.

[0106] The array of capacitors 880 may include a common second electrode 883, a plurality of first electrodes 881, and a capacitor dielectric layer 885 between the first electrodes 881 and the common second electrode 883. As shown, the array of capacitors 880 may be an array. In some embodiments, the first electrode 881 and / or the common second electrode 883 may include a conductive material, including (but not limited to) W, Co, Cu, Al, TiN, TaN, polycrystalline silicon, silicides, or any combination thereof. In some embodiments, the capacitor dielectric layer 885 includes a dielectric material such as silicon oxide, silicon nitride, or a high-k dielectric, including but not limited to Al2O3, HfO2, Ta2O5, ZrO2, TiO2, or any combination thereof.

[0107] In some embodiments, the array of capacitors 880 can be formed by a series of manufacturing processes, including thin film deposition processes (e.g., chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), etc.) and patterning processes (e.g., photolithography, dry etching, wet etching, cleaning, chemical mechanical polishing (CMP), etc.). It should be noted that the manufacturing processes and / or sequence for forming the first electrode 881, the common second electrode 883, and the capacitor dielectric layer 885 may vary depending on whether the process is front-side or back-side.

[0108] like Figure 7 As shown, method 700 can proceed to operation 720, in which multiple word lines can be formed on an array of capacitors. Figure 8B A schematic side cross-sectional view of a 3D memory device in the xz plane is shown after operation 720 of method 700.

[0109] In such Figure 8B In some embodiments shown, a first dielectric layer 852 may be formed on an array of capacitors 880, a conductive layer may be formed on the first dielectric layer 852, and a second dielectric layer 854 may be formed on the conductive layer. The conductive layer may be patterned to form multiple word lines 850 arranged parallel to each other in a second lateral direction (y-direction), each word line 850 extending along a first lateral direction (x-direction). The word lines 850 may comprise any suitable conductive material, such as polysilicon, metals (e.g., W, Cu, Al, etc.), metal compounds (e.g., TiN, TaN, etc.), or silicides. For example, word lines 850 may comprise doped polysilicon. In some embodiments, word lines 850 comprise multiple conductive layers, such as a W layer over a TiN layer.

[0110] like Figure 7 As shown, method 700 can proceed to operation 730, in which a plurality of vias can be formed, each via penetrating a corresponding word line and a first dielectric layer and a second dielectric layer to expose a corresponding capacitor among a plurality of capacitors. Figure 8C A schematic side cross-sectional view of a 3D memory device in the xz plane is shown after operation 730 of method 700.

[0111] like Figure 8C As shown, multiple vias 870 can be formed along each word line 850 using any suitable etching process. Each via 870 can penetrate the second dielectric layer 854, the corresponding word line 850, and the first dielectric layer 852, and expose the first electrode 881 of the corresponding capacitor 880.

[0112] like Figure 7As shown, method 700 can proceed to operation 740, in which a gate dielectric layer, a semiconductor layer, and a fill structure can be formed in each via. Figure 8D A schematic side cross-sectional view of a 3D memory device in the xz plane is shown after operation 740 of method 700. The gate dielectric layer 855, semiconductor layer 860, and fill structure 875 can be formed by a variety of thin film deposition processes (e.g., CVD, PVD, ALD, etc.) and one or more CMP processes.

[0113] like Figure 8D As shown, the gate dielectric layer 855 can be formed to cover the sidewalls of each via 870. The gate dielectric layer 855 can include any suitable dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or a high-k dielectric. For example, the gate dielectric layer 855 can include silicon oxide, i.e., gate oxide. The semiconductor layer 860 can be formed to cover the bottom of the gate dielectric layer 855 and each via 870. The semiconductor layer 860 can have a leakage value below picoamperes. In some embodiments, the leakage value of the semiconductor layer 860 is lower than the intrinsic leakage value of single-crystal silicon. In some embodiments, the material of the semiconductor layer 860 can be a metal oxide semiconductor material, such as IGZO. In some embodiments, the semiconductor layer 860 can include a first lateral semiconductor portion 862 located at the bottom of the via 870 and in contact with the first electrode 881 of the corresponding capacitor 880, a vertical semiconductor portion 864 on the sidewall of the via 870, and a second lateral semiconductor portion 866 located outside the via 870.

[0114] like Figure 7 As shown, method 700 can proceed to operation 750, in which a plurality of bit line contacts and bit lines can be formed. The bit line contacts can be formed in vias above the fill structure and contact the upper portion of the semiconductor layer. The bit lines can extend parallel to a second lateral direction, and each bit line contacts a row of bit line contacts of a vertical transistor. Figure 8E A schematic side cross-sectional view of a 3D memory device in the xz plane is shown after operation 750 of method 700.

[0115] like Figure 8E As shown, forming bit line contacts 645 may include removing the upper portion of each fill structure 875 using an etch-back process to form a groove in each via 870, depositing conductive material in the groove in the via 870, and a subsequent CMP process to remove excess conductive material outside the via 870 to form a plurality of bit line contacts 645. Each bit line contact 645 may contact the upper portion of the semiconductor layer 860.

[0116] In some embodiments, forming the bit line 840 may include forming a third dielectric layer 830 to cover the top surface of the semiconductor layer 860 and the bit line contacts 845, patterning the third dielectric layer 830 to form a plurality of trenches (not shown), and depositing a conductive material in the trenches to form the bit line 840. The plurality of bit lines 840 are arranged in parallel along a first lateral direction (x-direction), and each bit line extends along a second lateral direction (y-direction) and is coupled in the second lateral direction to the bit line contacts 845 of a column of vertical transistors.

[0117] The foregoing description of specific embodiments can be readily modified and / or adapted to various applications. Therefore, based on the teachings and guidance presented herein, such adaptations and modifications are intended to fall within the meaning and scope of equivalents of the disclosed embodiments.

[0118] The scope and extent of this disclosure should not be limited by any of the above embodiments, but should be defined solely by the appended claims and their equivalents.

Claims

1. A semiconductor device, comprising: Multiple vertical transistors, each vertical transistor comprising: A semiconductor layer having a leakage value below picoamperes and comprising a vertical semiconductor portion and at least one lateral semiconductor portion. A gate dielectric layer, the gate dielectric layer comprising a vertical gate dielectric portion extending in the vertical direction on the vertical semiconductor portion, A gate electrode, located on the gate dielectric layer and separated from the semiconductor layer by the gate dielectric layer, wherein the gate electrode extends along the vertical direction and is laterally surrounded by the vertical gate dielectric portion, and the gate electrode contacts the sidewall of the vertical gate dielectric portion; and A plurality of capacitors, each capacitor being coupled to a semiconductor layer corresponding to one of the plurality of vertical transistors, wherein each capacitor is in direct contact with at least one lateral semiconductor portion of the semiconductor layer corresponding to the vertical transistor.

2. The semiconductor device according to claim 1, wherein: The vertical gate dielectric portion is laterally surrounded by the vertical semiconductor portion.

3. The semiconductor device according to claim 2, wherein: The gate dielectric layer also includes a lateral gate dielectric portion that contacts the first end of the gate electrode.

4. The semiconductor device according to claim 3, wherein: The first lateral semiconductor portion is located between the lateral gate dielectric portion and a corresponding capacitor.

5. The semiconductor device according to claim 1, further comprising: Each word line extends along a first lateral direction and is connected to the second end of the gate electrode.

6. The semiconductor device according to claim 2, further comprising: Bit lines, each bit line extending along a second lateral direction and in direct contact with the vertical semiconductor portion.

7. The semiconductor device according to claim 6, wherein: The bit line completely surrounds the sidewall of the vertical semiconductor portion and contacts the second lateral semiconductor portion.

8. The semiconductor device according to claim 6, wherein: The bit line partially surrounds the sidewall of the vertical semiconductor portion and contacts the second lateral semiconductor portion.

9. The semiconductor device according to claim 1, wherein: The leakage value of the semiconductor layer is lower than the intrinsic leakage value of monocrystalline silicon.

10. The semiconductor device according to claim 1, wherein: The semiconductor layer is a metal oxide semiconductor layer.

11. A semiconductor device, comprising: Multiple vertical transistors, each vertical transistor comprising: A gate electrode that extends in a vertical direction. A gate dielectric layer covering a first end of the gate electrode, wherein the gate dielectric layer includes a vertical gate dielectric portion extending in the vertical direction, and the gate electrode is laterally surrounded by the vertical gate dielectric portion and contacts the sidewall of the vertical gate dielectric portion. A semiconductor layer that laterally surrounds the gate dielectric layer and covers a first end of the gate dielectric layer; A plurality of capacitors, each capacitor being coupled to a semiconductor layer corresponding to a vertical transistor in the vertical transistor, wherein each capacitor is in direct contact with a portion of the semiconductor layer corresponding to the vertical transistor covering a first end of the gate dielectric layer; Multiple word lines, each word line extending along a first lateral direction and coupled to the gate electrode; and Multiple bit lines, each extending along a second lateral direction and coupled to the semiconductor layer.

12. The semiconductor device according to claim 11, wherein: The bit lines at least partially surround the semiconductor layer of each vertical transistor in the lateral plane.

13. The semiconductor device according to claim 12, wherein: The leakage value of the semiconductor layer is lower than the intrinsic leakage value of monocrystalline silicon.

14. The semiconductor device according to claim 12, wherein: The semiconductor layer is a metal oxide semiconductor layer.

15. A method of forming a semiconductor device, comprising: Multiple capacitors are formed; A dielectric layer is formed on the plurality of capacitors; A conductive layer is formed on the dielectric layer; Multiple vias are formed, each via penetrating the conductive layer and the dielectric layer to expose a corresponding capacitor among the multiple capacitors; A semiconductor layer is formed to cover the bottom and sidewalls of each via, wherein the portion of the semiconductor layer covering the bottom of the via is in direct contact with a corresponding capacitor among the plurality of capacitors; A gate dielectric layer is formed to cover the semiconductor layer, wherein the gate dielectric layer includes a vertically extending gate dielectric portion; and A gate electrode is formed on the gate dielectric layer in each via, wherein the gate electrode extends along the vertical direction and is laterally surrounded by the vertical gate dielectric portion, and the gate electrode contacts the sidewall of the vertical gate dielectric portion.

16. The method of claim 15, further comprising: Before forming the plurality of vias, the conductive layer is cut to form a plurality of bit lines, each bit line extending along a second lateral direction.

17. The method of claim 15, further comprising: Multiple word lines are formed, each word line extending along a first lateral direction and coupled to the gate electrode.

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