Vertical transistor cell structure utilizing top side and back side resources

Abstract

Various structures are disclosed that implement top-side metal wiring and back-side metal wiring in combination with vertical transistors. These various structures include cells that form inverter devices, NAND devices, and MUX (multiplexer) devices. The disclosed cells include two or four vertical transistors, where the transistors are subjected to various connections, including connected gate logic for inverters and NAND devices or disconnected gate logic for MUX devices.

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