Modular scalable boundary scan controller based on PCIe and test method

Abstract

This invention relates to a modular and scalable boundary scan controller and testing method based on PCIe, belonging to the field of electronic testing technology. This invention addresses the shortcomings of existing boundary scan test controllers and methods in terms of data transmission speed, scalability, and testing efficiency. The FPGA of this invention includes a PCIe interface module, an interrupt control module, a data packet module, a read / write BAR module, a memory management interface module, a memory management module, and multiple boundary scan interface modules. The entire testing process includes the stage where the host computer sends test data packets to the board under test (DUT), and the stage where the DUT sends test responses to the host computer. The widespread application of the PCIe interface module ensures that this controller can be seamlessly integrated into a wide range of general-purpose computer platforms. By achieving high-speed test signal transmission, testing efficiency is significantly improved. This invention is mainly used for fault testing of the board under test.

Description

Technical Field

[0001] This invention relates to the field of electronic testing technology. Background Technology

[0002] As electronic devices become increasingly complex and integrated, boundary scan testing technology, as a highly efficient testing method, has been widely applied in the testing of integrated circuits and electronic circuit boards. This technology uses a boundary scan unit attached to each pin of the chip to test for soldering faults and internal connection faults on the circuit board.

[0003] Most existing boundary scan test controllers use USB or PCI interfaces, which limit their data transfer speed and scalability. While JTAG controllers based on the PCI bus offer higher data transfer speeds, their scalability and compatibility still need improvement.

[0004] In recent years, PCIe interfaces have become increasingly common in the slots of industrial control computers (ICS) for instruments. As a next-generation high-bandwidth, low-latency bus standard, PCIe offers limitless possibilities for the expandability of ICS. Through the PCIe interface, ICS can easily connect to various high-performance expansion cards, such as high-speed data acquisition cards, image processing cards, and industrial communication cards. These expansion cards can significantly enhance the functionality and performance of ICS, enabling them to meet the needs of different industrial applications. Therefore, researching a boundary scan controller with a PCIe interface and its testing method, as an upgrade to PCI controllers, is essential.

[0005] In summary, existing boundary scan test controllers and methods are insufficient in terms of data transmission speed, scalability, and test efficiency, and cannot meet the high requirements of modern electronic equipment testing. These problems urgently need to be solved. Summary of the Invention

[0006] The purpose of this invention is to address the shortcomings of existing boundary scan test controllers and methods in terms of data transmission speed, scalability, and test efficiency. This invention provides a modular and scalable boundary scan controller and test method based on PCIe.

[0007] A modular and scalable boundary scan controller based on PCIe, including an FPGA and external memory. The FPGA includes a PCIe interface module, an interrupt control module, a data packet module, a read / write BAR module, a memory management interface module, a memory management module, and multiple boundary scan interface modules.

[0008] (I) Stage of sending test data packets from the host computer to the board under test:

[0009] The PCIe interface module is used to parse and convert the total test data packets and total packet addresses of all the boards under test output by the host computer. After that, the total test data packets and their addresses are sent to the data packet module and the read / write BAR module respectively. Then, an interrupt instruction is generated and sent to the interrupt control module. The total packet address includes the storage address of the test data packets of each board under test.

[0010] The interrupt control module is used to process the received interrupt commands across clock cycles and send the resulting interrupt request signal to the memory management module.

[0011] The BAR module is used to read the storage addresses of each test data packet within the total test data packet.

[0012] The data packet module is used to unpack the received total test data packet and output the test data packets of each board under test to the memory management module. Each test data packet includes: test data input signal TDI, test mode selection signal TMS and test clock signal TCK.

[0013] The memory management module, upon receiving the downlink interrupt request signal, caches the test data packets of each board under test to the external memory through the memory management interface module according to the storage address of each test data packet; it is also used to read the test data packets of each board under test from the external memory according to the storage address of each test data packet, and after sending each test data packet to the corresponding boundary scan interface module, it generates a protocol conversion start interrupt signal and sends it to the boundary scan interface module.

[0014] The boundary scan interface module is used to cache test data packets; it is also used to convert the protocol of the cached test data packets into the protocol of the corresponding board under test according to the received protocol conversion start interrupt signal, and then send them to the corresponding board under test.

[0015] (II) The stage in which the board under test sends a test response to the host computer:

[0016] Each board under test generates a test response based on the received test data packet and sends its test response to the corresponding boundary scan interface module;

[0017] The boundary scan interface module is used to sequentially convert the received test responses from serial to parallel and buffer them before generating a buffer end interrupt signal and sending it to the memory management module.

[0018] Upon receiving an interrupt signal, the memory management module caches the test response to external memory via the memory management interface module according to the storage address of the test data packet corresponding to each test response. It is also used to read the test response of each board under test from external memory according to the storage address of the test data packet corresponding to each test response, and send the test response to the data packet module. After all test responses have been sent, a cache end interrupt signal is generated and sent to the interrupt control module.

[0019] The data packet module is used to assemble all test responses into packets;

[0020] The interrupt control module is used to perform cross-clock processing based on the received buffer end interrupt signal, and send the resulting upload interrupt request signal to the PCIe interface module.

[0021] The PCIe interface module is used to read the packet assembly test response from the data packet module after receiving the upload interruption request signal, and then perform protocol conversion on the packet assembly test response before uploading it to the host computer.

[0022] Preferably, during the stage where the host computer sends test data packets to the board under test, the PCIe interface module is used to convert the total test data packets and total packet addresses of all the boards under test that it receives into the AXI4 protocol format;

[0023] During the test response phase where the board under test sends a test response to the host computer, the test response is converted into PCIe protocol format after the PCIe interface module is packaged.

[0024] Preferably, the boundary scan interface module includes a cache module and a JTAG module;

[0025] The caching module is used for caching operations.

[0026] The JTAG module is used for protocol conversion, serial-to-parallel conversion, and generating buffer end interrupt signals.

[0027] Preferably, the caching module is implemented using dual RAM modules, with one RAM module used to cache test responses and the other RAM module used to cache test data packets.

[0028] Preferably, all the test boards have the same or different interface protocols.

[0029] Preferably, the memory management interface module is implemented using a MIG IP core, and the MIG IP core communicates with the memory management module via an AXI4 bus.

[0030] Preferably, the PCIe interface module is implemented using an XDMA IP core.

[0031] The test method implemented using the aforementioned PCIe-based modular scalable boundary scan controller includes:

[0032] After the host computer parses the test responses after packaging, it compares each parsed test response with the standard data of the board under test corresponding to that test response to complete the test.

[0033] Advantages of this invention:

[0034] This invention utilizes an FPGA to implement a boundary scan controller, significantly improving testing efficiency. The programmability and flexibility of the FPGA allow for rapid adaptation to different testing requirements without hardware replacement, thus enhancing test adaptability. Its parallel processing capabilities support multiple boundary scan interface modules operating simultaneously, enabling concurrent testing of multiple boards under test (DUTs) and greatly improving test concurrency. Furthermore, the efficient modular design within the FPGA, such as high-speed data transmission via the PCIe interface module, fast caching and retrieval of the memory management module, and dynamic adjustment of the test clock signal (TCK), further optimizes the testing process, reduces testing time, and ensures high efficiency and reliability.

[0035] The PCIe interface, as a new generation of high-speed serial computer expansion bus standard, features high data transfer speed, low latency, and excellent scalability, facilitating the integration of various high-performance expansion cards. The PCIe interface was chosen because of its high data transfer speed, excellent scalability, and compatibility, which meet the high-performance requirements of modern electronic equipment testing.

[0036] This invention leverages the PCIe interface for efficient test data transmission, combined with the flexibility of programmable logic devices. The controller in this invention precisely controls the output of test data packets and accurately retrieves test responses. This design allows test engineers to flexibly adjust the rate of test signals according to specific test scenarios and requirements to achieve optimal test performance and adaptability. This invention not only enhances the flexibility and accuracy of testing but also provides users with an efficient and reliable test solution to address the complexity and challenges of testing modern electronic devices.

[0037] This invention uses a programmable logic device (FPGA) to implement a boundary scan controller. In scenarios requiring different numbers and frequencies of test interfaces, the requirements can be easily adapted through programming. When faced with different test interfaces, simply converting the protocol to the corresponding interface protocol is sufficient to perform the testing of the board under test.

[0038] Combining the advantages of PCIe interface and boundary scan technology can effectively solve problems such as data transmission bottlenecks, insufficient scalability, and low testing efficiency in existing test equipment, thereby improving testing efficiency and accuracy. The test clock signal TCK frequency of the boundary scan controller can be dynamically adjusted between 10MHz and 100MHz. Theoretically, with sufficient FPGA resources, the number of expandable boundary scan interface modules can handle all situations. Attached Figure Description

[0039] Figure 1 This is a schematic diagram of the PCIe-based modular scalable boundary scan controller described in this invention;

[0040] Figure 2 This is a schematic diagram of a link connecting the boundary scan controller of the present invention to the board under test; where TDO is the test response;

[0041] Figure 3 This is a schematic diagram of the timing capture waveform of the output signal of the boundary scan controller of the present invention; Detailed Implementation

[0042] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0043] It should be noted that, unless otherwise specified, the embodiments and features described in the present invention can be combined with each other.

[0044] Detailed Implementation Method 1, see [link / reference] Figures 1 to 3 This embodiment describes a PCIe-based modular scalable boundary scan controller, which includes an FPGA and external memory. The FPGA includes a PCIe interface module, an interrupt control module, a data packet module, a read / write BAR module, a memory management interface module, a memory management module, and multiple boundary scan interface modules.

[0045] (I) Stage of sending test data packets from the host computer to the board under test:

[0046] The PCIe interface module is used to parse and convert the total test data packets and total packet addresses of all the boards under test output by the host computer. After that, the total test data packets and their addresses are sent to the data packet module and the read / write BAR module respectively. Then, an interrupt instruction is generated and sent to the interrupt control module. The total packet address includes the storage address of the test data packets of each board under test.

[0047] The interrupt control module is used to process the received interrupt commands across clock cycles and send the resulting interrupt request signal to the memory management module.

[0048] The BAR module is used to read the storage addresses of each test data packet within the total test data packet.

[0049] The data packet module is used to unpack the received total test data packet and output the test data packets of each board under test to the memory management module. Each test data packet includes: test data input signal TDI, test mode selection signal TMS and test clock signal TCK.

[0050] The memory management module, upon receiving the downlink interrupt request signal, caches the test data packets of each board under test to the external memory through the memory management interface module according to the storage address of each test data packet; it is also used to read the test data packets of each board under test from the external memory according to the storage address of each test data packet, and after sending each test data packet to the corresponding boundary scan interface module, it generates a protocol conversion start interrupt signal and sends it to the boundary scan interface module.

[0051] The boundary scan interface module is used to cache test data packets; it is also used to convert the protocol of the cached test data packets into the protocol of the corresponding board under test according to the received protocol conversion start interrupt signal, and then send them to the corresponding board under test.

[0052] (II) The stage in which the board under test sends a test response to the host computer:

[0053] Each board under test generates a test response based on the received test data packet and sends its test response to the corresponding boundary scan interface module;

[0054] The boundary scan interface module is used to sequentially convert the received test responses from serial to parallel and buffer them before generating a buffer end interrupt signal and sending it to the memory management module.

[0055] Upon receiving an interrupt signal, the memory management module caches the test response to external memory via the memory management interface module according to the storage address of the test data packet corresponding to each test response. It is also used to read the test response of each board under test from external memory according to the storage address of the test data packet corresponding to each test response, and send the test response to the data packet module. After all test responses have been sent, a cache end interrupt signal is generated and sent to the interrupt control module.

[0056] The data packet module is used to assemble all test responses into packets;

[0057] The interrupt control module is used to perform cross-clock processing based on the received buffer end interrupt signal, and send the resulting upload interrupt request signal to the PCIe interface module.

[0058] The PCIe interface module is used to read the packet assembly test response from the data packet module after receiving the upload interruption request signal, and then perform protocol conversion on the packet assembly test response before uploading it to the host computer.

[0059] In practical applications, the PCIe interface module can use the PCIe 2.0 x4 interface, achieving a read / write bandwidth of up to 1.2 GB / s, which greatly improves data transmission speed and shortens test time, especially in large-scale interconnect tests.

[0060] The PCIe interface, as a new generation of high-speed serial computer expansion bus standard, features high data transfer speed, low latency, and excellent scalability, facilitating the integration of various high-performance expansion cards. The PCIe interface was chosen because of its high data transfer speed, excellent scalability, and compatibility, which meet the high-performance requirements of modern electronic equipment testing.

[0061] This invention uses an FPGA as the controller. FPGA chips possess high programmability and flexibility, enabling complex logic control and data processing, thus providing excellent scalability. FPGA chips can be easily connected to a PCIe interface to achieve high-speed data transmission and multi-channel data processing, meeting the high-performance requirements of modern electronic device testing. Furthermore, FPGAs can be programmed to implement various test modes and functions, further improving the flexibility and efficiency of testing.

[0062] This invention uses a programmable logic device (FPGA) to implement a boundary scan controller. In scenarios requiring different numbers and frequencies of test interfaces, the requirements can be easily adapted through programming. When faced with different test interfaces, simply converting the protocol to the corresponding interface protocol is sufficient to perform the testing of the board under test.

[0063] Combining the advantages of PCIe interface and boundary scan technology can effectively solve problems such as data transmission bottlenecks, insufficient scalability, and low testing efficiency in existing test equipment, thereby improving testing efficiency and accuracy. The TCK frequency of the boundary scan controller can be dynamically adjusted between 10MHz and 100MHz. Theoretically, with sufficient FPGA resources, the number of expandable boundary scan interface modules can handle all situations.

[0064] In practical applications, the interface protocols of all the boards under test may be the same or different, depending on the specific circumstances.

[0065] Furthermore, during the stage where the host computer sends test data packets to the board under test, the PCIe interface module is used to convert the total test data packets and total packet addresses of all the boards under test that it receives into the AXI4 protocol format;

[0066] During the test response phase where the board under test sends a test response to the host computer, the test response is converted into PCIe protocol format after the PCIe interface module is packaged.

[0067] In this preferred embodiment, the AXI4 protocol has high versatility and scalability, simplifies system integration, and adapts to future module upgrade needs.

[0068] Furthermore, the boundary scan interface module includes a cache module and a JTAG module;

[0069] The caching module is used for caching operations.

[0070] The JTAG module is used for protocol conversion, serial-to-parallel conversion, and generating buffer end interrupt signals.

[0071] This controller is also well-suited for boards under test with multiple JTAG interfaces. When a board under test has an excessively long boundary scan chain, the long scan chain can be appropriately shortened into a shorter scan chain with multiple JTAG interfaces, and then the boundary scan controller of this invention can be used, thereby reducing test time.

[0072] A boundary scanner implemented using an FPGA can achieve this functionality simply by instantiating a few cache and JTAG modules and adjusting parameters in other modules. This design fully leverages the programmability of the FPGA and the flexibility of reading and writing base addresses in the BAR module, realizing a truly modular design for the boundary scan controller.

[0073] The specific structure of the boundary scan interface module is presented. In this configuration, the buffer module ensures the continuity of data transmission, and the JTAG module enables flexible protocol conversion and serial-to-parallel conversion, significantly improving testing efficiency and accuracy. Furthermore, the modular design facilitates collaborative work among modules, is easy to expand and maintain, and can flexibly adapt to various testing needs.

[0074] Furthermore, the caching module is implemented using dual RAM modules, with one RAM module used to cache test responses and the other RAM module used to cache test data packets. This design effectively utilizes time parallelism, improves data throughput, and avoids problems caused by data stream conflicts. Regarding cross-clock domain data transmission, this invention employs a handshake protocol to ensure data integrity and synchronization. The handshake protocol is a commonly used cross-clock domain communication method that confirms data transmission and reception through a series of signal exchanges, thereby avoiding data errors caused by clock domain asynchrony. This method not only improves the reliability of data transmission but also enhances system stability.

[0075] Furthermore, the memory management interface module is implemented using a MIG IP core, which communicates with the memory management module via the AXI4 bus. The MIG IP core interacts with the internal FPGA modules through the AXI4 (Advanced eXtensible Interface 4) bus, leveraging its high performance and flexibility to achieve efficient data transfer. The memory management module sends read / write requests to the MIG IP core via the AXI4 bus. The MIG IP core translates these requests into external memory operation instructions, completes the data read or write operation, and returns the results to the internal modules via the AXI4 bus. This design not only simplifies the development process but also improves the overall system performance, enabling the memory management module to efficiently manage external memory read / write operations.

[0076] Furthermore, the PCIe interface module is implemented using the XDMA IP core.

[0077] Specific Implementation Method Two: This implementation method adopts the test method implemented using the PCIe-based modular scalable boundary scan controller described in Specific Implementation Method One. The method includes:

[0078] After the host computer parses the test responses after packaging, it compares each parsed test response with the standard data of the board under test corresponding to that test response to complete the test.

[0079] While the invention has been described herein with reference to specific embodiments, it should be understood that these embodiments are merely examples of the principles and applications of the invention. Therefore, it should be understood that many modifications can be made to the exemplary embodiments, and other arrangements can be designed without departing from the spirit and scope of the invention as defined by the appended claims. It should be understood that different dependent claims and features described herein can be combined in ways different from those described in the original claims. It is also understood that features described in conjunction with individual embodiments can be used in other described embodiments.

Claims

1. A modular and scalable boundary scan controller based on PCIe, comprising an FPGA and external memory, characterized in that, The FPGA includes a PCIe interface module, an interrupt control module, a data packet module, a read / write BAR module, a memory management interface module, a memory management module, and multiple boundary scan interface modules; (a) The stage where the host computer sends test data packets to the board under test: The PCIe interface module is used to parse and convert the total test data packets and total packet addresses of all the boards under test output by the host computer. After that, the total test data packets and their addresses are sent to the data packet module and the read / write BAR module respectively. Then, an interrupt instruction is generated and sent to the interrupt control module. The total packet address includes the storage address of the test data packets of each board under test. The interrupt control module is used to process the received interrupt commands across clock cycles and send the resulting interrupt request signal to the memory management module. The BAR module is used to read the storage addresses of each test data packet within the total test data packet. The data packet module is used to unpack the received total test data packet and output the test data packets of each board under test to the memory management module. Each test data packet includes: test data input signal TDI, test mode selection signal TMS and test clock signal TCK. The memory management module, upon receiving the downlink interrupt request signal, caches the test data packets of each board under test to the external memory through the memory management interface module according to the storage address of each test data packet; it is also used to read the test data packets of each board under test from the external memory according to the storage address of each test data packet, and after sending each test data packet to the corresponding boundary scan interface module, it generates a protocol conversion start interrupt signal and sends it to the boundary scan interface module. The boundary scan interface module is used to cache test data packets; it is also used to convert the protocol of the cached test data packets into the protocol of the corresponding board under test according to the received protocol conversion start interrupt signal, and then send them to the corresponding board under test. (II) The stage where the board under test sends a test response to the host computer: Each board under test generates a test response based on the received test data packet and sends its test response to the corresponding boundary scan interface module; The boundary scan interface module is used to sequentially convert the received test responses from serial to parallel and buffer them before generating a buffer end interrupt signal and sending it to the memory management module. Upon receiving an interrupt signal, the memory management module caches the test response to external memory via the memory management interface module according to the storage address of the test data packet corresponding to each test response. It is also used to read the test response of each board under test from external memory according to the storage address of the test data packet corresponding to each test response, and send the test response to the data packet module. After all test responses have been sent, a cache end interrupt signal is generated and sent to the interrupt control module. The data packet module is used to assemble all test responses into packets; The interrupt control module is used to perform cross-clock processing based on the received buffer end interrupt signal, and send the resulting upload interrupt request signal to the PCIe interface module. The PCIe interface module is used to read the packet assembly test response from the data packet module after receiving the upload interruption request signal, and then perform protocol conversion on the packet assembly test response before uploading it to the host computer.

2. The modular and scalable boundary scan controller based on PCIe according to claim 1, characterized in that, During the stage when the host computer sends test data packets to the board under test, the PCIe interface module is used to convert the total test data packets and total packet addresses of all the boards under test that it receives into the AXI4 protocol format; During the test response phase where the board under test sends a test response to the host computer, the test response is converted into PCIe protocol format after the PCIe interface module is packaged.

3. The modular and scalable boundary scan controller based on PCIe according to claim 1, characterized in that, The boundary scan interface module includes a cache module and a JTAG module; The caching module is used for caching operations. The JTAG module is used for protocol conversion, serial-to-parallel conversion, and generating buffer end interrupt signals.

4. The PCIe-based modular and scalable boundary scan controller according to claim 3, characterized in that, The caching module is implemented using dual RAM modules, with one RAM module used to cache test responses and the other RAM module used to cache test data packets.

5. The modular and scalable boundary scan controller based on PCIe according to claim 1, characterized in that, All the interfaces of the boards under test may have the same or different protocols.

6. The modular and scalable boundary scan controller based on PCIe according to claim 1, characterized in that, The memory management interface module is implemented using the MIG IP core, which communicates with the memory management module via the AXI4 bus.

7. The modular and scalable boundary scan controller based on PCIe according to claim 1, characterized in that, The PCIe interface module is implemented using the XDMA IP core.

8. The test method implemented using the PCIe-based modular scalable boundary scan controller as described in claim 1, characterized in that, The method includes: After the host computer parses the test responses after packaging, it compares each parsed test response with the standard data of the board under test corresponding to that test response to complete the test.

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