Image centroid coordinate extraction circuit without divider

Abstract

The application discloses a kind of image centroid coordinate extraction circuits without divider, rely on field programmable gate array (FPGA) to realize, core is in the quotient operation in centroid calculation formula is converted into addition, subtraction and multiplication operation, to avoid the trial division and remainder process required by division.Wherein, to further optimize the area of circuit and enhance its functionality, one adder unit in multiplier is extended, so it can not only support multiplication operation, but also can perform subtraction operation.Through this design, combined with time-sharing multiplexing technology, the multiplier circuit can execute the entire arithmetic flow of centroid extraction iterative approximation.The application optimizes the processing speed of centroid extraction circuit, through less clock cycle and controllable circuit area, realizes the fast centroid extraction of large target surface image, has wide application potential in image recognition, target tracking and artificial intelligence and multiple fields.

Description

Technical Field

[0001] This invention belongs to the fields of image centroid extraction, digital integrated circuit design, and real-time signal processing technology, and specifically relates to an image centroid coordinate extraction circuit without a divider. Background Technology

[0002] Centroid extraction circuits play a crucial role in image processing, identifying the center position of objects in an image and serving as essential for target tracking, object recognition, and wavefront detection. Specifically, digital circuits calculate the weighted average of each pixel in an image to pinpoint the precise coordinates of an object. They have wide applications in fields such as autonomous driving, facial recognition, and aerospace.

[0003] In practical applications, centroid extraction is typically performed using digital circuits, primarily due to the separation of the acquisition system from signal processing. Therefore, building adders, multipliers, and dividers on an FPGA enables rapid centroid calculation. However, in typical centroid calculation circuit designs, division requires repeated trial divisions and remainder comparisons, resulting in extremely long processing times. In applications involving large target images, shift-compare cyclic division proves inadequate. Summary of the Invention

[0004] To address the aforementioned technical problems, this invention provides an image centroid coordinate extraction circuit without a divider. Its core is based on the concept of numerical approximation. It utilizes a lookup table to read the inaccurate initial centroid coordinate solutions, constructs an iterative loop circuit, and achieves the successive solution of the accurate centroid coordinate values ​​through iterative approximation. This circuit extends one stage of the matrix multiplier with an adder, enabling it to support multiplication, addition, and subtraction operations. This allows a single set of circuit modules to perform all the operations required for numerical iteration, completing the centroid coordinate extraction of a large-bit-width image within tens of clock cycles with minimal logic resources.

[0005] To achieve the above objectives, the technical solution adopted by the present invention is as follows:

[0006] An image centroid coordinate extraction circuit without a divider includes an FPGA-based lookup table unit, a multiplier consisting of N cascaded adders, and a clock design unit; wherein,

[0007] The FPGA's lookup table unit is used to find the corresponding reciprocal initial value based on the first m bits of the sum of the input image pixels. The reciprocal initial value is passed through a first algorithm selector and entered into the multiplier along with the first m bits of the sum of the pixels to perform a multiplication operation, obtaining a first multiplication result. The first multiplication result is fed back to the Nth adder in the multiplier through a second algorithm selector. By inverting the adder's value, a difference calculation operation is performed to obtain a first subtraction result. The first subtraction result is then used as a multiplier and passed through the first algorithm selector, along with the first m bits of the sum of the pixels, to be input into the multiplier again to perform a second multiplication operation, obtaining a second multiplication result, which is also the first iteration result.

[0008] The first m+1 bits of the pixel sum value are fed into the multiplier along with the first iteration result to perform the multiplication operation, the difference calculation operation, and the second multiplication operation in sequence, and the loop is iterated until the corresponding iteration of all bits of the pixel sum is completed.

[0009] The clock design unit is used to control the control pins placed on the cascaded adder, the Nth adder, and the shift register to achieve timing control.

[0010] Furthermore, the sum of the input image pixels includes M bits, where M ≥ 2; the sum of the pixel values ​​is input into a shift register to obtain the first m bits of the sum of pixel values, where m < M.

[0011] Furthermore, the Nth adder is an enhanced adder that supports multiplication and subtraction operations.

[0012] Furthermore, the enhanced adder extends the input channel of the lookahead adder on the FPGA, allowing the clock signal to control the source of the addend and augend, enabling the lookahead adder circuit to dynamically switch between addition and subtraction operations.

[0013] Furthermore, the addend input of the enhanced adder is the result of the previous adder or a fixed value of 2, and the augend input is the multiplier or the inverse of the multiplier operation result.

[0014] Furthermore, when the addend input is the result of the previous stage adder, the augend input is the multiplier; when the addend input is a fixed value of 2, the augend input is the inverse of the multiplier operation result.

[0015] Furthermore, the timing design unit performs iterative approximation according to the following formula:

[0016] ,

[0017] In the formula, X i+1 X represents the result after iteration. i represents the initial value of the iteration, and b represents the iteration parameter.

[0018] On the other hand, the present invention provides a method for extracting the centroid coordinates of an image without a divider, comprising the following steps:

[0019] The FPGA's lookup table unit searches for the corresponding reciprocal initial value based on the first m bits of the sum of the input image pixels. This reciprocal initial value, along with the first m bits of the sum of the pixels, is passed through a first algorithm selector and input into the multiplier to perform a multiplication operation, obtaining a first multiplication result. The first multiplication result is fed back to the Nth adder in the multiplier via a second algorithm selector. By inverting the adder's value, a difference calculation is performed to obtain a first subtraction result. The first subtraction result, as the multiplier, is passed through the first algorithm selector and input again with the first m bits of the sum of the pixels to the multiplier to perform a second multiplication operation, obtaining a second multiplication result, which is also the first iteration result.

[0020] The first m+1 bits of the pixel sum value are fed into the multiplier along with the first iteration result to perform the multiplication operation, the difference calculation operation, and the second multiplication operation in sequence, and the loop is iterated until the corresponding iteration of all bits of the pixel sum is completed.

[0021] The clock design unit controls the timing by placing control pins on the cascaded adders, the Nth adder, and the shift register.

[0022] Thirdly, the present invention provides an electronic device, comprising: one or more processors; and a memory for storing one or more programs; wherein, when the one or more programs are executed by the one or more processors, the one or more processors implement the aforementioned method for extracting image centroid coordinates without a divider.

[0023] Fourthly, the present invention provides a computer-readable storage medium having executable instructions stored thereon, which, when executed by a processor, enable the processor to implement the aforementioned method for extracting image centroid coordinates without a divider.

[0024] The beneficial effects of this invention are as follows:

[0025] This invention employs initial value lookup table and numerical approximation, which does not involve division operations, thereby improving the operation speed of the centroid extraction circuit in principle.

[0026] This invention extends the first-stage adder in a matrix multiplier to enable it to perform addition and subtraction operations. By applying time-division multiplexing technology, complete numerical iterative arithmetic operations are implemented on a single multiplier circuit, thereby significantly reducing the overall area of ​​the centroid extraction circuit.

[0027] This invention utilizes time-domain segmentation and timing matching techniques, and through a circuit loop mechanism, to achieve automatic function switching and iterative calculation of the arithmetic unit without the need for an additional control unit. Attached Figure Description

[0028] Figure 1 This is a schematic diagram of the principle of an image centroid coordinate extraction circuit without a divider according to the present invention;

[0029] Figure 2 This is a schematic diagram of an image centroid coordinate extraction circuit without a divider according to the present invention;

[0030] Figure 3 The circuit diagram of an 8-bit carry-lookahead adder on an FPGA is shown.

[0031] Figure 4 This is a device implementation diagram of an 8-bit carry-lookahead adder on an FPGA.

[0032] Figure 5 A schematic diagram of an enhanced adder that supports multiplication and fixed-value subtraction operations;

[0033] Figure 6 This is a schematic diagram of the clock distribution for an image centroid coordinate extraction circuit without a divider according to the present invention;

[0034] Figure 7 The timing design of the entire circuit includes the timing relationships between the arithmetic unit, shift register, selector, and flip-flops. Detailed Implementation

[0035] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0036] like Figure 1 As shown, this invention demonstrates a schematic diagram of an image centroid coordinate extraction circuit design without a divider. This design utilizes a lookup table device in a programmable logic unit to read the inexact solution corresponding to the high-order bits of the pixel value. By enhancing the matrix-cascaded multiplier circuit and applying the time-division multiplexing principle, the inexact solution can undergo Newton's iterative approximation operation on the enhanced multiplier, thereby achieving successive approximation of the exact solution.

[0037] like Figure 2 As shown, the overall architecture of the image centroid coordinate extraction circuit without a divider of the present invention comprises three main parts: a lookup table unit of FPGA, a multiplier composed of N cascaded adders, and a clock design unit including multiple associated clock domains.

[0038] The sum of all pixel values ​​in the input image is obtained and used as the input to the centroid coordinate extraction circuit of this invention, denoted as the pixel sum. The pixel sum is assumed to have M bits, where M ≥ 2. Specifically:

[0039] The sum of pixel values ​​is input into a shift register to obtain the first m bits of the pixel sum, where m < M; where,

[0040] The FPGA's lookup table unit is used to find the corresponding reciprocal initial value based on the first m bits of the pixel sum. The reciprocal initial value is passed through a first algorithm selector and entered into the multiplier along with the first m bits of the pixel sum to perform a multiplication operation, obtaining a first multiplication result, which is stored in flip-flop FF2. The first multiplication result is fed back to the Nth adder in the multiplier through a second algorithm selector. By inverting the adder's value, a difference calculation operation is performed to obtain a first subtraction result, which is stored in flip-flop FF3. The first subtraction result is then used as a multiplier and passed through the first algorithm selector, along with the first m bits of the pixel sum, to be input into the multiplier again to perform a second multiplication operation, obtaining a second multiplication result, which is also the first iteration result, and is stored in flip-flop FF1.

[0041] The value of the pixel sum is input into the shift register again to obtain the first m+1 bits of the pixel sum. The first m+1 bits of the pixel sum and the first iteration result are fed into the multiplier to perform multiplication, difference calculation and second multiplication operations in sequence. The process is repeated until the M-bit iteration of the pixel sum is completed.

[0042] The clock design unit is used to control the control pins and clock located on the cascaded adder, inverter and shift register to achieve automatic timing control.

[0043] like Figure 3 As shown, the cascaded adder includes N stages of look-ahead adders, each stage of which is constructed from a lookup table (LUT) and a carry chain component in a CLB (programmable logic unit). By inputting the addend and augend into an XOR gate synthesized from the lookup table (LUT), and using the XOR gate result to control the carry chain selector S, the arithmetic sum signal and carry signal are generated rapidly. See [link to documentation]. Figure 4 .

[0044] like Figure 5 As shown, the Nth-stage adder in the extended multiplier, as an enhanced adder, can have a selector added to each pin of the adder's input. This selector allows dynamic control over the source of the addend, the source of the augend, and whether it is inverted. Specifically, when the selector control signal is high, the addend and augend are set as the previous stage input and multiplier input, respectively, to perform multiplication. Conversely, when the control signal is low, the adder input is set to a fixed value '2' and the inverse of the previous multiplication result, to perform the difference operation between 2 and the product. Through this setup, using a time-division multiplexing strategy, this circuit can perform multiplication or fixed-number subtraction at different times to achieve the arithmetic functions required for centroid iteration.

[0045] In the time domain, such as Figure 6By designing five clock domains and precisely controlling their timing, seamless integration of multiplication, difference calculation, and double multiplication operations can be achieved. Specifically, when the CLK_02 signal goes high, the multiplexer (MUX) is placed in multiplication mode. The CLK_03 signal activates flip-flop FF2 to capture and hold the intermediate result of the multiplication operation, i.e., the aforementioned first multiplication result. Immediately afterwards, the CLK_02 signal goes low, switching the MUX to subtraction mode, allowing the previous calculation result stored in FF2 to perform the subtraction operation. After the operation is completed, the CLK_04 signal triggers FF3 to latch the subtraction result, i.e., the aforementioned first subtraction result. Subsequently, the rising edge of CLK_02 switches the multiplexer (MUX) back to multiplier mode. In this stage, the rising edge of CLK_05 first switches the multiplier input to FF3, and the falling edge switches the multiplier input back to FF1 and triggers FF1 to acquire the result, i.e., the aforementioned second multiplication result.

[0046] The above steps can be summarized as the iterative process shown in Table 1, represented by Equation (1), in which the pixel value is preferably moved to 2k bits precision in each iteration.

[0047] Table 1

[0048] (1)

[0049] Here, X i+1 X represents the result after iteration. i 'b' represents the initial value for the iteration, and 'b' represents the iteration parameter (this parameter is shifted to 2k bits of precision by a shift register in each iteration, where k represents the number of iterations to match the increasing iteration precision). In this way, the circuit can accurately perform the computational iterations necessary for the Newton-Raphson rational number approximation.

[0050] Figure 7 The timing sequence is fully displayed in a tiled diagram. It can be seen that the operation mode, shift register, and MUX_2 of this circuit switch at the same frequency, while FF1, FF2, and FF3 are driven by different clocks to capture the operation results generated in different operation modes.

[0051] In summary, this invention successfully constructed an arithmetic circuit capable of performing multiplication and subtraction operations on an FPGA platform using existing circuit components and time-division multiplexing technology. Subsequently, by decomposing the centroid calculation process into two stages—initial value lookup and successive approximation circuit—and employing clock domain decomposition technology, a single-circuit modular implementation of numerical iterative calculation was achieved.

[0052] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above descriptions are merely specific embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A circuit for extracting the centroid coordinates of an image without a divider, characterized in that, This includes an FPGA-based lookup table unit, a multiplier composed of N cascaded adders, and a clock design unit. The multiplier, composed of N cascaded adders, performs multiplication operations through the cascaded structure of each adder stage and reuses the cascaded structure during iteration. The FPGA's lookup table unit is used to find the corresponding reciprocal initial value based on the first m bits of the sum of the input image pixels. The reciprocal initial value is passed through a first algorithm selector and entered into the multiplier along with the first m bits of the sum of the pixels to perform a multiplication operation, obtaining a first multiplication result. The first multiplication result is fed back to the Nth adder in the multiplier through a second algorithm selector. By inverting the adder's value, a difference calculation operation is performed to obtain a first subtraction result. The first subtraction result is then used as a multiplier and passed through the first algorithm selector, along with the first m bits of the sum of the pixels, to be input into the multiplier again to perform a second multiplication operation, obtaining a second multiplication result, which is also the first iteration result. The first m+1 bits of the pixel sum value are fed into the multiplier along with the first iteration result to perform the multiplication operation, the difference calculation operation, and the second multiplication operation in sequence. The process is repeated by expanding the number of bits in the pixel sum until the corresponding iteration of all bits in the pixel sum is completed. The clock design unit is used to control the control pins placed on the cascaded adder, the Nth adder, and the shift register to achieve timing switching between multiplication and subtraction modes and timing control of the iteration process.

2. The image centroid coordinate extraction circuit without a divider according to claim 1, characterized in that, The sum of the input image pixels includes M bits, where M ≥ 2; the sum of the pixel values ​​is input into a shift register to obtain the first m bits of the sum of pixel values, where m < M.

3. The image centroid coordinate extraction circuit without a divider according to claim 1, characterized in that, The Nth adder is an enhanced adder that supports multiplication and subtraction operations.

4. The image centroid coordinate extraction circuit without a divider according to claim 3, characterized in that, The enhanced adder extends the input channel of the lookahead adder on the FPGA, allowing the clock signal to control the source of the addend and augend, enabling the lookahead adder circuit to dynamically switch between addition and subtraction operations.

5. The image centroid coordinate extraction circuit without a divider according to claim 4, characterized in that, The addend input of the enhanced adder is the result of the previous adder or a fixed value of 2, and the augend input is the multiplier or the inverse of the result of the multiplier operation.

6. The image centroid coordinate extraction circuit without a divider according to claim 5, characterized in that, When the addend input is the result of the previous adder, the augend input is the multiplier; when the addend input is a fixed value of 2, the augend input is the inverse of the multiplier operation result.

7. The image centroid coordinate extraction circuit without a divider according to claim 6, characterized in that, The clock design unit performs iterative approximation according to the following formula: （1） In the formula, X i+1 X represents the result after iteration. i represents the initial value of the iteration, and b represents the iteration parameter.

8. A method for extracting the centroid coordinates of an image without a divider, applied to the circuit described in any one of claims 1-7, characterized in that, Includes the following steps: The FPGA's lookup table unit searches for the corresponding reciprocal initial value based on the first m bits of the sum of the input image pixels. This reciprocal initial value, along with the first m bits of the sum of the pixels, is passed through a first algorithm selector and input into a multiplier to perform a multiplication operation, obtaining a first multiplication result. The first multiplication result is fed back to the Nth adder in the multiplier via a second algorithm selector. By inverting the adder's value, a difference calculation is performed to obtain a first subtraction result. The first subtraction result, as the multiplier, is passed through the first algorithm selector and input again with the first m bits of the sum of the pixels to the multiplier to perform a second multiplication operation, obtaining a second multiplication result, which is also the first iteration result. The first m+1 bits of the pixel sum value are fed into the multiplier along with the first iteration result to perform the multiplication operation, the difference calculation operation, and the second multiplication operation in sequence, and the loop is iterated until the corresponding iteration of all bits of the pixel sum is completed. The clock design unit controls the timing by placing control pins on the cascaded adders, the Nth adder, and the shift register.

9. An electronic device, characterized in that, include: One or more processors; Memory, used to store one or more programs; When one or more programs are executed by the one or more processors, the one or more processors implement the image centroid coordinate extraction method without a divider as described in claim 8.

10. A computer-readable storage medium, characterized in that, It stores executable instructions that, when executed by a processor, enable the processor to implement the image centroid coordinate extraction method without a divider as described in claim 8.

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