A method and apparatus for identifying sub-block transform information
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- HFI INNOVATION INC
- Filing Date
- 2020-07-24
- Publication Date
- 2026-08-07
Smart Images
Figure CN120017850B_ABST
Abstract
Description
[0001] Cross-reference to related applications
[0002] This disclosure claims priority to U.S. Provisional Application No. 62 / 900,395, filed September 13, 2019, which is incorporated herein by reference in its entirety. Background Technology
[0003] Video is a set of still images (or "pictures") that capture visual information. To reduce storage memory and transmission bandwidth, video can be compressed before storage or transmission and decompressed before display. The compression process is usually called encoding, and the decompression process is usually called decoding. Currently, there are various video coding formats that use standardized video coding technologies, the most common being those based on prediction, transform, quantization, entropy coding, and in-loop filtering. These video coding standards, such as HEVC / H.265 (High Efficiency video coding), VVC / H.266 (Versatile video coding), and AVS (AVS standards), have specific video coding formats defined by standardization organizations. With the application of more and more advanced video coding technologies in these standards, the coding efficiency of new video coding standards is also increasing. Summary of the Invention
[0004] Embodiments of the present invention provide a method and apparatus for video processing. In one exemplary embodiment, the video processing method includes: identifying a first flag bit in a sequence parameter set (SPS) of a video sequence to indicate whether subblock transform (SBT) is enabled; and identifying a second flag bit to indicate the maximum transform block (TB) size allowed by the SBT. In response to the first flag bit indicating that the SBT is enabled, the maximum coding unit (CU) size allowed by the SBT is determined directly based on the maximum transform block (TB) size.
[0005] In another exemplary embodiment, a video processing apparatus includes at least one memory for storing an instruction set and at least one processor. The at least one processor executes the instruction set to cause the apparatus to: identify a first flag in a sequence parameter set (SPS) of a video sequence to indicate whether subblock transform (SBT) is enabled; and identify a second flag to indicate the maximum transform block (TB) size allowed for the SBT. In response to the first flag indicating that the SBT is enabled, the maximum coding unit (CU) size allowed for the SBT is determined directly based on the maximum transform block (TB) size.
[0006] In another exemplary embodiment, a non-volatile computer-readable storage medium stores a set of instructions. This set of instructions is executable by at least one processor to cause a computer to perform a video processing method. The method includes: identifying a first flag bit in a sequence parameter set (SPS) of a video sequence to indicate whether subblock transform (SBT) is enabled; and identifying a second flag bit to indicate the maximum transform block (TB) size allowed for the SBT. In response to the first flag bit indicating that the SBT is enabled, the maximum coding unit (CU) size allowed for the SBT is determined directly based on the maximum transform block (TB) size. Attached Figure Description
[0007] Embodiments and aspects of this disclosure are described in the following detailed description and accompanying drawings. The various features shown in the figures are not drawn to scale.
[0008] Figure 1 A schematic diagram illustrating the structure of an exemplary video sequence is shown according to some embodiments of this disclosure.
[0009] Figure 2 According to some embodiments of this disclosure, a schematic diagram of an exemplary encoder in a hybrid video coding system is shown.
[0010] Figure 3 According to some embodiments of this disclosure, a schematic diagram of an exemplary decoder in a hybrid video coding system is shown.
[0011] Figure 4 According to some embodiments of this disclosure, block diagrams of exemplary apparatus for encoding or decoding video are shown.
[0012] Figure 5 According to some embodiments of the present invention, exemplary subblock transform (SBT) types and SBT locations of inter-predictive coding units (CUs) are shown.
[0013] Figure 6 as well as Figure 6-1 (Continued) Figure 6 According to some embodiments of this disclosure, an exemplary table 1 is shown, illustrating a portion of the SPS syntax table.
[0014] Figure 7 A flowchart of an exemplary video processing method is shown according to some embodiments of this disclosure.
[0015] Figure 8 as well as Figure 8-1 According to some embodiments of this disclosure, an exemplary table 2 is shown, illustrating a portion of the SPS syntax table.
[0016] Figure 9According to some embodiments of this disclosure, exemplary Table 3 is shown, illustrating a portion of the CU syntax table.
[0017] Figure 10 According to some embodiments of this disclosure, a flowchart of another exemplary video processing method is shown. Detailed Implementation
[0018] Preferred embodiments will now be described in detail, examples illustrated in the accompanying drawings. Unless otherwise stated, the following description refers to the drawings, wherein the same numbers in different figures denote the same or similar elements. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present invention. Rather, they are merely examples of apparatuses and methods consistent with aspects of the invention as described in the appended claims. Specific aspects of this disclosure will be described in more detail below. In the event of any conflict with terms and / or definitions contained in the references, the terms and definitions provided herein shall prevail.
[0019] The Joint Video Experts Group (JVET) of the ITU-T Video Coding Experts Group (ITU-T VCEG) and the ISO / IEC Moving Picture Experts Group (ISO / IEC MPEG) are currently developing the Universal Video Coding (VVC / H.266) standard. The goal of the VVC standard is to double the compression efficiency of its predecessor, High Efficiency Video Coding (HEVC / H.265). In other words, VVC aims to achieve the same subjective quality as HEVC / H.265 while using half the bandwidth.
[0020] To achieve the same subjective quality as HEVC / H.265 while using half the bandwidth, JVET has been developing techniques beyond HEVC using the Joint Exploratory Model (JEM) reference software. Because the coding techniques are incorporated into JEM, its coding performance is significantly higher than HEVC.
[0021] The VVC standard is a relatively recent development and continues to incorporate more coding techniques that offer improved compression performance. VVC is based on the same hybrid video coding system used in modern video compression standards such as HEVC, H.264 / AVC, MPEG2, and H.263.
[0022] Video is a series of still images (or "frames") arranged chronologically to store visual information. Video capture devices (such as cameras) can be used to capture and store these images in a time series, and video playback devices (such as televisions, computers, smartphones, tablets, video players, or any end-user terminal with a display function) can be used to display such images in the time series. Similarly, in some applications, video capture devices can transmit captured video to video playback devices (e.g., computers with monitors) in real time, for purposes such as surveillance, conferencing, or live streaming.
[0023] To reduce the storage space and transmission bandwidth required for such applications, video can be compressed before storage and transmission, and decompressed before display. Compression and decompression can be implemented by software executed by a processor (e.g., a processor in a general-purpose computer) or by dedicated hardware. The module used for compression is typically called an "encoder," and the module used for decompression is typically called a "decoder." Encoders and decoders can be collectively referred to as "codecs." Encoders and decoders can be implemented in any form, such as various suitable hardware, software, or combinations thereof. For example, hardware implementations of encoders and decoders can include circuits such as one or more microprocessors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), discrete logic, or any combination thereof. Software implementations of encoders and decoders can include program code, computer-executable instructions, firmware, or any suitable computer-implemented algorithm or process embedded in a computer-readable medium. Video compression and decompression can be implemented using various algorithms or standards, such as MPEG-1, MPEG-2, MPEG-4, H.26x series, etc. In some applications, a codec can decompress a video from a first encoding standard and then recompress the decompressed video using a second encoding standard. In this case, the codec can be called a "transcoder".
[0024] Video encoding processes can identify and retain useful information that can be used to reconstruct an image, while ignoring information that is not important to the reconstruction. If the ignored, unimportant information cannot be fully reconstructed, such an encoding process can be called "lossy." Otherwise, it can be called "lossless." Most encoding processes are lossy, as a trade-off to reduce required storage space and transmission bandwidth.
[0025] Useful information about an encoded image (referred to as the "current frame") includes changes relative to a reference frame (e.g., previously encoded and reconstructed frames). These changes can include changes in pixel position, luminance, or color, with changes in position being of most interest. Changes in the position of a set of pixels representing an object can reflect the movement of that object between the reference frame and the current frame.
[0026] A coded frame that does not reference another frame (i.e., it is its own reference frame) is called an "I-frame". A coded frame that uses a previous frame as its reference frame is called a "P-frame". A coded frame that uses both a previous frame and a future frame as its reference frame (i.e., the reference is "bidirectional") is called a "B-frame".
[0027] Figure 1 According to some embodiments of this disclosure, the structure of an exemplary video sequence 100 is shown. The video sequence 100 can be real-time video or video that has already been captured and archived. The video 100 can be real-life video, computer-generated video (such as computer game video), or a combination of both (such as real-life video with augmented reality effects). The video sequence 100 can be input from a video capture device (such as a camera), a video archive containing previously captured video (such as a video file stored on a storage device), or from a video feed interface (such as a video broadcast transceiver) to receive video from a video content provider.
[0028] like Figure 1 As shown, video sequence 100 may include a series of frames arranged along the time axis, including frames 102, 104, 106, and 108. Frames 102-106 are consecutive, with many frames between frame 106 and frame 108. Figure 1 In the diagram, frame 102 is an I-frame, and its reference frame is frame 102 itself. Frame 104 is a P-frame, and its reference frame is frame 102, as shown by the arrow. Frame 106 is a B-frame, and its reference frames are frames 104 and 108, as shown by the arrow. In some embodiments, the reference frame of a frame (e.g., frame 104) is not directly before or after the frame. For example, the reference frame of frame 104 could be a frame preceding frame 102. It should be noted that the reference frames of frames 102-106 are merely examples, and this disclosure is not limited to them. Figure 1 An example of the reference frame is shown.
[0029] Typically, due to the computational complexity of such tasks, video codecs do not encode or decode the entire frame at once. Instead, they divide the frame into basic segments and encode or decode the frame segment by segment. These basic segments are referred to in this disclosure as basic processing units (“BPUs”). For example, Figure 1Structure 110 in the diagram shows an example structure of a frame of video sequence 100 (e.g., any frame from frames 102 to 108). In structure 110, a frame is divided into 4×4 basic processing units, with their boundaries indicated by dashes. In some embodiments, basic processing units are referred to as “macroblocks” in some video coding standards (e.g., the MPEG series, H.261, H.263, or H.264 / AVC), or as “coding tree units” (“CTUs”) in some other video coding standards (e.g., H.265 / HEVC or H.266 / VVC). Basic processing units in a frame can have different sizes, such as 128×128, 64×64, 32×32, 16×16, 4×8, 16×32, or pixels of any shape and size. The size and shape of the basic processing units can be chosen for a frame based on a balance between coding efficiency and the level of detail to be preserved within the basic processing units.
[0030] A basic processing unit can be a logical unit, which may include a set of different types of video data stored in computer memory (e.g., in a video frame buffer). For example, a basic processing unit for a color image may contain a luma component (Y) representing achromatic luminance information, one or more chroma components (e.g., Cb and Cr) representing color information, and associated syntax elements. The luma and chroma components may have the same size. In some video coding standards (e.g., H.265 / HEVC or H.266 / VVC), the luma and chroma components may be referred to as “code tree blocks” (CTBs). Any operation performed on a basic processing unit can be repeatedly performed on its individual luma and chroma components.
[0031] Video encoding involves multiple operational stages, examples of which are as follows: Figure 2 and Figure 3As shown. For each stage, the size of the basic processing unit may still be too large to process, and therefore can be further divided into segments referred to herein as "basic processing subunits". In some embodiments, the basic processing subunit may be referred to as a "block" in some video coding standards (e.g., MPEG series, H.261, H.263, or H.264 / AVC), or as a "coding unit" ("CUs") in some other video coding standards (e.g., H.265 / HEVC or H.266 / VVC). The basic processing subunit may have the same or smaller size as the basic processing unit. Similar to the basic processing unit, the basic processing subunit is also a logical unit, which may include a set of different types of video data (e.g., Y, Cb, Cr, and associated syntax elements) stored in computer memory (e.g., video frame buffers). Any operation performed on the basic processing subunit can be repeatedly performed on its individual luma and chroma components. It should be noted that this division can be further performed as needed for processing. It should also be noted that different stages may use different schemes to divide the basic processing unit.
[0032] For example, in the pattern decision-making stage (such as...) Figure 2 As shown in the example, the encoder should decide what prediction mode to use for a basic processing unit (e.g., intra-frame prediction or inter-frame prediction); but the basic processing unit may be too large to make such a decision, the encoder can break the basic processing unit into multiple basic processing sub-units (e.g., CUs in H.265 / HEVC or H.266 / VVC) and determine a prediction type for each individual basic processing sub-unit.
[0033] For example, in the prediction phase ( Figure 2 (As one example is shown), the encoder can perform prediction operations at the level of basic processing subunits (such as CUs). However, in some cases, the basic processing subunits may still be too large to process. The encoder can further divide the basic processing subunits into smaller segments (e.g., referred to as "prediction blocks" or "PBs" in H.265 / HEVC or H.266 / VVC), at which level the prediction operations can be performed.
[0034] To give another example, in the transformation phase ( Figure 2(As one example is shown), the encoder can perform transformation operations on the remaining basic processing subunits (such as CUs). However, in some cases, the basic processing subunits may still be too large to process. The encoder can further divide the basic processing subunits into smaller segments (e.g., referred to as "conversion blocks" or "TBs" in H.265 / HEVC or H.266 / VVC), at which level the transformation operations can be performed. It should be noted that the partitioning scheme of the same basic processing subunit may differ between the prediction and transformation phases. For example, in H.265 / HEVC or H.266 / VVC, the prediction blocks and transformation blocks of the same CU can have different sizes and numbers.
[0035] exist Figure 1 In structure 110, the basic processing unit 112 is further divided into 3×3 basic processing sub-units, and the boundaries of the sub-units are shown as dashed lines in the figure. In different schemes, different basic processing units of the same frame can be divided into different basic processing sub-units.
[0036] In some implementations, video encoding and decoding provide parallel processing capabilities and error recovery. A frame can be divided into several regions for processing, allowing the encoding or decoding of one region of the frame to proceed independently without relying on information from other regions of the frame. In other words, each region in the frame can be processed independently. This allows the codec to process different regions of the image frame in parallel, thereby improving encoding efficiency. Furthermore, when data in one region is corrupted during processing or lost during network transmission, the codec can correctly encode or decode other regions of the same image frame without relying on the corrupted or lost data, thus providing fault tolerance. In some video coding standards, a frame can be divided into different types of regions. For example, H.265 / HEVC and H.266 / VVC provide two types of regions: "slices" and "tiles." It should also be noted that different frames of the video sequence 100 can have different schemes for dividing the frame into regions.
[0037] For example, in Figure 1 In the diagram, structure 110 is divided into three regions: 114, 116, and 118. The boundaries of these regions are represented by solid lines within structure 110. Region 114 comprises four basic processing units. Regions 116 and 118 each comprise six basic processing units. It should be noted that... Figure 1 The basic processing unit, basic processing subunit, and region of the structure 110 are merely examples, and this disclosure does not limit its implementation.
[0038] According to some embodiments of this disclosure Figure 2A schematic diagram of an exemplary encoder 200 in a hybrid video coding system is shown. The video encoder 200 can perform intra-block or inter-block coding within a video frame, including video blocks, or partitions or sub-partitions of video blocks. Intra-block coding can rely on spatial prediction to reduce or eliminate video spatial redundancy within a given video frame. Inter-block coding can rely on temporal prediction to reduce or remove temporal redundancy between adjacent frames in a video sequence. Intra-block modes can refer to spatially based compression modes. Inter-block modes (such as single prediction or double prediction) can refer to temporally based compression modes.
[0039] Reference Figure 2 The input video signal 202 can be processed block by block. For example, a video block unit can be a 16×16 pixel block (e.g., a macroblock (MB)). The size of the video block unit may vary depending on the coding technique used and the required accuracy and efficiency. In HEVC, extended block sizes (such as coding tree units (CTUs)) can be used to compress video signals with a resolution of 1080p or higher. In HEVC, a CTU can include up to 64×64 luma samples corresponding to chroma samples, along with associated syntax elements. In VVC, the size of the CTU can be further increased to 128x128 luma samples corresponding to chroma samples, along with associated syntax elements. A CTU can be further divided into coding units (CUs), for example, using quadtrees, binary trees, or ternary trees. A CU can be further divided into prediction units (PUs), to which different prediction methods can be applied. Each input video block can be processed using spatial prediction unit 260 or temporal prediction unit 262.
[0040] Spatial prediction unit 260 uses information from the same frame / slice containing the current block to perform spatial prediction (e.g., intra-block prediction) on the current block / CU. Spatial prediction can utilize pixels from adjacent blocks already encoded in the same video frame / slice to predict the current video block. Spatial prediction can reduce the inherent spatial redundancy in the video signal.
[0041] The timing prediction unit 262 uses information from frames / slices other than those containing the current block to perform timing prediction (e.g., inter-block prediction). The timing prediction of a video block can be identified by one or more motion vectors. In unidirectional timing prediction, only one motion vector identifying a reference frame is used to generate the prediction identifier for the current block. On the other hand, in bidirectional timing prediction, two motion vectors, each identifying a reference frame, can be used to generate the prediction identifier for the current block. The motion vectors can indicate the amount and direction of motion between the current block and one or more related blocks in the reference frames. If multiple reference frames are supported, one or more reference frame indices can be sent for a video block. The one or more reference indices are used to identify which reference frame from the reference image library or decoded image buffer (DPB) 264 can generate the timing prediction signal.
[0042] The mode decision and encoder control unit 280 in the encoder can select the prediction mode, for example, rate-distortion based optimization. A prediction block can be obtained based on the determined prediction mode. The prediction block can be subtracted from the current video block at adder 216. The prediction residual can be transformed using transform unit 204 and quantized using quantization unit 206. The quantized residual coefficients can be dequantized using dequantization unit 210 and inverse transformed using inverse transform unit 212 to form a reconstruction residual. The reconstruction residual is added to the prediction block at adder 226 to form a reconstructed video block. The reconstructed video block before loop filtering can be used as a reference sample for internal prediction.
[0043] The reconstructed video block can be loop-filtered on the loop filter 266. For example, loop filtering such as deblocking filtering, sample adaptive offset (SAO), and adaptive loop filter (ALF) can be used. The loop-filtered reconstructed block can be stored in the reference image library 264 and can provide inter-prediction reference samples for encoding other video blocks. To form the output video bitstream 220, before compressing and packaging the data to form the bitstream 220, the encoding mode (such as inter-frame or intra-frame), prediction mode information, motion information, quantization residual coefficients, etc., can be sent to the entropy coding unit 208 to further reduce the bit rate.
[0044] According to some embodiments of this disclosure Figure 3 A schematic diagram of an exemplary decoder 300 in a hybrid video coding system is shown. (Refer to...) Figure 3 The video bitstream 302 can be unpacked or entropy-decoded on the entropy decoding unit 308. Encoding mode information can be used to determine whether to select spatial prediction unit 360 or temporal prediction unit 362. Prediction mode information can be sent to the appropriate prediction unit to generate prediction blocks. For example, temporal prediction unit 362 can apply motion-compensated prediction to form the temporal prediction block.
[0045] The residual coefficients are sent to the inverse quantization unit 310 and the inverse transform unit 312 to obtain the reconstructed residuals. The predicted block and the reconstructed residuals are added at 326 to form a reconstructed block before loop filtering. The reconstructed block can then be loop filtered at the loop filter 366. For example, deblocking filtering, SAO, ALF, etc., can be applied. The loop-filtered reconstructed block can be stored in the reference image library 364. The reconstructed data in the reference image library 364 can be used to obtain the decoded video 320 or to predict subsequent video blocks. The decoded video 320 can be displayed on a display device, such as a television, PC, smartphone, or tablet, for end-user viewing.
[0046] According to some embodiments of the present invention, Figure 4 A block diagram of an exemplary device 400 for encoding or decoding video is shown. Figure 4 As shown, device 400 may include processor 402. When processor 402 executes the instruction set described herein, device 400 may become a dedicated machine for video encoding or decoding. Processor 402 may be any type of circuit system capable of operating or processing information. For example, processor 402 may include any number and any combination of central processing units (CPU), graphics processing units (GPU), neural processing units (NPU), a microcontroller unit (MCU), an optical processor, a programmable logic controller, a microcontroller, a digital signal processor, an IP core, a programmable logic array (PLA), a programmable array logic (PAL), a general-purpose array logic (GAL), a complex programmable logic device (CPLD), a field-programmable gate array (FPGA), a system-on-a-chip (SoC), an application-specific integrated circuit (ASIC), etc. In some embodiments, processor 402 may also be a group of processors grouped into a single logic component. For example, as Figure 4 As shown, processor 402 may include multiple processors, including processor 402a, processor 402b and processor 402n.
[0047] The device 400 may also include memory 404 configured to store data (e.g., a set of instructions, computer code, intermediate data, or the like). For example, as Figure 4 As shown, the stored data may include program instructions (e.g., instructions for executing...). Figure 2 or Figure 3The processor 402 can access the program instructions and data to be processed (e.g., via bus 410) and execute the program instructions to perform operations or control on the data for processing. The memory 404 may include a high-speed random access storage device or a non-volatile storage device. In some embodiments, the memory 404 may include any combination of any number of random access memories (RAM), a read-only memory (ROM), an optical disc, a magnetic disk, a hard disk, a solid-state drive, a flash drive, a secure digital card (SD) card, a memory stick, a compact flash memory (CF) card, or other similar elements. The memory 404 may also be a group of memories combined into a single logical component. Figure 4 (Not displayed).
[0048] Bus 410 may be a communication device for transmitting data between internal components of device 400, such as an internal bus (e.g., CPU-Memory Bus), an external bus (e.g., Universal Serial Bus Port, Peripheral Component Interconnect Fast Port), or similar devices.
[0049] For ease of explanation and to avoid ambiguity, processor 402 and other data processing circuitry are collectively referred to as "data processing circuitry" in this disclosure. Data processing circuitry can be implemented entirely in hardware or as a combination of software, hardware, or firmware. Furthermore, data processing circuitry can be a standalone module or can be wholly or partially integrated into other components of device 400.
[0050] The device 400 may also include a network interface 406 to provide wired or wireless communication with a network (e.g., the Internet, intranet, local area network, mobile communication network, or the like). In some embodiments, the network interface 406 may include a network interface controller (NIC), a radio frequency (RF) module, a transceiver, a transceiver, a modem, a router, a gateway, a wired network card, a wireless network card, a Bluetooth network card, an infrared network card, a near field communication (NFC) adapter, a cellular network chip, or the like.
[0051] In some embodiments, the device 400 may optionally include a peripheral interface 408 to provide connectivity to one or more peripheral devices. Figure 4 As shown, peripheral devices may include, but are not limited to, cursor control devices (such as mice, touchpads, or touchscreens), keyboards, displays (e.g., cathode ray tube displays, liquid crystal displays, or light-emitting diode displays), video input devices (e.g., cameras or input interfaces connected to video files), or other similar devices.
[0052] It should be noted that the video codec can be implemented as any combination of any software or hardware modules in device 400. For example, Figure 2 encoder 200 or Figure 3 Some or all stages of the decoder 300 can be implemented as one or more software modules of the device 400, for example, program instructions that can be loaded into memory 404. In another example, Figure 2 encoder 200 or Figure 3 Some or all stages of the decoder 300 can be implemented as one or more hardware modules of the device 400, such as dedicated data processing circuitry (e.g., FPGA, ASIC, NPU, or similar circuitry).
[0053] In quantization and dequantization function blocks (such as...) Figure 2 Quantization unit 206 and dequantization unit 210, Figure 3 The dequantization unit 310 uses quantization parameters (QP) to determine the amount of quantization (and dequantization) applied to the prediction residual. The initial QP value used to encode a frame or slice can be identified at a higher level, for example, using the syntax element `init_qp_minus26` in the frame parameter set (PPS) or the syntax element `slice_qp_delta` in the slice header. Furthermore, the incremental QP values sent at the quantization group granularity can be used to adjust the QP value for each CU at this level.
[0054] In VVC, Subblock Transform (SBT) is used for inter-predictive coding units (CUs). In this transform mode, only a specific sub-part of the remaining block is encoded and provided to the coding unit. When the inter-predictive unit with the syntax element `cu_cbf` is equal to 1, the syntax element `cu_sbt_flag` can be used to indicate whether the entire remaining block or a specific sub-part of the remaining block is encoded. In the former case, the inter-multiple transform-selected (MTS) information is further parsed to determine the transform type of the CU. In the latter case, a portion of the residual block is encoded using an inference adaptive transform, while the rest of the residual block is set to zero.
[0055] When SBT is used for an inter-prediction CU, the SBT type and SBT location information are identified in the bitstream. There are two SBT types and two SBT locations, such as... Figure 5As shown. For SBT-V (or SBT-H), the width (or height) of the transform unit (TU) can be equal to half the width (or height) or 1 / 4 of the CU width (or height), forming a 2:2 split or a 1:3 / 3:1 split. The 2:2 split is similar to a binary tree (BT) split, while the 1:3 / 3:1 split is similar to an asymmetric binary tree (ABT) split. In an ABT split, only its small regions contain non-zero residuals. If a coding unit has 8 luminance samples in a certain dimension, then a 1:3 / 3:1 split along that dimension is not allowed. A coding unit can have a maximum of 8 SBT modes.
[0056] The Sequence Parameter Set (SPS) level syntax can use the syntax element `sps_sbt_enabled_flag` to specify whether SBT is enabled or disabled. When the syntax element `sps_sbt_enabled_flag` equals 0, it indicates that SBT for inter-predictive coding units is disabled throughout the entire video sequence referencing this SPS. When the syntax element `sps_sbt_enabled_flag` equals 1, it indicates that SBT for inter-predictive coding units is enabled for the entire video sequence referencing this SPS.
[0057] Furthermore, when `sps_sbt_enabled_flag` equals 1, another SPS syntax element, `sps_sbt_max_size_64_flag`, can be used to specify the maximum allowed CU width and height for the SBT. When the syntax element `sps_sbt_max_size_64_flag` equals 0, it indicates that the maximum allowed CU width and height for the SBT is 32 luma samples. When the syntax element `sps_sbt_max_size_64_flag` equals 1, it indicates that the maximum allowed CU width and height for the SBT is 64 luma samples. The variable `MaxSbtSize` is calculated according to Formula 1 below, which specifies the maximum allowed CU size for the SBT:
[0058] MaxSbtSize=Min(MaxTbSizeY,sps_sbt_max_size_64_flag?64:32)(Formula 1)
[0059] Where MaxTbSizeY is the maximum allowed transformation block (TB) size, which can be derived from another SPS-level syntax element sps_max_luma_transform_size_64_flag according to Formula 2 below:
[0060] MaxTbSizeY=sps_max_luma_transform_size_64_flag? 64:32(Formula 2)
[0061] As mentioned above, the source of MaxSbtSize depends on two syntax elements: `sps_max_luma_transform_size_64_flag` and `sps_sbt_max_size_64_flag`. If the value of the syntax element `sps_max_luma_transform_size_64_flag` is 0, then MaxSbtSize is always 32 regardless of the value of the syntax element `sps_sbt_max_size_64_flag`. Therefore, when the syntax element `sps_max_luma_transform_size_64_flag` is 0, it is not necessary to flag the syntax element `sps_sbt_max_size_64_flag`. This syntax redundancy in VVC unnecessarily increases signaling overhead.
[0062] To improve video encoding efficiency, according to some publicly available embodiments, the syntax element sps_sbt_max_size_64_flag is only identified when both the syntax elements sps_max_luma_transform_size_64_flag and sps_sbt_enabled_flag are 1. Figure 6 Exemplary Table 1 is shown according to some embodiments of the present disclosure. Table 1 shows exemplary SPS syntax tables for some embodiments. As shown in Table 1 (emphasis is shown in italics), the syntax element sps_sbt_max_size_64_flag is only identified when both the syntax elements sps_max_luma_transform_size_64_flag and sps_sbt_enabled_flag are 1. If the syntax element sps_max_luma_transform_size_64_flag is 0, then the syntax element sps_sbt_max_size_64_flag can be inferred to be 0, which means that the maximum width and height of the CU allowed for SBT is 32 (in luminance samples).
[0063] Figure 7 A flowchart of an exemplary video processing method 700 according to some embodiments of the present disclosure is shown. In some embodiments, method 700 may be performed by an encoder (e.g., Figure 2 The encoder 200), decoder (e.g., Figure 3 A decoder 300) or a device containing one or more software or hardware components (e.g., a ... Figure 4 The device 400 in the middle) executes. For example, the processor (e.g., Figure 4The processor 402 can execute method 700. In some embodiments, method 700 can be implemented by a computer program product contained in a computer-readable medium, the product including computer-executable instructions, such as program code executable by a computer (e.g., Figure 4 (device 400 in the middle).
[0064] In step 702, method 700 may include determining whether subblock transform (SBT) is enabled in the sequence parameter set (SPS) of a video sequence. In some embodiments, a flag bit (e.g., as shown in the image) Figure 6 The syntax element `sps_sbt_enabled_flag` shown in Table 1 can be used to identify whether SBT is enabled in an SPS. For example, a syntax element `sps_sbt_enabled_flag` equal to 0 can specify that SBT for inter-predictive coding units is disabled for the entire video sequence referencing the SPS. And a syntax element `sps_sbt_enabled_flag = 1` can specify that SBT for inter-predictive coding units is enabled for the entire video sequence referencing the SPS.
[0065] In step 704, method 700 may include determining the value of a first flag bit in the SPS, which indicates the maximum transfer block (TB) size allowed for the SBT. The first flag bit may be set to a first value or a second value. For example, the first value is 1, and the second value is 0. The maximum TB size may be 32, 64, or similar. In some embodiments, method 700 may further include setting the first flag bit to a first value corresponding to a maximum TB size of 64, and setting the value of the first flag bit to a second value corresponding to a maximum TB size of 32. In some embodiments, the first flag bit may be... Figure 6 The syntax element sps_max_luma_transform_size_64_flag in Table 1.
[0066] In step 706, method 700 may include identifying a second flag bit in response to SBT being enabled and the value of the first flag bit being equal to a first value, indicating the maximum coding unit (CU) size allowed for SBT. In response to SBT being disabled or the value of the first flag bit being equal to a second value, the second flag bit is not identified. For example, the second flag bit could be as follows: Figure 6 The syntax element sps_sbt_max_size_64_flag is shown in Table 1. The syntax element sps_sbt_max_size_64_flag will only be marked when both the syntax elements sps_max_luma_transform_size_64_flag and sps_sbt_enabled_flag are 1.
[0067] In some embodiments, method 700 may further include identifying a third flag bit in the SPS (e.g., such as...). Figure 6 The syntax element `sps_sbt_enabled_flag` shown in Table 1 indicates whether SBT is enabled, and identifies the first flag bit in SPS (e.g., ...). Figure 6 The syntax element in Table 1 is `sps_max_luma_transform_size_64_flag`.
[0068] In some embodiments, the maximum CU size can be 32 or 64. The maximum CU width or height allowed for the SBT can be determined based on the smaller of the maximum TB size and the maximum CU size (e.g., according to Formula 1).
[0069] In some publicly available embodiments, the syntax element `sps_sbt_max_size_64_flag` is not specified at all. In this case, the maximum allowed width and height of the SBT's CU directly depends on the syntax element `sps_max_luma_transform_size_64_flag`. If the syntax element `sps_max_luma_transform_size_64_flag` is equal to 0, the maximum allowed CU width and height of the SBT is 32 luma samples. If the syntax element `sps_max_luma_transform_size_64_flag` is equal to 1, the maximum allowed CU width and height of the SBT is 64 luma samples. In other words, `MaxSbtSize` is set to be equal to `MaxTbSizeY`. Figure 8 According to some embodiments of this disclosure, exemplary Table 2 is shown. Table 2 shows exemplary SPS syntax for implementing these embodiments. As shown in Table 2, the syntax element sps_sbt_max_size_64_flag is not identified and is removed from the syntax. Figure 9 According to some embodiments of this disclosure, an exemplary Table 3 is shown. Table 3 (emphasized in italics) shows an exemplary coding unit (CU) syntax table that directly uses MaxTbSizeY to set the maximum width and height of the CU. MaxTbSizeY is calculated by Equation 3 as follows:
[0070] MaxTbSizeY=sps_max_luma_transform_size_64_flag? 64:32(Formula 3)
[0071] Figure 10 A flowchart of another exemplary video processing method 1000 according to some embodiments of the present disclosure is shown. In some embodiments, method 1000 may be performed by an encoder (e.g., Figure 2The encoder 200), decoder (e.g., Figure 3 The decoder 300) or one or more software or hardware components of a device (e.g., Figure 4 The device 400) executes. For example, the processor (e.g., Figure 4 The processor 402) can execute method 1000. In some embodiments, method 1000 may be implemented by a computer program product contained in a computer-readable medium, the product including computer-executable instructions, such as those from a computer (e.g., a processor 402). Figure 4 The program code executed by device 400 in the middle.
[0072] In step 1002, method 1000 includes a first flag bit in the sequence parameter set (SPS) that identifies the video sequence, indicating whether subblock transform (SBT) is enabled. In some embodiments, the first flag bit may be the syntax element sps_sbt_enabled_flag, such as Figure 8 As shown in Table 2. For example, a syntax element `sps_sbt_enabled_flag` equal to 0 can specify that SBT for inter-predictive coding units is disabled for the entire video sequence referencing SPS. And, a syntax element `sps_sbt_enabled_flag` equal to 1 can specify that SBT for inter-predictive coding units is enabled for the entire video sequence referencing SPS.
[0073] In step 1004, method 1000 may include identifying a second flag bit to indicate the maximum transfer block (TB) size allowed for the SBT. The second flag bit may be set to either a first value or a second value. For example, the first value is 1, and the second value is 0. The maximum TB size may be 32, 64, or a similar value. In some embodiments, method 1000 may further include setting the value of the second flag bit to 0 when the maximum TB size is 32, and setting the value of the second flag bit to 1 when the maximum TB size is 64. In some embodiments, the first flag bit may be... Figure 8 The syntax element `sps_max_luma_transform_size_64_flag` in Table 2.
[0074] In response to the first flag indicating that SBT is enabled, the maximum CU size of the SBT can be determined directly from the maximum TB size. For example, the maximum CU size is equal to the maximum TB size. The maximum CU size includes the maximum width and maximum height of the CU.
[0075] In some embodiments, a non-volatile computer-readable storage medium including an instruction set is also provided, and the instruction set can be executed by a device (such as the encoder and decoder) for performing the methods described above. Common forms of non-volatile media include, for example, floppy disks, flexible disks, hard disks, solid-state drives, magnetic tape, or any other magnetic data storage medium, CD-ROMs, any other optical data storage media, any punched physical media mode, RAM, PROMs, and EPROMs, flash-based EPROMs or other flash memory, NVRAMs, caches, registers, any other storage chips or magnetic tape, and similar network versions. The device may include one or more processors (CPUs), input / output interfaces, network interfaces, and / or memory.
[0076] The embodiments may be further described using the following terms:
[0077] 1. A video processing method, comprising:
[0078] Determine whether Subblock Transform (SBT) is enabled in the Sequence Parameter Set (SPS) of the video sequence;
[0079] Determine the value of the first flag bit in the SPS, which indicates the maximum transfer block (TB) size allowed for the SBT; and
[0080] In response to SBT being enabled and the value of the first flag bit being equal to the first value, a second flag bit is identified, indicating the maximum coding unit (CU) size allowed for SBT.
[0081] 2. According to the method in paragraph 1, wherein, in response to the SBT not being enabled, or the value of the first flag bit being equal to the second value, the second flag bit is not marked.
[0082] 3. The method according to Article 1 or Article 2 further includes:
[0083] The third flag in the SPS indicates whether SBT is enabled; and
[0084] Identify the first flag bit in the SPS.
[0085] 4. According to the method described in Article 2, the first value is 1 and the second value is 0.
[0086] 5. According to any one of the methods in clauses 1-4, where the maximum TB size is 32 or 64.
[0087] 6. The method according to Article 5 further includes: in response to a maximum TB size of 64, setting the value of the first flag bit to a first value.
[0088] 7. The method according to Article 5 further includes:
[0089] In response to a maximum TB size of 32, the value of the first flag is set to the second value.
[0090] 8. According to any one of the methods in Clauses 1-7, where the maximum CU size allowed for the SBT is 32 or 64.
[0091] 9. The method according to any one of clauses 1-8, wherein the maximum CU width allowed for SBT is determined based on the smaller of the maximum TB size and the maximum CU size allowed for SBT.
[0092] 10. According to any one of the methods in Sections 1-9, wherein the maximum CU height allowed for SBT is determined based on the smaller of the maximum TB size and the maximum CU size allowed for SBT.
[0093] 11. A video processing apparatus, comprising:
[0094] At least one memory for storing instruction sets; and
[0095] At least one processor executes the instruction set to enable the device to perform:
[0096] Determine whether Subblock Transform (SBT) is enabled in the Sequence Parameter Set (SPS) of the video sequence;
[0097] Determine the value of the first flag bit in the SPS, which indicates the maximum transfer block (TB) size allowed for the SBT; and
[0098] In response to the SBT being enabled and the value of the first flag bit being equal to the first value, the second flag bit is identified, indicating the maximum coding unit (CU) size allowed for the SBT.
[0099] 12. The device according to Article 11, wherein the second flag is not marked when the SBT is not enabled or the value of the first flag bit is equal to the second value.
[0100] 13. The device according to paragraph 11 or 12, wherein at least one processor further executes the instruction set to cause the device to perform:
[0101] Identify the third flag bit in the SPS to indicate whether the SBT is enabled; and
[0102] Identify the first flag bit in SPS.
[0103] 14. The device according to Article 12, wherein the first value is 1 and the second value is 0.
[0104] 15. According to any one of clauses 11-14, where the maximum TB size is 32 or 64.
[0105] 16. The equipment according to Clause 15 further comprises:
[0106] In response to a maximum TB size of 64, the value of the first flag is set to the first value.
[0107] 17. The equipment according to Clause 15, further comprising:
[0108] In response to a maximum TB size of 32, the value of the first flag is set to the second value.
[0109] 18. The device according to any one of clauses 11-17, wherein the maximum CU size of the SBT is allowed to be 32 or 64.
[0110] 19. The device according to any one of clauses 11-18, wherein the maximum CU width allowed by the SBT is determined based on the smaller of the maximum TB size and the maximum CU size allowed by the SBT.
[0111] 20. The device according to any one of Clauses 11-19, wherein the maximum CU height allowed for SBT is determined based on the smaller of the maximum TB size and the maximum CU size allowed for SBT.
[0112] 21. A non-volatile computer-readable storage medium storing a set of instructions, said set of instructions being executed by at least one processor to cause a computer to perform a video processing method, comprising:
[0113] Determine whether Subblock Transform (SBT) is enabled in the Sequence Parameter Set (SPS) of the video sequence;
[0114] Determine the value of the first flag bit in the SPS, which indicates the maximum transfer block (TB) size allowed for the SBT; and
[0115] In response to the SBT being enabled and the value of the first flag bit being equal to the first value, the second flag bit is identified, indicating the maximum coding unit (CU) size allowed for the SBT.
[0116] 22. A non-volatile computer-readable storage medium according to Clause 21, wherein the second flag is not identified when the SBT is not enabled or the value of the first flag bit is equal to the second value.
[0117] 23. A non-volatile computer-readable storage medium according to clause 21 or 22, wherein a set of instructions executable by at least one processor causes the computer to further perform:
[0118] The third flag bit in the SPS indicates whether the SBT is enabled; and
[0119] Identify the first flag bit in SPS.
[0120] 24. A non-volatile computer-readable storage medium pursuant to Clause 22, wherein the first value is 1 and the second value is 0.
[0121] 25. A non-volatile computer-readable storage medium, according to any one of clauses 21-24, wherein the maximum TB size is 32 or 64.
[0122] 26. A non-volatile computer-readable storage medium pursuant to clause 25, wherein a set of instructions executable by at least one processor causes the computer to further perform:
[0123] In response to the maximum TB size being 64, the value of the first flag is set to the first value.
[0124] 27. A non-volatile computer-readable storage medium pursuant to Section 25, wherein a set of instructions executable by at least one processor causes a computer to further perform:
[0125] In response to a maximum TB size of 32, the value of the first flag is set to the second value.
[0126] 28. A non-volatile computer-readable storage medium according to any one of clauses 21-27, wherein the maximum CU size allowed for the SBT is 32 or 64.
[0127] 29. A non-volatile computer-readable storage medium according to any one of clauses 21-28, wherein the maximum CU width allowed by the SBT is determined based on the smaller of the maximum TB size and the maximum CU size allowed by the SBT.
[0128] 30. A non-volatile computer-readable storage medium according to any one of clauses 21-29, wherein the maximum CU height that allows SBT is determined based on the smaller of the maximum TB size and the maximum CU size that allows SBT.
[0129] 31. A video processing method, comprising:
[0130] In the Sequence Parameter Set (SPS) of the video sequence, a first flag is used to indicate whether Subblock Transform (SBT) is enabled; and
[0131] The second flag bit is used to indicate the maximum allowable SBT conversion block size (TB).
[0132] In response to the first flag indicating that the SBT is enabled, the maximum coding unit (CU) size of the SBT is allowed to be determined directly based on the maximum transformation block (TB) size.
[0133] 32. The method according to Section 31, wherein the maximum CU size allowed for the SBT is the maximum CU width or the maximum CU height.
[0134] 33. The method according to section 31 or 32, wherein the maximum CU size allowed by the SBT is determined to be equal to the maximum TB size.
[0135] 34. The method described in any one of clauses 31-33, wherein the maximum TB size is 32 or 64.
[0136] 35. The method according to Article 34 further includes:
[0137] In response to a maximum TB size of 32, the value of the second flag is set to 0.
[0138] 36. The method according to Article 34 further includes:
[0139] In response to a maximum TB size of 64, the value of the second flag is set to 1.
[0140] 37. A video processing apparatus, comprising:
[0141] At least one memory for storing instructions; and
[0142] At least one processor executes a set of instructions to enable the device to perform:
[0143] In the Sequence Parameter Set (SPS) of the video sequence, a first flag is used to indicate whether Subblock Transform (SBT) is enabled; and
[0144] In response to the first flag indicating that the SBT is enabled, the maximum coding unit (CU) size of the SBT is allowed to be determined directly based on the maximum transformation block (TB) size.
[0145] 38. The apparatus according to Article 37, wherein the maximum CU size of the SBT is allowed to be the maximum CU width or the maximum CU height.
[0146] 39. The apparatus according to Clause 37 or 38, wherein the maximum CU size of the SBT is determined to be equal to the maximum TB size.
[0147] 40. The device according to any one of clauses 37-39, wherein the maximum TB size is 32 or 64.
[0148] 41. The apparatus according to Article 40, wherein at least one processor further executes instructions to cause the apparatus to perform: in response to a maximum TB size of 32, setting the value of the second flag bit to 0.
[0149] 42. The apparatus according to Article 40, wherein at least one processor further executes a set of instructions to cause the apparatus to perform: in response to the maximum TB size being 64, setting the value of the second flag bit to 1.
[0150] 43. A non-volatile computer-readable storage medium storing a set of instructions executable by at least one processor to cause the computer to perform a video processing method, comprising:
[0151] In the Sequence Parameter Set (SPS) of the video sequence, a first flag is used to indicate whether Subblock Transform (SBT) is enabled; and
[0152] The second flag bit is used to indicate the maximum allowable SBT conversion block size (TB).
[0153] In response to the first flag indicating that the SBT is enabled, the maximum coding unit (CU) size of the SBT is allowed to be determined directly based on the maximum transformation block (TB) size.
[0154] 44. A non-volatile computer-readable storage medium pursuant to Clause 43, wherein the maximum CU size permitted for the SBT is the maximum CU width or the maximum CU height.
[0155] 45. A non-volatile computer-readable storage medium pursuant to section 43 or 44, wherein the maximum CU size of the SBT is determined to be equal to the maximum TB size.
[0156] 46. The non-volatile computer-readable storage medium according to any one of Clauses 43-45, wherein the maximum TB size is 32 or 64.
[0157] 47. A non-volatile computer-readable storage medium pursuant to section 46, wherein a set of instructions executable by at least one processor causes a computer to further perform:
[0158] In response to a maximum TB size of 32, the value of the second flag is set to 0.
[0159] 48. A non-volatile computer-readable storage medium pursuant to clause 46, wherein a set of instructions executed by the at least one processor causes the computer to further perform:
[0160] In response to a maximum TB size of 64, the value of the second flag is set to 1.
[0161] It should be noted that the relational terms such as "first" and "second" used in this document are only used to distinguish one entity or operation from another, and do not require or imply any actual relationship or order between these entities or operations. Furthermore, "including," "having," "containing," and other similar terms are synonymous, and the conclusion of any one or more items following any of the foregoing words is open-ended; none of the foregoing terms indicates that the one or more items have been exhaustively listed, or are limited to only one or more of the listed items.
[0162] When used herein, unless otherwise expressly stated, the term "or" includes all possible combinations except those that are impractical. For example, if expressed as a database may include A or B, then unless otherwise specified or impractical, it may include database A, or B, or A and B. As a second example, if expressed as a database may include A, B, or C, then unless otherwise specified or impractical, the database may include database A, or B, or C, or A and B, or A and C, or B and C, or A and B and C.
[0163] It is worth noting that the above embodiments can be implemented by hardware or software (program code), or a combination of hardware and software. If implemented by software, it can be stored in the above-described computer-readable medium. When executed by a processor, the software can perform the methods disclosed above. The computing units and other functional units described in this disclosure can be implemented by hardware or software, or a combination of hardware and software. Those skilled in the art will also understand that the above-described multiple modules / units can be combined into one module / unit, and each of the above-described modules / units can be further divided into multiple sub-modules / sub-units.
[0164] In the above detailed description, embodiments have been described with reference to numerous specific details, which may vary depending on the implementation. Certain adaptations and modifications can be made to the embodiments. Other implementations will be readily apparent to those skilled in the art from the specific embodiments disclosed herein. This specification and examples are for illustrative purposes only, and the true scope and essence of the invention are defined by the claims. The sequence of steps shown in the figures is also for illustrative purposes only and is not intended to limit to any particular step or order. Therefore, those skilled in the art will recognize that these steps can be performed in a different order when implementing the same method.
[0165] Exemplary embodiments are disclosed in the figures and detailed description of this application. However, many variations and modifications can be made to these embodiments. Accordingly, although specific terms are used, they are only general and descriptive and not for limiting purposes.
Claims
1. A method for decoding a bitstream to output one or more images of a video sequence, the method comprising: Decoding the bitstream includes: decoding a flag associated with the video sequence, wherein the flag is received in a sequence parameter set (SPS) of the bitstream; Determining the maximum conversion size in units of luminance samples based on the decoded bitstream includes: determining the maximum conversion size in units of luminance samples based on the value of the flag; and Determine whether the coding unit (CU) of the video sequence allows subblock transform (SBT); The determination of whether the SBT is allowed to be used in the CU is based on a comparison between the size of the CU and the maximum conversion size in units of luminance samples.
2. The method according to claim 1, wherein: The flag is sps_max_luma_transform_size_64_flag.
3. The method according to claim 1, further comprising: In response to the value of the flag being 1, the maximum conversion size in units of luminance samples is determined to be equal to 64; or In response to the value of the flag being 0, the maximum conversion size in units of luminance samples is determined to be equal to 32.
4. The method according to claim 1, further comprising: In response to the flag having a first value, the maximum conversion size in units of luminance samples is determined to be equal to a second value; or In response to the flag having a third value, the maximum conversion size in units of luminance samples is determined to be equal to a fourth value.
5. The method according to claim 1, wherein, The comparison between the size of the CU and the maximum conversion size in units of luminance samples includes: The comparison between the width of the CU and the maximum conversion size in units of luminance samples, and The height of the CU is compared with the maximum conversion size in units of luminance samples.
6. The method according to claim 1, further comprising: Determine the maximum allowable CU size for the SBT, the maximum CU size being equal to the maximum transformation size in units of luminance samples.
7. A method for encoding a video sequence into a bitstream, the method comprising: The maximum conversion size in units of luminance samples is determined for the video sequence, and a flag indicating the maximum conversion size in units of luminance samples is encoded in the sequence parameter set (SPS) of the bitstream associated with the video sequence. Determine whether to use Subblock Transform (SBT) for the coding units of the video sequence; in, Whether to use the SBT for the CU is determined by comparing the size of the coding unit (CU) with the maximum conversion size in units of luminance samples.
8. The method according to claim 7, wherein: The flag is sps_max_luma_transform_size_64_flag.
9. The method according to claim 7, further comprising: In response to the maximum conversion size in units of luminance samples being determined to be equal to 64, the value of the flag is set to 1; or In response to the maximum conversion size in units of luminance samples being determined to be equal to 32, the value of the flag is set to 0.
10. The method of claim 7, further comprising: In response to the maximum conversion size in units of luminance samples being determined to be equal to a first value, the flag is set to have a second value; or In response to the maximum conversion size in units of luminance samples being determined to be equal to the third value, the flag is set to have a fourth value.
11. The method of claim 7, wherein the comparison of the size of the CU with the maximum conversion size in units of luminance samples comprises: The comparison between the width of the CU and the maximum conversion size in units of luminance samples, and The height of the CU is compared with the maximum conversion size in units of luminance samples.
12. A non-transitory computer-readable storage medium storing an instruction set and a bitstream associated with a video sequence, the instruction set being executed by one or more processors in a method to generate the bitstream, the method comprising: The maximum transition size in units of luminance samples is determined for the video sequence, and a flag indicating the maximum transition size in units of luminance samples is encoded in the Sequence Parameter Set (SPS) of the bitstream associated with the video sequence; and Determine whether subblock transform (SBT) is allowed for the coding unit (CU) of the video sequence; Specifically, the SBT is determined to be allowed for use in the CU based on a comparison between the size of the CU and the maximum conversion size in units of luminance samples.
13. The non-transitory computer-readable storage medium according to claim 12, characterized in that, The bitstream can be decoded in the following ways: In response to the value of the flag being 1, the maximum conversion size in units of luminance samples is determined to be 64; or In response to the value of the flag being 0, the maximum conversion size in units of luminance samples is determined to be 32.
14. The non-transitory computer-readable storage medium according to claim 12, characterized in that, The bitstream can be decoded in the following ways: In response to the flag having a first value, the maximum conversion size in units of luminance samples is determined to be equal to a second value; or In response to the flag having a third value, the maximum conversion size in units of luminance samples is determined to be equal to a fourth value.