Detector serial image data training method based on high-speed multichannel application

Abstract

The invention relates to the technical field of image data training, in particular to a detector serial image data training method based on high-speed multichannel application, and the method comprises the steps: immediately carrying out the stability detection after the delay value of an iodelay element begins to change, and judging that the sampling is jittered as long as the sampling change occurs; in order to avoid inaccurate detection results caused by superposition of stable count values under different delay values due to system data link delay, a stable counter starts to perform zero clearing when sending is delayed; meanwhile, a preparation state before bit correction is entered in advance before a first delay value is judged, so that the first delay value lasts for a relatively long time, and false detection caused by inconsistency of initial states is avoided; at the end of the detection stage, whether sampling is stable or not is judged according to a count value of a stable counter; in this way, the unstable area can be effectively detected.

Description

Technical Field

[0001] The invention belongs to the technical field of image data training, and in particular relates to a detector serial image data training method based on high-speed multi-channel application. Background Art

[0002] CMOS detectors usually output image data in serial mode. In order to perform bit correction of serial image data and find the best sampling position, iodelay components are usually used. For FPGAs before the Xilinx 7 series, there are many reference clocks for iodelay components, usually with a minimum of 200MHz. When the data rate of the serial image is higher than 400MHz, two transition edge positions can be detected during data transition edge position detection. When the data rate of the serial image is lower than 200Mbps, the transition edge of the serial image data may not be detected.

[0003] For FPGAs of Xilinx7 series and higher levels, during the delay adjustment process of the iodelay element, the unstable delay position may only appear in an unstable sampling state for a short period of time when the delay value changes, and it is difficult to detect the unstable state in the long sampling after a delay period. Using the traditional unstable area detection method, the unstable area will be missed after the delay setting of the iodelay element for a long time, resulting in the risk of sampling errors in the final set sampling position. In addition, for FPGAs of Xilinx6 series and higher levels, the delay value setting of the iodelay element can be increased or decreased based on the current position, and the target value to be set can also be directly loaded, thereby shortening the set delay time. Finally, if the training control pulse and the sampling clock inside the detector are not established and maintained for a long time, especially when the width of the detector control pulse is affected by the rising and falling edge times and is less than the width of a pixel clock cycle, there may be a risk of sampling metastable state or failure to sample the trigger pulse, thereby not outputting the training word. Summary of the invention

[0004] In view of this, the present invention aims to provide a detector serial image data training method based on high-speed multi-channel application, so as to solve the technical problem that the detection timing of the iodelay element is relatively delayed for a long time and then detected again, which will result in unstable area missed detection, thereby causing sampling errors in the final set sampling position.

[0005] To achieve the above object, the technical solution created by the present invention is implemented as follows: A detector serial image data training method based on high-speed multi-channel application includes the following steps: when the detector is in a power-on waiting state, the count value of the cycle counter is incremented from zero, when the count value of the cycle counter reaches the maximum cycle value and the training enable signal is at a high level, the sub-state machine enters a preparatory state before bit correction, at which time the count value of the cycle counter is cleared and incremented from zero and the delay value of the iodelay element is set, when the count value of the cycle counter reaches the maximum cycle value, the sub-state machine enters a bit correction delay state, at which time the count value of the cycle counter is cleared and incremented from zero and the delay value of the iodelay element is set, when the count value of the cycle counter reaches the maximum cycle value, the sub-state machine enters a stable sampling state, at which time the count value of the cycle counter is cleared and incremented from zero, when the count value of the cycle counter reaches the maximum cycle value, the sub-state machine enters In the stable situation judgment state, when the second jump edge is detected and the interval length between the second jump edge and the first jump edge is greater than 1 / 4 of the length of the serial image data or when the number of detections reaches the maximum delay value of the iodelay element, the sub-state machine enters the sampling position calculation state, otherwise the sub-state machine returns to the bit correction delay state; after the sub-state machine enters the sampling position calculation state, the final delay value of the iodelay element is calculated, and then the sub-state machine enters the delay setting state after bit correction, and sets the final delay value of the iodelay element of the current channel, and then the sub-state machine enters the word correction sub-state for word correction training. When the word correction succeeds or the number of word correction failures is the same as the bit width of the serial image data, the sub-state machine enters the channel correction sub-state for word correction training. When the channel correction succeeds or the number of channel correction failures is the same as the bit width of the serial image data, the sub-state machine returns to the power-on waiting state.

[0006] Furthermore, in the preparation state before bit correction, the bit correction delay state, and the delay setting state after bit correction, the delay value of the Iodelay element is set by the delay device and is issued when the count value of the loop counter is zero; wherein the delay value set in the preparation state before bit correction is zero; the first delay value set in the bit correction delay state is the same as the delay value set in the preparation state before bit correction; and the delay value set in the delay setting state after bit correction is the calculated sampling position.

[0007] Furthermore, there are two ways to set the delay value of the delayer. The first setting method is to use a delay reset signal, a delay indication signal and a delay enable signal. The delay indication signal includes a delay increase indication signal and a decrease indication signal. The delay enable signal includes a delay increase enable signal and a delay decrease enable signal. When the delay enable signal is high and the delay indication signal is low, the delay value decreases. When the delay enable signal is high and the delay indication signal is high, the delay value increases. When the delay reset signal is high, the delay value is reset to zero. The second setting method is to use a delay load value signal and a delay load enable signal. When the delay load enable signal is high, the delay value of the delay load value signal is directly written into the delayer.

[0008] Further, in the stable situation judgment state, if the stable state indication signal is at a high level, the sampling is judged to be stable; if the unstable indication signal is at a low level, the sampling is judged to be unstable.

[0009] Furthermore, in the stable sampling state, when the count value of the cycle counter reaches the maximum cycle value, the count value of the stable cycle counter is judged. When the count value of the stable cycle counter is greater than or equal to twice the maximum cycle value of the cycle counter, the stable state indication signal is set to a high level, otherwise the unstable indication signal is set to a high level.

[0010] Furthermore, in the stable situation sampling state, when the count value of the loop counter is zero, the count value of the stable loop counter is set to zero, and under the remaining count values ​​of the stable loop counter, it is determined whether the current sampling value is equal to the current sampling delay value. If they are equal, the count value of the stable loop counter is increased by 1, otherwise the count value of the stable loop counter is set to zero; in the stable situation judgment state, it is determined whether the current sampling value is equal to the current sampling delay value. If they are equal, the count value of the stable loop counter is increased by 1, otherwise the count value of the stable loop counter is set to zero.

[0011] Furthermore, for the timing reset signal of the detector and the other drive control signals, the same driver, the same routing layer and routing length are used on the physical medium layer of the circuit board; in the timing software, the timing reset signal and the other drive control signals operate under the same clock control so that the positions of the transition edges are aligned.

[0012] Compared with the prior art, the invention can achieve the following beneficial effects: 1. A more stringent sampling instability detection strategy is adopted in the detection algorithm, that is, stability detection is performed immediately after the delay value of the iodelay element begins to change. As long as there is a sampling change, it is determined that the sampling has jitter. In order to avoid the system data link delay causing the stable count values ​​under different delay values ​​to be superimposed together and resulting in inaccurate detection results, the stable counter begins to be cleared when the delay is sent; at the same time, before the first delay value is judged, the pre-bit correction preparation state is entered in advance, so that the first delay value lasts for a longer time to avoid false detection due to inconsistency in the initial state; at the end of the detection stage, the sampling is determined to be stable by the count value of the stable counter; in this way, the unstable area can be effectively detected.

[0013] 2. For the delay setting of the delayer, the expected delay value is reached by directly loading the delay value in one step, rather than resetting the delayer first and then increasing the tap position one by one, which requires (expected delay value + 1) steps to reach the expected delay value. This can reduce the adjustment time of the delayer and improve timeliness.

[0014] 3. In view of the fact that high-speed signals may be affected by timing and transmission links during transmission, resulting in sampling metastable states and unstable operation, the timing reset signal of the detector and the other drive control signals including the training control signal use the same driver, the same routing layer and routing length on the physical medium layer of the circuit board; in the timing software, the timing reset signal and the other drive control signals work under the same clock control to ensure that the positions of the jump edges are aligned, thereby ensuring that the internal sampling of the detector has sufficient setup and hold time. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The drawings constituting part of the present invention are used to provide a further understanding of the present invention. The exemplary embodiments and descriptions of the present invention are used to explain the present invention and do not constitute an improper limitation on the present invention. In the drawings: Figure 1 is a schematic diagram of a loop of a sub-state machine for per-channel correction according to an embodiment of the invention; Figure 2 Schematic diagram of two ways of setting the delay value of the delayer according to an embodiment of the invention. DETAILED DESCRIPTION

[0016] In order to make the purpose, technical solution and advantages of the invention more clear, the invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described here are only used to explain the invention and do not constitute a limitation of the invention.

[0017] It should be noted that, in the absence of conflict, the embodiments of the present invention and the features in the embodiments may be combined with each other.

[0018] In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside" and the like indicate positions or positional relationships based on the positions or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present invention. In addition, the terms "first", "second", etc. are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, features defined as "first", "second", etc. may explicitly or implicitly include one or more of the features. In the description of the present invention, unless otherwise specified, "multiple" means two or more.

[0019] In the description of the invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installation", "connection" and "connection" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in the invention can be understood according to specific circumstances.

[0020] The present invention will be described in detail below with reference to the drawings and in combination with embodiments.

[0021] like Figure 1 and Figure 2 As shown, the present invention provides a detector serial image data training method based on high-speed multi-channel application, comprising the following steps: Before the detector is powered on or after training is completed, it is in the power-on waiting state. When the detector is in the power-on waiting state, the count value of the cycle counter starts to increase from zero. When the count value of the cycle counter reaches the maximum cycle value and the training enable signal is at a high level, the sub-state machine enters the preparatory state before bit correction. After the sub-state machine enters the preparatory state before bit correction, the count value of the cycle counter is cleared and starts to increase from zero and the delay value of the iodelay element is set. When the count value of the cycle counter reaches the maximum cycle value, the sub-state machine enters the bit correction delay state. After the sub-state machine enters the bit correction delay state, the count value of the cycle counter is cleared and starts to increase from zero and the delay value of the iodelay element is set. When the count value of the cycle counter reaches the maximum cycle value, the sub-state machine enters the stable situation sampling state. After the sub-state machine enters the stable situation sampling state, the count value of the cycle counter is cleared and starts to increase from zero. When the count value of the cycle counter reaches the maximum cycle value, the sub-state machine enters the stable situation sampling state. , the sub-state machine enters the stable situation judgment state. When the second jump edge is detected and the interval length between the second jump edge and the first jump edge is greater than 1 / 4 of the serial image data length or when the number of detections reaches the maximum delay value of the iodelay element, the sub-state machine enters the sampling position calculation state, otherwise the sub-state machine returns to the bit correction delay state; after the sub-state machine enters the sampling position calculation state, the final delay value of the iodelay element is calculated, and then the sub-state machine enters the delay setting state after bit correction. After the sub-state machine enters the delay setting state after bit correction, the final delay value of the iodelay element of the current channel is set, and then the sub-state machine enters the word correction sub-state for word correction training. When the word correction succeeds or the number of word correction failures is the same as the bit width of the serial image data, the sub-state machine enters the channel correction sub-state for word correction training. When the channel correction succeeds or the number of channel correction failures is the same as the bit width of the serial image data, the sub-state machine returns to the power-on waiting state.

[0022] The delay operation of the Iodelay element is only performed in the preparation state before bit correction, the bit correction delay state, and the delay setting state after bit correction. Specifically, the delay value of the Iodelay element is set by the delay device, and it is issued when the count value of the loop counter in the three states is zero; among them, the delay value set in the preparation state before bit correction is zero, which means setting an initial delay value. The initial delay value can select any value in the delay value of the Iodelay element. The initial delay value represents the nominal starting point. When the delay value is set to zero, the corresponding delay time length is equal to the number of delay steps (tap number) multiplied by the length of a single step, which is convenient for statistical calculation. ; The delay value set in the bit correction delay state is various possible delay values, but the first delay value set is the same as the delay value set in the preparation state before the bit correction, ensuring that the delay value does not change during the transition from the preparation state before the bit correction to the bit correction delay state; The delay value set in the delay setting state after the bit correction is the calculated sampling position, for example: if two unstable areas are detected, the sampling position is set to the midpoint of the two unstable areas; if no unstable area is detected, the sampling position is set to the midpoint of the entire delay value; if an unstable area is detected, the sampling position is set to half the edge offset data length relative to the unstable area.

[0023] There are two ways to set the delay value of the delayer. The first setting method is to use a delay reset signal, a delay indication signal and a delay enable signal. The delay indication signal includes a delay increment indication signal and a decrement indication signal. The delay enable signal includes a delay increment enable signal and a delay decrement enable signal. When the delay enable signal is high and the delay indication signal is low, the delay value decreases. When the delay enable signal is high and the delay indication signal is high, the delay value increases. When the delay reset signal is high, the delay value is reset to zero. The second setting method is to use a delay load value signal and a delay load enable signal. When the delay load enable signal is high, the delay value of the delay load value signal is directly written into the delayer, saving time to adjust to the target delay value and improving the adjustment efficiency. The second setting method is preferably used.

[0024] In the stable situation judgment state, if the stable state indication signal is at a high level, the sampling is judged to be stable; if the unstable indication signal is at a low level, the sampling is judged to be unstable.

[0025] The basis for judging whether the stable state indication signal and the unstable indication signal are stable is as follows: in the stable sampling state, when the count value of the cycle counter reaches the maximum cycle value, the count value of the stable cycle counter is judged; when the count value of the stable cycle counter is greater than or equal to 2 times the maximum cycle value of the cycle counter, the stable state indication signal is set to a high level; otherwise, the unstable indication signal is set to a high level.

[0026] In the stable situation sampling state, when the count value of the loop counter is zero, the count value of the stable loop counter is set to zero. Under the remaining count values ​​of the stable loop counter, it is determined whether the current sampling value is equal to the current sampling delay value. If they are equal, the count value of the stable loop counter is increased by 1, otherwise the count value of the stable loop counter is set to zero; in the stable situation judgment state, it is determined whether the current sampling value is equal to the current sampling delay value. If they are equal, the count value of the stable loop counter is increased by 1, otherwise the count value of the stable loop counter is set to zero.

[0027] The solution to the problem that high-speed signals may be affected by timing and transmission links during transmission, resulting in sampling metastable states and unstable operation, is to use the same driver, the same routing layer and routing length for the detector's timing reset signal and the remaining drive control signals (including training control signals) on the physical medium level of the circuit board; in the timing software, the timing reset signal and the remaining drive control signals operate under the same clock control to ensure that the positions of the transition edges are aligned, thereby ensuring that the internal sampling of the detector has sufficient setup and hold time, avoiding the risk of sampling metastable states or failing to sample the trigger pulse and thus not outputting the training word.

[0028] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps described in the disclosure of the present invention can be performed in parallel, sequentially or in different orders, as long as the desired results of the technical solution disclosed in the present invention can be achieved, and this document does not limit this.

[0029] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A detector serial image data training method based on high-speed multi-channel application, characterized in that: The steps include: When the detector is in the power-on waiting state, the count value of the cycle counter starts to increase from zero. When the count value of the cycle counter reaches the maximum cycle value and the training enable signal is at a high level, the sub-state machine enters the preparation state before bit correction. At this time, the count value of the cycle counter is cleared and starts to increase from zero and the delay value of the iodelay element is set. When the count value of the cycle counter reaches the maximum cycle value, the sub-state machine enters the bit correction delay state. At this time, the count value of the cycle counter is cleared and starts to increase from zero and the delay value of the iodelay element is set. When the count value of the cycle counter reaches the maximum cycle value, the sub-state machine enters the stable situation sampling state. At this time, the count value of the cycle counter is cleared and starts to increase from zero. When the count value of the cycle counter reaches the maximum cycle value, the sub-state machine enters the stable situation judgment state. When the second jump is detected, When the interval length between the second jump edge and the first jump edge is greater than 1 / 4 of the length of the serial image data or when the number of detections reaches the maximum delay value of the iodelay element, the sub-state machine enters the state of calculating the sampling position, otherwise the sub-state machine returns to the state of bit correction delay; after the sub-state machine enters the state of calculating the sampling position, the final delay value of the iodelay element is calculated, and then the sub-state machine enters the state of delay setting after bit correction, sets the final delay value of the iodelay element of the current channel, and then the sub-state machine enters the word correction sub-state for word correction training. When the number of word correction successes or word correction failures is the same as the bit width of the serial image data, the sub-state machine enters the channel correction sub-state for word correction training. When the number of channel correction successes or channel correction failures is the same as the bit width of the serial image data, the sub-state machine returns to the power-on waiting state.

2. The detector serial image data training method based on high-speed multi-channel application according to claim 1 is characterized in that: In the preparation state before bit correction, the bit correction delay state, and the delay setting state after bit correction, the delay value of the Iodelay element is set by the delayer and is issued when the count value of the loop counter is zero; wherein the delay value set in the preparation state before bit correction is zero; the first delay value set in the bit correction delay state is the same as the delay value set in the preparation state before bit correction; the delay value set in the delay setting state after bit correction is the calculated sampling position.

3. The detector serial image data training method based on high-speed multi-channel application according to claim 2, characterized in that: There are two ways to set the delay value of the delayer. The first setting method is to use a delay reset signal, a delay indication signal and a delay enable signal. The delay indication signal includes a delay increase indication signal and a decrease indication signal. The delay enable signal includes a delay increase enable signal and a delay decrease enable signal. When the delay enable signal is high and the delay indication signal is low, the delay value decreases. When the delay enable signal is high and the delay indication signal is high, the delay value increases. When the delay reset signal is high, the delay value is reset to zero. The second setting method is to use a delay load value signal and a delay load enable signal. When the delay load enable signal is high, the delay value of the delay load value signal is directly written into the delayer.

4. The detector serial image data training method based on high-speed multi-channel application according to claim 1, characterized in that: In the stable situation judgment state, if the stable state indication signal is at a high level, the sampling is judged to be stable; if the unstable indication signal is at a low level, the sampling is judged to be unstable.

5. The detector serial image data training method based on high-speed multi-channel application according to claim 4, characterized in that: In the stable sampling state, when the count value of the cycle counter reaches the maximum cycle value, the count value of the stable cycle counter is judged. When the count value of the stable cycle counter is greater than or equal to twice the maximum cycle value of the cycle counter, the stable state indication signal is set to a high level, otherwise the unstable indication signal is set to a high level.

6. The detector serial image data training method based on high-speed multi-channel application according to claim 5, characterized in that: In the stable situation sampling state, when the count value of the loop counter is zero, the count value of the stable loop counter is set to zero. Under the remaining count values ​​of the stable loop counter, it is determined whether the current sampling value is equal to the current sampling delay value. If they are equal, the count value of the stable loop counter is increased by 1, otherwise the count value of the stable loop counter is set to zero; in the stable situation judgment state, it is determined whether the current sampling value is equal to the current sampling delay value. If they are equal, the count value of the stable loop counter is increased by 1, otherwise the count value of the stable loop counter is set to zero.

7. The detector serial image data training method based on high-speed multi-channel application according to claim 1, characterized in that: For the timing reset signal of the detector and the other drive control signals, the same driver, the same routing layer and routing length are used on the physical medium layer of the circuit board; in the timing software, the timing reset signal and the other drive control signals work under the same clock control so that the positions of the jump edges are aligned.

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