Three-dimensional memory, manufacturing method thereof and electronic equipment

Abstract

The invention relates to a three-dimensional memory, a manufacturing method thereof and electronic equipment. The manufacturing method of the three-dimensional memory comprises the following steps: alternately forming insulating layers and sacrificial layers along a third direction to form a laminated structure, and dividing the laminated structure into a transistor preset region, a capacitor preset region and a bit line preset region; forming a dummy transistor in the transistor preset area and forming a dummy capacitor in the capacitor preset area; replacing the material of the sacrificial layer with a conductive material to form each conductive layer; removing the dummy transistor to form a transistor comprising a preset semiconductor layer, a gate insulating layer and a gate; removing the dummy capacitor; oppositely etching the insulating layers from the bit line preset area and the capacitor preset area along the first direction; and etching is continued to remove the preset semiconductor layer corresponding to each insulating layer until the preset semiconductor layer reaches the position of the gate insulating layer, so that the preset semiconductor layer is disconnected at the insulating layer along the third direction, and a semiconductor layer is formed. According to the manufacturing process, the parasitic channel can be easily and rapidly removed.

Description

Technical Field

[0001] The present disclosure relates to but is not limited to semiconductor technology, and in particular to a three-dimensional memory and a manufacturing method thereof, and an electronic device. Background Art

[0002] With the development of integrated circuit technology, the critical dimensions of devices are shrinking, and the types and numbers of devices contained in a single chip are increasing accordingly, so that any slight difference in process production may affect device performance.

[0003] In order to reduce the cost of products as much as possible, people hope to make as many device units as possible on a limited substrate. Since the advent of Moore's Law, the industry has proposed various semiconductor structure designs and process optimizations to meet people's needs for current products. Summary of the invention

[0004] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of protection of the present disclosure.

[0005] In one aspect, some embodiments of the present disclosure provide a method for manufacturing a three-dimensional memory, comprising the following steps:

[0006] Alternatingly forming insulating layers and sacrificial layers along a third direction perpendicular to the substrate to form a stacked structure, dividing the stacked structure into a bit line preset region, a transistor preset region, and a capacitor preset region arranged along a first direction, the first direction being parallel to the substrate;

[0007] forming a dummy transistor in the transistor preset region and forming a dummy capacitor in the capacitor preset region;

[0008] Replacing the material of the sacrificial layer with a conductive material to form each conductive layer;

[0009] removing the dummy transistor;

[0010] forming a predetermined semiconductor layer, a gate insulating layer and a word line;

[0011] removing the dummy capacitor;

[0012] At the same time, the insulating layers and the preset semiconductor layers are removed from the bit line preset area and the capacitor preset area in opposite directions along the first direction until the etching reaches the position of the gate insulating layer, so that the preset semiconductor layer is disconnected at each insulating layer along the third direction to form semiconductor layers disconnected from each other.

[0013] In an exemplary embodiment, forming a dummy transistor and a dummy capacitor includes:

[0014] forming a transistor hole in the transistor preset region and a capacitor hole in the capacitor preset region, wherein the transistor hole and the capacitor hole are arranged along a first direction;

[0015] Depositing an insulating material film on the bottom wall and side wall of the transistor hole and the capacitor hole to form a protective layer;

[0016] A protection layer of a material to be replaced is deposited to cover the transistor hole and the capacitor hole to form the dummy transistor and the dummy capacitor, respectively.

[0017] In an exemplary embodiment, forming each conductive layer includes:

[0018] forming a plurality of first trenches extending along the first direction and penetrating the stacked structure in the stacked structure, wherein the first trenches separate two adjacent dummy transistors in the second direction and separate two adjacent dummy capacitors in the second direction;

[0019] Etching away the sacrificial layer along the second direction by means of the first groove to form a plurality of empty grooves;

[0020] The plurality of empty grooves are filled with a conductive material to form each of the conductive layers.

[0021] In an exemplary embodiment, the method further includes forming a transistor, and before forming the transistor, the method further includes the following steps:

[0022] Filling the first trench in the preset area of ​​the capacitor with an insulating material to form a first isolation layer;

[0023] In the transistor preset area, etching each of the conductive layers along the second direction by means of the first trench until reaching the position of the dummy transistor to form a second trench;

[0024] In a preset region of the transistor, the first trench and the second trench are filled with an insulating material different from that of the first isolation layer to form the second isolation layer;

[0025] In the second direction, a size of the second isolation layer between adjacent dummy transistors is greater than a size of the first isolation layer between adjacent dummy capacitors.

[0026] In an exemplary embodiment, the steps of forming a transistor include:

[0027] In the transistor preset area, removing the dummy transistor and the protection layer to expose the sidewall of the conductive layer along the third direction to form a third trench;

[0028] Etching each insulating layer along the first direction by means of the third trench to expose the upper surface and the lower surface of the conductive layer and the sidewall of the insulating layer along the third direction, thereby forming a fourth trench;

[0029] Depositing a semiconductor material film along the exposed upper and lower surfaces of the conductive layer and the exposed sidewalls of the insulating layer and the conductive layer along the third direction to form a predetermined semiconductor layer of the transistor;

[0030] Depositing a gate insulating layer film to cover the preset semiconductor layer to form a gate insulating layer;

[0031] A conductive material is filled to cover the gate insulating layer to form a gate.

[0032] In an exemplary embodiment, the method of disconnecting the predetermined semiconductor layer at each insulating layer along the third direction comprises the following steps:

[0033] In the capacitor preset area, removing the dummy capacitor and the protection layer to form a fifth trench;

[0034] By means of the fifth trench, each insulating layer is laterally etched along the first direction to expose the semiconductor layer at each insulating layer, thereby forming a sixth trench;

[0035] In the bit line preset region, each insulating layer is laterally etched along the first direction to expose the semiconductor layer at each insulating layer to form a seventh trench;

[0036] At the same time, with the help of the sixth groove and the seventh groove, at the insulating layer, the semiconductor layer is etched away simultaneously along both sides of the annular semiconductor layer until it reaches the position of the gate insulating layer and stops, so that in the third direction, the semiconductor layer is disconnected at each insulating layer.

[0037] In an exemplary embodiment, after forming the dummy transistor, the following steps are further included:

[0038] In the capacitor preset area, removing the dummy capacitor to form an eighth groove;

[0039] By means of the eighth groove, the sacrificial layer is etched along the first direction, so that the sacrificial layer is more concave than the adjacent insulating layer in the first direction, thereby forming a ninth groove;

[0040] Depositing a first conductive material in the eighth and ninth grooves to form a first electrode of the capacitor;

[0041] Continue filling the material to be replaced, filling the ninth groove completely and only partially filling the eighth groove;

[0042] The material to be replaced is etched and the first conductive material on the sidewall of the eighth trench is etched away at the same time, so that the first electrodes of capacitors at different layers are disconnected.

[0043] On the other hand, some embodiments of the present disclosure provide a three-dimensional memory, comprising a substrate, and a plurality of memory cells stacked at intervals in a third direction perpendicular to the substrate, each layer of memory cells comprising at least two memory cells arranged at intervals in a second direction and extending along a first direction, the memory cells comprising at least one transistor, the first direction intersecting the second direction and both perpendicular to the third direction;

[0044] It also includes a word line and a gate insulating layer extending along a third direction, and a semiconductor layer located on a side of the gate insulating layer away from the word line, wherein the semiconductor layer is disconnected between two adjacent layers of memory cells, and the semiconductor layer serves as an active layer of the transistor; the gate insulating layer has an isolation portion between two adjacent layers of memory cells, and the isolation portion separates the semiconductor layers of the two adjacent layers of memory cells.

[0045] In an exemplary embodiment, the memory cell includes a transistor and a capacitor arranged along a first direction; in a plane passing through a layer of memory cells and parallel to the substrate, an isolation layer is included between the two memory cells, the isolation layer includes a first isolation layer between two adjacent capacitors in a second direction and a second isolation layer between two adjacent transistors in the second direction, the first isolation layer includes a material different from that of the second isolation layer.

[0046] In an exemplary embodiment, a dimension of the first isolation layer along the second direction is smaller than a dimension of the second isolation layer along the second direction.

[0047] In an exemplary embodiment, a material of the first isolation layer includes silicon oxide, and a material of the second isolation layer includes silicon nitride.

[0048] In an exemplary embodiment, in a plane passing through a region between two adjacent layers of memory cells and parallel to the substrate, a first isolation layer and a second isolation layer are provided between two adjacent gate insulating layers in the second direction.

[0049] In an exemplary embodiment, the first isolation layer is in contact with the gate insulating layer, and the second isolation layer is located on a side of the first isolation layer away from the gate insulating layer.

[0050] In an exemplary embodiment, transistors of each memory cell vertically stacked along the third direction are connected to the same word line, and a gate of the transistor is a part of the connected word line.

[0051] In another aspect, some embodiments of the present disclosure provide an electronic device.

[0052] The present application opens the capacitor region and the bit line region, and etches the insulating layer in a first direction to connect the insulating layer with the semiconductor layer of the transistor (i.e., the location of the parasitic channel), then removes the insulating layer surrounding the semiconductor layer, and finally removes the semiconductor layer. The method provided by the present application etches in a direction along the annular parasitic channel, which is equivalent to an etching depth of only 1 / 4 of the distance of the annular parasitic channel, thereby easily achieving the removal of the parasitic channel material.

[0053] The present application removes parasitic channels along the bit line direction and the capacitor direction, so that the space between adjacent memory cells in the second direction does not need to be very large, thereby reducing the size of a single memory cell and significantly improving the storage density of the memory cell.

[0054] This application removes parasitic channels from opposite sides. Under the premise of the same transistor size, the difficulty of wet etching is greatly reduced, the aspect ratio is reduced by half, and the acid is easier to enter, which can ensure the effective removal of parasitic channels around the same layer of devices. For a three-dimensional stacked memory architecture, it can ensure that each layer of devices is etched evenly and the structural morphology is intact.

[0055] Other features and advantages of the present application will be described in the following description, and partly become apparent from the description, or be understood by implementing the present application. Other advantages of the present application can be realized and obtained by the schemes described in the description and the drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0056] The accompanying drawings are used to provide an understanding of the technical solution of the present application and constitute a part of the specification. They are preferred implementation modes and are used together with the embodiments of the present application to explain the technical solution of the present application, but do not constitute a limitation on the technical solution of the present application.

[0057] Figure 1A A schematic diagram of a three-dimensional structure of a three-dimensional memory provided for some embodiments of the present application, with the storage unit exposed;

[0058] Figure 1B A schematic diagram of a three-dimensional structure of a three-dimensional memory provided in some embodiments of the present application, wherein an insulating layer between two adjacent layers of memory cells is exposed;

[0059] Figure 1C for Figure 1A A schematic top view of the structure shown;

[0060] Figure 1D for Figure 1B A schematic top view of the structure shown;

[0061] Figure 1E For along Figure 1A A cross-sectional view perpendicular to the substrate taken along the cross-sectional line AA' in the structure shown;

[0062] Figure 1F For along Figure 1A A cross-sectional view perpendicular to the substrate taken along the cross-sectional line BB' in the structure shown;

[0063] Figure 2 A schematic vertical cross-sectional view of a method for manufacturing a three-dimensional memory provided in some embodiments of the present application, taken along a plane perpendicular to a substrate and parallel to a first direction after forming a stacked structure including an insulating layer and a sacrificial layer;

[0064] Figure 3A A schematic horizontal cross-sectional view of an intermediate product obtained in an intermediate step of a method for manufacturing a three-dimensional memory provided in some embodiments of the present application, taken along a plane parallel to a substrate;

[0065] Figure 3B For along Figure 3A A schematic cross-sectional view perpendicular to the substrate taken along the cross-sectional line AA';

[0066] Figure 4A A schematic horizontal cross-sectional view of an intermediate product obtained in an intermediate step of a method for manufacturing a three-dimensional memory provided in some embodiments of the present application, taken along a plane parallel to a substrate;

[0067] Figure 4B For along Figure 4A A schematic cross-sectional view perpendicular to the substrate taken along the cross-sectional line AA';

[0068] Figure 4C For along Figure 4A A schematic cross-sectional view perpendicular to the substrate taken along the cross-sectional line BB';

[0069] Figure 5A A schematic horizontal cross-sectional view of an intermediate product obtained in an intermediate step of a method for manufacturing a three-dimensional memory provided in some embodiments of the present application, taken along a plane parallel to a substrate;

[0070] Figure 5B For along Figure 5A A schematic cross-sectional view perpendicular to the substrate taken along the cross-sectional line BB';

[0071] Fig. 6A A schematic horizontal cross-sectional view of an intermediate product obtained in an intermediate step of a method for manufacturing a three-dimensional memory provided in some embodiments of the present application, taken along a plane parallel to a substrate;

[0072] Figure 6B For along Fig. 6A A schematic cross-sectional view perpendicular to the substrate taken along the cross-sectional line BB';

[0073] Figure 7A schematic vertical cross-sectional view of an intermediate product obtained in an intermediate step of a method for manufacturing a three-dimensional memory provided in some embodiments of the present application, taken along a plane perpendicular to the substrate and parallel to the first direction;

[0074] Fig. 8A A schematic horizontal cross-sectional view of an intermediate product obtained in an intermediate step of a method for manufacturing a three-dimensional memory provided in some embodiments of the present application, taken along a plane parallel to a substrate;

[0075] Figure 8B For along Fig. 8A A schematic cross-sectional view perpendicular to the substrate taken along the cross-sectional line AA';

[0076] Figure 8C For along Fig. 8A A schematic cross-sectional view perpendicular to the substrate taken along the cross-sectional line BB';

[0077] Fig. 9 A schematic vertical cross-sectional view of an intermediate product obtained in an intermediate step of a method for manufacturing a three-dimensional memory provided in some embodiments of the present application, taken along a plane perpendicular to the substrate and parallel to the first direction;

[0078] Fig. 10A A schematic vertical cross-sectional view of an intermediate product obtained in an intermediate step of a method for manufacturing a three-dimensional memory provided in some embodiments of the present application, taken along a plane perpendicular to the substrate and parallel to the first direction;

[0079] Fig. 10B A schematic vertical cross-sectional view of an intermediate product obtained in an intermediate step of a method for manufacturing a three-dimensional memory provided in some embodiments of the present application, taken along a plane perpendicular to the substrate and parallel to the second direction;

[0080] Fig.11A A schematic vertical cross-sectional view of an intermediate product obtained in an intermediate step of a method for manufacturing a three-dimensional memory provided in some embodiments of the present application, taken along a plane perpendicular to the substrate and parallel to the first direction;

[0081] Fig. 11B A schematic vertical cross-sectional view of an intermediate product obtained in an intermediate step of a method for manufacturing a three-dimensional memory provided in some embodiments of the present application, taken along a plane perpendicular to the substrate and parallel to the second direction;

[0082] Fig. 12A A schematic vertical cross-sectional view of an intermediate product obtained in an intermediate step of a method for manufacturing a three-dimensional memory provided in some embodiments of the present application, taken along a plane perpendicular to the substrate and parallel to the first direction;

[0083] Fig. 12BA vertical cross-sectional schematic diagram of an intermediate product obtained in an intermediate step of a method for manufacturing a three-dimensional memory provided in some embodiments of the present application, taken along a plane perpendicular to the substrate and parallel to the second direction; and

[0084] Figures 13A-13F A schematic vertical cross-sectional view of an intermediate product obtained in an intermediate step of another method for manufacturing a three-dimensional memory provided in some embodiments of the present application, taken along a plane perpendicular to a substrate and parallel to a first direction. DETAILED DESCRIPTION

[0085] In order to make the purpose, technical solution and advantages of the present application more clear, the embodiments of the present application will be described in detail below with reference to the accompanying drawings. It should be noted that the embodiments and features in the embodiments of the present application can be combined with each other arbitrarily without conflict.

[0086] The embodiments herein can be implemented in a plurality of different forms. A person skilled in the art can easily understand the fact that the implementation and content can be transformed into various forms without departing from the purpose and scope of the present application. Therefore, the present application should not be interpreted as being limited to the contents recorded in the following embodiments. In the absence of conflict, the embodiments in the present application and the features in the embodiments can be combined arbitrarily with each other.

[0087] The proportions of the drawings in this application can be used as a reference in the actual process, but are not limited to this. For example, the aspect ratio of the semiconductor layer, the thickness and spacing of each film layer can be adjusted according to actual needs. The drawings described in this application are only schematic diagrams of the structure, and one embodiment of this application is not limited to the shapes or values ​​shown in the drawings.

[0088] In this specification, for the sake of convenience, the words and phrases indicating the orientation or positional relationship such as "middle", "upper", "lower", "front", "back", "vertical", "horizontal", "top", "bottom", "inside", "outside" and the like are used to illustrate the positional relationship of the constituent elements with reference to the drawings. This is only for the convenience of describing this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore cannot be understood as a limitation on this application. The positional relationship of the constituent elements is appropriately changed according to the direction in which each constituent element is described. Therefore, it is not limited to the words and phrases described in the specification and can be appropriately replaced according to the situation.

[0089] In this specification, unless otherwise clearly specified and limited, the terms "disposed" and "connected" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate, or the internal communication of two elements. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0090] In the description of the present application, ordinal numbers such as "first" and "second" are provided to avoid confusion among constituent elements rather than to limit the quantity.

[0091] In this specification, "film" and "layer" may be interchanged. For example, "metal layer" may be replaced with "metal film" in some cases.

[0092] In the description of the present application, a transistor refers to an element including at least three terminals: a gate, a drain, and a source. The transistor has a channel layer between the drain (drain terminal, drain region, or drain) and the source (source terminal, source region, or source), and current can flow through the drain, the channel layer, and the source. In the present application, the channel layer refers to the area where the current mainly flows. In the present application, the terms "metal oxide semiconductor channel", "channel layer", and "semiconductor layer" are interchangeable.

[0093] The architecture design of three-dimensional memories in related technologies, such as 3D DRAM, usually has problems of a large number of parasitic capacitors and parasitic MOS.

[0094] Therefore, the present application provides a method for manufacturing a three-dimensional memory to easily manufacture a memory without or with reduced parasitic capacitance and parasitic MOS.

[0095] Therefore, the manufacturing method of the three-dimensional memory provided in the present application includes the following steps: alternately forming insulating layers and sacrificial layers along a third direction perpendicular to the substrate to form a stacked structure, dividing the stacked structure into a bit line preset area, a transistor preset area and a capacitor preset area arranged along a first direction, the first direction being parallel to the substrate; forming a dummy transistor in the transistor preset area and forming a dummy capacitor in the capacitor preset area; replacing the material of the sacrificial layer with a conductive material to form each conductive layer; removing the dummy transistor; forming a preset semiconductor layer, a gate insulating layer and a word line; removing the dummy capacitor; and simultaneously etching away each insulating layer and the preset semiconductor layer from the bit line preset area and the capacitor preset area in the first direction toward each other until the etching is stopped at the position of the gate insulating layer, so that the preset semiconductor layer is disconnected at each insulating layer along the third direction to form mutually disconnected semiconductor layers.

[0096] As used in the embodiments of the present disclosure, the term "first direction" X is defined as the arrangement direction of the capacitors and transistors; the term "second direction" Y is defined as a direction that intersects the "first direction" X and is parallel to the direction in which the bit lines extend; the term "third direction" Z is defined as a direction perpendicular to the plane where the substrate is located, that is, a direction parallel to the direction in which the word lines extend; the plane formed by the first direction X and the second direction Y is parallel to the substrate. The "first direction" X, the "second direction" Y, and the "third direction" Z can be as follows: Figure 1A-1F As shown in the following table.

[0097] As used in this application, the term "an integrated structure" may refer to the fact that there is no obvious boundary interface such as a fault or gap between A and B in the microstructure. Generally, a film layer patterned to form a connection is an integrated structure. For example, A and B are formed into a film layer using the same material and are simultaneously formed into a structure having a connection relationship through the same patterning process.

[0098] like Figure 1A-1F As shown, some embodiments of the present application provide a three-dimensional memory that may include a substrate 10, and a plurality of layers of memory cells stacked at intervals in a third direction Z perpendicular to the substrate 10, each layer of memory cells including at least two memory cells arranged at intervals in a second direction Y and extending along a first direction X, and the memory cells including at least one transistor.

[0099] In some embodiments, the memory cell may include a transistor and a capacitor.

[0100] In the present application, the storage unit may be 2T0C, 1T0C, etc. in addition to 1T1C.

[0101] Continue to refer Figure 1C , Figure 1C The transistor region and capacitor region are shown as being roughly bounded by the dashed line II-I' and the transistor region and bit line region are shown as being roughly bounded by the dashed line II-II'. Figure 1C A first source / drain 71 and a second source / drain 72 are shown on both sides of the semiconductor layer 61 along the first direction X. The first source / drain 71 may be connected to the first electrode 70 of the capacitor, and the second source / drain 72 may be connected to the bit line 80 .

[0102] Figure 1CIt is also shown that at each conductive layer, the conductive layer refers to a film layer including a first source / drain 71 and a second source / drain 72. A first isolation layer 31 may be included between two adjacent capacitors in the second direction Y, and a second isolation layer 32 may be included between two adjacent transistors in the second direction Y. The first isolation layer 31 may include a material different from that of the second isolation layer 32. In some embodiments, the material of the first isolation layer 31 may include silicon oxide, etc., and the material of the second isolation layer 32 may include silicon nitride, etc., but not silicon oxide. Compared with silicon oxide, silicon nitride has a better effect of reducing the parasitic capacitance between the bit line and the semiconductor. Moreover, the isolation layer formed by the two materials has a better isolation effect, which can further reduce the leakage between adjacent semiconductor layers.

[0103] Figure 1C It is also shown that the dimension L1 of the first isolation layer 31 along the second direction is smaller than the dimension L2 of the second isolation layer 32 along the second direction. Some embodiments of the present disclosure can reduce the contact area between the bit line and the source and drain of the transistor by making the dimension L1 of the first isolation layer along the second direction smaller than the dimension L2 of the second isolation layer along the second direction, thereby reducing the parasitic capacitance between the two.

[0104] Figure 1D It is shown that at each insulating layer, the insulating layer refers to a film layer adjacent to the conductive layer and does not include the first source / drain 71 and the second source / drain 72. A first isolation layer 31 is included between two adjacent capacitors in the second direction Y, and a second isolation layer 32 is included between two adjacent transistors in the second direction Y. The first isolation layer 31 includes a material different from that of the second isolation layer 32, but the size L1 of the first isolation layer 31 along the second direction between the two adjacent capacitors is greater than or equal to the size L2 of the second isolation layer 32 along the second direction between the two adjacent transistors. There is also a first isolation layer 31 between the transistor and the second isolation layer 32; by arranging the first isolation layer 31 between the transistor and the second isolation layer 32, the two isolation layers between adjacent transistors are made of different materials, thereby effectively reducing the parasitic capacitance between the bit line and the transistor and the parasitic capacitance between the word line and the capacitor. In addition, arranging the first isolation layer 31, such as silicon oxide, between the channels of two adjacent layers of storage cells can provide a better isolation effect and avoid leakage.

[0105] refer to Figure 1E and Figure 1FThe three-dimensional memory of the present application may also include a word line 90 and a gate insulating layer 62 extending along a third direction Z, and a semiconductor layer 61 located on a side of the gate insulating layer away from the word line; the semiconductor layer 61 is disconnected between two adjacent layers of memory cells, and the semiconductor layer 61 can be used as an active layer of the transistor; the gate insulating layer 62 has an isolation portion 620 between two adjacent layers of memory cells, and the isolation portion 620 separates the semiconductor layer 61 of the two adjacent layers of memory cells. The isolation portion can isolate adjacent semiconductor layers, thereby avoiding semiconductor layer connection and reducing leakage; the present application can reduce the etching of the gate insulating layer by removing the semiconductor layer from the bit line preset area and the capacitor preset area in opposite directions, thereby forming the isolation portion.

[0106] in addition, Figure 1E It is shown that the first source / drain 71 and the second source / drain 72 can be made of a double-layer composite material, that is, the core can be metal tungsten, and then a layer of TiN is wrapped outside. However, in some other embodiments, the first source / drain 71 and the second source / drain 72 can also be formed of only one conductive material, such as metal tungsten, TiN, polysilicon, etc.

[0107] The structure of the three-dimensional memory of the present application can reduce the parasitic capacitance between the bit lines, capacitors and word lines, and can also help remove the parasitic channels.

[0108] The technical solution of the present application is further explained below through the manufacturing process of the memory of some embodiments of the present application. The "patterning process" mentioned in some embodiments of the present application includes deposition of film layers, coating of photoresist, mask exposure, development, etching, stripping of photoresist and other processes, which are mature manufacturing processes in the relevant technology. The "photolithography process" mentioned in some embodiments of the present application includes coating of film layers, mask exposure and development, which are mature manufacturing processes in the relevant technology. Deposition can adopt known processes such as sputtering, evaporation, chemical vapor deposition, coating can adopt known coating processes, and etching can adopt known methods, which are not specifically limited here. In the description of some embodiments of the present application, it should be understood that "thin film" refers to a thin film made of a certain material on a substrate using a deposition or coating process. If the "thin film" does not require a patterning process or a photolithography process during the entire manufacturing process, the "thin film" can also be called a "layer". If the "thin film" also requires a patterning process or a photolithography process during the entire manufacturing process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process or the photolithography process contains at least one "pattern".

[0109] The following describes the manufacturing method of the three-dimensional memory of the present application by taking a three-dimensional DRAM as an example.

[0110] In an exemplary embodiment, a manufacturing process of a three-dimensional DRAM may include:

[0111] S100: forming a laminated structure.

[0112] An exemplary step may include: providing a substrate 10, and alternately depositing an insulating layer film and a sacrificial layer film on the substrate 10 along a third direction Z to form a stacked structure 1 including an insulating layer 20 and a sacrificial layer 30, such as Figure 2 As shown. Among them, Figure 2 A schematic vertical cross-sectional view of a method for manufacturing a three-dimensional memory provided for some embodiments of the present application, taken along a plane perpendicular to a substrate and parallel to a first direction after forming a stacked structure including an insulating layer and a sacrificial layer.

[0113] In an exemplary embodiment, the insulating layer film and the sacrificial layer film may be deposited using a chemical vapor deposition method or the like.

[0114] In an exemplary embodiment, the substrate 10 may be a single crystal silicon substrate.

[0115] In an exemplary embodiment, the insulating layer 20 may be made of oxide, such as silicon dioxide.

[0116] In an exemplary embodiment, the sacrificial layer 30 may be made of nitride, such as silicon nitride.

[0117] Figure 2 The stacked structure 1 shown in FIG. 1 may include four insulating layers 20 and three sacrificial layers 30. In other exemplary embodiments, the stacked structure may further include more or fewer insulating layers 20 and sacrificial layers 30 that are alternately arranged.

[0118] In addition, a hard mask layer (not shown) may be disposed on the top of the stacked structure 1 for use in subsequent patterning processes and will be removed after patterning.

[0119] In an exemplary embodiment, the hard mask layer may be formed of an oxide such as silicon dioxide.

[0120] S200: forming a dummy transistor and a dummy capacitor.

[0121] Exemplary steps may include: dividing the stacked structure 1 into a transistor preset area 100 and a capacitor preset area 200 (the dotted line II-I' shows the approximate boundary between the transistor preset area and the capacitor preset area) and a bit line preset area 300 (the dotted line II-II' shows the approximate boundary between the transistor preset area and the bit line preset area); photolithography and etching the stacked structure 1, forming a transistor hole (not shown) and a capacitor hole (not shown) penetrating the stacked structure and terminating at the upper surface of the substrate in the transistor preset area 100 and the capacitor preset area 200 of the stacked structure 1, respectively, wherein the capacitor hole is located on one side of the transistor hole along the first direction X and the positive projection of the transistor hole on the substrate 10 is smaller than the positive projection of the capacitor hole on the substrate 10, and each row has one transistor hole and one capacitor hole, forming three rows in total; depositing a layer of insulating material on the sidewall and bottom wall of each transistor hole and each capacitor hole to form a protective layer 40 that plays a protective isolation role in subsequent processes; then continuing to deposit the material to be replaced in the transistor hole and the capacitor hole until the two holes are filled, forming a dummy transistor 41 and a dummy capacitor 42, respectively, such as Figure 3A and Figure 3B shown. Figure 3A A schematic horizontal cross-sectional view of an intermediate product obtained in an intermediate step of a method for manufacturing a three-dimensional memory provided in some embodiments of the present application, taken along a plane parallel to a substrate; Figure 3B For along Figure 3A A schematic cross-sectional view perpendicular to the substrate taken along the section line AA' in FIG.

[0122] In an exemplary embodiment, the orthographic projections of the transistor holes and the capacitor holes on the substrate may be in the shape of a circle, an ellipse, a square, a rectangle, or the like.

[0123] In an exemplary embodiment, the insulating material may be an oxide, such as SiO 2 .

[0124] In an exemplary embodiment, the material to be replaced may be polysilicon or Al2O3.

[0125] In other exemplary embodiments, more rows of transistor holes and capacitor holes may be formed.

[0126] S300: forming a conductive layer.

[0127] Exemplary steps may include: forming two first trenches T1 penetrating the stacked structure, extending along the first direction X and terminating at the substrate in the stacked structure 1 by photolithography and etching, wherein each first trench T1 extends along the first direction X and separates three rows of dummy transistors 41 and dummy capacitors 42, and the distance between adjacent dummy capacitors 42 in the second direction is equal to the size of the first trench T1 in the second direction, and the distance between adjacent dummy transistors 41 in the second direction is greater than the size of the first trench T1 in the second direction; etching away the material of the sacrificial layer 30 along the second direction Y with the help of the first trenches T1 to form a plurality of empty grooves (not shown), exposing the upper and lower surfaces of the insulating layer 20 and the protective layer 40 in the first direction X; filling the plurality of empty grooves with a conductive material to form a plurality of conductive layers 50, such as Figure 4A , Figure 4B as well as Figure 4C shown. Figure 4A A schematic horizontal cross-sectional view of an intermediate product obtained in an intermediate step of a method for manufacturing a three-dimensional memory provided in some embodiments of the present application, taken along a plane parallel to a substrate; Figure 4B For along Figure 4A A schematic cross-sectional view perpendicular to the substrate taken along the cross-sectional line AA'; Figure 4C For along Figure 4A A schematic cross-sectional view perpendicular to the substrate taken along the cross-sectional line BB' in FIG.

[0128] In an exemplary embodiment, the conductive material may include a metal material such as W, TiN, or the like.

[0129] In other exemplary embodiments, when filling multiple empty grooves with conductive material, TiN can be first deposited on the upper and lower surfaces of the exposed insulating layer and both sides of the empty grooves in the first direction (ie, the exposed protective layer), and then each empty groove is filled with metal tungsten.

[0130] S400: forming a first isolation layer and a second trench.

[0131] Exemplary steps may include: in the capacitor preset region 200, filling each first trench T1 with an insulating material to form a first isolation layer 31 between two dummy capacitors 42 adjacent to each other along the second direction Y in the capacitor preset region 200, while retaining the first trench T1 in the transistor preset region 100; in the transistor preset region 100, etching each conductive layer 50 along the second direction Y by means of the first trench T1, and continuing to etch around the position of the dummy transistor 41 until all the materials of the conductive layer 50 are etched away to form a plurality of second trenches T2, exposing the protective layer 40 in the second direction Y, such as Figure 5A and Figure 5B shown. Figure 5AA schematic horizontal cross-sectional view of an intermediate product obtained in an intermediate step of a method for manufacturing a three-dimensional memory provided in some embodiments of the present application, taken along a plane parallel to a substrate; Figure 5B For along Figure 5A A schematic cross-sectional view perpendicular to the substrate taken along the cross-sectional line BB' in FIG.

[0132] In an exemplary embodiment, the insulating material used for the first isolation layer 31 may be the same material as that used for the insulating layer 20 , such as silicon dioxide.

[0133] S500: forming a second isolation layer in a preset region of the transistor.

[0134] An exemplary step may include: in the transistor preset region 100, at each conductive layer, filling the first trench T1 and the second trench T2 with an insulating material to form a second isolation layer 32 between adjacent dummy transistors 41 along the second direction Y in the transistor preset region 100, such as Fig. 6A and Figure 6B shown. Fig. 6A A schematic horizontal cross-sectional view of an intermediate product obtained in an intermediate step of a method for manufacturing a three-dimensional memory provided in some embodiments of the present application, taken along a plane parallel to a substrate; Figure 6B For along Fig. 6A A schematic cross-sectional view perpendicular to the substrate taken along the cross-sectional line BB' in FIG.

[0135] In an exemplary embodiment, the second isolation layer 32 may be made of insulating dielectric materials such as low-k dielectric constant, but cannot be made of the same material as the insulating layer 20 and the first isolation layer 31, such as SiO2. For example, the second isolation layer 32 may be made of silicon nitride.

[0136] Fig. 6A It is shown that at each conductive layer, the dimension L2 of the second isolation layer 32 along the second direction Y is larger than the dimension L1 of the first isolation layer 31 along the second direction Y. In the present application, at each conductive layer, the dimension between two adjacent transistors along the second direction Y is larger than the dimension between two adjacent capacitors along the second direction Y, so that in the first direction, the contact area between the capacitor and the transistor and the contact area between the transistor and the bit line are significantly reduced, and the two isolation layers are made of different materials, so that the parasitic capacitance between the bit line and the transistor and the parasitic capacitance between the word line and the capacitor can be effectively reduced.

[0137] S600: forming a third trench and a fourth trench.

[0138] An exemplary step may include: in the transistor preset area 100, removing the material of the dummy transistor 41 and the protective layer 40 in the transistor hole, exposing the side wall of the conductive layer 50 along the third direction Z, and forming a third trench T3; transversely etching the insulating layer 20 along the first direction, exposing the upper surface and the lower surface of the conductive layer 50 and the side wall of the insulating layer 20 along the third direction Z, and forming a fourth trench T4, such as Figure 7 As shown. Among them, Figure 7 A schematic vertical cross-sectional view of an intermediate product obtained in an intermediate step of a method for manufacturing a three-dimensional memory provided in some embodiments of the present application, taken along a plane perpendicular to a substrate and parallel to a first direction.

[0139] S700: forming a word line.

[0140] An exemplary step may include: depositing a semiconductor material film along the exposed upper and lower surfaces of the conductive layer 50 and the exposed sidewalls of the insulating layer 20 and the conductive layer 50 along the third direction Z by means of the third trench T3 to form a predetermined semiconductor layer 61' of the transistor; then depositing a gate insulating layer film to completely cover the predetermined semiconductor layer 61' to form a gate insulating layer 62; filling a conductive material to completely cover the gate insulating layer 62 and fill the third trench T3 to form a gate 60 / word line 90, as shown in FIG. Fig. 8A , Figure 8B as well as Figure 8C shown. Fig. 8A A schematic horizontal cross-sectional view of an intermediate product obtained in an intermediate step of a method for manufacturing a three-dimensional memory provided in some embodiments of the present application, taken along a plane parallel to a substrate; Figure 8B For along Fig. 8A A schematic cross-sectional view perpendicular to the substrate taken along the cross-sectional line AA'; Figure 8C For along Fig. 8A A schematic cross-sectional view perpendicular to the substrate taken along the cross-sectional line BB' in FIG.

[0141] S800: forming a fifth trench.

[0142] An exemplary step may include: removing the material of the dummy capacitor 42 and the protective layer 40 in the capacitor preset area 200 to form a fifth trench T5, such as Fig. 9 shown. Fig. 9 A schematic vertical cross-sectional view of an intermediate product obtained in an intermediate step of a method for manufacturing a three-dimensional memory provided in some embodiments of the present application, taken along a plane perpendicular to a substrate and parallel to a first direction.

[0143] S900: exposing a preset semiconductor layer at the insulating layer.

[0144] An exemplary step may include: in the capacitor preset region 200, by means of the fifth trench T5, each insulating layer 20 is laterally etched along the first direction X to expose the preset semiconductor layer 61' at each insulating layer 20, thereby forming a sixth trench T6; and at the same time, in the bit line preset region 300, each insulating layer 20 is laterally etched along the first direction to expose the preset semiconductor layer 61' at each insulating layer 20, thereby forming a seventh trench T7, such as Fig. 10A and Fig. 10B shown. Fig. 10A A schematic vertical cross-sectional view of an intermediate product obtained in an intermediate step of a method for manufacturing a three-dimensional memory provided in some embodiments of the present application, taken along a plane perpendicular to the substrate and parallel to the first direction; Fig. 10B A vertical cross-sectional schematic diagram of an intermediate product obtained in an intermediate step of a method for manufacturing a three-dimensional memory provided in some embodiments of the present application, taken along a plane perpendicular to a substrate and parallel to a second direction.

[0145] S1000: Remove parasitic channels.

[0146] An exemplary step may include: using the sixth trench T6 and the seventh trench T7 at the same time, at each insulating layer 20, etching and removing the preset semiconductor layer 61' along both sides of the annular semiconductor layer simultaneously, until the gate insulating layer 62 is contacted and stopped; at this time, the remaining preset semiconductor layer 61' is flush with the gate insulating layer 62 along the third direction Z, that is, a semiconductor layer 61 disconnected in the third direction is formed, the parasitic channel is removed, and an isolation portion 620 of the gate insulating layer 62 is formed, and the isolation portion 620 can separate the semiconductor layer 61 in the third direction, such as Fig.11A and Fig. 11B shown. Fig.11A A schematic vertical cross-sectional view of an intermediate product obtained in an intermediate step of a method for manufacturing a three-dimensional memory provided in some embodiments of the present application, taken along a plane perpendicular to the substrate and parallel to the first direction; Fig. 11B A vertical cross-sectional schematic diagram of an intermediate product obtained in an intermediate step of a method for manufacturing a three-dimensional memory provided in some embodiments of the present application, taken along a plane perpendicular to a substrate and parallel to a second direction.

[0147] S1100: Filled with insulating material.

[0148] Exemplary steps may include: filling the sixth trench T6 and the seventh trench T7 with an insulating material and filling the fifth trench in the capacitor preset area 200, and making the upper surface of the stacked structure flush by a CMP process, such as Fig. 12A and Fig. 12B shown. Fig. 12AA schematic vertical cross-sectional view of an intermediate product obtained in an intermediate step of a method for manufacturing a three-dimensional memory provided in some embodiments of the present application, taken along a plane perpendicular to the substrate and parallel to the first direction; Fig. 12B A vertical cross-sectional schematic diagram of an intermediate product obtained in an intermediate step of a method for manufacturing a three-dimensional memory provided in some embodiments of the present application, taken along a plane perpendicular to a substrate and parallel to a second direction.

[0149] S1200: removing the insulating layer in the capacitor preset area 200 again, manufacturing the first electrode 70, the second electrode and the dielectric layer of the capacitor, and completing the manufacturing of the capacitor.

[0150] Some embodiments of the present application further provide a manufacturing method, which further comprises the following steps after forming the dummy transistor:

[0151] In the preset area of ​​the capacitor, the dummy capacitor is removed to form an eighth groove; with the help of the eighth groove T8, the sacrificial layer is etched along the first direction, so that the sacrificial layer is concave in the first direction than the adjacent insulating layer, forming a ninth groove T9; in the eighth groove T8 and the ninth groove T9, a first conductive material is deposited to form a first electrode of the capacitor; the material to be replaced is continuously filled to fill the ninth groove T9 and only partially fill the eighth groove T8; the material to be replaced is etched along the first direction, and part of the material to be replaced in the ninth groove T9 is removed, and at the same time, the first conductive material located on the side wall of the eighth groove T8 is etched away, so that the first electrodes of capacitors of different layers are disconnected, such as Figures 13A-13F After forming the first electrode of the capacitor, other steps are also included to form a memory device. For details, please refer to Figures 4A-12B Corresponding instruction manual content.

[0152] The second method of the present application is based on the post-formation of capacitors, such as the transistors of the IGZO semiconductor layer are formed first. In order to reduce the damage to the transistor IGZO semiconductor layer caused by the relatively high temperature (>400°C) in the post-processing of the capacitor, the first electrode material of the capacitor (such as TiN) can be formed first when the capacitor hole is formed. This can reduce a high-temperature process to a certain extent, and only requires a second electrode material such as TiN process. For devices using low-temperature capacitor materials, this solution of removing parasitic channels based on the post-formation of capacitors in the present application can significantly reduce the damage to the IGZO semiconductor layer and the like caused by temperature.

[0153] Some embodiments of the present application also provide an electronic device, comprising the memory provided in some embodiments of the present application as above.

[0154] In some embodiments, the electronic device may include a storage device, a smart phone, a computer, a tablet computer, an artificial intelligence device, a wearable device, or a mobile power source.

[0155] Although the embodiments disclosed in this application are as above, the contents described are only embodiments adopted to facilitate understanding of this application and are not intended to limit this application. Any technician in the field to which this application belongs can make any modifications and changes in the form and details of implementation without departing from the spirit and scope disclosed in this application, but the scope of protection of this application shall still be based on the scope defined in the attached claims.

Claims

1. A method for manufacturing a three-dimensional memory, characterized in that: The steps include: Alternatingly forming insulating layers and sacrificial layers along a third direction perpendicular to the substrate to form a stacked structure, dividing the stacked structure into a bit line preset region, a transistor preset region, and a capacitor preset region arranged along a first direction, the first direction being parallel to the substrate; forming a dummy transistor in the transistor preset region and forming a dummy capacitor in the capacitor preset region; Replacing the material of the sacrificial layer with a conductive material to form each conductive layer; removing the dummy transistor; forming a predetermined semiconductor layer, a gate insulating layer and a word line; removing the dummy capacitor; At the same time, the insulating layers and the preset semiconductor layers are removed from the bit line preset area and the capacitor preset area in opposite directions along the first direction until the etching reaches the position of the gate insulating layer, so that the preset semiconductor layer is disconnected at each insulating layer along the third direction to form semiconductor layers disconnected from each other.

2. The manufacturing method according to claim 1, characterized in that: Forming dummy transistors and dummy capacitors includes: forming a transistor hole in the transistor preset region and a capacitor hole in the capacitor preset region, wherein the transistor hole and the capacitor hole are arranged along a first direction; Depositing an insulating material film on the bottom wall and side wall of the transistor hole and the capacitor hole to form a protective layer; A protection layer of a material to be replaced is deposited to cover the transistor hole and the capacitor hole to form the dummy transistor and the dummy capacitor, respectively.

3. The manufacturing method according to claim 2, characterized in that: Forming each conductive layer includes: forming a plurality of first trenches extending along the first direction and penetrating the stacked structure in the stacked structure, wherein the first trenches separate two adjacent dummy transistors in the second direction and separate two adjacent dummy capacitors in the second direction; Etching away the sacrificial layer along the second direction by means of the first groove to form a plurality of empty grooves; The plurality of empty grooves are filled with a conductive material to form each of the conductive layers.

4. The manufacturing method according to claim 3, characterized in that: The method further includes forming a transistor, and before forming the transistor, the method further includes the following steps: Filling the first trench in the preset area of ​​the capacitor with an insulating material to form a first isolation layer; In the transistor preset area, etching each of the conductive layers along the second direction by means of the first trench until reaching the position of the dummy transistor to form a second trench; In a preset region of the transistor, the first trench and the second trench are filled with an insulating material different from that of the first isolation layer to form the second isolation layer; In the second direction, a size of the second isolation layer between adjacent dummy transistors is greater than a size of the first isolation layer between adjacent dummy capacitors.

5. The manufacturing method according to claim 4, characterized in that: The steps of forming the transistor include: In the transistor preset area, removing the dummy transistor and the protection layer to expose the sidewall of the conductive layer along the third direction to form a third trench; Etching each insulating layer along the first direction by means of the third trench to expose the upper surface and the lower surface of the conductive layer and the sidewall of the insulating layer along the third direction, thereby forming a fourth trench; Depositing a semiconductor material film along the exposed upper and lower surfaces of the conductive layer and the exposed sidewalls of the insulating layer and the conductive layer along the third direction to form a predetermined semiconductor layer of the transistor; Depositing a gate insulating layer film to cover the preset semiconductor layer to form a gate insulating layer; A conductive material is filled to cover the gate insulating layer to form a gate.

6. The manufacturing method according to claim 5, characterized in that: The method of disconnecting the predetermined semiconductor layer at each insulating layer along the third direction comprises the following steps: In the capacitor preset area, removing the dummy capacitor and the protection layer to form a fifth trench; By means of the fifth trench, each insulating layer is laterally etched along the first direction to expose the semiconductor layer at each insulating layer, thereby forming a sixth trench; In the bit line preset region, each insulating layer is laterally etched along the first direction to expose the semiconductor layer at each insulating layer to form a seventh trench; At the same time, with the help of the sixth groove and the seventh groove, at the insulating layer, the semiconductor layer is etched away simultaneously along both sides of the annular semiconductor layer until it reaches the position of the gate insulating layer and stops, so that in the third direction, the semiconductor layer is disconnected at each insulating layer.

7. The manufacturing method according to claim 1, characterized in that: After forming the dummy transistor, the following steps are also included: In the capacitor preset area, removing the dummy capacitor to form an eighth groove; By means of the eighth groove, the sacrificial layer is etched along the first direction, so that the sacrificial layer is more concave than the adjacent insulating layer in the first direction, thereby forming a ninth groove; Depositing a first conductive material in the eighth and ninth grooves to form a first electrode of the capacitor; Continue filling the material to be replaced, filling the ninth groove completely and only partially filling the eighth groove; The material to be replaced is etched and the first conductive material on the sidewall of the eighth trench is etched away at the same time, so that the first electrodes of capacitors at different layers are disconnected.

8. A three-dimensional memory, characterized in that: A method for manufacturing a semiconductor device comprising a substrate and a plurality of memory cells stacked in a third direction perpendicular to the substrate, wherein each layer of memory cells comprises at least two memory cells arranged in a second direction and extending in a first direction, wherein the memory cells comprise at least one transistor, and the first direction intersects with the second direction and is perpendicular to the third direction; It also includes a word line and a gate insulating layer extending along a third direction, and a semiconductor layer located on a side of the gate insulating layer away from the word line, wherein the semiconductor layer is disconnected between two adjacent layers of memory cells, and the semiconductor layer serves as an active layer of the transistor; the gate insulating layer has an isolation portion between two adjacent layers of memory cells, and the isolation portion separates the semiconductor layers of the two adjacent layers of memory cells.

9. The three-dimensional memory according to claim 8, characterized in that: The memory cell includes a transistor and a capacitor arranged along a first direction; in a plane passing through a layer of memory cells and parallel to the substrate, an isolation layer is included between the two memory cells, the isolation layer includes a first isolation layer between two adjacent capacitors in a second direction and a second isolation layer between two adjacent transistors in the second direction, the first isolation layer includes a material different from that of the second isolation layer.

10. The three-dimensional memory according to claim 9, characterized in that: A size of the first isolation layer along the second direction is smaller than a size of the second isolation layer along the second direction.

11. The three-dimensional memory according to claim 9, characterized in that: The material of the first isolation layer includes silicon oxide, and the material of the second isolation layer includes silicon nitride.

12. The three-dimensional memory according to claim 9, characterized in that: In a plane passing through a region between two adjacent layers of memory cells in the third direction and parallel to the substrate, a first isolation layer and a second isolation layer are provided between two adjacent gate insulating layers in the second direction.

13. The three-dimensional memory according to claim 12, characterized in that: The first isolation layer is in contact with the gate insulating layer, and the second isolation layer is located on a side of the first isolation layer away from the gate insulating layer.

14. The three-dimensional memory according to claim 8, characterized in that: The transistors of each memory cell vertically stacked along the third direction are connected to the same word line, and the gate of the transistor is a part of the connected word line.

15. An electronic device, characterized in that: Comprising a three-dimensional memory according to any one of claims 8-14.

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