Three-dimensional memory and its manufacturing method, electronic devices

Abstract

This application relates to a three-dimensional memory and its manufacturing method, as well as an electronic device. The manufacturing method of the three-dimensional memory includes: alternately forming insulating layers and sacrificial layers along a third direction to form a stacked structure, dividing the stacked structure into a transistor preset region, a capacitor preset region, and a bit line preset region; forming dummy transistors in the transistor preset regions and dummy capacitors in the capacitor preset regions; replacing the material of the sacrificial layers with conductive material to form each conductive layer; removing the dummy transistors to form a transistor including a preset semiconductor layer, a gate insulating layer, and a gate; removing the dummy capacitors; simultaneously etching each insulating layer from the bit line preset region and the capacitor preset region towards each other along a first direction; continuing etching to remove the preset semiconductor layer corresponding to each insulating layer until reaching the position of the gate insulating layer and stopping the etching, such that the preset semiconductor layer is broken along the third direction at the insulating layer, forming a semiconductor layer. The manufacturing process of this application facilitates rapid removal of parasitic channels.

Description

Technical Field

[0001] This disclosure relates to, but is not limited to, semiconductor technology, and in particular to a three-dimensional memory and its manufacturing method, and an electronic device. Background Technology

[0002] With the development of integrated circuit technology, the critical dimensions of devices are shrinking, and the types and number of devices contained in a single chip are increasing, which means that any slight difference in the manufacturing process can affect the performance of the devices.

[0003] To minimize product costs, the goal is to fabricate as many device units as possible on a limited substrate. Since the advent of Moore's Law, the industry has proposed various semiconductor structure designs and process optimizations to meet current product demands. Summary of the Invention

[0004] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of this disclosure.

[0005] In one aspect, some embodiments of this disclosure provide a method for manufacturing a three-dimensional memory, comprising the following steps:

[0006] An insulating layer and a sacrificial layer are alternately formed along a third direction perpendicular to the substrate to form a stacked structure, which is divided into a bit line preset region, a transistor preset region and a capacitor preset region arranged along a first direction parallel to the substrate.

[0007] A dummy transistor is formed within the transistor preset region, and a dummy capacitor is formed within the capacitor preset region.

[0008] Each conductive layer is formed by replacing the material of the sacrificial layer with a conductive material;

[0009] Remove the dummy transistor;

[0010] Form a preset semiconductor layer, gate insulating layer, and word lines;

[0011] Remove the dummy capacitor;

[0012] Simultaneously, etching is performed from the bit line preset region and the capacitor preset region along the first direction to remove each of the insulating layers and the preset semiconductor layers until the etching stops at the position of the gate insulating layer, so that the preset semiconductor layers are broken at each of the insulating layers along the third direction, forming mutually disconnected semiconductor layers.

[0013] In an exemplary embodiment, forming a dummy transistor and a dummy capacitor includes:

[0014] A transistor hole is formed in the transistor preset region and a capacitor hole is formed in the capacitor preset region, the transistor hole and the capacitor hole being arranged along a first direction;

[0015] An insulating material film is deposited on the bottom and sidewalls of the transistor hole and the capacitor hole to form a protective layer;

[0016] A protective layer of material to be replaced is deposited to cover the transistor aperture and the capacitor aperture to form the dummy transistor and the dummy capacitor, respectively.

[0017] In an exemplary embodiment, forming each conductive layer includes:

[0018] A plurality of first trenches are formed in the stacked structure, extending along the first direction and penetrating the stacked structure, the first trenches separating two adjacent dummy transistors in the second direction and separating two adjacent dummy capacitors in the second direction;

[0019] The sacrificial layer is removed by etching along the second direction using the first trench, forming multiple empty trenches;

[0020] Multiple empty slots are filled with conductive material to form each of the conductive layers.

[0021] In an exemplary embodiment, the method further includes forming a transistor, and prior to forming the transistor, the method includes the following steps:

[0022] The first trench within the preset area of ​​the capacitor is filled with insulating material to form a first isolation layer;

[0023] Within the transistor preset region, each of the conductive layers is etched along the second direction using the first trench until the position of the dummy transistor is reached, forming a second trench.

[0024] Within the transistor preset region, the first trench and the second trench are filled with an insulating material different from the first isolation layer to form the second isolation layer;

[0025] In the second direction, the size of the second isolation layer between adjacent dummy transistors is larger than the size of the first isolation layer between adjacent dummy capacitors.

[0026] In an exemplary embodiment, the step of forming a transistor includes:

[0027] Within the transistor preset area, the dummy transistor and the protective layer are removed, exposing the conductive layer along the sidewall in the third direction, forming a third trench;

[0028] By using the third trench to etch each insulating layer along the first direction, the upper and lower surfaces of the conductive layer and the sidewalls of the insulating layer along the third direction are exposed, forming a fourth trench;

[0029] A semiconductor material thin film is deposited along the exposed upper and lower surfaces of the conductive layer and along the exposed sidewalls of the insulating and conductive layers in a third direction to form a preset semiconductor layer for the transistor.

[0030] A gate insulating layer thin film is deposited to cover a predetermined semiconductor layer to form a gate insulating layer;

[0031] A conductive material is filled to cover the gate insulating layer, forming the gate.

[0032] In an exemplary embodiment, causing the preset semiconductor layer to be disconnected at each insulating layer along a third direction includes the following steps:

[0033] Within the capacitor preset area, the dummy capacitor and protective layer are removed to form the fifth trench;

[0034] By using the fifth trench to etch each insulating layer laterally along the first direction, the semiconductor layer at each insulating layer is exposed, forming the sixth trench;

[0035] Within the bit line preset area, each insulating layer is etched laterally along the first direction to expose the semiconductor layer at each insulating layer, forming the seventh trench;

[0036] Simultaneously, using the sixth and seventh trenches, the semiconductor layer is etched away from both sides of the annular semiconductor layer at the insulating layer until the gate insulating layer is reached, so that the semiconductor layer is disconnected at each insulating layer in the third direction.

[0037] In an exemplary embodiment, the following steps are further included after forming the dummy transistor:

[0038] Within the capacitor preset area, the dummy capacitor is removed to form the eighth trench;

[0039] Using the eighth trench, the sacrificial layer is etched along the first direction, such that the sacrificial layer is recessed in the first direction compared to the adjacent insulating layer, forming the ninth trench;

[0040] In the eighth and ninth trenches, a first conductive material is deposited to form the first electrode of the capacitor;

[0041] Continue filling with the material to be replaced, filling the ninth groove and only partially filling the eighth groove;

[0042] The material to be replaced is etched away, and at the same time the first conductive material located on the sidewall of the eighth trench is etched away, so that the first electrode of the capacitor in different layers is disconnected.

[0043] In another aspect, some embodiments of this disclosure provide a three-dimensional memory, including a substrate and a multilayer of memory cells stacked at intervals in a third direction perpendicular to the substrate, each layer of memory cells including at least two memory cells spaced apart in a second direction and extending along a first direction, each memory cell including at least one transistor, the first direction intersecting the second direction and both perpendicular to the third direction;

[0044] It also includes word lines and gate insulating layers extending along a third direction, and a semiconductor layer located on the side of the gate insulating layer away from the word lines, the semiconductor layer being disconnected between two adjacent memory cells, the semiconductor layer serving as the active layer of the transistor; the gate insulating layer having an isolation portion between two adjacent memory cells, the isolation portion separating the semiconductor layers of the two adjacent memory cells.

[0045] In an exemplary embodiment, the memory cell includes a transistor and a capacitor arranged along a first direction; in a plane passing through a layer of memory cells and parallel to the substrate, an isolation layer is included between the two memory cells, the isolation layer including a first isolation layer between two adjacent capacitors in a second direction and a second isolation layer between two adjacent transistors in the second direction, the first isolation layer comprising a material different from the second isolation layer.

[0046] In an exemplary embodiment, the dimension of the first isolation layer along the second direction is smaller than the dimension of the second isolation layer along the second direction.

[0047] In an exemplary embodiment, the material of the first isolation layer includes silicon oxide, and the material of the second isolation layer includes silicon nitride.

[0048] In an exemplary embodiment, a first isolation layer and a second isolation layer are provided between two adjacent gate insulating layers in a plane passing through the region between two adjacent memory cells and parallel to the substrate, in a second direction.

[0049] In an exemplary embodiment, the first isolation layer is in contact with the gate insulating layer, and the second isolation layer is located on the side of the first isolation layer away from the gate insulating layer.

[0050] In an exemplary embodiment, transistors of memory cells stacked vertically along a third direction are connected to the same word line, and the gate of the transistor is part of the connected word line.

[0051] On the other hand, some embodiments of this disclosure provide an electronic device.

[0052] This application involves opening the capacitor region and bit line region, etching an insulating layer in a first direction to connect it to the semiconductor layer of the transistor (i.e., the location of the parasitic channel), removing the insulating layer surrounding the semiconductor layer, and finally removing the semiconductor layer. The method provided in this application etches in a counter-current manner along the annular parasitic channel, which is equivalent to an etching depth of only 1 / 4 of the distance of the annular parasitic channel, thus easily achieving the removal of the parasitic channel material.

[0053] This application removes parasitic channels along the bit line direction and capacitor direction, so that the space between adjacent memory cells in the second direction does not need to be large, thereby reducing the size of individual memory cells and significantly improving the storage density of memory cells.

[0054] This application removes parasitic channels from both sides, significantly reducing the difficulty of wet etching while maintaining the same transistor size. The aspect ratio is halved, allowing for easier acid penetration and ensuring effective removal of parasitic channels around the same layer of the device. For three-dimensional stacked memory architectures, this ensures uniform etching and intact structural morphology for each layer.

[0055] Other features and advantages of this application will be set forth in the following description, and will be apparent in part from the description, or may be learned by practicing the application. Other advantages of this application can be realized and obtained by means of the solutions described in the description and the accompanying drawings. Attached Figure Description

[0056] The accompanying drawings are used to provide an understanding of the technical solutions of this application and constitute a part of the specification. They represent preferred embodiments and are used together with the embodiments of this application to explain the technical solutions of this application, but do not constitute a limitation on the technical solutions of this application.

[0057] Figure 1A A three-dimensional structural diagram of a three-dimensional memory is provided for some embodiments of this application, and the memory cells are exposed;

[0058] Figure 1B This is a three-dimensional structural diagram of a three-dimensional memory provided for some embodiments of this application, and the insulating layer between two adjacent memory cells is exposed.

[0059] Figure 1C for Figure 1A A top view of the structure shown;

[0060] Figure 1D for Figure 1B A top view of the structure shown;

[0061] Figure 1E For along Figure 1A The cross-sectional view perpendicular to the substrate is taken by the cross-section line AA' in the structure shown;

[0062] Figure 1F For along Figure 1A The cross-sectional view perpendicular to the substrate is taken by the cross-section line BB' in the structure shown.

[0063] Figure 2 A schematic diagram of a vertical cross-section taken along a plane perpendicular to the substrate and parallel to a first direction after forming a stacked structure including an insulating layer and a sacrificial layer, according to some embodiments of this application, is provided for a method of manufacturing a three-dimensional memory.

[0064] Figure 3A A schematic diagram of a horizontal cross-section of an intermediate product obtained from an intermediate step in a method for manufacturing a three-dimensional memory according to some embodiments of this application, taken along a plane parallel to the substrate.

[0065] Figure 3B For along Figure 3A A schematic diagram of a cross-section perpendicular to the substrate, taken by section line AA'.

[0066] Figure 4A A schematic diagram of a horizontal cross-section of an intermediate product obtained from an intermediate step in a method for manufacturing a three-dimensional memory according to some embodiments of this application, taken along a plane parallel to the substrate.

[0067] Figure 4B For along Figure 4A A schematic diagram of a cross-section perpendicular to the substrate, taken by section line AA'.

[0068] Figure 4C For along Figure 4A A schematic diagram of a cross-section perpendicular to the substrate, taken by the cross-section line BB'.

[0069] Figure 5A A schematic diagram of a horizontal cross-section of an intermediate product obtained from an intermediate step in a method for manufacturing a three-dimensional memory according to some embodiments of this application, taken along a plane parallel to the substrate.

[0070] Figure 5B For along Figure 5A A schematic diagram of a cross-section perpendicular to the substrate, taken by the cross-section line BB'.

[0071] Figure 6A A schematic diagram of a horizontal cross-section of an intermediate product obtained from an intermediate step in a method for manufacturing a three-dimensional memory according to some embodiments of this application, taken along a plane parallel to the substrate.

[0072] Figure 6B For along Figure 6A A schematic diagram of a cross-section perpendicular to the substrate, taken by the cross-section line BB'.

[0073] Figure 7A schematic diagram of a vertical cross-section taken along a plane perpendicular to the substrate and parallel to a first direction after an intermediate product obtained from an intermediate step in a method for manufacturing a three-dimensional memory according to some embodiments of this application.

[0074] Figure 8A A schematic diagram of a horizontal cross-section of an intermediate product obtained from an intermediate step in a method for manufacturing a three-dimensional memory according to some embodiments of this application, taken along a plane parallel to the substrate.

[0075] Figure 8B For along Figure 8A A schematic diagram of a cross-section perpendicular to the substrate, taken by section line AA'.

[0076] Figure 8C For along Figure 8A A schematic diagram of a cross-section perpendicular to the substrate, taken by the cross-section line BB'.

[0077] Figure 9 A schematic diagram of a vertical cross-section of an intermediate product obtained from an intermediate step in a method for manufacturing a three-dimensional memory according to some embodiments of this application, taken along a plane perpendicular to the substrate and parallel to a first direction.

[0078] Figure 10A A schematic diagram of a vertical cross-section of an intermediate product obtained from an intermediate step in a method for manufacturing a three-dimensional memory according to some embodiments of this application, taken along a plane perpendicular to the substrate and parallel to a first direction.

[0079] Figure 10B A schematic diagram of a vertical cross-section of an intermediate product obtained from an intermediate step in a method for manufacturing a three-dimensional memory according to some embodiments of this application, taken along a plane perpendicular to the substrate and parallel to a second direction.

[0080] Figure 11A A schematic diagram of a vertical cross-section of an intermediate product obtained from an intermediate step in a method for manufacturing a three-dimensional memory according to some embodiments of this application, taken along a plane perpendicular to the substrate and parallel to a first direction.

[0081] Figure 11B A schematic diagram of a vertical cross-section of an intermediate product obtained from an intermediate step in a method for manufacturing a three-dimensional memory according to some embodiments of this application, taken along a plane perpendicular to the substrate and parallel to a second direction.

[0082] Figure 12A A schematic diagram of a vertical cross-section of an intermediate product obtained from an intermediate step in a method for manufacturing a three-dimensional memory according to some embodiments of this application, taken along a plane perpendicular to the substrate and parallel to a first direction.

[0083] Figure 12BA schematic diagram of a vertical cross-section of an intermediate product obtained from an intermediate step in a method for manufacturing a three-dimensional memory, provided for some embodiments of this application, taken along a plane perpendicular to the substrate and parallel to a second direction; and

[0084] Figures 13A-13F A schematic diagram of a vertical cross-section of an intermediate product obtained from an intermediate step in a method for manufacturing another three-dimensional memory provided for some embodiments of this application, taken along a plane perpendicular to the substrate and parallel to a first direction. Detailed Implementation

[0085] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in detail below with reference to the accompanying drawings. It should be noted that, unless otherwise specified, the embodiments and features described in these embodiments can be arbitrarily combined with each other.

[0086] The embodiments described herein can be implemented in many different forms. Those skilled in the art will readily understand that the implementation methods and content can be varied in many ways without departing from the spirit and scope of this application. Therefore, this application should not be construed as limited to the contents described in the following embodiments. Unless otherwise specified, the embodiments and features described in this application can be arbitrarily combined with each other.

[0087] The scale of the figures in this application can be used as a reference in actual processes, but is not limited thereto. For example, the aspect ratio of the semiconductor layer, the thickness and spacing of each film layer can be adjusted according to actual needs. The figures described in this application are only schematic diagrams of the structure, and the approach of this application is not limited to the shapes or values ​​shown in the figures.

[0088] In this specification, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification, and does not imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this application. The positional relationships of the constituent elements may be appropriately varied depending on the direction in which each constituent element is described. Therefore, the terminology used is not limited to those described in the specification and may be appropriately replaced as needed.

[0089] In this specification, unless otherwise expressly specified and limited, the terms "setup" and "connection" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or an electrical connection; a direct connection, an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art will understand the specific meaning of these terms in this application based on the specific circumstances.

[0090] In the description of this application, ordinal numbers such as "first" and "second" are used to avoid confusion of constituent elements, rather than to limit the quantity.

[0091] In this specification, "film" and "layer" may be interchanged. For example, "metal layer" may sometimes be replaced with "metal film".

[0092] In the description of this application, a transistor refers to a device that includes at least three terminals: a gate, a drain, and a source. A transistor has a channel layer between the drain (drain terminal, drain region, or drain) and the source (source terminal, source region, or source), and current can flow through the drain, the channel layer, and the source. In this application, the channel layer refers to the region through which current primarily flows. In this application, the terms "metal-oxide-semiconductor channel," "channel layer," and "semiconductor layer" are used interchangeably.

[0093] The architecture design of three-dimensional memory in related technologies, such as 3D DRAM, often suffers from a large number of parasitic capacitances and parasitic MOS problems.

[0094] Therefore, this application provides a method for manufacturing three-dimensional memory, which easily produces memory with no or reduced parasitic capacitance and parasitic MOS.

[0095] Therefore, the method for manufacturing a three-dimensional memory provided in this application includes the following steps: alternately forming an insulating layer and a sacrificial layer along a third direction perpendicular to the substrate to form a stacked structure; dividing the stacked structure into a bit line preset region, a transistor preset region, and a capacitor preset region arranged along a first direction parallel to the substrate; forming a dummy transistor in the transistor preset region and a dummy capacitor in the capacitor preset region; replacing the material of the sacrificial layer with a conductive material to form each conductive layer; removing the dummy transistor; forming a preset semiconductor layer, a gate insulating layer, and a word line; removing the dummy capacitor; and simultaneously etching away each insulating layer and the preset semiconductor layer from the bit line preset region and the capacitor preset region along the first direction until the etching stops at the position of the gate insulating layer, so that the preset semiconductor layer is broken at each insulating layer along the third direction to form mutually disconnected semiconductor layers.

[0096] As used in embodiments of this disclosure, the term "first direction" X is defined as the arrangement direction of the capacitors and transistors; the term "second direction" Y is defined as a direction that intersects "first direction" X and is parallel to the bit line extension direction; the term "third direction" Z is defined as a direction perpendicular to the plane containing the substrate, i.e., a direction parallel to the word line extension direction; the plane formed by the first direction X and the second direction Y is parallel to the substrate. "First direction" X, "second direction" Y, and "third direction" Z can be as follows: Figures 1A-1F As shown in the figure.

[0097] As used in this application, the term "monolithic structure" can refer to a structure in which A and B have no obvious boundary interface such as discontinuities or gaps in their microstructure. Generally, a monolithic structure is formed by patterning interconnected membrane layers on a single membrane layer. For example, A and B may be formed using the same material to create a single membrane layer and simultaneously formed into a structure with interconnected relationships through the same patterning process.

[0098] like Figures 1A-1F As shown, some embodiments of this application provide a three-dimensional memory that may include a substrate 10 and multiple layers of memory cells stacked at intervals in a third direction Z perpendicular to the substrate 10. Each layer of memory cells includes at least two memory cells spaced apart in a second direction Y and extending along a first direction X. Each memory cell includes at least one transistor.

[0099] In some implementations, the memory cell may include a transistor and a capacitor.

[0100] In this application, the storage unit can be 1T1C, 2T0C, 1T0C, etc.

[0101] Continue to refer to Figure 1C , Figure 1C The transistor and capacitor regions are roughly divided by dashed line I-I', and the transistor and bit line regions are roughly divided by dashed line II-II'. Figure 1C The first source / drain 71 and the second source / drain 72 are shown on both sides of the semiconductor layer 61 along the first direction X. The first source / drain 71 can be connected to the first electrode 70 of the capacitor, while the second source / drain 72 can be connected to the bit line 80.

[0102] Figure 1CIt is also shown that at each conductive layer, the conductive layer refers to a film layer including a first source / drain 71 and a second source / drain 72. A first isolation layer 31 may be included between two adjacent capacitors in the second direction Y, and a second isolation layer 32 may be included between two adjacent transistors in the second direction Y. The first isolation layer 31 may include a different material than the second isolation layer 32. In some embodiments, the material of the first isolation layer 31 may include silicon oxide, while the material of the second isolation layer 32 may include silicon nitride, but not silicon oxide. Compared to silicon oxide, silicon nitride has a better effect on reducing parasitic capacitance between bit lines and semiconductors. Moreover, the isolation layer formed by the two materials has a better isolation effect, which can further reduce leakage current between adjacent semiconductor layers.

[0103] Figure 1C It is also shown that the dimension L1 of the first isolation layer 31 along the second direction is smaller than the dimension L2 of the second isolation layer 32 along the second direction. Some embodiments of this disclosure reduce the contact area between the bit line and the source and drain of the transistor by making the dimension L1 of the first isolation layer along the second direction smaller than the dimension L2 of the second isolation layer along the second direction, thereby reducing the parasitic capacitance between them.

[0104] Figure 1D It is shown that at each insulating layer, which is a film layer adjacent to the conductive layer and excluding the first source / drain 71 and the second source / drain 72, a first isolation layer 31 is included between two adjacent capacitors in the second direction Y, and a second isolation layer 32 is included between two adjacent transistors in the second direction Y. The first isolation layer 31 is made of a different material than the second isolation layer 32, but the dimension L1 of the first isolation layer 31 between two adjacent capacitors in the second direction is greater than or equal to the dimension L2 of the second isolation layer 32 between two adjacent transistors in the second direction. There is also a first isolation layer 31 between the transistors and the second isolation layer 32. By providing a first isolation layer 31 between the transistors and the second isolation layer 32, the two isolation layers between adjacent transistors use different materials, thereby effectively reducing the parasitic capacitance between the bit line and the transistor and the word line and the capacitor. Furthermore, providing a first isolation layer 31, such as silicon oxide, between the channels of two adjacent memory cells can provide better isolation and prevent leakage.

[0105] refer to Figure 1E and Figure 1FThe three-dimensional memory of this application may further include a word line 90 extending along a third direction Z and a gate insulating layer 62, as well as a semiconductor layer 61 located on the side of the gate insulating layer away from the word line; the semiconductor layer 61 is disconnected between two adjacent memory cells, and the semiconductor layer 61 can serve as the active layer of the transistor; the gate insulating layer 62 has an isolation portion 620 between two adjacent memory cells, the isolation portion 620 separating the semiconductor layer 61 of the two adjacent memory cells. The isolation portion can isolate adjacent semiconductor layers, thereby avoiding semiconductor layer connections and reducing leakage current; this application reduces the etching of the gate insulating layer by removing the semiconductor layer from the bit line preset region and the capacitor preset region, thereby forming the isolation portion.

[0106] in addition, Figure 1E The first source / drain 71 and the second source / drain 72 can be made of a two-layer composite material, i.e., the core can be tungsten metal, and then coated with a layer of TiN. However, in some other embodiments, the first source / drain 71 and the second source / drain 72 can also be formed of only one conductive material, such as tungsten metal, TiN, polycrystalline silicon, etc.

[0107] The structure of the three-dimensional memory in this application can reduce the parasitic capacitance between bit lines, capacitors, and word lines, and can also help to eliminate parasitic channels.

[0108] The technical solution of this application is further illustrated below through the manufacturing process of the memory according to some embodiments of this application. The "patterning process" mentioned in these embodiments includes processes such as depositing a film layer, coating photoresist, mask exposure, development, etching, and photoresist stripping, which are mature manufacturing processes in related technologies. The "photolithography process" mentioned in these embodiments includes coating a film layer, mask exposure, and development, which are mature manufacturing processes in related technologies. Deposition can employ known processes such as sputtering, evaporation, and chemical vapor deposition; coating can employ known coating processes; and etching can employ known methods, without specific limitations. In the description of these embodiments, it should be understood that a "thin film" refers to a thin film made by depositing or coating a certain material on a substrate. If the "thin film" does not require a patterning process or photolithography process during the entire manufacturing process, it can also be called a "layer." If the "thin film" requires a patterning process or photolithography process during the entire manufacturing process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process or photolithography process contains at least one "pattern."

[0109] The manufacturing method of the three-dimensional memory of this application will be described below using three-dimensional DRAM as an example.

[0110] In an exemplary embodiment, the manufacturing process of a three-dimensional DRAM may include:

[0111] S100: Forms a layered structure.

[0112] Exemplary steps may include: providing a substrate 10, and alternately depositing an insulating layer film and a sacrificial layer film along a third direction Z on the substrate 10 to form a stacked structure 1 including an insulating layer 20 and a sacrificial layer 30, such as... Figure 2 As shown. Among them, Figure 2 This is a schematic diagram of a vertical cross-section taken along a plane perpendicular to the substrate and parallel to a first direction after forming a stacked structure including an insulating layer and a sacrificial layer, according to some embodiments of this application, in a method for manufacturing a three-dimensional memory.

[0113] In an exemplary embodiment, insulating and sacrificial thin films can be deposited using methods such as chemical vapor deposition.

[0114] In an exemplary embodiment, substrate 10 may be a monocrystalline silicon substrate.

[0115] In an exemplary embodiment, the insulating layer 20 may be an oxide, such as silicon dioxide.

[0116] In an exemplary embodiment, the sacrificial layer 30 may be a nitride, such as silicon nitride.

[0117] Figure 2 The stacked structure 1 shown may include four insulating layers 20 and three sacrificial layers 30. In other exemplary embodiments, the stacked structure may also include more or fewer layers of insulating layers 20 and sacrificial layers 30 arranged alternately.

[0118] In addition, a hard mask layer (not shown) can be placed on top of the stacked structure 1 for subsequent patterning processes, which will be removed after patterning.

[0119] In an exemplary embodiment, the hard mask layer may be an oxide, such as silicon dioxide.

[0120] S200: Creates dummy transistors and dummy capacitors.

[0121] Exemplary steps may include: dividing the stacked structure 1 into a transistor preset region 100 and a capacitor preset region 200 (dashed line I-I' shows the approximate boundary between the transistor preset region and the capacitor preset region) and a bit line preset region 300 (dashed line II-II' shows the approximate boundary between the transistor preset region and the bit line preset region); photolithographically and etching the stacked structure 1 to form transistor holes (not shown) and capacitor holes (not shown) penetrating the stacked structure and terminating on the upper surface of the substrate in the transistor preset region 100 and the capacitor preset region 200 of the stacked structure 1, respectively. The capacitor holes are located on the side of the transistor holes along the first direction X, and the orthographic projection of the transistor holes on the substrate 10 is smaller than the orthographic projection of the capacitor holes on the substrate 10. One transistor hole and one capacitor hole are formed in each row, for a total of three rows; depositing an insulating material on the sidewalls and bottom walls of each transistor hole and each capacitor hole to form a protective layer 40 that provides protection and isolation in subsequent processes; then continuing to deposit replacement material in the transistor holes and capacitor holes until both holes are filled, forming a dummy transistor 41 and a dummy capacitor 42, respectively. Figure 3A and Figure 3B As shown. Figure 3A A schematic diagram of a horizontal cross-section of an intermediate product obtained from an intermediate step in a method for manufacturing a three-dimensional memory according to some embodiments of this application, taken along a plane parallel to the substrate. Figure 3B For along Figure 3A A schematic diagram of a cross section perpendicular to the substrate, taken by the cross section line AA'.

[0122] In an exemplary embodiment, the orthographic projection of the transistor hole and capacitor hole onto the substrate can be circular, elliptical, square, rectangular, or other shapes.

[0123] In an exemplary embodiment, the insulating material may be an oxide, such as SiO2.

[0124] In an exemplary embodiment, the material to be replaced may be polycrystalline silicon or Al2O3, etc.

[0125] In other exemplary embodiments, more rows of transistor holes and capacitor holes may be formed.

[0126] S300: Forms a conductive layer.

[0127] Exemplary steps may include: forming two first trenches T1 in the stacked structure 1 by photolithography and etching, extending through the stacked structure, along a first direction X, and terminating at a substrate. Each first trench T1 extends along the first direction X and separates three rows of dummy transistors 41 and dummy capacitors 42. The distance between adjacent dummy capacitors 42 in a second direction is equal to the dimension of the first trench T1 in the second direction, while the distance between adjacent dummy transistors 41 in the second direction is greater than the dimension of the first trench T1 in the second direction. Etching away the material of the sacrificial layer 30 along the second direction Y using the first trenches T1 forms multiple empty trenches (not shown), exposing the upper and lower surfaces of the insulating layer 20 and the protective layer 40 in the first direction X. Filling the multiple empty trenches with a conductive material forms multiple conductive layers 50, such as... Figure 4A , Figure 4B as well as Figure 4C As shown. Figure 4A A schematic diagram of a horizontal cross-section of an intermediate product obtained from an intermediate step in a method for manufacturing a three-dimensional memory according to some embodiments of this application, taken along a plane parallel to the substrate. Figure 4B For along Figure 4A A schematic diagram of a cross-section perpendicular to the substrate, taken by section line AA'. Figure 4C For along Figure 4A A schematic diagram of a cross-section perpendicular to the substrate, taken by the cross-section line BB'.

[0128] In an exemplary embodiment, the conductive material may include a metallic material, such as W, TiN, etc.

[0129] In other exemplary embodiments, when filling multiple empty slots with conductive material, TiN can be deposited first on the upper and lower surfaces of the exposed insulating layer and on both sides of the empty slots in the first direction (i.e., the exposed protective layer), and then each empty slot can be filled with tungsten metal.

[0130] S400: Forms the first isolation layer and the second trench.

[0131] Exemplary steps may include: filling each first trench T1 with insulating material within the capacitor preset region 200 to form a first isolation layer 31 between two adjacent dummy capacitors 42 along the second direction Y within the capacitor preset region 200, while retaining the first trench T1 within the transistor preset region 100; within the transistor preset region 100, etching each conductive layer 50 along the second direction Y using the first trench T1, and continuing etching around the location of the dummy transistor 41 until all material of the conductive layer 50 is removed, forming a plurality of second trenches T2, exposing the protective layer 40 in the second direction Y, such as... Figure 5A and Figure 5B As shown. Figure 5AA schematic diagram of a horizontal cross-section of an intermediate product obtained from an intermediate step in a method for manufacturing a three-dimensional memory according to some embodiments of this application, taken along a plane parallel to the substrate. Figure 5B For along Figure 5A A schematic diagram of a cross-section perpendicular to the substrate, taken by the cross-section line BB'.

[0132] In an exemplary embodiment, the insulating material used for the first insulating layer 31 may be the same material used for the insulating layer 20, such as silicon dioxide.

[0133] S500: Forms the second isolation layer within the preset region of the transistor.

[0134] An exemplary step may include: within the transistor preset region 100, at each conductive layer, filling the first trench T1 and the second trench T2 with an insulating material to form a second isolation layer 32 between adjacent dummy transistors 41 along the second direction Y within the transistor preset region 100, such as... Figure 6A and Figure 6B As shown. Figure 6A A schematic diagram of a horizontal cross-section of an intermediate product obtained from an intermediate step in a method for manufacturing a three-dimensional memory according to some embodiments of this application, taken along a plane parallel to the substrate. Figure 6B For along Figure 6A A schematic diagram of a cross-section perpendicular to the substrate, taken by the cross-section line BB'.

[0135] In an exemplary embodiment, the second isolation layer 32 may be selected from insulating dielectric materials with low dielectric constant (low-k), but it cannot be made of the same material as the insulating layer 20 and the first isolation layer 31, such as SiO2. For example, the second isolation layer 32 may be made of silicon nitride.

[0136] Figure 6A It is shown that at each conductive layer, the dimension L2 of the second isolation layer 32 along the second direction Y is greater than the dimension L1 of the first isolation layer 31 along the second direction Y. This application achieves this by making the dimension between two adjacent transistors along the second direction Y at each conductive layer greater than the dimension between two adjacent capacitors along the second direction Y, thereby significantly reducing the contact area between the capacitor and the transistor and the contact area between the transistor and the bit line in the first direction. Furthermore, by using different materials for the two isolation layers, the parasitic capacitance between the bit line and the transistor, as well as the parasitic capacitance between the word line and the capacitor, can be effectively reduced.

[0137] S600: Forms the third and fourth trenches.

[0138] Exemplary steps may include: removing the material of the dummy transistor 41 and the protective layer 40 within the transistor preset region 100, exposing the sidewall of the conductive layer 50 along the third direction Z, forming a third trench T3; laterally etching the insulating layer 20 along the first direction, exposing the upper and lower surfaces of the conductive layer 50 and the sidewall of the insulating layer 20 along the third direction Z, forming a fourth trench T4, as shown. Figure 7 As shown. Among them, Figure 7 This is a schematic diagram of a vertical cross-section taken from an intermediate product obtained in an intermediate step of a manufacturing method for a three-dimensional memory provided in some embodiments of this application, along a plane perpendicular to the substrate and parallel to a first direction.

[0139] S700: Forms word lines.

[0140] Exemplary steps may include: depositing a semiconductor material thin film along the exposed upper and lower surfaces of the conductive layer 50 and the exposed sidewalls of the insulating layer 20 and the conductive layer 50 in a third direction Z using a third trench T3 to form a predetermined semiconductor layer 61' of the transistor; then depositing a gate insulating layer thin film to completely cover the predetermined semiconductor layer 61' to form a gate insulating layer 62; filling the third trench T3 with conductive material to completely cover the gate insulating layer 62 and fill it to form a gate 60 / word line 90, as shown below. Figure 8A , Figure 8B as well as Figure 8C As shown. Figure 8A A schematic diagram of a horizontal cross-section of an intermediate product obtained from an intermediate step in a method for manufacturing a three-dimensional memory according to some embodiments of this application, taken along a plane parallel to the substrate. Figure 8B For along Figure 8A A schematic diagram of a cross-section perpendicular to the substrate, taken by section line AA'. Figure 8C For along Figure 8A A schematic diagram of a cross-section perpendicular to the substrate, taken by the cross-section line BB'.

[0141] S800: Formation of the fifth trench.

[0142] An exemplary step may include: removing material from the dummy capacitor 42 and the protective layer 40 within the capacitor preset region 200 to form a fifth trench T5, such as... Figure 9 As shown. Figure 9 This is a schematic diagram of a vertical cross-section of an intermediate product obtained from an intermediate step in a method for manufacturing a three-dimensional memory according to some embodiments of this application, taken along a plane perpendicular to the substrate and parallel to a first direction.

[0143] S900: Expose the preset semiconductor layer at the insulating layer.

[0144] Exemplary steps may include: within the capacitor preset region 20, laterally etching each insulating layer 20 along the first direction X using a fifth trench T5 to expose a preset semiconductor layer 61' at each insulating layer 20, forming a sixth trench T6; simultaneously, within the bit line preset region 300, laterally etching each insulating layer 20 along the first direction to expose a preset semiconductor layer 61' at each insulating layer 20, forming a seventh trench T7, as shown below. Figure 10A and Figure 10B As shown. Figure 10A A schematic diagram of a vertical cross-section of an intermediate product obtained from an intermediate step in a method for manufacturing a three-dimensional memory according to some embodiments of this application, taken along a plane perpendicular to the substrate and parallel to a first direction. Figure 10B This is a schematic diagram of a vertical cross-section of an intermediate product obtained from an intermediate step in a method for manufacturing a three-dimensional memory according to some embodiments of this application, taken along a plane perpendicular to the substrate and parallel to a second direction.

[0145] S1000: Remove parasitic channels.

[0146] An exemplary step may include: simultaneously using the sixth trench T6 and the seventh trench T7, etching away a preset semiconductor layer 61' along both sides of the annular semiconductor layer at each insulating layer 20 until it contacts the gate insulating layer 62; at this point, the remaining preset semiconductor layer 61' is flush with the gate insulating layer 62 in the third direction Z, thus forming a semiconductor layer 61 that is disconnected in the third direction, completing the removal of the parasitic channel, and also forming an isolation portion 620 of the gate insulating layer 62. This isolation portion 620 can separate the semiconductor layer 61 in the third direction, such as... Figure 11A and Figure 11B As shown. Figure 11A A schematic diagram of a vertical cross-section of an intermediate product obtained from an intermediate step in a method for manufacturing a three-dimensional memory according to some embodiments of this application, taken along a plane perpendicular to the substrate and parallel to a first direction. Figure 11B This is a schematic diagram of a vertical cross-section of an intermediate product obtained from an intermediate step in a method for manufacturing a three-dimensional memory according to some embodiments of this application, taken along a plane perpendicular to the substrate and parallel to a second direction.

[0147] S1100: Filler insulating material.

[0148] Exemplary steps may include: filling the sixth trench T6 and the seventh trench T7 with insulating material, as well as the fifth trench within the capacitor preset region 200, and flushing the upper surface of the laminated structure using a CMP process, such as... Figure 12A and Figure 12B As shown. Figure 12AA schematic diagram of a vertical cross-section of an intermediate product obtained from an intermediate step in a method for manufacturing a three-dimensional memory according to some embodiments of this application, taken along a plane perpendicular to the substrate and parallel to a first direction. Figure 12B This is a schematic diagram of a vertical cross-section of an intermediate product obtained from an intermediate step in a method for manufacturing a three-dimensional memory according to some embodiments of this application, taken along a plane perpendicular to the substrate and parallel to a second direction.

[0149] S1200: Remove the insulating layer in the capacitor preset area 200 again, and manufacture the first electrode 70, the second electrode, and the dielectric layer of the capacitor to complete the manufacturing of the capacitor.

[0150] Some embodiments of this application also provide a manufacturing method, which further includes the following steps after forming the dummy transistor:

[0151] Within the capacitor preset area, a dummy capacitor is removed to form an eighth trench. Using the eighth trench T8, a sacrificial layer is etched along a first direction, making the sacrificial layer concave inwards than the adjacent insulating layer in the first direction, forming a ninth trench T9. A first conductive material is deposited within the eighth trench T8 and the ninth trench T9 to form the first electrode of the capacitor. The material to be replaced continues to be filled, filling the ninth trench T9 and only partially filling the eighth trench T8. The material to be replaced is etched along the first direction, and a portion of the material to be replaced within the ninth trench T9 is removed. Simultaneously, the first conductive material located on the sidewall of the eighth trench T8 is etched away, disconnecting the first electrodes of the capacitors in different layers. Figures 13A-13F As shown. After forming the first electrode of the capacitor, other steps are included to form the memory device; details can be found in [reference needed]. Figures 4A-12B The corresponding instruction manual content.

[0152] The second method of this application is based on post-formed capacitors. For example, transistors with IGZO semiconductor layers are formed first. To reduce the damage to the IGZO semiconductor layer caused by the relatively high temperatures (>400°C) in the post-processing of the capacitor, the first electrode material (such as TiN) of the capacitor can be formed first when forming the capacitor vias. This can reduce one high-temperature process to some extent, requiring only one additional process for forming the second electrode material, such as TiN. For devices using low-temperature capacitor materials, this post-formed capacitor-based parasitic channel removal scheme can significantly reduce temperature damage to the IGZO semiconductor layer, etc.

[0153] Some embodiments of this application also provide an electronic device, including the memory provided in some embodiments of this application as described above.

[0154] In some implementations, the electronic device may include a storage device, a smartphone, a computer, a tablet computer, an artificial intelligence device, a wearable device, or a power bank.

[0155] While the embodiments disclosed in this application are as described above, the content is merely for the purpose of facilitating understanding of this application and is not intended to limit this application. Any person skilled in the art to which this application pertains may make any modifications and changes in the form and details of the implementation without departing from the spirit and scope disclosed in this application; however, the scope of protection of this application shall still be determined by the scope defined in the appended claims.

Claims

1. A method for manufacturing a three-dimensional memory, characterized in that, Includes the following steps: An insulating layer and a sacrificial layer are alternately formed along a third direction perpendicular to the substrate to form a stacked structure, which is divided into a bit line preset region, a transistor preset region and a capacitor preset region arranged along a first direction parallel to the substrate. A dummy transistor is formed within the transistor preset region, and a dummy capacitor is formed within the capacitor preset region. Each conductive layer is formed by replacing the material of the sacrificial layer with a conductive material; Within the capacitor preset area, a first isolation layer is formed between two adjacent dummy capacitors in the second direction, wherein the second direction intersects the first direction and is perpendicular to the third direction. Within the transistor preset region, a second isolation layer is formed between two adjacent dummy transistors in the second direction, and the material forming the first isolation layer is different from the material forming the second isolation layer; Remove the dummy transistor; Form a preset semiconductor layer, gate insulating layer, and word lines; Remove the dummy capacitor; Simultaneously, the insulating layer and the preset semiconductor layer are etched away from the bit line preset region and the capacitor preset region along the first direction until the etching stops at the position of the gate insulating layer, so that the preset semiconductor layer is broken at each of the insulating layers along the third direction, forming mutually disconnected semiconductor layers.

2. The manufacturing method according to claim 1, characterized in that, The formation of dummy transistors and dummy capacitors includes: A transistor hole is formed in the transistor preset region and a capacitor hole is formed in the capacitor preset region, the transistor hole and the capacitor hole being arranged along the first direction; An insulating material film is deposited on the bottom and sidewalls of the transistor hole and the capacitor hole to form a protective layer; A protective layer of material to be replaced is deposited to cover the transistor aperture and the capacitor aperture to form the dummy transistor and the dummy capacitor, respectively.

3. The manufacturing method according to claim 2, characterized in that, The formation of each conductive layer includes: A plurality of first trenches are formed in the stacked structure, extending along the first direction and penetrating the stacked structure, the first trenches separating two adjacent dummy transistors in the second direction and separating two adjacent dummy capacitors in the second direction; The sacrificial layer is removed by etching along the second direction using the first trench, forming multiple empty trenches; Multiple empty slots are filled with conductive material to form each of the conductive layers.

4. The manufacturing method according to claim 3, characterized in that, It also includes forming a transistor, and prior to forming the transistor, the following steps are included: The first trench within the preset area of ​​the capacitor is filled with insulating material to form the first isolation layer; Within the transistor preset region, each of the conductive layers is etched along the second direction using the first trench until the position of the dummy transistor is reached, forming a second trench. Within the transistor preset region, the first trench and the second trench are filled with an insulating material different from the first isolation layer to form the second isolation layer; In the second direction, the size of the second isolation layer between adjacent dummy transistors is larger than the size of the first isolation layer between adjacent dummy capacitors.

5. The manufacturing method according to claim 4, characterized in that, The steps for forming the transistor include: Within the transistor preset area, the dummy transistor and the protective layer are removed, exposing the conductive layer along the sidewall in the third direction, forming a third trench; By using the third trench to etch each insulating layer along the first direction, the upper and lower surfaces of the conductive layer and the sidewalls of the insulating layer along the third direction are exposed, forming a fourth trench; A semiconductor material thin film is deposited along the exposed upper and lower surfaces of the conductive layer and along the exposed sidewalls of the insulating and conductive layers in the third direction to form a preset semiconductor layer for the transistor. A gate insulating layer thin film is deposited to cover the predetermined semiconductor layer to form a gate insulating layer; A conductive material is filled to cover the gate insulating layer, forming the gate.

6. The manufacturing method according to claim 5, characterized in that, The process of breaking the preset semiconductor layer at each insulating layer along the third direction includes the following steps: Within the capacitor preset area, the dummy capacitor and protective layer are removed to form the fifth trench; By using the fifth trench to etch each insulating layer laterally along the first direction, the semiconductor layer at each insulating layer is exposed, forming the sixth trench; Within the bit line preset area, each insulating layer is laterally etched along the first direction to expose the semiconductor layer at each insulating layer, forming the seventh trench; Simultaneously, using the sixth and seventh trenches, the semiconductor layer is etched away from both sides of the annular semiconductor layer at the insulating layer until the gate insulating layer is reached, so that the semiconductor layer is broken at each insulating layer in the third direction.

7. The manufacturing method according to claim 1, characterized in that, After the dummy transistor is formed, the following steps are also included: Within the capacitor preset area, the dummy capacitor is removed to form the eighth trench; Using the eighth trench, the sacrificial layer is etched along the first direction, such that the sacrificial layer is recessed in the first direction compared to the adjacent insulating layer, forming the ninth trench; In the eighth and ninth trenches, a first conductive material is deposited to form the first electrode of the capacitor; Continue filling with the material to be replaced, filling the ninth groove and only partially filling the eighth groove; The material to be replaced is etched away, and at the same time the first conductive material located on the sidewall of the eighth trench is etched away, so that the first electrode of the capacitor in different layers is disconnected.

8. A three-dimensional memory, characterized in that, The invention includes a substrate and multiple layers of memory cells stacked at intervals in a third direction perpendicular to the substrate. Each memory cell layer includes at least two memory cells spaced apart in a second direction and extending along a first direction. Each memory cell includes a transistor and a capacitor arranged along the first direction. The first direction intersects the second direction and is perpendicular to the third direction. It also includes a word line and a gate insulating layer extending along the third direction, and a semiconductor layer located on the side of the gate insulating layer away from the word line, the semiconductor layer being disconnected between two adjacent memory cells, the semiconductor layer serving as the active layer of the transistor; the gate insulating layer having an isolation portion between two adjacent memory cells, the isolation portion separating the semiconductor layer of the two adjacent memory cells; In a plane passing through a storage cell and parallel to the substrate, an isolation layer is included between the two storage cells. The isolation layer includes a first isolation layer between two adjacent capacitors in the second direction and a second isolation layer between two adjacent transistors in the second direction. The first isolation layer is made of a different material than the second isolation layer.

9. The three-dimensional memory according to claim 8, characterized in that, The dimension of the first isolation layer along the second direction is smaller than the dimension of the second isolation layer along the second direction.

10. The three-dimensional memory according to claim 8, characterized in that, The first isolation layer is made of silicon oxide, and the second isolation layer is made of silicon nitride.

11. The three-dimensional memory according to claim 8, characterized in that, In the region between two adjacent memory cells in the third direction and in a plane parallel to the substrate, there is a first isolation layer and a second isolation layer between two adjacent gate insulating layers in the second direction.

12. The three-dimensional memory according to claim 11, characterized in that, The first isolation layer is in contact with the gate insulating layer, and the second isolation layer is located on the side of the first isolation layer away from the gate insulating layer.

13. The three-dimensional memory according to claim 8, characterized in that, The transistors of the memory cells stacked vertically along the third direction are connected to the same word line, and the gate of the transistor is part of the connected word line.

14. An electronic device, characterized in that, Includes a three-dimensional memory according to any one of claims 8-13.

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