Semiconductor memory device and manufacturing method thereof

Abstract

The embodiment of the invention provides a semiconductor memory device and a manufacturing method thereof, and relates to the field of semiconductors, and the semiconductor memory device comprises a substrate, a plurality of stacked structures, a word line, a bit line and a first isolation layer. The plurality of stacked structures are located on the substrate and are isolated from one another in the vertical direction, the plurality of stacked structures comprise semiconductor layers, and each semiconductor layer comprises a first doped region, a channel region and a second doped region; the word line extends along the vertical direction and is adjacent to the channel region; the bit line extends along the horizontal direction and is electrically connected with the first doped region; and the first isolation layer is located between the adjacent bit lines, and the material of the first isolation layer comprises a semiconductor material. According to the semiconductor memory device provided by the embodiment of the invention, the electric coupling between the bit lines can be reduced.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor memory device and a method for manufacturing the same. Background Art

[0002] With the development of semiconductor technology, semiconductor memory devices are widely used in various electronic devices. Semiconductor memory devices include word lines (WL), bit lines (BL), transistors and capacitors. The gate of the transistor is connected to the word line, the drain of the transistor is connected to the bit line, and the source of the transistor is connected to the capacitor. The word line controls the opening or closing of the transistor, and the bit line reads and writes data in the capacitor.

[0003] However, electrical coupling easily occurs between adjacent bit lines, which degrades the performance of the semiconductor memory device. Summary of the invention

[0004] The embodiments of the present application provide a semiconductor memory device and a method for manufacturing the same, so as to achieve the effect of reducing coupling between bit lines.

[0005] In a first aspect, an embodiment of the present application provides a semiconductor memory device, comprising: a substrate; a plurality of stacked structures located on the substrate and isolated from each other in a vertical direction, the plurality of stacked structures comprising a semiconductor layer, the semiconductor layer comprising a first doped region, a channel region, and a second doped region; a word line extending along the vertical direction and adjacent to the channel region; a bit line extending along a horizontal direction and electrically connected to the first doped region; a first isolation layer located between adjacent bit lines, the material of the first isolation layer comprising a semiconductor material.

[0006] In a possible implementation manner, the first isolation layer surrounds a portion of the bit line and a portion of the first doping region.

[0007] In a possible implementation manner, the first isolation layer covers a portion of an upper surface, a portion of a lower surface, and a portion of a side surface of the bit line, and the upper surface and the lower surface of the bit line are opposite to each other along the vertical direction.

[0008] In a possible implementation, the stacked structure further includes an insulating layer disposed between adjacent semiconductor layers, and surfaces of the insulating layer and the first isolation layer facing each other overlap.

[0009] In a possible implementation, the stack structure further includes a second isolation layer, where the second isolation layer is disposed between the semiconductor layer and the first isolation layer.

[0010] In a possible implementation, along the vertical direction, an orthographic projection of the first isolation layer on the substrate and an orthographic projection of the channel region on the substrate are spaced apart.

[0011] In a possible implementation manner, the device further includes a first electrode, a second electrode, and a dielectric layer disposed between the first electrode and the second electrode, and the first electrode is electrically connected to the second doping region.

[0012] In a possible implementation manner, it further includes a first metal silicide and a second metal silicide; the first metal silicide is located between the bit line and the first doped region, and the second metal silicide is located between the first electrode and the second doped region.

[0013] In a possible implementation, the word line includes a first word line and a second word line; the first word line is adjacent to a first side of the channel region, the second word line is adjacent to a second side of the channel region, and the second side of the channel region is opposite to the first side along an extension direction of the bit line.

[0014] The semiconductor memory device provided in the embodiment of the present application includes a substrate, a plurality of stacked structures, a word line, a bit line and a first isolation layer. Among them, the plurality of stacked structures are located on the substrate and isolated from each other in the vertical direction, and the plurality of stacked structures include a semiconductor layer, and the semiconductor layer includes a first doped region, a channel region and a second doped region. The word line extends in the vertical direction and is adjacent to the channel region, and the bit line extends in the horizontal direction and is electrically connected to the first doped region. The first isolation layer is located between adjacent bit lines, and the material of the first isolation layer includes a semiconductor material. By isolating adjacent bit lines using semiconductor materials, the electrical coupling between adjacent bit lines can be reduced, thereby improving the performance of the semiconductor memory device.

[0015] In a second aspect, an embodiment of the present application provides a method for manufacturing a semiconductor memory device, comprising: providing a substrate; forming a stacking structure, a word line, a bit line and a first isolation layer; wherein the stacking structure is located on the substrate and isolated from each other in a vertical direction, the stacking structure comprises a semiconductor layer, the semiconductor layer comprises a first doping region, a channel region and a second doping region; the word line extends along the vertical direction and is adjacent to the channel region; the bit line extends along the horizontal direction and is electrically connected to the first doping region; the first isolation layer is located between adjacent bit lines, and the material of the first isolation layer comprises a semiconductor material.

[0016] In a possible implementation manner, the first isolation layer surrounds a portion of the bit line and a portion of the first doping layer.

[0017] In a possible implementation manner, the first isolation layer covers a portion of an upper surface, a portion of a lower surface, and a portion of a side surface of the bit line, and the upper surface and the lower surface of the bit line are opposite to each other along the vertical direction.

[0018] In a possible implementation, forming a stacked structure, a word line, a bit line and a first isolation layer further includes: forming an insulating layer disposed between adjacent semiconductor layers, wherein surfaces of the insulating layer and the first isolation layer facing each other overlap.

[0019] In a possible implementation, forming a stacked structure, a word line, a bit line and a first isolation layer further includes: forming a second isolation layer, wherein the second isolation layer is disposed between the semiconductor layer and the first isolation layer.

[0020] In a possible implementation, along the vertical direction, an orthographic projection of the first isolation layer on the substrate and an orthographic projection of the channel region on the substrate are spaced apart.

[0021] In a possible implementation, forming a stacked structure, a word line, a bit line and a first isolation layer also includes: forming a first electrode, a second electrode, and a dielectric layer disposed between the first electrode and the second electrode, wherein the first electrode is electrically connected to the second doped region.

[0022] In one possible implementation, forming a stacked structure, a word line, a bit line and a first isolation layer also includes: forming a first metal silicide and a second metal silicide, the first metal silicide being located between the bit line and the first doped region, and the second metal silicide being located between the first electrode and the second doped region.

[0023] In a possible implementation, the word line includes a first word line and a second word line; the first word line is adjacent to a first side of the channel region, the second word line is adjacent to a second side of the channel region, and the second side of the channel region is opposite to the first side along an extension direction of the bit line.

[0024] In the method for manufacturing a semiconductor memory device in an embodiment of the present application, a plurality of stacked structures, word lines, bit lines and a first isolation layer are formed on a substrate. The plurality of stacked structures are isolated from each other in the vertical direction, and the plurality of stacked structures include a semiconductor layer, and the semiconductor layer includes a first doping region, a channel region and a second doping region; the word line extends in the vertical direction and is adjacent to the channel region; the bit line extends in the horizontal direction and is electrically connected to the first doping region; the first isolation layer is located between adjacent bit lines, and the material of the first isolation layer includes a semiconductor material. By isolating adjacent bit lines using semiconductor materials, the electrical coupling between adjacent bit lines can be reduced, thereby improving the performance of the semiconductor memory device. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0026] Figure 1 A three-dimensional diagram of a semiconductor memory device provided for the present application;

[0027] Figure 2 A cross-sectional view of a semiconductor memory device provided for the present application;

[0028] Figure 3 A three-dimensional diagram after forming the initial layer and the insulating layer provided in the present application;

[0029] Figure 4 A top view after forming the initial layer and the insulating layer provided in the present application;

[0030] Figure 5 A cross-sectional view after forming the initial layer and the insulating layer provided in the present application;

[0031] Figure 6 A three-dimensional diagram after forming a word line provided by the present application;

[0032] Figure 7 A top view after forming a word line provided by the present application;

[0033] Figure 8 A three-dimensional diagram after forming the first doped region provided in the present application;

[0034] Fig. 9 A top view after forming the first doped region provided in the present application;

[0035] Fig.10 A cross-sectional view after forming the first doped region provided in the present application;

[0036] Fig.11 A three-dimensional diagram after forming the bit line provided by the present application;

[0037] Fig.12 A top view after forming a bit line provided by the present application;

[0038] Fig.13 A cross-sectional view after forming a bit line provided by the present application;

[0039] Fig.14 A three-dimensional image after removing part of the insulating layer provided for this application;

[0040] Fig.15 A cross-sectional view after removing part of the insulating layer provided in the present application;

[0041] Fig.16 A three-dimensional diagram after forming the first isolation layer provided in the present application;

[0042] Fig.17 A top view after forming the first isolation layer provided in the present application;

[0043] Fig.18 A cross-sectional view after forming the first isolation layer provided in the present application;

[0044] Fig.19 A three-dimensional image after forming the second doping region provided in the present application;

[0045] Fig. 20 A top view after forming the second doping region provided in the present application;

[0046] Fig.21 A cross-sectional view after forming the second doping region provided in the present application;

[0047] Fig. 22 A three-dimensional diagram after forming the second electrode provided in the present application;

[0048] Fig.23 A top view after forming the second electrode provided in the present application;

[0049] Fig.24 This is a cross-sectional view after the second electrode is formed provided in the present application.

[0050] Description of reference numerals:

[0051] 10-semiconductor layer; 11-first doping region; 12-channel region; 13-second doping region; 14-initial layer;

[0052] 20-first word line; 21-first gate dielectric layer;

[0053] 30-a second word line; 31-a second gate dielectric layer;

[0054] 40-bit line;

[0055] 50- first isolation layer;

[0056] 60-insulation layer;

[0057] 70- second isolation layer;

[0058] 81-first metal silicide; 82-second metal silicide;

[0059] 91-first electrode; 92-second electrode; 93-dielectric layer;

[0060] 100-substrate;

[0061] 110 - the third isolation layer. DETAILED DESCRIPTION

[0062] Exemplary embodiments will be described in detail herein, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, the same numbers in different drawings represent the same or similar elements unless otherwise indicated. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present application. Instead, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the appended claims.

[0063] In the related art, adjacent bit lines are often isolated by an interlayer dielectric (ILD), and electrical coupling is likely to occur between adjacent bit lines, such as parasitic capacitance formed between adjacent bit lines and the interlayer dielectric layer, which affects the performance of semiconductor memory devices.

[0064] The semiconductor memory device provided in the embodiment of the present application sets a first isolation layer between adjacent bit lines. The material of the first isolation layer includes semiconductor material. The semiconductor material is used to isolate adjacent bit lines, which can reduce the electrical coupling between adjacent bit lines, thereby improving the performance of the semiconductor memory device.

[0065] Reference Figure 1 , Figure 2 , Fig.23 and Fig.24 , an embodiment of the present application provides a semiconductor memory device, the semiconductor memory device is, for example, a dynamic random access memory (DRAM). Figure 1 and Fig.24 As shown, the semiconductor memory device includes a substrate 100, a plurality of stacked structures, word lines, bit lines 40, and a first isolation layer 50. The substrate 100 provides support for the structures thereon, such as the stacked structures, word lines, bit lines 40, and the first isolation layer 50. The substrate 100 is, for example, a silicon substrate, a silicon-containing (such as silicon germanium) substrate, or a silicon-on-insulator (such as Silicon On Insulator, SOI) substrate.

[0066] A plurality of stacked structures are located on a substrate 100 and are isolated from each other in a vertical direction. The plurality of stacked structures include a semiconductor layer 10. The semiconductor layer 10 includes a first doping region 11, a channel region 12, and a second doping region 13. The plurality of stacked structures are arranged at intervals on the substrate 100. The arrangement direction of the plurality of stacked structures is as follows: Figure 1 As shown in D3.

[0067] like Fig.23As shown, at least the third isolation layer 110 is filled between adjacent stacked structures, and the third isolation layer 110 is used to isolate the stacked structures from each other. The third isolation layer 110 is also located on the substrate 100 and extends in the vertical direction to ensure that the stacked structures are not connected to each other in the vertical direction. Exemplarily, the top surface of the third isolation layer 110 can be higher than or flush with the top surface of the stacked structure. The top surface refers to the surface away from the substrate 100, and the vertical direction refers to the direction perpendicular to the top surface of the substrate 100, such as Figure 1 As shown in D2 in the figure, the material of the third isolation layer 110 includes insulating materials, such as silicon oxide, silicon nitride, silicon carbonitride, etc.

[0068] Each stacked structure includes a semiconductor layer 10, for example, each stacked structure includes at least two semiconductor layers 10, and these semiconductor layers 10 are arranged at intervals in the vertical direction. The semiconductor layer 10 in each stacked structure can be in contact with the substrate 100, or can be spaced from the substrate 100. The material of the semiconductor layer 10 includes semiconductor materials, such as single crystal silicon, polycrystalline silicon, amorphous silicon, etc.

[0069] Each semiconductor layer 10 includes a first doping region 11, a channel region 12, and a second doping region 13, which are arranged in sequence. That is, the first doping region 11 and the second doping region 13 are connected to both sides of the channel region 12. The first doping region 11, the channel region 12, and the second doping region 13 are adjacent to each other in sequence and are parallel to the top surface of the substrate 100. The arrangement direction of the first doping region 11, the channel region 12, and the second doping region 13 is as follows: Figure 1 The D1 direction shown can also be considered as the extension direction of the semiconductor layer 10 .

[0070] The surfaces of the first doping region 11 and the channel region 12 facing each other may overlap, for example, completely overlap, and the surfaces of the second doping region 13 and the channel region 12 facing each other may overlap, for example, completely overlap. Both the first doping region 11 and the second doping region 13 may be heavily doped regions, for example, doping is achieved by ion implantation. The first doping region 11 may be used as a drain region (Drain), which is connected to the bit line 40, and the second doping region 13 may be used as a source region (Source), which is connected to a capacitor.

[0071] In order to achieve mutual isolation between adjacent semiconductor layers 10 in the same stacked structure, the stacked structure further includes an insulating layer 60, which is disposed between adjacent semiconductor layers 10. The insulating layer 60 is at least filled between adjacent semiconductor layers 10, and is in full contact with the surfaces of two adjacent semiconductor layers 10 facing each other, so as to ensure the isolation effect between the semiconductor layers 10. The material of the insulating layer 60 includes, for example, silicon oxide, silicon nitride, phosphosilicate glass, etc.

[0072] Continue reading Figure 1 , Figure 2 and Fig.24 , the bit line 40 is arranged on the substrate 100 and extends in a horizontal direction, which is parallel to the top surface of the substrate 100. The bit line 40 is electrically connected to the first doping region 11, that is, the bit line 40 and the first doping region 11 can be electrically conductive. In some possible implementations, the height of the bit line 40 and the semiconductor layer 10 are adapted, the top surface of the bit line 40 is higher than the bottom surface of the semiconductor layer 10 to which it is connected, and is lower than or flush with the top surface of the semiconductor layer 10 to which it is connected; or, the bottom surface of the bit line 40 is higher than or flush with the bottom surface of the semiconductor layer 10 to which it is connected, and is lower than the top surface of the semiconductor layer 10 to which it is connected. Specifically, the top surface of the bit line 40 is flush with the top surface of the semiconductor layer 10 to which it is connected, and the bottom surface of the bit line 40 is flush with the bottom surface of the semiconductor layer 10 to which it is connected, that is, the bit line 40 and the semiconductor layer 10 are arranged in the same layer, which is convenient for the manufacture of the bit line 40 and can also improve the transmission performance between the bit line 40 and the corresponding semiconductor layer 10.

[0073] In some possible examples, the extending direction of the bit line 40 is parallel to the arrangement direction of the plurality of stacked structures, so that the bit line 40 can connect a plurality of semiconductor layers 10, which are located in different stacked structures, to simplify the structure of the semiconductor memory device, thereby facilitating the improvement of storage density. Figure 1 The bit line 40 may be a single-layer structure or a stacked-layer structure. For example, the bit line 40 includes a first conductor layer, and the material of the first conductor layer includes a metal material, such as a low-resistance metal material such as tungsten, aluminum or copper. The specific structure of the bit line 40 in the embodiment of the present application is not limited.

[0074] Among them, Figure 2 As shown, a first metal silicide 81 is further provided between the bit line 40 and the first doped region 11, that is, the semiconductor memory device further includes a first metal silicide 81, and the first metal silicide 81 is located between the bit line 40 and the first doped region 11. The first metal silicide 81 contacts both the bit line 40 and the first doped region 11, and realizes conduction between the bit line 40 and the first doped region 11. By providing the first metal silicide 81, the contact resistance between the bit line 40 and the first doped region 11 can be reduced. The material of the first metal silicide 81 includes, for example, tungsten silicide, titanium silicide, cobalt silicide, etc.

[0075] It is understandable that there may be a plurality of bit lines 40, which are arranged at intervals in the vertical direction to avoid connection between adjacent bit lines 40. The number of bit lines 40 may be consistent with the number of semiconductor layers 10 in the stacked structure, so that each stacked structure can be led out of each semiconductor layer 10 therein through a plurality of bit lines 40.

[0076] Continue reading Figure 1 , Figure 2 and Fig.24 The word line is located on the substrate 100 and extends in a vertical direction. Specifically, the word line extends in a direction away from the top surface of the substrate 100. The word line is adjacent to the channel region 12 and is used to form a gate to control the opening or closing of the channel region 12. The word line can be opposite to the channel regions 12 of multiple semiconductor layers 10 in the same stacked structure to simultaneously control the opening or closing of multiple channel regions 12.

[0077] In some possible implementations, the word line includes a first word line 20 and a second word line 30; the first word line 20 is adjacent to a first side of the channel region 12, the second word line 30 is adjacent to a second side of the channel region 12, and the second side and the first side of the channel region 12 are opposite to each other along the extension direction of the bit line 40. Figure 1 As shown, the first word line 20 and the second word line 30 are respectively located at the first side and the second side of the channel region 12, wherein the first word line 20 is adjacent to the first side of the channel region 12 and is opposite to at least a portion of the channel region 12, and the second word line 30 is adjacent to the second side of the channel region 12 and is opposite to at least a portion of the channel region 12. The first side of the channel region 12 and the second side of the channel region 12 are opposite to each other along the extension direction of the bit line 40, so that the channel region 12 can be controlled by the two word lines.

[0078] It can be understood that, in the first word line 20 and the second word line 30, the region directly opposite to the channel region 12 along the extension direction of the bit line 40 forms a gate. The structures of the first word line 20 and the second word line 30 can be the same or different. The first word line 20 and the second word line 30 can be a single layer or a stacked layer, for example, including a second conductor layer, the material of the second conductor layer includes a semiconductor material such as doped polysilicon, doped amorphous silicon, or includes a low-resistance metal material such as tungsten, aluminum or copper, and the embodiment of the present application is not limited to this.

[0079] In order to realize the control function of the first word line 20 and the second word line 30, the semiconductor memory device further includes a first gate dielectric layer 21 and a second gate dielectric layer 31, wherein the first gate dielectric layer 21 is at least arranged between the first word line 20 and the channel region 12, and the second gate dielectric layer 31 is at least arranged between the second word line 30 and the channel region 12. Exemplarily, the first gate dielectric layer 21 extends in the vertical direction, that is, the first gate dielectric layer 21 is also arranged between the first word line 20 and the insulating layer 60. The second gate dielectric layer 31 extends in the vertical direction, that is, the second gate dielectric layer 31 is also arranged between the second word line 30 and the insulating layer 60. The materials of the first gate dielectric layer 21 and the second gate dielectric layer 31 include silicon oxide, hafnium oxide, etc. Among them, along the extension direction of the bit line 40, the thickness of the first gate dielectric layer 21 and the second gate dielectric layer 31 can be equal.

[0080] Continue reading Figure 1 and Figure 2The semiconductor memory device further includes a first isolation layer 50, which is located between adjacent bit lines 40. For example, the first isolation layer 50 is at least filled between adjacent bit lines 40. The material of the first isolation layer 50 includes semiconductor material, and the semiconductor material includes, for example, SiGe, SiC, SiP, Si, etc. The first isolation layer 50 is used to isolate adjacent bit lines 40, avoid connection between adjacent bit lines 40, and ensure that adjacent bit lines 40 are isolated from each other; at the same time, the material of the first isolation layer 50 includes semiconductor material, which can reduce the electrical coupling between adjacent bit lines 40, thereby improving the performance of the semiconductor memory device.

[0081] In the example where the insulating layer 60 is disposed between adjacent semiconductor layers 10, the surfaces of the insulating layer 60 and the first isolation layer 50 facing each other overlap, for example, completely overlap. In this way, the insulating layer 60 isolates the adjacent semiconductor layers 10, the first isolation layer 50 isolates the adjacent bit lines 40, and the bit lines 40 and the semiconductor layers 10 are disposed in the same layer, and the insulating layer 60 and the first isolation layer 50 are disposed in the same layer, which can ensure that the overall structure formed by the bit lines 40 and the semiconductor layers 10 is reliably isolated from each other in the vertical direction and will not be electrically conductive.

[0082] Continue reading Figure 1 , Figure 2 and Fig.24 , along the vertical direction, the orthographic projection of the first isolation layer 50 on the substrate 100 is spaced from the orthographic projection of the channel region 12 on the substrate 100. In this way, the surface of the first isolation layer 50 facing the insulating layer 60 is located on the side of the channel region 12 away from the second doping region 13, that is, along the vertical direction, the first isolation layer 50 and the insulating layer 60 do not overlap, which can prevent the first isolation layer 50 from extending below the channel region 12, facilitate the formation of the first word line 20 and the second word line 30 beside the channel region 12, and ensure the gate control capability of the first word line 20 and the second word line 30.

[0083] In some possible examples, the first isolation layer 50 surrounds part of the bit line 40, for example, the surface of the first isolation layer 50 facing the insulating layer 60 is flush with the surface of the bit line 40 facing the semiconductor layer 10, so as to avoid the first isolation layer 50 from contacting and conducting with the semiconductor layer 10. The first isolation layer 50 covers part of the upper surface, part of the lower surface and part of the side surface of the bit line 40, and the upper surface and the lower surface of the bit line 40 are opposite to each other in a vertical direction. Part of the side surface of the bit line 40 refers to the part of the surface of the bit line 40 facing away from the semiconductor layer 10. Along the extension direction of the bit line 40, the width of the first isolation layer 50 is, for example, equal to the width of the insulating layer 60. Specifically, along the extension direction of the bit line 40, the opposite surfaces of the first isolation layer 50 are respectively aligned with the opposite surfaces of the insulating layer 60.

[0084] In some other possible examples, the first isolation layer 50 surrounds a portion of the bit line 40 and a portion of the first doped region 11, that is, the first isolation layer 50 surrounds a portion of the bit line 40 and extends between adjacent first doped regions 11. The first isolation layer 50 covers a portion of the upper surface, a portion of the lower surface, and a portion of the side surface of the bit line 40, the upper surface and the lower surface of the bit line 40 are opposite to each other in a vertical direction, and a portion of the side surface of the bit line 40 refers to a portion of the surface of the bit line 40 that is away from the semiconductor layer 10.

[0085] Furthermore, the first isolation layer 50 also covers a portion of the upper surface and a portion of the lower surface of the first doping region 11, and the upper surface and the lower surface of the first doping region 11 are opposite to each other in a vertical direction. Along the extension direction of the bit line 40, the width of the first isolation layer 50 is, for example, equal to the width of the insulating layer 60. Specifically, along the extension direction of the bit line 40, the opposite surfaces of the first isolation layer 50 are respectively aligned with the opposite surfaces of the insulating layer 60.

[0086] In some possible implementations, the stacked structure further includes a second isolation layer 70, which is disposed between the semiconductor layer 10 and the first isolation layer 50. In this way, the first isolation layer 50 and the semiconductor layer 10 can be prevented from contacting each other, thereby reducing the impact between the first isolation layer 50 and the semiconductor layer 10 and ensuring the performance of the semiconductor memory device. The second isolation layer 70 can also extend between the bit line 40 and the first isolation layer 50 to form an integral film layer, which facilitates the formation of the second isolation layer 70. The material of the second isolation layer 70 includes silicon oxide, a high dielectric constant material, and the like.

[0087] Continue reading Figure 1 and Figure 2 The semiconductor memory device further includes a first electrode 91, a second electrode 92, and a dielectric layer 93 disposed between the first electrode 91 and the second electrode 92. The first electrode 91 is electrically connected to the second doping region 13. The first electrode 91, the second electrode 92 and the dielectric layer 93 are arranged to form a capacitor structure to realize the storage function of the semiconductor memory device. Among them, the insulating layer 60 can also extend between adjacent first electrodes 91 to isolate each first electrode 91.

[0088] Among them, the first electrode 91 is electrically connected to the second doping region 13, for example, the first electrode 91 is arranged on a side of the second doping region 13 away from the first doping region 11, and is electrically conductive with the second doping region 13. The first electrode 91, for example, covers the side of the second doping region 13, part of the upper surface and part of the lower surface of the insulating layer 60, and the upper surface and the lower surface of the insulating layer 60 are arranged opposite to each other in the vertical direction. A plurality of first electrodes 91 can be provided, so that a first electrode 91 is correspondingly provided beside each second doping region 13. One second electrode 92 is provided, that is, a plurality of first electrodes 91 can share one second electrode 92. The materials of the first electrode 91 and the second electrode 92 include low-resistance metal materials such as titanium nitride, aluminum, titanium, copper or tungsten, preferably titanium nitride. The material of the dielectric layer 93 includes high dielectric constant materials such as zirconium oxide, aluminum oxide, and hafnium oxide.

[0089] Some possible examples include Figure 2 As shown, the semiconductor memory device further includes a second metal silicide 82, which is located between the first electrode 91 and the second doping region 13, and the second metal silicide 82 is in contact with both the first electrode 91 and the second doping region 13, and realizes conduction between the first electrode 91 and the second doping region 13. The contact resistance between the first electrode 91 and the second doping region 13 can be reduced by providing the second metal silicide 82. The material of the second metal silicide 82 includes, for example, tungsten silicide, titanium silicide, cobalt silicide, etc., and the material of the second metal silicide 82 can be the same as that of the first metal silicide 81.

[0090] The semiconductor memory device provided by the embodiment of the present application includes a substrate 100, a plurality of stacked structures, a word line, a bit line 40 and a first isolation layer 50. The plurality of stacked structures are located on the substrate 100 and isolated from each other in the vertical direction. The plurality of stacked structures include a semiconductor layer 10, and the semiconductor layer 10 includes a first doping region 11, a channel region 12 and a second doping region 13. The word line extends in the vertical direction and is adjacent to the channel region 12, and the bit line 40 extends in the horizontal direction and is electrically connected to the first doping region 11. The first isolation layer 50 is located between adjacent bit lines 40, and the material of the first isolation layer 50 includes a semiconductor material. By isolating adjacent bit lines 40 using semiconductor materials, the electrical coupling between adjacent bit lines 40 can be reduced, thereby improving the performance of the semiconductor memory device.

[0091] The present application also provides a method for manufacturing a semiconductor memory device, see Figures 1 to 24 , the preparation method specifically comprises the following steps:

[0092] Step S100: providing a substrate 100 .

[0093] The substrate 100 provides support for the structures thereon, for example, providing support for the stacked structure, the word line, the bit line 40 and the first isolation layer 50. The substrate 100 is, for example, a silicon substrate 100, a silicon-containing (for example, silicon germanium) substrate 100 or a silicon-on-insulator (for example, SOI) substrate 100, etc., which is not limited in the embodiments of the present application.

[0094] Step S200: forming a stack structure, a word line, a bit line 40 and a first isolation layer 50;

[0095] Among them, the stacked structure is located on the substrate 100 and is isolated from each other in the vertical direction. The stacked structure includes a semiconductor layer 10, and the semiconductor layer 10 includes a first doping region 11, a channel region 12 and a second doping region 13; the word line extends in the vertical direction and is adjacent to the channel region 12; the bit line 40 extends in the horizontal direction and is electrically connected to the first doping region 11; the first isolation layer 50 is located between adjacent bit lines 40, and the material of the first isolation layer 50 includes semiconductor material.

[0096] A plurality of stacked structures are formed on the substrate 100 and isolated from each other in the vertical direction. The plurality of stacked structures are arranged on the substrate 100 at intervals so that the plurality of stacked structures are not connected to each other in the vertical direction. The arrangement direction of the plurality of stacked structures is as follows: Figure 1 As shown in D3. The multiple stacked structures include semiconductor layers 10, for example, each stacked structure includes at least two semiconductor layers 10, and these semiconductor layers 10 are arranged at intervals in the vertical direction. The semiconductor layer 10 in each stacked structure can be in contact with the substrate 100, or can be spaced from the substrate 100. The material of the semiconductor layer 10 includes semiconductor materials, such as single crystal silicon, polycrystalline silicon, amorphous silicon, etc.

[0097] Each semiconductor layer 10 includes a first doping region 11, a channel region 12, and a second doping region 13, which are arranged in sequence. That is, the first doping region 11 and the second doping region 13 are connected to both sides of the channel region 12. The first doping region 11, the channel region 12, and the second doping region 13 are adjacent to each other in sequence and are parallel to the top surface of the substrate 100. The arrangement direction of the first doping region 11, the channel region 12, and the second doping region 13 is as follows: Figure 1 The D1 direction shown can also be considered as the extension direction of the semiconductor layer 10 .

[0098] The surfaces of the first doping region 11 and the channel region 12 facing each other may overlap, for example, completely overlap, and the surfaces of the second doping region 13 and the channel region 12 facing each other may overlap, for example, completely overlap. Both the first doping region 11 and the second doping region 13 may be heavily doped regions, for example, doping is achieved by ion implantation. The first doping region 11 may be used as a drain region, which is connected to the bit line 40, and the second doping region 13 may be used as a source region, which is connected to a capacitor.

[0099] The bit line 40 is formed on the substrate 100 and extends in a horizontal direction, which is parallel to the top surface of the substrate 100. The bit line 40 is electrically connected to the first doping region 11, that is, the bit line 40 and the first doping region 11 can be electrically conductive. The height of the bit line 40 and the semiconductor layer 10 are adapted. In some possible implementations, the top surface of the bit line 40 is higher than the bottom surface of the semiconductor layer 10 to which it is connected, and is lower than or flush with the top surface of the semiconductor layer 10 to which it is connected; or, the bottom surface of the bit line 40 is higher than or flush with the bottom surface of the semiconductor layer 10 to which it is connected, and is lower than the top surface of the semiconductor layer 10 to which it is connected. Specifically, the top surface of the bit line 40 is flush with the top surface of the semiconductor layer 10 to which it is connected, and the bottom surface of the bit line 40 is flush with the bottom surface of the semiconductor layer 10 to which it is connected, that is, the bit line 40 and the semiconductor layer 10 are arranged in the same layer, which is convenient for the manufacture of the bit line 40 and can also improve the transmission performance between the bit line 40 and the corresponding semiconductor layer 10.

[0100] Exemplarily, the extending direction of the bit line 40 is parallel to the arrangement direction of the plurality of stacked structures, so that the bit line 40 can connect the plurality of semiconductor layers 10, which are located in different stacked structures, to simplify the structure of the semiconductor memory device, thereby facilitating the improvement of storage density. Figure 1 The bit line 40 may be a single-layer structure or a stacked structure. Exemplarily, the bit line 40 includes a first conductor layer, and the material of the first conductor layer includes a metal material, such as a low-resistance metal material such as tungsten, aluminum or copper. There may be a plurality of bit lines 40, and the plurality of bit lines 40 are arranged at intervals in the vertical direction to avoid connection between adjacent bit lines 40. The number of bit lines 40 may be consistent with the number of semiconductor layers 10 in the stacked structure, so that each stacked structure can be led out of each semiconductor layer 10 therein through a plurality of bit lines 40.

[0101] The word line is formed on the substrate 100 and extends in a vertical direction. Specifically, the word line extends in a direction away from the top surface of the substrate 100. The word line is adjacent to the channel region 12 and is used to form a gate to control the opening or closing of the channel region 12. The word line can be opposite to the channel regions 12 of multiple semiconductor layers 10 in the same stacked structure to simultaneously control the opening or closing of multiple channel regions 12.

[0102] In some possible implementations, the word line includes a first word line 20 and a second word line 30; the first word line 20 is adjacent to a first side of the channel region 12, the second word line 30 is adjacent to a second side of the channel region 12, and the second side and the first side of the channel region 12 are opposite to each other along the extension direction of the bit line 40. Figure 1As shown, the first word line 20 and the second word line 30 are respectively located at the first side and the second side of the channel region 12, wherein the first word line 20 is adjacent to the first side of the channel region 12 and is opposite to at least a portion of the channel region 12, and the second word line 30 is adjacent to the second side of the channel region 12 and is opposite to at least a portion of the channel region 12. The first side of the channel region 12 and the second side of the channel region 12 are opposite to each other along the extension direction of the bit line 40, so that the channel region 12 can be controlled by the two word lines.

[0103] It can be understood that, in the first word line 20 and the second word line 30, the region directly opposite to the channel region 12 along the extension direction of the bit line 40 forms a gate. The structures of the first word line 20 and the second word line 30 can be the same or different. The first word line 20 and the second word line 30 can be a single layer or a stacked layer, for example, including a second conductor layer, the material of the second conductor layer includes a semiconductor material such as doped polysilicon, doped amorphous silicon, or includes a low-resistance metal material such as tungsten, aluminum or copper, and the embodiment of the present application is not limited to this.

[0104] In order to realize the control function of the first word line 20 and the second word line 30, the semiconductor memory device further includes a first gate dielectric layer 21 and a second gate dielectric layer 31, wherein the first gate dielectric layer 21 is at least arranged between the first word line 20 and the channel region 12, and the second gate dielectric layer 31 is at least arranged between the second word line 30 and the channel region 12. Exemplarily, the first gate dielectric layer 21 extends in the vertical direction, that is, the first gate dielectric layer 21 is also arranged between the first word line 20 and the insulating layer 60. The second gate dielectric layer 31 extends in the vertical direction, that is, the second gate dielectric layer 31 is also arranged between the second word line 30 and the insulating layer 60. The materials of the first gate dielectric layer 21 and the second gate dielectric layer 31 include silicon oxide, hafnium oxide, etc. Among them, along the extension direction of the bit line 40, the thickness of the first gate dielectric layer 21 and the second gate dielectric layer 31 can be equal.

[0105] The first isolation layer 50 is formed between adjacent bit lines 40, for example, the first isolation layer 50 is at least filled between adjacent bit lines 40. The material of the first isolation layer 50 includes semiconductor material, and the semiconductor material includes, for example, silicon germanium. The first isolation layer 50 is used to isolate adjacent bit lines 40, avoid connection between adjacent bit lines 40, and ensure that adjacent bit lines 40 are isolated from each other; at the same time, the material of the first isolation layer 50 includes semiconductor material, which can reduce the electrical coupling between adjacent bit lines 40, thereby improving the performance of the semiconductor memory device.

[0106] Continue reading Figures 1 to 24, along the vertical direction, the orthographic projection of the first isolation layer 50 on the substrate 100 is spaced from the orthographic projection of the channel region 12 on the substrate 100. In this way, the surface of the first isolation layer 50 facing the insulating layer 60 is located on the side of the channel region 12 away from the second doping region 13, that is, along the vertical direction, the first isolation layer 50 and the insulating layer 60 do not overlap, which can prevent the first isolation layer 50 from extending below the channel region 12, facilitate the formation of the first word line 20 and the second word line 30 beside the channel region 12, and ensure the gate control capability of the first word line 20 and the second word line 30.

[0107] In some possible examples, the first isolation layer 50 surrounds part of the bit line 40, for example, the surface of the first isolation layer 50 facing the insulating layer 60 is flush with the surface of the bit line 40 facing the semiconductor layer 10, so as to avoid the first isolation layer 50 from contacting and conducting with the semiconductor layer 10. The first isolation layer 50 covers part of the upper surface, part of the lower surface and part of the side surface of the bit line 40, and the upper surface and the lower surface of the bit line 40 are opposite to each other in a vertical direction. Part of the side surface of the bit line 40 refers to the part of the surface of the bit line 40 facing away from the semiconductor layer 10. Along the extension direction of the bit line 40, the width of the first isolation layer 50 is, for example, equal to the width of the insulating layer 60. Specifically, along the extension direction of the bit line 40, the opposite surfaces of the first isolation layer 50 are respectively aligned with the opposite surfaces of the insulating layer 60.

[0108] In some other possible examples, the first isolation layer 50 surrounds part of the bit line 40 and part of the first doping region 11, that is, the first isolation layer 50 surrounds part of the bit line 40 and extends between adjacent first doping regions 11. The first isolation layer 50 covers part of the upper surface, part of the lower surface and part of the side surface of the bit line 40, the upper surface and the lower surface of the bit line 40 are opposite to each other in a vertical direction, and the partial side surface of the bit line 40 refers to the partial surface of the bit line 40 facing away from the semiconductor layer 10. Further, the first isolation layer 50 also covers part of the upper surface and part of the lower surface of the first doping region 11, and the upper surface and the lower surface of the first doping region 11 are opposite to each other in a vertical direction. Along the extension direction of the bit line 40, the width of the first isolation layer 50 is, for example, equal to the width of the insulating layer 60. Specifically, along the extension direction of the bit line 40, the opposite surfaces of the first isolation layer 50 are respectively aligned with the opposite surfaces of the insulating layer 60.

[0109] In the method for manufacturing a semiconductor memory device in the embodiment of the present application, a plurality of stacked structures, word lines, bit lines 40 and a first isolation layer 50 are formed on a substrate 100. The plurality of stacked structures are isolated from each other in the vertical direction, and the plurality of stacked structures include a semiconductor layer 10, the semiconductor layer 10 includes a first doping region 11, a channel region 12 and a second doping region 13; the word lines extend in the vertical direction and are adjacent to the channel region 12; the bit lines 40 extend in the horizontal direction and are electrically connected to the first doping region 11; the first isolation layer 50 is located between adjacent bit lines 40, and the material of the first isolation layer 50 includes a semiconductor material. By isolating adjacent bit lines 40 using semiconductor materials, the electrical coupling between adjacent bit lines 40 can be reduced, thereby improving the performance of the semiconductor memory device.

[0110] In some possible implementations, see Figures 3 to 5 , forming a stacked structure, a word line, a bit line 40 and a first isolation layer 50, and also including: forming an insulating layer 60 disposed between adjacent semiconductor layers 10, and the surfaces of the insulating layer 60 and the first isolation layer 50 facing each other overlap.

[0111] The insulating layer 60 is formed between adjacent semiconductor layers 10 to achieve mutual isolation between adjacent semiconductor layers 10 in the same stacked structure. Exemplarily, the insulating layer 60 is at least filled between adjacent semiconductor layers 10 and is in full contact with the surfaces of two adjacent semiconductor layers 10 facing each other to ensure the isolation effect between the semiconductor layers 10. The material of the insulating layer 60 includes, for example, silicon oxide, silicon nitride, phosphosilicate glass, etc.

[0112] The surfaces of the insulating layer 60 and the first isolation layer 50 facing each other overlap, for example, they are completely overlapped. In this way, the insulating layer 60 isolates the adjacent semiconductor layer 10, and the first isolation layer 50 isolates the adjacent bit line 40. Moreover, the bit line 40 and the semiconductor layer 10 are arranged in the same layer, and the insulating layer 60 and the first isolation layer 50 are arranged in the same layer, which can ensure that the overall structure formed by the bit line 40 and the semiconductor layer 10 is reliably isolated from each other in the vertical direction and will not be electrically conductive.

[0113] In some possible implementations, see Figure 2 , forming a stacked structure, a word line, a bit line 40 and a first isolation layer 50 , and also including: forming a second isolation layer 70 , the second isolation layer 70 is disposed between the semiconductor layer 10 and the first isolation layer 50 .

[0114] The second isolation layer 70 is formed between the semiconductor layer 10 and the first isolation layer 50, which can avoid the first isolation layer 50 from contacting the semiconductor layer 10, thereby reducing the influence between the first isolation layer 50 and the semiconductor layer 10 and ensuring the performance of the semiconductor memory device. The second isolation layer 70 can also extend between the bit line 40 and the first isolation layer 50 to form an integral film layer, which facilitates the formation of the second isolation layer 70. The material of the second isolation layer 70 includes insulating materials such as silicon oxide.

[0115] In some possible implementations, see Figure 22 to Figure 24 , forming a stacked structure, a word line, a bit line 40 and a first isolation layer 50, and also including: forming a first electrode 91, a second electrode 92, and a dielectric layer 93 arranged between the first electrode 91 and the second electrode 92, and the first electrode 91 is electrically connected to the second doping region 13.

[0116] The first electrode 91, the second electrode 92 and the dielectric layer 93 form a capacitor structure to realize the storage function of the semiconductor memory device. The first electrode 91 is electrically connected to the second doping region 13. For example, the first electrode 91 is arranged on a side of the second doping region 13 away from the first doping region 11, and is electrically connected to the second doping region 13. The first electrode 91, for example, covers the side of the second doping region 13, part of the upper surface and part of the lower surface of the insulating layer 60, and the upper surface and the lower surface of the insulating layer 60 are arranged opposite to each other in the vertical direction. A plurality of first electrodes 91 can be provided so that a first electrode 91 is correspondingly provided next to each second doping region 13.

[0117] In some possible examples, one second electrode 92 is provided, that is, a plurality of first electrodes 91 may share one second electrode 92. The materials of the first electrode 91 and the second electrode 92 include low-resistance metal materials such as titanium nitride, aluminum, titanium, copper or tungsten, preferably titanium nitride. The material of the dielectric layer 93 includes high dielectric constant materials such as zirconium oxide, aluminum oxide, and hafnium oxide.

[0118] In some possible implementations, see Figure 2 , forming a stacked structure, a word line, a bit line 40 and a first isolation layer 50, and also including: forming a first metal silicide 81 and a second metal silicide 82, the first metal silicide 81 is located between the bit line 40 and the first doped region 11, and the second metal silicide 82 is located between the first electrode 91 and the second doped region 13.

[0119] The first metal silicide 81 is located between the bit line 40 and the first doped region 11. The first metal silicide 81 contacts both the bit line 40 and the first doped region 11, and realizes conduction between the bit line 40 and the first doped region 11. By providing the first metal silicide 81, the contact resistance between the bit line 40 and the first doped region 11 can be reduced. The material of the first metal silicide 81 includes, for example, tungsten silicide, titanium silicide, cobalt silicide, etc.

[0120] The second metal silicide 82 is located between the first electrode 91 and the second doping region 13. The second metal silicide 82 contacts both the first electrode 91 and the second doping region 13, and realizes conduction between the first electrode 91 and the second doping region 13. The contact resistance between the first electrode 91 and the second doping region 13 can be reduced by providing the second metal silicide 82. The material of the second metal silicide 82 includes, for example, tungsten silicide, titanium silicide, cobalt silicide, etc., and the material of the second metal silicide 82 can be the same as that of the first metal silicide 81.

[0121] Combined with the following Figures 1 to 14 A process for forming a semiconductor memory device will be specifically described.

[0122] See also Figures 3 to 5 , an initial layer 14 and an insulating layer 60 are sequentially stacked and alternately arranged on the substrate 100, and the initial layer 14 and the insulating layer 60 are etched to form an isolation trench. The isolation trench can be formed by a patterning process.

[0123] See also Figure 6 and Figure 7 , word lines are formed in the isolation trenches, the word lines include a first word line 20 located on the first side of the initial layer 14, and a first word line 20 and a second word line 30 located on the second side of the initial layer 14, the second side of the initial layer 14 and the first side are horizontally opposite. Before forming the first word line 20 and the second word line 30, a first gate dielectric layer 21 and a second gate dielectric layer 31 are formed on the first side and the second side of the initial layer 14, respectively. The first gate dielectric layer 21, the second gate dielectric layer 31, the first word line 20 and the second word line 30 can be formed by deposition.

[0124] See also Figures 8 to 10 , a first doping region 11 is formed in the initial layer 14. The first doping region 11 is formed by, for example, performing ion implantation on a partial region of the initial layer 14.

[0125] See also Figures 11 to 13, remove part of the initial layer 14 to form a bit line 40 extending in the horizontal direction, and the bit line 40 is connected to the first doped region 11. Part of the initial layer 14 is removed by etching, and then deposited to form the bit line 40, the bit line 40 extends in the horizontal direction and is connected to the first doped region 11. Before forming the bit line 40, a first metal silicide 81 may also be formed on the corresponding end of the first doped region 11.

[0126] See also Fig.14 and Fig.15 , remove part of the insulating layer 60, and expose the bit line 40 and part of the first doping region 11. For example, remove part of the insulating layer 60 by etching, and expose the upper surface, lower surface and side surface of the bit line 40, and part of the upper surface and lower surface of the first doping region 11.

[0127] See also Figures 16 to 18 , forming a first isolation layer 50, the first isolation layer 50 at least surrounds a portion of the bit line 40. The first isolation layer 50 can be formed by deposition, the first isolation layer 50 surrounds a portion of the bit line 40 and surrounds a portion of the first doping region 11. Before forming the first isolation layer 50, a second isolation layer 70 is also deposited to conformally cover the bit line 40 and the first doping region 11, and the second isolation layer 70 does not fill the area between two bit lines 40 adjacent in the vertical direction.

[0128] See also Figures 19 to 21 , forming a channel region 12 and a second doping region 13 to form a semiconductor layer 10. The second doping region 13 is formed, for example, by ion implantation, and the initial layer 14 between the first doping region 11 and the second doping region 13 forms the channel region 12. Before or after the second doping region 13 is formed, a portion of the initial layer 14 away from the bit line 40 is further etched away, so that one end of the insulating layer 60 away from the first isolation layer 50 is exposed.

[0129] See also Figure 22 to Figure 24 , forming a first electrode 91, a dielectric layer 93 and a second electrode 92 in sequence. Exemplarily, the first electrode 91 is deposited on the exposed surface of the insulating layer 60 and on the side away from the first isolation layer 50. The first electrode 91 conformally covers part of the upper surface, part of the lower surface and the side of the second doping region 13 of the insulating layer 60. The first electrode 91 does not fill the space between the insulating layers 60 adjacent in the vertical direction. The dielectric layer 93 is deposited to form. The dielectric layer 93 conformally covers the surface of the first electrode 91 and the side of the insulating layer 60. The dielectric layer 93 does not fill the remaining space between the insulating layers 60 adjacent in the vertical direction. The second electrode 92 is deposited to form. The second electrode 92 covers the dielectric layer 93 and fills the remaining space between the insulating layers 60 adjacent in the vertical direction. Before forming the first electrode 91, a second metal silicide 82 is also formed on the surface of the second doping region 13 away from the bit line 40.

[0130] It is understandable that in the above process, after forming the first word line 20 and the second word line 30, a third isolation layer 110 may be formed in the isolation trench to isolate the first word line 20 and the second word line 30, and to isolate the initial layer 14 / semiconductor layer 10. For example, after forming the channel region 12 and the second doping region 13, the third isolation layer 110 is deposited in the isolation trench.

[0131] Finally, it should be noted that those skilled in the art will readily conceive of other embodiments of the present invention after considering the specification and practicing the invention disclosed herein. The present invention is intended to cover any variations, uses or adaptations of the present invention, which follow the general principles of the present invention and include common knowledge or customary technical means in the art not disclosed by the present invention, are not limited to the precise structure described above and shown in the drawings, and may be modified and changed in various ways without departing from the scope thereof. The scope of the present invention is limited only by the appended claims.

Claims

1. A semiconductor memory device, characterized in that: include: substrate; A plurality of stacked structures, located on the substrate and isolated from each other in a vertical direction, the plurality of stacked structures comprising a semiconductor layer, the semiconductor layer comprising a first doping region, a channel region, and a second doping region; a word line extending along the vertical direction and adjacent to the channel region; A bit line extending in a horizontal direction and electrically connected to the first doped region; The first isolation layer is located between adjacent bit lines, and the material of the first isolation layer includes semiconductor material.

2. The semiconductor memory device according to claim 1, wherein: The first isolation layer surrounds a portion of the bit line and a portion of the first doping region.

3. The semiconductor memory device according to claim 2, wherein: The first isolation layer covers a portion of an upper surface, a portion of a lower surface, and a portion of a side surface of the bit line, and the upper surface and the lower surface of the bit line are opposite to each other along the vertical direction.

4. The semiconductor memory device according to any one of claims 1 to 3, characterized in that: The stacked structure further includes an insulating layer disposed between adjacent semiconductor layers, and surfaces of the insulating layer and the first isolation layer facing each other overlap.

5. The semiconductor memory device according to any one of claims 1 to 3, characterized in that: The stack structure further includes a second isolation layer disposed between the semiconductor layer and the first isolation layer.

6. The semiconductor memory device according to any one of claims 1 to 3, characterized in that: Along the vertical direction, an orthographic projection of the first isolation layer on the substrate and an orthographic projection of the channel region on the substrate are spaced apart.

7. The semiconductor memory device according to any one of claims 1 to 3, characterized in that: The invention also includes a first electrode, a second electrode, and a dielectric layer disposed between the first electrode and the second electrode, wherein the first electrode is electrically connected to the second doping region.

8. The semiconductor memory device according to claim 7, wherein: Also includes a first metal silicide and a second metal silicide; The first metal silicide is located between the bit line and the first doping region, and the second metal silicide is located between the first electrode and the second doping region.

9. The semiconductor memory device according to any one of claims 1 to 3, characterized in that: The word lines include a first word line and a second word line; The first word line is adjacent to a first side of the channel region, the second word line is adjacent to a second side of the channel region, and the second side and the first side of the channel region are opposite to each other along an extending direction of the bit line.

10. A method for manufacturing a semiconductor memory device, characterized in that: include: providing a substrate; forming a stacked structure, a word line, a bit line and a first isolation layer; Wherein, the stacked structure is located on the substrate and isolated from each other in a vertical direction, and the stacked structure includes a semiconductor layer, and the semiconductor layer includes a first doping region, a channel region, and a second doping region; The word line extends along the vertical direction and is adjacent to the channel region; The bit line extends in a horizontal direction and is electrically connected to the first doped region; The first isolation layer is located between adjacent bit lines, and the material of the first isolation layer includes semiconductor material.

11. The manufacturing method according to claim 10, characterized in that: The first isolation layer surrounds a portion of the bit line and a portion of the first doping layer.

12. The manufacturing method according to claim 11, characterized in that: The first isolation layer covers a portion of an upper surface, a portion of a lower surface, and a portion of a side surface of the bit line, and the upper surface and the lower surface of the bit line are opposite to each other along the vertical direction.

13. The production method according to any one of claims 10 to 12, characterized in that: The stack structure, the word line, the bit line and the first isolation layer are formed, and further comprising: An insulating layer is formed between adjacent semiconductor layers, and surfaces of the insulating layer and the first isolation layer facing each other overlap.

14. The production method according to any one of claims 10 to 12, characterized in that: The stack structure, the word line, the bit line and the first isolation layer are formed, and further comprising: A second isolation layer is formed, the second isolation layer being disposed between the semiconductor layer and the first isolation layer.

15. The production method according to any one of claims 10 to 12, characterized in that: Along the vertical direction, an orthographic projection of the first isolation layer on the substrate and an orthographic projection of the channel region on the substrate are spaced apart.

16. The production method according to any one of claims 10 to 12, characterized in that: The stack structure, the word line, the bit line and the first isolation layer are formed, and further comprising: A first electrode, a second electrode, and a dielectric layer disposed between the first electrode and the second electrode are formed, wherein the first electrode is electrically connected to the second doped region.

17. The manufacturing method according to claim 16, characterized in that: The stack structure, the word line, the bit line and the first isolation layer are formed, and further comprising: A first metal silicide and a second metal silicide are formed, wherein the first metal silicide is located between the bit line and the first doped region, and the second metal silicide is located between the first electrode and the second doped region.

18. The production method according to any one of claims 10 to 12, characterized in that: The word lines include a first word line and a second word line; The first word line is adjacent to a first side of the channel region, the second word line is adjacent to a second side of the channel region, and the second side and the first side of the channel region are opposite to each other along an extending direction of the bit line.

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