Three-dimensional memory device and manufacturing method thereof

Abstract

Embodiments of three-dimensional (3D) memory devices and methods of fabricating the same are disclosed. A disclosed semiconductor device includes: a stack structure including an array region and a contact region; and a gate line slot structure vertically extending through the stack structure and laterally extending along a first lateral direction to divide the stack structure into memory blocks. The gate line gap structure includes: a first dummy channel structure located at a boundary between the array region and the contact region; a first gate line slot segment laterally extending from the first dummy channel structure into the array region; and a second gate line slot segment extending laterally from the first dummy channel structure into the contact region.

Description

Technical Field

[0001] The present disclosure relates generally to the field of semiconductor technology, and more particularly, to a three-dimensional (3D) memory device and a manufacturing method for forming a three-dimensional (3D) memory device. Background Art

[0002] Planar memory cells can be scaled to smaller sizes by improving process technology, circuit design, programming algorithms, and manufacturing processes. However, as the feature size of memory cells approaches a lower limit, planar processes and manufacturing techniques become challenging and costly. As a result, the storage density of planar memory cells approaches an upper limit. Three-dimensional (3D) memory architectures can address density limitations in planar memory cells.

[0003] With the advancement of semiconductor technology, 3D memory devices, such as 3D NAND memory devices, continue to scale more film layers to improve the area utilization of the chip. In some existing 3D NAND memory devices, as the number of film layers increases and the structure of the film layers becomes more complex, the silicon substrate used as a carrier of the film layer may not support the wafer deformation caused by the film stress, which may eventually cause the wafer to be curved. In addition, as the number of oxide / nitride (ON) layers increases, the etching depth of the gate line slit (GLS) increases accordingly, resulting in changes in the critical dimension of the GLS, thereby increasing the risk of structural instability due to stress and other factors. This unstable structure may cause storage finger bending / collapse, wafer bow effect, and affect subsequent 3D memory device manufacturing processes, such as increasing the overlap error in the lithography alignment process. Summary of the invention

[0004] Embodiments of three-dimensional (3D) memory devices and methods of making the same are disclosed herein.

[0005] One aspect of the present disclosure provides a semiconductor device, which includes: a stacked structure, including an array region and a contact region; and a gate line gap structure, which vertically extends through the stacked structure and extends laterally along a first lateral direction to divide the stacked structure into storage blocks, the gate line gap structure including: a first dummy channel structure, located at a boundary between the array region and the contact region; a first gate line gap segment, which extends laterally from the first dummy channel structure to the array region; and a second gate line gap segment, which extends laterally from the first dummy channel structure to the contact region.

[0006] In some embodiments, the semiconductor device further includes: channel structures each vertically extending through the stack structure and located in the array region; and second dummy channel structures each vertically extending through the stack structure and located in the contact region.

[0007] In some embodiments, the stacked structure in the array area includes a conductive layer and a first dielectric layer alternately stacked in a vertical direction; and the stacked structure in the contact area includes: a first contact portion, adjacent to the second gate line gap segment, and including the conductive layer and the first dielectric layer alternately stacked in the vertical direction; and a second contact portion, separated from the second gate line gap segment by the first contact portion, and including the first dielectric layer and the second dielectric layer alternately stacked in the vertical direction.

[0008] In some embodiments, the second dummy channel structures each extend vertically through the first contact portion.

[0009] In some embodiments, a first width of the first dummy channel structure along the first lateral direction is greater than a second width of the first dummy channel structure along a second lateral direction orthogonal to the first lateral direction.

[0010] In some embodiments, the first dummy channel structure includes a high-k layer, a first oxide layer, a nitride layer, a second oxide layer, a semiconductor layer, and a filling structure.

[0011] In some embodiments, the first dummy channel structure includes an oxide structure and a semiconductor segment laterally surrounded by the oxide structure.

[0012] In some embodiments, the oxide structure includes: a convex sidewall surface adjacent to the first gate line slit segment; and a concave sidewall surface adjacent to the second gate line slit segment.

[0013] In some embodiments, each of the first gate line slit segment and the second gate line slit segment includes a wall structure extending laterally in the first lateral direction and insulated from the conductive layer.

[0014] In some embodiments, the semiconductor device further includes: gate line contact structures, each extending vertically in the second contact portion and laterally contacting a corresponding conductive layer in the first contact portion.

[0015] In some embodiments, each gate line contact structure includes: a conductive landing layer in the second contact portion and in laterally contact with the corresponding conductive layer; and a conductive via vertically passing through the second dielectric layer and the first dielectric layer above the conductive landing layer and in contact with the conductive landing layer.

[0016] Another aspect of the present disclosure provides a method for forming a semiconductor device, the method comprising: forming a dielectric stack, the dielectric stack comprising alternating second dielectric layers and first dielectric layers; forming a row of first through holes, the first through holes being laterally aligned along a first lateral direction and each vertically passing through the dielectric stack; forming a sacrificial filling structure in the first through holes; removing the sacrificial filling structure from a first through hole at a boundary between an array area and a contact area; forming a first dummy channel structure in the one first through hole; removing the sacrificial filling structure from other first through holes and removing a portion of the dielectric stack to form a first groove in the array area and a second groove in the contact area; and forming a first gate line gap segment in the first groove and a second gate line gap segment in the second groove.

[0017] In some embodiments, the method further includes: when forming the row of the first through holes, forming a second through hole in the array area, and forming a third through hole adjacent to the first through hole in the contact area; wherein a first distance between adjacent first through holes is less than a second distance between adjacent second through holes.

[0018] In some embodiments, the method further includes: when forming the sacrificial filling structure in the first through hole, forming a sacrificial filling structure in the second through hole and the third through hole.

[0019] In some embodiments, the method further includes: when removing the sacrificial filling structure from the one first through hole, removing the sacrificial filling structure from the second through hole and the third through hole.

[0020] In some embodiments, when forming the first dummy channel structure, a channel structure is formed in the second through hole, and a second dummy channel structure is formed in the third through hole.

[0021] In some embodiments, the method further includes: forming a first sacrificial wall in the first trench and forming a second sacrificial wall in the second trench; removing the first sacrificial wall to reopen the first trench; replacing the second dielectric layer in the array area with a conductive layer through the reopened first trench; removing the second sacrificial wall to reopen the second trench; and replacing a portion of the second dielectric layer in the contact area adjacent to the second trench with a conductive layer.

[0022] In some embodiments, forming the first dummy channel structure includes: forming a first oxide layer on the sidewall of the one first through hole; forming a nitride layer on the first oxide layer; forming a second oxide layer on the nitride layer; forming a semiconductor layer on the second oxide layer; and forming a filling structure on the semiconductor layer to fill the one first through hole.

[0023] In some embodiments, the method further includes: removing portions of the first oxide layer, the nitride layer, and the second oxide layer to expose the side walls of the semiconductor layer in the first trench and the second trench when removing the sacrificial filling structure from other first through holes and removing portions of the dielectric stack; oxidizing the exposed side walls of the semiconductor layer; removing the remaining portion of the nitride layer to form a curved opening when replacing the second dielectric layer in the array area; and oxidizing the portion of the second sacrificial wall exposed by the curved opening.

[0024] In some embodiments, the method further includes: forming a high-k layer on the sidewall of the one first through hole; wherein the first oxide layer is formed on the high-k layer.

[0025] In some embodiments, forming the first gate line gap segment and the second gate line gap segment includes: forming an insulating layer on sidewalls and bottoms of the first trench and the second trench; and forming a wall structure on the insulating layer to fill the first trench and the second trench.

[0026] In some embodiments, the method further includes forming a gate line contact structure that passes through a remaining portion of the dielectric stack in the contact region and contacts a corresponding conductive layer in the contact region.

[0027] In some embodiments, forming the gate line contact structure includes: forming a contact hole through a portion of the dielectric stack to expose a sacrificial layer in the same horizontal plane as the corresponding conductive layer; removing a portion of the sacrificial layer to form a lateral recess to expose the corresponding conductive layer; forming a landing conductive layer in the lateral recess that contacts the corresponding conductive layer; and forming a conductive via in the contact hole to contact the landing conductive layer.

[0028] Another aspect of the present disclosure provides a memory device, which includes: a stacked structure, including: a first conductive / dielectric stack in an array area; a second conductive / dielectric stack in a contact area; and a dielectric stack in the contact area; and a gate line gap structure, which extends vertically through the stacked structure and extends laterally along a first lateral direction to divide the stacked structure into memory blocks, the gate line gap structure including: a first dummy channel structure, located at a boundary between the array area and the contact area; a first gate line gap segment, which extends laterally from the first dummy channel structure to the array area; and a second gate line gap segment, which extends laterally from the first dummy channel structure to the contact area; and channel structures, both extending vertically through the first conductive / dielectric stack; second dummy channel structures, both extending vertically through the second conductive / dielectric stack and adjacent to the second gate line gap segment; and gate line contact structures, both extending vertically in the dielectric stack and laterally contacting the corresponding conductive layer of the second conductive / dielectric stack.

[0029] Those skilled in the art can understand other aspects of the present disclosure based on the specification, claims and drawings of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The accompanying drawings, which are incorporated herein and form a part of the specification, illustrate embodiments of the present disclosure and, together with the description, also serve to explain the principles of the present disclosure and enable those skilled in the relevant art to make and use the present disclosure.

[0031] Figure 1 A block diagram of a system having a memory device according to some aspects of the present disclosure is shown.

[0032] Figure 2A A diagram showing a memory card having a storage device according to some embodiments.

[0033] Figure 2B A diagram of a solid-state drive (SSD) having memory according to some embodiments is shown.

[0034] Figure 3A top view of a 3D memory device according to some embodiments of the present disclosure is shown.

[0035] Figure 4 A perspective view of a portion of a 3D memory array structure according to some embodiments of the present disclosure is shown.

[0036] Figure 5 A top perspective view of a portion of a 3D memory array structure according to some embodiments of the present disclosure is shown.

[0037] Figure 6 A flow chart of a method for forming a 3D memory device according to some embodiments of the present disclosure is shown.

[0038] Fig. 7A In a top perspective view, some embodiments of the present disclosure are shown. Figure 6 Schematic diagram of a portion of a 3D memory device at a certain manufacturing stage of the method shown in FIG.

[0039] Figure 7B In a cross-sectional side view, some embodiments of the present disclosure are shown. Figure 6 Schematic diagram of a portion of a 3D memory device at a certain manufacturing stage of the method shown in FIG.

[0040] Fig. 8A In a top perspective view, some embodiments of the present disclosure are shown. Figure 6 Schematic diagram of a portion of a 3D memory device at a certain manufacturing stage of the method shown in FIG.

[0041] Figure 8B In a cross-sectional side view, some embodiments of the present disclosure are shown. Figure 6 Schematic diagram of a portion of a 3D memory device at a certain manufacturing stage of the method shown in FIG.

[0042] Fig. 9A In a top perspective view, some embodiments of the present disclosure are shown. Figure 6 Schematic diagram of a portion of a 3D memory device at a certain manufacturing stage of the method shown in FIG.

[0043] Fig. 9B In a cross-sectional side view, some embodiments of the present disclosure are shown. Figure 6 Schematic diagram of a portion of a 3D memory device at a certain manufacturing stage of the method shown in FIG.

[0044] Fig. 9C In another cross-sectional side view, some embodiments of the present disclosure are shown. Figure 6 Schematic diagram of a portion of a 3D memory device at a certain manufacturing stage of the method shown in FIG.

[0045] Fig. 10A In a top perspective view, some embodiments of the present disclosure are shown. Figure 6 Schematic diagram of a portion of a 3D memory device at a certain manufacturing stage of the method shown in FIG.

[0046] Fig. 10B In a cross-sectional side view, some embodiments of the present disclosure are shown. Figure 6 Schematic diagram of a portion of a 3D memory device at a certain manufacturing stage of the method shown in FIG.

[0047] Fig. 10C In another cross-sectional side view, some embodiments of the present disclosure are shown. Figure 6 Schematic diagram of a portion of a 3D memory device at a certain manufacturing stage of the method shown in FIG.

[0048] Fig. 10D An enlarged top view perspective view of some embodiments of the present disclosure is shown. Figure 6 Schematic diagram of a portion of a 3D memory device at a certain manufacturing stage of the method shown in FIG.

[0049] Fig. 10E In an enlarged top perspective view, some other embodiments of the present disclosure are shown. Figure 6 Schematic diagram of a portion of a 3D memory device at a certain manufacturing stage of the method shown in FIG.

[0050] Fig.11A In a top perspective view, some embodiments of the present disclosure are shown. Figure 6 Schematic diagram of a portion of a 3D memory device at a certain manufacturing stage of the method shown in FIG.

[0051] Fig. 11B In a cross-sectional side view, some embodiments of the present disclosure are shown. Figure 6 Schematic diagram of a portion of a 3D memory device at a certain manufacturing stage of the method shown in FIG.

[0052] Fig. 11C In another cross-sectional side view, some embodiments of the present disclosure are shown. Figure 6 Schematic diagram of a portion of a 3D memory device at a certain manufacturing stage of the method shown in FIG.

[0053] Fig.11D An enlarged top view perspective view of some embodiments of the present disclosure is shown. Figure 6 Schematic diagram of a portion of a 3D memory device at a certain manufacturing stage of the method shown in FIG.

[0054] Fig.11EIn an enlarged top perspective view, some other embodiments of the present disclosure are shown. Figure 6 Schematic diagram of a portion of a 3D memory device at a certain manufacturing stage of the method shown in FIG.

[0055] Fig. 12A In a top perspective view, some embodiments of the present disclosure are shown. Figure 6 Schematic diagram of a portion of a 3D memory device at a certain manufacturing stage of the method shown in FIG.

[0056] Fig. 12B In a cross-sectional side view, some embodiments of the present disclosure are shown. Figure 6 Schematic diagram of a portion of a 3D memory device at a certain manufacturing stage of the method shown in FIG.

[0057] Fig. 12C In a cross-sectional side view, some embodiments of the present disclosure are shown. Figure 6 Schematic diagram of a portion of a 3D memory device at a certain manufacturing stage of the method shown in FIG.

[0058] Fig.12D An enlarged top view perspective view of some embodiments of the present disclosure is shown. Figure 6 Schematic diagram of a portion of a 3D memory device at a certain manufacturing stage of the method shown in FIG.

[0059] Fig.12E In an enlarged top perspective view, some other embodiments of the present disclosure are shown. Figure 6 Schematic diagram of a portion of a 3D memory device at a certain manufacturing stage of the method shown in FIG.

[0060] Fig.13A In a top perspective view, some embodiments of the present disclosure are shown. Figure 6 Schematic diagram of a portion of a 3D memory device at a certain manufacturing stage of the method shown in FIG.

[0061] Fig. 13B In a cross-sectional side view, some embodiments of the present disclosure are shown. Figure 6 Schematic diagram of a portion of a 3D memory device at a certain manufacturing stage of the method shown in FIG.

[0062] Fig. 13C In another cross-sectional side view, some embodiments of the present disclosure are shown. Figure 6 Schematic diagram of a portion of a 3D memory device at a certain manufacturing stage of the method shown in FIG.

[0063] Fig.13D An enlarged top view perspective view of some embodiments of the present disclosure is shown. Figure 6Schematic diagram of a portion of a 3D memory device at a certain manufacturing stage of the method shown in FIG.

[0064] Fig.13E In an enlarged top perspective view, some other embodiments of the present disclosure are shown. Figure 6 Schematic diagram of a portion of a 3D memory device at a certain manufacturing stage of the method shown in FIG.

[0065] Fig.14A In a top perspective view, some embodiments of the present disclosure are shown. Figure 6 Schematic diagram of a portion of a 3D memory device at a certain manufacturing stage of the method shown in FIG.

[0066] Fig. 14B In a cross-sectional side view, some embodiments of the present disclosure are shown. Figure 6 Schematic diagram of a portion of a 3D memory device at a certain manufacturing stage of the method shown in FIG.

[0067] Fig. 14C In another cross-sectional side view, some embodiments of the present disclosure are shown. Figure 6 Schematic diagram of a portion of a 3D memory device at a certain manufacturing stage of the method shown in FIG.

[0068] Fig.14D An enlarged top view perspective view of some embodiments of the present disclosure is shown. Figure 6 Schematic diagram of a portion of a 3D memory device at a certain manufacturing stage of the method shown in FIG.

[0069] Fig.14E In an enlarged top perspective view, some other embodiments of the present disclosure are shown. Figure 6 Schematic diagram of a portion of a 3D memory device at a certain manufacturing stage of the method shown in FIG.

[0070] Fig.15A In a top perspective view, some embodiments of the present disclosure are shown. Figure 6 Schematic diagram of a portion of a 3D memory device at a certain manufacturing stage of the method shown in FIG.

[0071] Fig. 15B In a cross-sectional side view, some embodiments of the present disclosure are shown. Figure 6 Schematic diagram of a portion of a 3D memory device at a certain manufacturing stage of the method shown in FIG.

[0072] Embodiments of the present disclosure will be described with reference to the accompanying drawings. DETAILED DESCRIPTION

[0073] Although specific configurations and arrangements are discussed, it should be understood that this is done for illustrative purposes only. Those skilled in the relevant art will recognize that other configurations and arrangements may be used without departing from the spirit and scope of the present disclosure. It will be apparent to those skilled in the relevant art that the present disclosure may also be used in various other applications.

[0074] It should be noted that references in the specification to "one embodiment", "an embodiment", "an exemplary embodiment", "some embodiments", etc. indicate that the described embodiments may include certain features, structures, or characteristics, but each embodiment may not necessarily include certain features, structures, or characteristics. In addition, these phrases do not necessarily refer to the same embodiment. In addition, when a certain feature, structure, or characteristic is described in conjunction with an embodiment, whether or not explicitly described, it is within the knowledge of a technician in the relevant field to implement such feature, structure, or characteristic in conjunction with other embodiments.

[0075] In general, terms can be understood, at least in part, from their use in context. For example, the term "one or more" as used herein can be used to describe any feature, structure, or characteristic in a singular sense, or can be used to describe a combination of features, structures, and characteristics in a plural sense, depending, at least in part, on the context. Similarly, terms such as "a," "an," or "the" can still be understood to express singular usage or to express plural usage, depending, at least in part, on the context.

[0076] It should be easily understood that the meaning of “on,” “over,” and “over” in the present disclosure should be interpreted in the broadest manner, so that “on” not only means “directly on something,” but also includes the meaning of “on something” with intervening features or layers therebetween, and “over” and “over” not only mean the meaning of “above something” and “on something,” but also include the meaning of “over something” and “on something” with no intervening features or layers therebetween (i.e., directly on something).

[0077] Additionally, for ease of description, spatially relative terms, such as "under," "beneath," "lower," "above," "upper," etc., may be used herein to describe the relationship of one element or feature to another element (single or multiple) or feature (single or multiple) as shown in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation other than the orientation shown in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein may likewise be interpreted accordingly.

[0078] As used herein, the term "substrate" refers to a material to which subsequent layers of material are added. The substrate itself may be patterned. The material added on top of the substrate may be patterned or may remain unpatterned. In addition, the substrate may include a wide range of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of a non-conductive material, such as glass, plastic, or a sapphire wafer.

[0079] As used herein, the term "layer" refers to a material portion including an area with a thickness. A layer may extend over the entire underlying or overlying structure, or may have a range that is less than the range of the underlying or overlying structure. In addition, a layer may be a region of a uniform or non-uniform continuous structure, the thickness of which is less than the thickness of the continuous structure. For example, a layer may be located between or between any pair of lateral planes between the top surface and the bottom surface of a continuous structure. A layer may extend laterally, vertically and / or along a tapered surface. A substrate may be a layer, may include one or more layers therein, and / or may have one or more layers thereon, above and / or below it. A layer may include multiple layers. For example, an interconnect layer may include one or more conductors and contact layers (wherein contact portions, interconnects and / or vias are formed) and one or more dielectric layers.

[0080] As used herein, the term "nominal / nominally" refers to an expected or target value for a characteristic or parameter of a component or process operation set during the design phase of a product or process, as well as a range of values ​​above and / or below the expected value. The range of values ​​may be due to slight variations in manufacturing processes or tolerances. As used herein, the term "approximately" refers to a value of a given quantity that may vary based on a specific technology node associated with the subject semiconductor device. Based on a specific technology node, the term "approximately" may refer to a value of a given quantity that varies within a range of, for example, 10-30% (e.g., ±10%, ±20%, or ±30% of the value).

[0081] As used herein, the term "3D memory device" refers to a semiconductor device having a vertically oriented memory cell transistor string (i.e., a region referred to herein as a "memory string" (e.g., a NAND string)) on a laterally oriented substrate, such that the memory string extends in a vertical direction relative to the substrate. As used herein, the term "vertical / vertically" refers to a semiconductor device that is nominally orthogonal to a lateral surface of the substrate.

[0082] As described above, 3D NAND memory devices keep scaling more film layers to improve the area utilization of the wafer. In some existing 3D NAND memory devices, as the number of film layers increases and the structure of the film layers becomes more complex, the silicon substrate used as a carrier of the film layers may not support the wafer deformation caused by the film stress, which may eventually cause the wafer to be curved. In addition, as the number of oxide / nitride (ON) layers increases, the etching depth of the gate line gap (GLS) increases accordingly, resulting in changes in the critical dimension of the GLS, thereby increasing the risk of structural instability due to stress and other factors. This unstable structure may cause storage finger bending / collapse, wafer bow effect, and affect subsequent 3D memory device manufacturing processes, such as increasing the overlay error in the lithography alignment process.

[0083] Therefore, according to various embodiments of the present disclosure, a 3D memory device and a manufacturing method for forming the 3D memory device are provided, which has a novel design of a gate line gap (GLS) structure for a memory array (also referred to herein as an "array device"). Based on the GLS extension process, the patterning processes of the channel holes, GLS openings, and contact holes can be merged into a single mask. By eliminating the traditional long GLS isolation structure, a storage finger support portion can be designed between the GLS structure segments. The dummy contact structure can be used as a storage finger support portion and can be formed in the same process as the contact structure. And the isolation function can be achieved by a silicon nitride recess process and an oxide deposition process, and is achieved together with the short GLS structure segment.

[0084] Since there is no long GLS running through the entire plane, the risk of structural instability due to stress can be suppressed by using short GLS structural segments and storage finger support portions. The filling oxide and polysilicon materials in the short GLS structural segments and storage finger support portions can significantly reduce device defects, including storage finger bending / collapse and / or wafer bow effect. In addition, by merging the channel structure formation process and the GLS structure formation process, the application of the photolithography process can be reduced, thereby reducing the process difficulty and production cost. In summary, the present disclosure can solve the manufacturing problems caused by structural stress, thereby breaking through the technical bottleneck in the research and development of higher-level 3D memory devices.

[0085] Figure 1 1 shows a block diagram of a system 100 having a storage device according to some aspects of the present disclosure. The system 100 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a car computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having storage therein. Figure 1 As shown, the system 100 may include a host 108 and a storage system 102, wherein the storage system 102 has one or more storage devices 104 and a memory controller 106. The host 108 may be a processor of an electronic device, such as a central processing unit (CPU), or a system-on-chip (SoC), such as an application processor (AP). The host 108 may be configured to send data to the storage device 104 or receive data from the storage device 104.

[0086] The memory device 104 may be any memory device disclosed herein, such as a NAND flash memory device. Consistent with the scope of the present disclosure, the memory controller 106 may control the multi-pass programming on the memory device 104 so that in a non-final programming pass of the multi-pass programming, NGS operations are enabled on all memory cells, even those that have passed corresponding verification operations. A peripheral circuit, such as a word line driver, may apply a low voltage, such as a ground (GND) voltage, to the DSG of each memory string coupled to a selected word line, and may apply a low voltage or a negative voltage to the selected word line to enable NGS operations on all memory cells coupled to the selected word line during a non-final programming pass.

[0087] According to some embodiments, the memory controller 106 is coupled to the memory device 104 and the host 108 and is configured to control the memory device 104. The memory controller 106 can manage data stored in the memory device 104 and communicate with the host 108. In some embodiments, the memory controller 106 is designed to operate in a low duty cycle environment, such as a secure digital (SD) card, a compact Flash (CF) card, a universal serial bus (USB) flash drive, or other media used in electronic devices (such as personal computers, digital cameras, mobile phones, etc.). In some embodiments, the memory controller 106 is designed to operate in a high duty cycle environment SSD or embedded multi-media card (embedded multi-media-card, eMMC), which is used as a data storage and enterprise storage array for mobile devices (such as smart phones, tablets, laptops, etc.). The memory controller 106 can be configured to control the operation of the memory device 104, such as read, erase, and program operations. The memory controller 106 may also be configured to manage various functions regarding data stored or to be stored in the memory device 104, including but not limited to bad block management, garbage collection, logical to physical address translation, wear leveling, etc. In some embodiments, the memory controller 106 is also configured to process error correction code (ECC) regarding data read from or written to the memory device 104. Any other suitable functions may also be performed by the memory controller 106, such as programming the memory device 104. The memory controller 106 may communicate with an external device (e.g., a host 108) according to a specific communication protocol. For example, the memory controller 106 can communicate with external devices through at least one of various interface protocols, such as USB protocol, MMC protocol, peripheral component interconnection (PCI) protocol, PCI express (PCI-E) protocol, advanced technology attachment (ATA) protocol, serial ATA protocol, parallel ATA protocol, small computer small interface (SCSI) protocol, enhanced small disk interface (ESDI) protocol, integrated drive electronics (IDE) protocol, FireWire protocol, etc.

[0088] The memory controller 106 and the one or more memory devices 104 may be integrated into various types of storage devices, for example, included in the same package, such as a universal flash storage (UFS) package or an eMMC package. That is, the storage system 102 may be implemented and packaged into different types of terminal electronic products. Figure 2A In one example shown, the memory controller 106 and the single memory device 104 may be integrated into a memory card 202. The memory card 202 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a smart media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 202 may also include a processor that connects the memory card 202 to a host (e.g., Figure 1 The host computer 108 in the embodiment of the present invention is coupled to the memory card connector 208. Figure 2B In another example shown, the memory controller 106 and the plurality of memory devices 104 may be integrated into the SSD 210. The SSD 210 may also include a processor that connects the SSD 210 to a host (eg, Figure 1 In some implementations, the storage capacity and / or operating speed of the SSD 210 is greater than the storage capacity or operating speed of the memory card 202.

[0089] Figure 3 A top view of a 3D memory device 300 according to some embodiments of the present disclosure is shown. The 3D memory device 300 may be a memory chip (package), a memory chip, or any portion of a memory chip, and may include one or more memory planes 301, each of which may include multiple memory blocks 303. The same and concurrent operations may occur at each memory plane 301. The size of the memory block 303 may be megabytes (MB), which may be the minimum size for performing erase operations. Figure 3 As shown, the 3D memory device 300 includes four memory planes 301, and each memory plane 301 includes six memory blocks 303. Each memory block 303 may include a plurality of memory cells, wherein each memory cell may be addressed by interconnections such as bit lines and word lines. The bit lines and word lines may be arranged orthogonally (e.g., in rows and columns, respectively) to form a metal line array. Figure 3In the embodiment of the present invention, the direction of the word line is referred to as the first lateral direction and is marked as the X direction, and the direction of the bit line is referred to as the second lateral direction and is marked as the Y direction. In the present disclosure, the memory block 303 is also referred to as a "memory array" or "array". The memory array is the core area in the memory device that performs the storage function.

[0090] 3D memory device 300 may include a peripheral region 305, an area surrounding storage plane 301. Peripheral region 305 may contain many digital, analog and / or mixed signal circuits to support the functions of the memory array, such as page buffers, row and column decoders, and sense amplifiers. Peripheral circuits use active and / or passive semiconductor devices, such as transistors, diodes, capacitors, resistors, etc., which will be apparent to those of ordinary skill in the art. Note that Figure 3 The arrangement of the memory planes 301 in the 3D memory device 300 and the arrangement of the memory blocks 303 in each memory plane 301 shown in FIG. 3 are provided only as examples, which do not limit the scope of the present disclosure.

[0091] Figure 4 A perspective view of a portion of a 3D memory array structure 400 according to some embodiments of the present disclosure is shown. The memory array structure 400 includes a substrate 430, an insulating film 431 on the substrate 430, one or more levels of bottom select gates (BSG) 432 on the insulating film 431, and multiple levels of control gates 433 stacked on top of the BSG 432 to form a stack structure 435 of alternating conductive layers and dielectric layers, also referred to as "word lines (WL)". For clarity, Figure 4 Not shown are dielectric layers adjacent to the level of the control gate.

[0092] The control gate 433 of each level is separated by the gap structure 416-1 and 416-2 passing through the stack structure 435. The memory array structure 400 may include one or more levels of top select gates (TSG) 434 above the stack of control gates 433. The stack of TSG 434, control gate 433 and BSG 432 is also referred to as a "gate structure". The memory array structure 400 also includes a doped source line region 344 in a portion of the memory string 412 and the substrate 430 between adjacent BSGs 432. Each memory string 412 includes a channel hole 436 extending through an insulating film 431 and a stack structure 435 of alternating conductive layers and dielectric layers. The memory string 412 may also include a memory film 437 (also referred to as a "functional layer") on the sidewalls of the channel hole 436, a channel layer 438 on the memory film 437, and a core fill film 439 surrounded by the channel layer 438. The memory cell 440 may be formed at the intersection of the control gate 433 and the memory string 412. The memory array structure 400 also includes a plurality of bit lines (BL) 441 connected to the memory string 412 over the TSG 434. The memory array structure 400 may include a plurality of metal interconnect lines 443 connected to the gate structure through a plurality of contact structures 414.

[0093] exist Figure 4 , for illustrative purposes, three levels of control gates 433-1, 433-2, and 433-3 are shown together with one level of TSG 434 and one level of BSG 432. In this example, each memory string 412 may include three memory cells 440-1, 440-2, and 440-3 corresponding to the control gates 433-1, 433-2, and 433-3, respectively. In some embodiments, the number of control gates and the number of memory cells may be greater than three to increase storage capacity. The memory array structure 400 may also include other structures, such as TSG cuts, common source contacts, and dummy channel structures. For simplicity, in Figure 4 These structures are not shown.

[0094] refer to Figure 5 , showing in an enlarged top view a portion 500 of a 3D memory device according to some embodiments of the present disclosure (e.g. Figure 3308). As shown, a portion 500 of a 3D memory device may include an array region 510 and a contact region 520, the array region 510 including a plurality of channel structures 550, and the contact region 520 including a plurality of contact structures 575. A plurality of slits may extend laterally in parallel along a word line direction (i.e., an X direction) and vertically through the stacked structure. A gate line slit (GLS) structure 530 may be formed in each slit to divide the memory array into a plurality of memory fingers 540. Each memory finger 540 may include a plurality of rows (e.g., nine rows) of channel structures 550 arranged between two adjacent GLS structures 530 in a staggered manner. The channel structure 550 may extend vertically through the conductive / dielectric stacked structure.

[0095] As described above, as the number of film layers increases and the structure of the film layers becomes more complex, the silicon substrate used as a carrier of the film layers may not support the wafer deformation caused by the film stress, which may eventually cause the wafer to be curved. In addition, as the 3D memory device keeps scaling a larger number of ON layers to improve the area utilization of the wafer, the etching depth of the GLS increases accordingly, resulting in the risk of collapse of the storage fingers 540 between adjacent GLS structures 530 due to stress and other factors in subsequent processes. The collapse of the storage fingers 540 can affect the subsequent 3D memory device manufacturing process, such as increasing the overlay error in the photolithography alignment process.

[0096] The present disclosure provides various segmented GLS structural designs as technical solutions to avoid the above problems. Figure 5 In some embodiments shown, each GLS structure 530 may include two gate line gap (GLS) structure segments 531 aligned along a word line direction (X direction), and a first dummy channel structure 535 located between the two GLS structure segments 531 in the word line direction. In some embodiments, each GLS structure segment 531 includes a wall structure extending laterally in the word line direction (X direction) and insulated from a conductive layer of the stacked structure. In some embodiments, one GLS structure segment 531 is located in the array region 510, another GLS structure segment 531 is located in the contact region 520, and the first dummy channel structure 535 may be located at a boundary between the array region 520 and the contact region 520. In some embodiments, a cross-section of the first dummy channel structure 535 along a transverse plane (i.e., an XY plane) may have an elliptical shape, with the longitudinal axis along the word line direction (X direction). Figure 5 In some other embodiments not shown in the figure, the cross-section of the first dummy channel structure 535 along the transverse plane can have any other suitable shape, such as a circle. In some embodiments, the width of the GLS structure segment 531 in the bit line direction (Y direction) can be substantially equal to the width of the first dummy channel structure 535 in the bit line direction.

[0097] like Figure 5 As shown, each storage finger 540 in the contact region 520 may include two conductive / dielectric stack regions 580 adjacent to the GLS structure segment 531, and a dielectric stack region 570 between the two conductive or dielectric stack regions 580. In some embodiments, each conductive / dielectric stack region 580 includes a conductive / dielectric stack including conductive layers and dielectric layers alternately stacked in a vertical direction (Z direction), and the dielectric stack region 570 includes a dielectric stack including two different dielectric layers alternately stacked in the vertical direction.

[0098] like Figure 5 As shown, a plurality of second dummy channel structures 555 may be located in a conductive / dielectric stack region 580 of the contact region 520, and a plurality of third dummy channel structures 553 may be located in a dielectric stack region 570 of the contact region 520 adjacent to the array region 510. In some embodiments, the channel structure 550, the first dummy channel structure 535, the second dummy channel structure 555, and the third dummy channel structure 553 may include similar structures. For example, each of the channel structure 550, the first dummy channel structure 535, the second dummy channel structure 555, and the third dummy channel structure 553 may include a functional layer, a channel layer, and a filling structure, which will be described in detail below.

[0099] like Figure 5 As shown, a plurality of gate line contact structures 575 can extend vertically in the dielectric stack region 570 of the contact region 520. In some embodiments, each gate line contact structure 575 includes a conductive via structure extending vertically through the upper portion of the dielectric stack structure, and a conductive landing layer contacting the lower end of the conductive via. The conductive landing layer can be laterally connected to a corresponding conductive layer of the conductive / dielectric stack in the conductive / dielectric stack region 580.

[0100] refer to Figure 6 , a flow chart of a method 600 for forming a 3D memory device according to some embodiments of the present disclosure is shown.

[0101] Figure 7A-7B , 8A-8B, 9A-9C, 10A-10E, 11A-11E, 12A-12E, 13A-13E, 14A-14E and 15A-15B show various views of various embodiments according to the present disclosure. Figure 66 is a schematic diagram of a portion of a 3D memory device at certain stages of manufacturing of method 600 shown in FIG. 6. It should be understood that the operations shown in method 600 are not exhaustive, and other operations may be performed before, after, or between any of the operations shown. In addition, some operations may be performed simultaneously or in parallel. Figure 6 The different orders are shown.

[0102] like Figure 6 As shown, the method may begin at operation 610, where a dielectric stack structure may be formed on a substrate, and a plurality of vias may be formed in an array region and a contact region of the dielectric stack structure. Fig. 7A A schematic diagram of a 3D structure after forming a plurality of vias at operation 610 is shown in a top-down perspective view, in accordance with some embodiments of the present disclosure. Figure 7B According to some embodiments of the present disclosure, Fig. 7A Schematic diagram of a portion of the 3D structure in a cross-sectional side view along line AA' shown in FIG.

[0103] like Figure 7B As shown, in some embodiments, substrate 710 may be any suitable semiconductor substrate having any suitable structure, such as a single crystal single layer substrate, a polycrystalline silicon (poly-Si) single layer substrate, a poly-Si and metal multi-layer substrate, etc.

[0104] A dielectric stack structure 720 including a plurality of dielectric layer pairs may be formed on a substrate 710. For example, the dielectric stack structure 720 may include an alternating stack of a first dielectric layer 722 (e.g., silicon oxide) and a second dielectric layer 724 (e.g., silicon nitride) different from the first dielectric layer 722. The plurality of first dielectric layers 722 and second dielectric layers 724 extend in a lateral direction parallel to a surface of the substrate 710. In some embodiments, there are more layers in the dielectric stack structure 720 than dielectric layer pairs made of different materials and having different thicknesses. The dielectric stack structure 720 may be formed by one or more thin film deposition processes, including but not limited to chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof.

[0105] In some embodiments, the dielectric stack structure 720 may include a plurality of silicon oxide / nitride layer pairs. Each dielectric layer pair includes a silicon oxide layer 722 and a silicon nitride layer 724. The plurality of oxide / nitride layer pairs are also referred to herein as "alternating oxide / nitride stacks". That is, in the dielectric stack structure 720, a plurality of oxide layers 722 (shown in the solid gray area) and a plurality of nitride layers 724 (shown in the grid area) alternate in the vertical direction. In other words, except for the top and bottom layers of a given alternating oxide / nitride stack, each of the other oxide layers 722 may be sandwiched by two adjacent nitride layers 724, and each of the nitride layers 724 may be sandwiched by two adjacent oxide layers 723.

[0106] The oxide layers may each have the same thickness or have different thicknesses. For example, the thickness of each oxide layer may be in the range of from 10 nm to 100 nm, preferably about 25 nm. Similarly, the nitride layers may each have the same thickness or have different thicknesses. For example, the thickness of each nitride layer may be in the range of from 10 nm to 100 nm, preferably about 35 nm.

[0107] It should be noted that in the present disclosure, the oxide layer 722 and / or the nitride layer 724 may include any suitable oxide material and / or nitride material. For example, the oxide material may include silicide, and the elements of the nitride material may include, but are not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), doped silicon, silicide, or any combination thereof. In some embodiments, the oxide layer may be a silicon oxide layer, and the nitride layer may be a silicon nitride layer.

[0108] The dielectric stack structure 720 may include any suitable number of layers of oxide layers 722 and nitride layers 724. In some embodiments, the total number of oxide layers 722 and nitride layers 724 in the dielectric stack structure 720 is equal to or greater than 64. That is, the number of oxide / nitride layer pairs may be equal to or greater than 32. In some embodiments, the alternating oxide / nitride stack 200 includes more oxide layers or more nitride layers having different materials and / or thicknesses than oxide / nitride layer pairs.

[0109] like Figure 7A-7BAs shown, in operation 610, a plurality of through holes 770 may be formed in the array region 730 and the contact region 740 of the dielectric stack structure 720. In some embodiments, the plurality of through holes 770 may include first through holes 771 that are laterally aligned along the word line direction (X direction) and extend straight through the dielectric stack 720. In some embodiments, the first through hole 771 may be located in both the array region 730 and the contact region 740. In some embodiments, the plurality of through holes 770 may also include second through holes 773 located in the array region 730. In some embodiments, the second through holes 773 may be arranged in a staggered array in the array region 730 and between adjacent rows of the first through holes 771. In some embodiments, the plurality of through holes 770 may also include third through holes 775 located in the contact region 740. In some embodiments, the third through hole 775 may be located adjacent to the first through hole 771. In some embodiments, the first through hole 771, the second through hole 773, and the third through hole 775 may be formed simultaneously. In some embodiments, a first distance between adjacent first through holes 771 may be smaller than a second distance between adjacent second through holes 773 and a third distance between adjacent third through holes 775 .

[0110] The process of forming multiple through holes 770 may include forming a hard mask layer (not shown) on the dielectric stack structure 720, and coating a photoresist layer (not shown) on the hard mask. A patterning process may be performed to pattern the hard mask layer. Using the hard mask layer as a mask, an etching process may then be performed to etch the dielectric stack structure 720 to form multiple through holes 770. Each of the multiple through holes 770 may completely penetrate the dielectric stack structure 720 and extend into the substrate 710. The etching process for forming multiple through holes 770 may be dry etching, wet etching, or a combination thereof. After the etching process, the photoresist layer and the hard mask layer may be removed. In some embodiments, the multiple through holes 770 and the channel holes formed in operation 610 may be formed in the same patterning process by using a single mask.

[0111] Return to reference Figure 6 , method 600 may proceed to operation 620, where a plurality of sacrificial filling structures may be formed in the plurality of through holes, and the sacrificial filling structures may be removed from the first subset of through holes. The first subset of through holes may be used as channel holes and / or dummy channel holes for forming channel structures and dummy channel structures in subsequent processes. Fig. 8A A schematic diagram of a 3D structure after forming a plurality of vias at operation 620 in a top-down perspective view is shown in accordance with some embodiments of the present disclosure. Figure 8B According to some embodiments of the present disclosure, Fig. 8ASchematic diagram of a portion of the 3D structure in a cross-sectional side view along line AA' shown in FIG.

[0112] like Figures 8A-8B As shown, a plurality of sacrificial filling structures 860 may be formed in the through-hole 770. In some embodiments, a deposition process may be performed to fill the through-hole 770, including the first through-hole 771, the second through-hole 773, and the third through-hole 775, with any suitable sacrificial material (e.g., a carbon-based material) to form the sacrificial filling structure 860. It should be noted that the sacrificial material of the sacrificial filling structure 860 may have a sufficiently high etching selectivity relative to the material of the first dielectric layer 722 and the second dielectric layer 724, so that a subsequent etching process of the sacrificial filling structure 860 may have minimal impact on the first dielectric layer 722 and the second dielectric layer 724.

[0113] like Figures 8A-8B As shown, the sacrificial filling structure 860 can be removed from the first subset of through holes 870. Specifically, the sacrificial filling structure 860 can be removed from a column of first through holes 871 at the boundary between the array region 730 and the contact region 740, and from the second through holes 773 and the third through holes 775 by using any suitable etching process, such as isotropic dry etching or wet etching. The etching process can have a sufficiently high etching selectivity to the sacrificial material of the sacrificial filling structure 860 relative to the material of the first dielectric layer 722 and the second dielectric layer 724, so that the etching process can have minimal impact on the first dielectric layer 722 and the second dielectric layer 724. In this way, a column of first through holes 871, second through holes 773 and third through holes 775 can be formed again for forming a channel structure or a dummy channel structure.

[0114] Return to reference Figure 6 , the method 600 may proceed to operation 630 , where a plurality of channel structures and dummy channel structures may be formed in the dielectric stack structure. Fig. 9A A schematic diagram of a 3D structure after operation 620 is shown in a top-down perspective view, in accordance with some embodiments of the present disclosure. Fig. 9B According to some embodiments of the present disclosure, Fig. 9A Schematic diagram of a portion of the 3D structure in a cross-sectional side view along line AA' shown in FIG. Fig. 9C According to some embodiments of the present disclosure, Fig. 9A Schematic diagram of a portion of the 3D structure in a cross-sectional side view of line BB' shown in FIG.

[0115] like Fig. 9A , 9B9C, in some embodiments, a plurality of channel structures 950 can be formed in the second through hole 773 in the array region 730, a plurality of first dummy channel structures 955 can be formed in the column of the first through hole 871, and a plurality of second dummy channel structures 975 can be formed in the column of the third through hole 775. Each channel structure 950, the first dummy channel structure 955, and / or the second dummy channel structure 975 can extend vertically through the dielectric stack structure 720 into the substrate 710. In some embodiments, the channel structure 950, the first dummy channel structure 955, and the second dummy channel structure 975 can include similar structures, including an optional high-k dielectric layer (not shown), a functional layer 910 on the sidewalls of the channel hole or covering the high-k dielectric layer, a channel layer 920 covering the functional layer 910, and a filling structure 928 surrounded by the channel layer 920. In some embodiments, the functional layer 910 may include a barrier layer 912, a storage layer 914, and a tunneling layer 916. In some embodiments, the plurality of first dummy channel structures 955 may have an elliptical cross-section in a lateral plane (XY plane) with a longitudinal axis in the wordline direction (X direction).

[0116] In some embodiments, a plurality of channel structures 950 may be formed in a staggered array form. In some embodiments, the array 950 of channel structures may include multiple rows of channel structures. Each row of channel structures 950 may be aligned along the word line direction (X direction). The channel structures 950 of adjacent rows may be misaligned. In some embodiments, the array of channel structures 950 may include multiple columns of channel structures 950. Each column of channel structures 950 may be aligned along the bit line direction (Y direction). The channel structures 950 of adjacent columns may be misaligned. In some embodiments, the first dummy channel structure 955 may be located at the boundary between the array region 730 and the contact region 740. In some embodiments, the second dummy channel structure 975 may be located in the contact region 740 and adjacent to the remaining sacrificial filling structure 860.

[0117] In some embodiments, the manufacturing process for forming the channel structure 950, the first dummy channel structure 955, and the second dummy channel structure 975 may include forming an epitaxial layer (not shown) at the bottom of each channel hole / dummy channel hole. In some embodiments, the epitaxial layer may be a polycrystalline silicon (polysilicon) layer formed by using a selective epitaxial growth (SEG) process. For example, a SEG pre-cleaning process may be performed to clean the plurality of channel holes. A subsequent deposition process may be performed to form a polysilicon layer at the bottom of each channel hole. In some embodiments, any suitable doping process, such as an ion metal plasma (IMP) process, may be performed on the polysilicon layer to form an epitaxial layer. In some embodiments, the epitaxial layer may not be formed directly on the surface of the substrate 710. One or more layers may be formed between the epitaxial layer and the substrate 710. That is, the epitaxial layer overlaps the substrate 710.

[0118] In some embodiments, the manufacturing process of forming the channel structure 950, the first dummy channel structure 955, and the second dummy channel structure 975 may include forming an optional high-k dielectric layer (not shown) on the sidewalls of each channel hole, and forming a functional layer 910 covering the high-k dielectric layer. The functional layer 910 may be a composite dielectric layer, such as a combination of a barrier layer 912, a storage layer 914, and a tunneling layer 916. The high-k dielectric layer, the functional layer 910 including the barrier layer 912, the storage layer 914, and the tunneling layer 916 may be formed by one or more thin film deposition processes, such as ALD, CVD, PVD, any other suitable process, or any combination thereof.

[0119] In some embodiments, a blocking layer 912 and / or a high-k dielectric layer may be formed between the storage layer 914 and the sidewalls of the channel hole / dummy channel hole. The blocking layer 912 and / or the high-k dielectric layer may be used to block the outflow of electronic charge. In some embodiments, the blocking layer 912 may be a silicon oxide layer or a combination of silicon oxide / silicon nitride / silicon oxide (ONO) layers. In some embodiments, the high-k dielectric layer includes any suitable high dielectric constant (high-k value) dielectric (e.g., aluminum oxide).

[0120] The storage layer 914 can be formed between the tunneling layer 916 and the barrier layer 912. Electrons or holes from the channel layer can tunnel to the storage layer 914 through the tunneling layer 916. The storage layer 914 can be used to store electronic charges (electrons or holes) for storage operations. The storage or removal of charges in the storage layer 914 can affect the on / off state and / or conductivity of the semiconductor channel. The storage layer 914 may include one or more material films, including but not limited to silicon nitride, silicon oxynitride, a combination of silicon oxide and silicon nitride, or any combination thereof. In some embodiments, the storage layer 914 may include a nitride layer formed by using one or more deposition processes.

[0121] Tunneling layer 916 may be formed on the sidewalls of storage layer 914. Tunneling layer may be used to tunnel electronic charges (electrons or holes). Tunneling layer 916 may include a dielectric material including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. In some embodiments, tunneling layer 916 may be an oxide layer formed using a deposition process.

[0122] In some embodiments, the manufacturing process of forming the channel structure 950, the first dummy channel structure 955, and the second dummy channel structure 975 further includes forming a channel layer 920 covering the sidewalls of the functional layer 910. In some embodiments, the channel layer 920 may be an amorphous silicon layer or a polysilicon layer formed by using a thin film deposition process, such as ALD, CVD, PVD, or any other suitable process.

[0123] In some embodiments, the manufacturing process of forming the channel structure 950, the first dummy channel structure 955, and the second dummy channel structure 975 further includes forming a filling structure 928 to cover the channel layer 920 and fill the channel hole. In some embodiments, the filling structure 928 can be an oxide layer formed by using any suitable deposition process, such as ALD, CVD, PVD, etc. In some embodiments, the filling structure 928 can include one or more air gaps (not shown).

[0124] Return to reference Figure 6 The method proceeds to operation 640, where the sacrificial fill structure may be removed from the second subset of vias and a plurality of gate line slits (GLS) may be formed in the dielectric stack structure. Fig. 10A A schematic diagram of the 3D structure after operation 640 is shown in a top-down perspective view, in accordance with some embodiments of the present disclosure. Fig. 10B According to some embodiments of the present disclosure, Fig. 10A Schematic diagram of a portion of the 3D structure in a cross-sectional side view along line AA' shown in FIG. Fig. 10CAccording to some embodiments of the present disclosure, Fig. 10A Schematic diagram of a portion of the 3D structure in a cross-sectional side view of line BB' shown in FIG. Fig. 10D A schematic diagram of a portion of a 3D structure after operation 640 is shown in an enlarged top view, in accordance with some embodiments of the present disclosure. Fig. 10E A schematic diagram of a portion of a 3D structure after operation 640 in an enlarged top view is shown according to some other embodiments of the present disclosure.

[0125] like Figures 10A-10E As shown in FIG. 1 , the sacrificial filling structures 860 in the remaining first through holes 771 except for the column of first through holes 871 and the portion of the dielectric stack structure 720 adjacent to the sacrificial filling structures 860 may be removed to form a plurality of gate line slits (GLS) 1060. Each of the plurality of GLS 1060 may extend vertically through the dielectric stack structure 720 into the substrate 710. Figures 10A-10B and Figures 10D-10E As shown, the first dummy channel structure 955 can be located between the GLS 1060, and the first dummy channel structure 955 and the GLS 1060 are laterally aligned in a straight line along the word line direction (X direction). In some embodiments, when the first dummy channel structure 955 includes Fig. 10D When the high-k dielectric layer 1090 is formed as shown, the GLS 1060 may expose the sidewalls of the high-k dielectric layer 1090 of the first dummy channel structure 955. Fig. 10E In some other embodiments shown, when the first dummy channel structure 955 does not include a high-k dielectric layer, portions of the functional layer 910 of the first dummy channel structure 955 may be removed during formation of the GLS 1060. The GLS 1060 may expose sidewalls of the channel layer 920 of the first dummy channel structure 955.

[0126] In some embodiments, a plurality of GLS 1060 may be formed by forming a mask layer (not shown) on the dielectric stack structure 720 and patterning the mask using, for example, photolithography to form a slit opening in the remaining first through hole 771 that covers the remaining sacrificial filling structure 860. A suitable etching process, such as dry etching and / or wet etching, may be performed to remove the remaining sacrificial filling structure 860 and the portion of the dielectric stack structure 720 exposed by the slit opening until the plurality of GLS 1060 exposes the substrate 710, as shown in FIG. Fig. 10B and 10CAs shown. The mask layer can be removed after forming multiple GLS1060. In some embodiments, a doped region (not shown) can be formed at the bottom of each GLS1060 in the substrate 710 by using any suitable doping process, such as ion implantation and / or thermal diffusion through GLS1060. The dopant in the doped region can be any suitable N+ or P+ ion. After forming a conductive wall in GLS1060 in a subsequent process, the lower end of each conductive wall can contact the corresponding doped region.

[0127] Return to reference Figure 6 The method proceeds to operation 650, where a sacrificial gap structure may be formed in the GLS. Fig.11A A schematic diagram of a 3D structure after operation 650 is shown in a top-down perspective view, in accordance with some embodiments of the present disclosure. Fig. 11B According to some embodiments of the present disclosure, Fig.11A Schematic diagram of a portion of the 3D structure in a cross-sectional side view along line AA' shown in FIG. Fig. 11C According to some embodiments of the present disclosure, Fig.11A Schematic diagram of a portion of the 3D structure in a cross-sectional side view of line BB' shown in FIG. Fig.11D A schematic diagram of a portion of a 3D structure after operation 650 is shown in an enlarged top view, in accordance with some embodiments of the present disclosure. Fig.11E A schematic diagram of a portion of a 3D structure after operation 650 is shown in an enlarged top view, in accordance with some embodiments of the present disclosure.

[0128] In some embodiments, before forming the sacrificial gap structure 1160, a pre-oxidation process may be performed in the GLS 1060 to form an oxide layer 1120 to protect the substrate 710, such as Fig. 11B and 11C It should be noted that when the GLS1060 is exposed to Fig. 10E When the sidewall of the channel layer 920 of the first dummy channel structure 955 is oxidized, the pre-oxidation process may also oxidize a portion of the channel layer 920 of the first dummy channel structure 955, such as Fig.11E As shown. In this way, the oxidized portion of the channel layer 920, the barrier layer 912, and the filling structure 928 of the first dummy channel structure 955 can form a first integrated filling structure 1128. The remaining portion of the channel layer 920 of the first dummy channel structure 955 can be embedded in the first integrated filling structure 1128, as shown. Fig.11E shown.

[0129] like Figures 11A-11EAs shown, a plurality of sacrificial gap structures 1160 may then be formed in the GLS 1060. A deposition process may be performed to fill the GLS 1060 with any suitable sacrificial material (e.g., polysilicon) to form the sacrificial gap structures 1160. It should be noted that the sacrificial material of the sacrificial gap structures 1160 may have a sufficiently high etch selectivity relative to the material of the first dielectric layer 722 and the second dielectric layer 724, so that a subsequent etching process of the sacrificial gap structures 1160 may have minimal impact on the first dielectric layer 722 and the second dielectric layer 724. In some embodiments, when the first dummy channel structure 955 includes a Fig.11D When the high-k dielectric layer 1090 is formed as shown, the sacrificial gap structure 1160 may contact the sidewall of the high-k dielectric layer 1090 of the first dummy channel structure 955. Fig.11E In some other embodiments shown, when the first dummy channel structure 955 does not include a high-k dielectric layer and a portion of the functional layer 910 of the first dummy channel structure 955 is removed during operation 640 to form GLS1060, the sacrificial gap structure 1160 can contact the sidewalls of the channel layer 920 of the first dummy channel structure 955.

[0130] Return to reference Figure 6 The method proceeds to operation 660, in which the sacrificial gap structure in the array region can be removed and the second dielectric layer of the dielectric stack structure in the array region can be replaced with a plurality of conductive layers. Fig. 12A A schematic diagram of a 3D structure after operation 660 is shown in a top-down perspective view, in accordance with some embodiments of the present disclosure. Fig. 12B According to some embodiments of the present disclosure, Fig. 12A Schematic diagram of a portion of the 3D structure in a cross-sectional side view along line AA' shown in FIG. Fig. 12C According to some embodiments of the present disclosure, Fig. 12A Schematic diagram of a portion of the 3D structure in a cross-sectional side view of line CC' shown in FIG. Fig.12D A schematic diagram of a portion of a 3D structure after operation 660 is shown in an enlarged top view, in accordance with some embodiments of the present disclosure. Fig.12E A schematic diagram of a portion of a 3D structure after operation 660 in an enlarged top view is shown according to some other embodiments of the present disclosure.

[0131] like Figures 12A-12BAs shown in FIGS. 12D-12E , the sacrificial slit structure 1160 in the array region 730 may be removed to form the GLS 1260 in the array region 730 again. The sacrificial slit structure 1160 in the array region 730 may be removed by using any suitable etching process, such as an isotropic dry etching or wet etching. The etching process may have a sufficiently high etching selectivity to the sacrificial material of the sacrificial slit structure 1160 relative to the material of the first dielectric layer 722, so that the etching process may have minimal impact on the first dielectric layer 722. In this way, the GLS 1260 in the array region 730 may be formed again.

[0132] In some embodiments, the second dielectric layer 724 (e.g., silicon nitride) of the dielectric stack structure 720 in the array region 730 may be removed via GLS1260. The second dielectric layer 724 in the dielectric stack structure 720 is used as a sacrificial layer and may be removed using any suitable etching process, such as an isotropic dry etching or a wet etching process. The etching process may have a sufficiently high etching selectivity to the material of the second dielectric layer 724 relative to the material of the first dielectric layer 722, so that the etching process may have minimal impact on the first dielectric layer 722. In some embodiments, the etching time of the isotropic dry etching and / or wet etching may be controlled, and a subsequent cleaning process may be performed to completely remove the second dielectric layer 724 in the array region 730 in all directions, thereby exposing the top and bottom surfaces of each first dielectric layer 722. In this way, a plurality of lateral grooves may be formed between the first dielectric layers 722 in the array region 730. The plurality of lateral grooves may extend in a lateral direction and may be used as a space for forming a conductive layer in a subsequent process. It should be noted that due to the blocking of the sacrificial gap structure 1160 and the first dummy channel structure 955 in the contact region 740 , the second dielectric layer 724 in the contact region 740 may be maintained.

[0133] In such Fig.12D In some embodiments shown, when the first dummy channel structure 955 includes a high-k dielectric layer 1190, the GLS 1260 formed in the array region 730 exposes the sidewalls of the high-k dielectric layer 1190. Fig.12E In some other embodiments shown, when the first dummy channel structure 955 does not include a high-k dielectric layer, the storage layer 914 of the functional layer 910 of the first dummy channel structure 955 may be exposed by the GLS 1260. In this case, during the removal of the second dielectric layer 724 (e.g., silicon nitride) of the dielectric stack structure 720, the storage layer 914 (e.g., silicon nitride) may also be removed. In this way, the curved gap 1214 may be formed, as shown in FIG. Fig.12E shown.

[0134] like Fig. 12C As shown, a plurality of conductive layers 1224 may be formed in the lateral trenches. In this way, the dielectric stack structure 720 may be converted into a memory stack structure 1220 including a plurality of conductive / dielectric layer pairs. That is, a gate replacement process (also referred to as a "word line replacement" process) may be performed to replace the second dielectric layer 724 (e.g., silicon nitride) of the dielectric stack structure 720 with the conductive layer 1224. In some embodiments, the plurality of conductive layers 1224 may be used as word lines (i.e., gate electrodes) in a 3D memory device.

[0135] In some embodiments, each conductive layer 1224 may be coated with one or more insulating layers (not shown) that serve as a gate dielectric layer for insulating the corresponding word line (i.e., gate electrode). In some embodiments, one or more insulating layers (not shown) may be formed in each of the plurality of lateral grooves to cover the exposed surface of the lateral grooves with one or more suitable insulating materials. For example, one or more suitable deposition processes, such as CVD, PVD, and / or ALD, may be used to deposit insulating materials into the lateral grooves. In some embodiments, recess etching and / or CMP processes may be used to remove excess insulating materials (single or multiple). One or more insulating materials may include any suitable material (e.g., a high-k value dielectric) that provides an electrical insulation function. For example, one or more insulating materials may include silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, titanium nitride, etc., and / or any suitable combination thereof. In some embodiments, the plurality of insulating layers may have different insulating materials.

[0136] Conductive layer 1224 may be formed in each lateral groove between one or more insulating layers. Conductive layer 1224 may be formed by filling the lateral groove with a suitable gate electrode metal material. Conductive layer 1224 may provide a base material for a subsequently formed word line (i.e., a gate electrode). The gate electrode metal material may include any suitable conductive material for forming a word line (i.e., a gate electrode), such as tungsten, aluminum, copper, cobalt, or any combination thereof. A suitable deposition method, such as CVD, PVD, PECVD, sputtering, MOCVD, and / or ALD, may be used to deposit the gate electrode material into the lateral groove. In some embodiments, conductive layer 1224 may include tungsten formed by CVD. In this way, the dielectric stack structure 720 in the array region 730 is converted into a stack structure 1220 including alternating conductive / dielectric layers.

[0137] Return to reference Figure 6 The method proceeds to operation 670, in which the sacrificial gap structure in the contact area can be removed and the portion of the second dielectric layer of the dielectric stack structure in the contact area can be replaced with a plurality of conductive layers. Fig.13AA schematic diagram of a 3D structure after operation 670 is shown in a top-down perspective view, in accordance with some embodiments of the present disclosure. Fig. 13B According to some embodiments of the present disclosure, Fig.13A Schematic diagram of a portion of the 3D structure in a cross-sectional side view along line AA' shown in FIG. Fig. 13C According to some embodiments of the present disclosure, Fig.13A Schematic diagram of a portion of the 3D structure in a cross-sectional side view of line BB' shown in FIG. Fig.13D A schematic diagram of a portion of a 3D structure after operation 670 is shown in an enlarged top view, in accordance with some embodiments of the present disclosure. Fig.13E A schematic diagram of a portion of a 3D structure after operation 670 in an enlarged top view is shown in accordance with some other embodiments of the present disclosure.

[0138] like Figures 13A-13B 13D-13E, the sacrificial slit structure 1160 in the contact region 740 may be removed to form the GLS 1360 in the contact region 740 again. The portion of the sacrificial slit structure 1160 adjacent to the GLS 1360 in the contact region 740 may be removed by using any suitable etching process (e.g., isotropic dry etching or wet etching). The etching process may have a sufficiently high etching selectivity to the sacrificial material of the sacrificial slit structure 1160 relative to the material of the first dielectric layer 722, so that the etching process may have minimal impact on the first dielectric layer 722. In this way, the GLS 1360 in the contact region 740 may be formed again.

[0139] In some embodiments, a portion of the second dielectric layer 724 (e.g., silicon nitride) of the dielectric stack structure 720 adjacent to the GLS 1360 in the contact region 740 can be removed via the GLS 1360. The second dielectric layer 724 in the dielectric stack structure 720 serves as a sacrificial layer and can be removed using any suitable etching process, such as an isotropic dry etch or a wet etch. The etching process can have a sufficiently high etching selectivity for the material of the second dielectric layer 724 relative to the material of the first dielectric layer 722, so that the etching process can have minimal impact on the first dielectric layer 722.

[0140] In some embodiments, the etching time of the isotropic dry etching and / or wet etching can be controlled, and a subsequent cleaning process can be performed to partially remove the second dielectric layer 724 in the contact area 740. In this way, a plurality of lateral recesses can be formed between the first dielectric layer 722 in the contact area 740. The plurality of lateral recesses can extend in the lateral direction and can be used as spaces for forming a conductive layer in a subsequent process. It should be noted that due to the controlled etching time, a portion of the second dielectric layer 724 in the contact area 740 having a distance from GLS1360 can be maintained. In this way, a portion of the dielectric stack structure 720 adjacent to GLS1360 can be converted into a conductive / dielectric stack structure 1320, and a portion of the dielectric stack structure 720 having a distance from GLS1360 can be maintained, as shown in FIG. Fig. 13C shown.

[0141] In some embodiments, each conductive layer 1324 may be coated with one or more insulating layers (not shown) for insulating the corresponding conductive layer 1324. In some embodiments, one or more insulating layers (not shown) may be formed in each of the plurality of lateral grooves to cover the exposed surface of the lateral grooves with one or more suitable insulating materials. For example, one or more suitable deposition processes, such as CVD, PVD and / or ALD, may be used to deposit insulating materials into the lateral grooves. In some embodiments, recess etching and / or CMP processes may be used to remove excess insulating materials (single or multiple). One or more insulating materials may include any suitable material (e.g., a high-k dielectric) that provides an electrical insulation function. For example, one or more insulating materials may include silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, titanium nitride, etc., and / or any suitable combination thereof. In some embodiments, the plurality of insulating layers may have different insulating materials.

[0142] Conductive layer 1324 may be formed in each lateral recess between one or more insulating layers. Conductive layer 1324 may be used as a word line connection layer. Conductive layer 1324 may be formed by filling the lateral trenches with any suitable conductive material (e.g., tungsten, aluminum, copper, cobalt, or any combination thereof) for forming a word line connection layer. Conductive material may be deposited into the lateral trenches using a suitable deposition method, such as CVD, PVD, PECVD, sputtering, MOCVD, and / or ALD. In some embodiments, conductive layer 1324 may include tungsten formed by CVD.

[0143] In such Fig.13D In some embodiments shown, when the first dummy channel structure 955 includes a high-k dielectric layer 1190, the GLS 1360 formed in the contact region 740 exposes the sidewalls of the high-k dielectric layer 1190. Fig.13EIn some other embodiments shown, when the first dummy channel structure 955 does not include a high-k dielectric layer and the curved slit 1214 exposes the sidewalls of the sacrificial slit structure 1160 in the contact region 740, the oxidation process during the formation of the conductive layer 1324 may also oxidize the exposed sidewalls of the sacrificial slit structure 1160. In this way, the formed second integrated filling structure 1328 has a concave sidewall exposed by the GLS 1360 in the contact region 740 and a convex sidewall exposed by the GLS 1260 in the array region 730, as shown in FIG. Fig.13E shown.

[0144] Return to reference Figure 6 The method proceeds to operation 680, in which a plurality of GLS structure segments may be formed in the GLS. Fig.14A A schematic diagram of a 3D structure after operation 680 is shown in a top-down perspective view, in accordance with some embodiments of the present disclosure.

[0145] Fig. 14B According to some embodiments of the present disclosure, Fig.14A Schematic diagram of a portion of the 3D structure in a cross-sectional side view along line AA' shown in FIG. Fig. 14C According to some embodiments of the present disclosure, Fig.14A Schematic diagram of a portion of the 3D structure in a cross-sectional side view of line BB' shown in FIG. Fig.14D A schematic diagram of a portion of a 3D structure after operation 680 is shown in an enlarged top view, in accordance with some embodiments of the present disclosure. Fig.14E A schematic diagram of a portion of a 3D structure after operation 680 in an enlarged top view is shown in accordance with some other embodiments of the present disclosure.

[0146] like Figures 14A-14E As shown, a plurality of GLS structure segments 1470 may be formed in the GLS 1260 / 1360. In some embodiments, the manufacturing process for forming the GLS structure segments 1470 may include forming a second insulating layer 1473 on the sidewalls of the plurality of GLS 1260 / 1360. The second insulating layer 1473 is also referred to as a gate line spacer (GLSP) layer and may be used to provide electrical insulation between the plurality of conductive layers 1224 / 1324 and the conductive walls formed in subsequent processes.

[0147] In some embodiments, the manufacturing process for forming the second insulating layer 1473 may include a conductive layer recess process. Portions of the plurality of conductive layers 1224 / 1324 exposed by the GLS1260 / 1360 may be removed by a recess etching process. In some embodiments, in order to ensure insulation between the plurality of conductive layers 1224 / 1324, a recess etching process, such as a wet etching process, may be performed to remove portions of the plurality of conductive layers 1224 / 1324 exposed by the GLS1260 / 1360. In doing so, a recess may be formed in each lateral groove adjacent to the GLS1260 / 1360.

[0148] In some embodiments, the second insulating layer 1473 may have a laminated structure (not shown) including two or more spacer sublayers formed by using any suitable deposition process (e.g., atomic layer deposition (ALD) process). For example, the second insulating layer 1473 may include a first spacer sublayer (not shown) covering the sidewalls of GLS1260 / 1360 and the exposed surfaces of the plurality of conductive layers 1224 / 1324. The first spacer sublayer may include a low-temperature oxide material, such as silicon oxide, which is configured to prevent the plurality of conductive layers 1224 / 1324 from being oxidized in subsequent processes. The second insulating layer 1473 may also include a second spacer sublayer (not shown) to cover the first spacer sublayer. The second spacer sublayer may include a high-k value material, such as silicon nitride. This laminated structure can effectively increase the equivalent oxide thickness (EOT) of the second insulating layer 1473, thereby improving the isolation performance of the second insulating layer 1473.

[0149] In some embodiments, the manufacturing process for forming the GLS structure segment 1470 may include forming a conductive wall 1475 in each GLS 1260 / 1360. The conductive wall 1475 may contact a doped region (not shown) in the substrate 710 and serve as an array common source (ACS) for multiple NAND strings. In some embodiments, the conductive wall 1475 may be formed by depositing a conductive material, such as polysilicon, silicide, tungsten, aluminum, copper, and / or combinations thereof. The conductive material may be deposited into the multiple GLS 1260 / 1360 using a suitable deposition method, such as CVD, PVD, PECVD, sputtering, MOCVD, and / or ALD. A subsequent CMP process may be performed to flatten the top surface of the formed 3D structure.

[0150] It should be noted that in Fig.14EIn some embodiments shown, when the first dummy channel structure 955 does not include a high-k dielectric layer, the curved gap 1214 can be filled with a dielectric material during the formation of the second insulating layer 1473. In this way, the tunneling layer 916, the second integrated filling structure 1128, and the dielectric material filled in the curved gap 1214 can form a third integrated filling structure 1328, and the remaining portion of the channel layer 920 is embedded in the third integrated filling structure 1328, as shown in FIG. Fig.14E As shown. Fig.14D In some other embodiments shown, when the first dummy channel structure 955 includes the high-k dielectric layer 1090 , the first dummy channel structure 955 can maintain a complete structure and be separated from the GLS structure segment 1470 by the high-k dielectric layer 1190 .

[0151] Return to reference Figure 6 The method proceeds to operation 690, in which a plurality of contact structures may be formed in the dielectric stack structure in the contact region. Fig.15A A schematic diagram of the 3D structure after removing a subset of dummy contacts at operation 690 is shown in a top-down perspective view, in accordance with some embodiments of the present disclosure. Fig. 15B According to some embodiments of the present disclosure, Fig.15A Schematic diagram of a portion of the 3D structure in a cross-sectional side view of line BB' shown in FIG.

[0152] like Fig.15A and 15B As shown, a plurality of contact structures 1510 may be formed in a plurality of contact holes in the dielectric stack 720 in the contact region 740. In some embodiments, forming the contact structure 1510 may include forming a plurality of contact holes in the dielectric stack structure 720 in the contact region 740. In some embodiments, each of the plurality of contact holes may penetrate the upper portion of the dielectric stack 720 in the contact region 740 and stop at a corresponding second dielectric layer 724. For example, one or more suitable etching processes, such as dry etching and / or wet etching, may be performed to remove portions of the dielectric stack 720 in the contact region 740, thereby forming a plurality of contact holes. A mask layer (not shown) may be used to control the shape of the contact holes during the etching process, and various etching times may be controlled to form a plurality of contact holes having different depths.

[0153] In some embodiments, a dielectric filling structure may be formed by any suitable deposition process to fill each contact hole. Stamp etching may be performed to remove a portion of the dielectric filling structure to expose a corresponding one of the second dielectric layers 724 at the bottom of each contact hole. The remaining portion of the dielectric filling structure forms a spacer 1533 on the sidewalls of each contact hole. A portion of the exposed second dielectric layer 724 may be removed by any suitable etching process to laterally expose a corresponding one of the conductive lines 1324 at the same level as the corresponding one of the second dielectric layers 724.

[0154] A conductive layer (including 1524 and 1526) may be formed using a first conductive material by any suitable thin film deposition process to cover the spacer layer 1572 and the bottom surface of each contact hole and to contact a corresponding conductive line 1324 in the lateral direction. In some embodiments, a second conductive material may then be filled in the contact hole to form a conductive filling structure 1528. The first and second conductive materials may be deposited into the contact hole using any suitable deposition method, such as CVD, PVD, PECVD, sputtering, MOCVD, and / or ALD. In some embodiments, the conductive layer (including 1524 and 1526) and the conductive filling structure 1528 may include any suitable conductive material, such as tungsten, aluminum, copper, cobalt, or any combination thereof.

[0155] Conductive layer 1526 and conductive filling structure 1528 may form a conductive via isolated from other conductive lines 1320 by spacer layer 1533. That is, contact structure 1510 may include conductive vias (including 1526 and 1528) and landing conductive layers 1524. Landing conductive layers 1524 may each laterally contact corresponding conductive layers 1324 in conductive / dielectric stack structure 1320 in contact region 740. Conductive via 1540 is in direct contact with landing conductive layer 1524 and electrically connected to corresponding conductive layer 1324. In this way, the formed contact structure 1510 may be used as a word line contact.

[0156] Therefore, a 3D memory device and a manufacturing method are provided. Based on the GLS extension process, the patterning process of the channel hole, the GLS opening and the through hole can be merged into a single mask. By eliminating the traditional long GLS isolation structure, a storage finger support portion can be designed between the GLS structure segments. The dummy channel structure can be used as a storage finger support portion and can be formed in the same process as the channel structure. And the isolation function can be achieved by the silicon nitride recess process and the oxide deposition process, and is achieved together with the short GLS structure segment.

[0157] Since there is no long GLS passing through the entire plane, the risk of structural instability due to stress can be suppressed by using short GLS structural segments and storage finger support portions. The filling oxide and polysilicon materials in the short GLS structural segments and storage finger support portions can significantly reduce device defects, including storage finger bending / collapse and / or wafer bow effect. In addition, by merging the contact formation process and the GLS structure formation process, the application of the photolithography process can be reduced, thereby reducing the process difficulty and production cost. In summary, the present disclosure can solve the manufacturing problems caused by structural stress, thereby breaking through the technical bottleneck in the research and development of higher-level 3D memory devices.

[0158] The foregoing description of the specific embodiments will fully reveal the general nature of the present disclosure, so that others can easily modify and / or adapt to various applications of such specific embodiments without departing from the overall concept of the present disclosure and without excessive experimentation by applying knowledge within the technical scope of the art. Therefore, based on the teachings and guidance presented herein, such adaptations and modifications are intended to be within the meaning and scope of the equivalents of the disclosed embodiments. It should be understood that the wording or terminology herein is for the purpose of description rather than limitation, so that the terms or wording of this specification will be interpreted by those skilled in the art based on teaching and guidance.

[0159] The embodiments of the present disclosure have been described above by means of functional building blocks that illustrate the embodiments of specific functions and their relationships. For ease of description, the boundaries of these functional building blocks are arbitrarily defined here. Alternative boundaries can be defined as long as the specified functions and their relationships are properly performed.

[0160] The Summary and Abstract sections may set forth one or more but not all embodiments of the present disclosure as contemplated by the inventor(s), and thus, are not intended to limit the present disclosure and the appended claims in any way.

[0161] The breadth and scope of the present disclosure should not be limited by any of the above-described embodiments, but should be defined only in accordance with the following claims and their equivalents.

Claims

1. A semiconductor device, comprising: A stacked structure including an array region and a contact region; as well as A gate line gap structure vertically extending through the stack structure and extending laterally along a first lateral direction to divide the stack structure into storage blocks, the gate line gap structure comprising: a first dummy channel structure located at a boundary between the array region and the contact region; a first gate line gap segment extending laterally from the first dummy channel structure to the array region; and A second gate line gap segment extends laterally from the first dummy channel structure into the contact region.

2. The semiconductor device according to claim 1, further comprising: Channel structures, each extending vertically through the stacked structure and located in the array region; as well as The second dummy channel structures each vertically extend through the stacked structure and are located in the contact region.

3. The semiconductor device according to claim 2, wherein: The stacked structure in the array region includes conductive layers and first dielectric layers alternately stacked in a vertical direction; and The stacked structure in the contact region comprises: a first contact portion, adjacent to the second gate line gap segment, and comprising the conductive layer and the first dielectric layer alternately stacked in the vertical direction; as well as The second contact portion is separated from the second gate line gap segment by the first contact portion and includes first dielectric layers and second dielectric layers alternately stacked in the vertical direction.

4. The semiconductor device according to claim 3, wherein: The second dummy channel structures each vertically extend through the first contact portion.

5. The semiconductor device according to claim 1, wherein: A first width of the first dummy channel structure along the first lateral direction is greater than a second width of the first dummy channel structure along a second lateral direction orthogonal to the first lateral direction.

6. The semiconductor device according to claim 1, wherein: The first dummy channel structure includes a high-k layer, a first oxide layer, a nitride layer, a second oxide layer, a semiconductor layer and a filling structure.

7. The semiconductor device according to claim 1, wherein: The first dummy channel structure includes an oxide structure and a semiconductor segment laterally surrounded by the oxide structure.

8. The semiconductor device according to claim 7, wherein: The oxide structure comprises: a convex sidewall surface adjacent to the first gate line gap segment; and A concave sidewall surface adjacent to the second gate line gap segment.

9. The semiconductor device according to claim 3, wherein: Each of the first gate line slit segment and the second gate line slit segment includes a wall structure extending laterally in the first lateral direction and insulated from the conductive layer.

10. The semiconductor device according to claim 3, further comprising: The gate line contact structures all extend vertically in the second contact portion and laterally contact the corresponding conductive layer in the first contact portion.

11. The semiconductor device according to claim 10, wherein: Each gate line contact structure includes: a conductive landing layer in the second contact portion and in lateral contact with the corresponding conductive layer; and A conductive via vertically passes through the second dielectric layer and the first dielectric layer above the conductive landing layer and contacts the conductive landing layer.

12. A method for forming a semiconductor device, comprising: forming a dielectric stack comprising alternating second dielectric layers and first dielectric layers; forming rows of first through holes, the first through holes being laterally aligned along a first lateral direction and each vertically passing through the dielectric stack; forming a sacrificial filling structure in the first through hole; removing the sacrificial filling structure from a first through hole at a boundary between the array region and the contact region; forming a first dummy channel structure in the one first through hole; removing the sacrificial fill structure from other first vias and removing portions of the dielectric stack to form a first trench in the array region and a second trench in the contact region; as well as A first gate line gap segment is formed in the first trench, and a second gate line gap segment is formed in the second trench.

13. The method according to claim 12, when forming the row of the first through holes, the method further comprises: forming a second through hole in the array region; as well as forming a third through hole adjacent to the first through hole in the contact region; Wherein, a first distance between adjacent first through holes is smaller than a second distance between adjacent second through holes.

14. The method according to claim 13, when forming a sacrificial filling structure in the first through hole, the method further comprises: A sacrificial filling structure is formed in the second through hole and the third through hole.

15. The method according to claim 14, when removing the sacrificial filling structure from the one first through hole, the method further comprises: The sacrificial fill structure is removed from the second and third vias.

16. The method according to claim 15, when forming the first dummy channel structure, the method further comprises: forming a channel structure in the second through hole; as well as A second dummy channel structure is formed in the third through hole.

17. The method according to claim 16, further comprising: forming a first sacrificial wall in the first trench and forming a second sacrificial wall in the second trench; removing the first sacrificial wall to reopen the first trench; The reopened first trench replaces the second dielectric layer in the array region with a conductive layer; removing the second sacrificial wall to reopen the second trench; as well as A portion of the second dielectric layer in the contact region adjacent to the second trench is replaced with a conductive layer.

18. The method according to claim 17, wherein: Forming the first dummy channel structure includes: forming a first oxide layer on a sidewall of the first through hole; forming a nitride layer on the first oxide layer; forming a second oxide layer on the nitride layer; forming a semiconductor layer on the second oxide layer; and A filling structure is formed on the semiconductor layer to fill the one first through hole.

19. The method according to claim 18, further comprising: When removing the sacrificial filling structure from other first through holes and removing portions of the dielectric stack, also removing portions of the first oxide layer, the nitride layer, and the second oxide layer to expose sidewalls of the semiconductor layer in the first trench and the second trench; oxidizing the exposed sidewalls of the semiconductor layer; When replacing the second dielectric layer in the array region, also removing a remaining portion of the nitride layer to form a curved opening; as well as A portion of the second sacrificial wall exposed by the curved opening is oxidized.

20. The method of claim 18, further comprising: forming a high-k layer on the sidewall of the one first through hole; Wherein, the first oxide layer is formed on the high-k layer.

21. The method according to claim 12, wherein: Forming the first gate line gap segment and the second gate line gap segment includes: forming an insulating layer on sidewalls and bottoms of the first trench and the second trench; and A wall structure is formed on the insulating layer to fill the first trench and the second trench.

22. The method of claim 17, further comprising: A gate line contact structure is formed that passes through a remaining portion of the dielectric stack in the contact region and contacts a corresponding conductive layer in the contact region.

23. The method according to claim 22, wherein: Forming the gate line contact structure includes: forming a contact hole through a portion of the dielectric stack to expose a sacrificial layer in the same horizontal plane as the corresponding conductive layer; removing a portion of the one sacrificial layer to form a lateral recess, thereby exposing the corresponding conductive layer; forming a landing conductive layer in the lateral recess in contact with the corresponding conductive layer; and A conductive via is formed in the contact hole to contact the landing conductive layer.

24. A storage device comprising: The stacking structure includes: a first conductive / dielectric stack in the array region; a second conductive / dielectric stack in the contact region; and a dielectric stack in said contact region; A gate line gap structure vertically extending through the stack structure and extending laterally along a first lateral direction to divide the stack structure into storage blocks, the gate line gap structure comprising: a first dummy channel structure located at a boundary between the array region and the contact region; a first gate line gap segment extending laterally from the first dummy channel structure to the array region; and a second gate line gap segment extending laterally from the first dummy channel structure to the contact region; channel structures, each extending vertically through the first conductive / dielectric stack; second dummy channel structures each extending vertically through the second conductive / dielectric stack and adjacent to the second gate line gap segment; and The gate line contact structures each extend vertically in the dielectric stack and laterally contact a corresponding conductive layer of the second conductive / dielectric stack.

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