High-voltage BJT (Bipolar Junction Transistor) device applying SiC BCD process and preparation method thereof

Abstract

The invention relates to a high-voltage BJT (Bipolar Junction Transistor) device applying a SiC BCD (Bipolar Compact Disc) process and a preparation method thereof. The high-voltage BJT device comprises a drift region; a collector region extending from the surface of the drift region to the inside of the drift region; the collector electrode is positioned on the collector region; the diversion layer is located on the drift region and is spaced from the collector region; the JTE-GR terminal junction extends from the surface of the drift region to the interior of the drift region and is located between the collector region and the diversion layer; the base region is located on the diversion layer; the base region ohmic contact region extends from the surface of the base region to the interior of the base region; the base electrode is located on the base region ohmic contact region; the emitter region is located on the base region, and the emitter region and the base region ohmic contact region are arranged at intervals; and the emitter is located on the emitter region, and the base is located between the emitter and the collector. According to the embodiment of the invention, the advantages of a JTE terminal and a GR terminal are combined, so that the sensitivity of the terminal junction to concentration is reduced while the terminal junction bears higher blocking voltage.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor technology, and in particular relates to a high-voltage BJT device using a SiC BCD process and a preparation method thereof. Background Art

[0002] With the development of microelectronics technology, high-voltage integrated circuits (HVIC) are becoming increasingly important in various high-voltage and high-power applications. In these applications, lateral high-voltage SiC bipolar junction transistors (BJTs) have attracted much attention due to their excellent performance. As a third-generation semiconductor material, SiC has a wider bandgap, higher breakdown electric field, thermal conductivity, electron saturation rate and radiation resistance, which gives it significant advantages in the field of high-temperature, high-frequency, radiation-resistant high-power devices.

[0003] SiC BJT has the advantages of high breakdown voltage, low on-resistance, high switching frequency, and high temperature reliability. However, in order to further improve the performance of SiC BJT, especially in its application in high-voltage integrated circuits, terminal design is crucial. At present, some common terminal design technologies include junction terminal extension (JTE) and floating field limiting rings (FFLRs). The JTE structure can effectively modulate the surface electric field of the device by adding a highly doped buffer layer at the junction terminal, thereby increasing the breakdown voltage. The FFLRs structure can further modulate the surface electric field and increase the breakdown voltage by forming a field limiting ring at the junction terminal. However, both terminal structures have problems such as strong charge sensitivity and electric field peaks. Summary of the invention

[0004] In order to solve the above problems existing in the prior art, the present invention provides a high voltage BJT device using SiC BCD process and a preparation method thereof. The technical problem to be solved by the present invention is achieved by the following technical solutions:

[0005] An embodiment of the present invention provides a high-voltage BJT device using a SiC BCD process, including:

[0006] Drift zone;

[0007] A collector region extending from a surface of the drift region to an interior of the drift region;

[0008] A collector electrode, located on the collector region;

[0009] A guide layer, located on the drift region and spaced apart from the collector region;

[0010] A JTE-GR terminal junction extends from the surface of the drift region to the interior of the drift region and is located between the collector region and the guide layer, wherein the JTE-GR terminal junction is formed by alternating distribution of the GR terminal region and the JTE terminal region and the GR terminal region is located outside the JTE terminal region;

[0011] A base region, located on the guide layer;

[0012] A base region ohmic contact region extending from the surface of the base region to the interior of the base region;

[0013] A base electrode, located on the base ohmic contact region;

[0014] An emitter region, located on the base region and spaced apart from the base region ohmic contact region;

[0015] The emitter is located on the emitter region, and the base is located between the emitter and the collector.

[0016] In one embodiment of the present invention, the JTE-GR terminal junction includes a plurality of GR terminal regions and a plurality of JTE terminal regions, wherein:

[0017] The plurality of GR terminal areas are distributed at intervals; the plurality of JTE terminal areas are distributed between two adjacent GR terminal areas and are in contact with the GR terminal areas;

[0018] The doping concentration of the GR terminal region is greater than the doping concentration of the JTE terminal region, and the depth of the GR terminal region is greater than the depth of the JTE terminal region.

[0019] In one embodiment of the present invention, the drift region is an N-type drift region, the guide layer is a P-type guide layer, the base region is a P-type base region, and the emitter region is an N-type emitter region.

[0020] In one embodiment of the present invention, an N-type ohmic contact is formed between the collector electrode and the collector region;

[0021] A P-type ohmic contact is formed between the base electrode and the base ohmic contact region;

[0022] An N-type ohmic contact is formed between the emitter and the emitter region.

[0023] In one embodiment of the present invention, it further comprises a RESURF region and a substrate, wherein:

[0024] The RESURF region is located on a surface of the drift region away from the collector region;

[0025] The substrate is located on a surface of the RESURF region away from the drift region.

[0026] In one embodiment of the present invention, the RESURF region is a P-type epitaxial layer.

[0027] Another embodiment of the present invention provides a method for preparing a high voltage BJT device using a SiC BCD process, comprising the steps of:

[0028] sequentially growing a guide layer and a base region on the drift region, and growing an emitter region on the base region;

[0029] Performing ion implantation in the base region to form a base region ohmic contact region spaced apart from the emitter region;

[0030] Performing ion implantation in the drift region to form a JTE-GR terminal junction spaced apart from the guide layer;

[0031] Performing ion implantation in the drift region to form a collector region spaced apart from the JTE-GR terminal junction, wherein the JTE-GR terminal junction is located between the collector region and the guide layer;

[0032] Metal is prepared on the emitter region, the base ohmic contact region and the collector region to form an emitter, a base and a collector.

[0033] In one embodiment of the present invention, ion implantation is performed in the drift region to form a JTE-GR terminal junction spaced apart from the guide layer, including:

[0034] Performing a first ion implantation in the drift region to form a plurality of GR terminal regions spaced apart from each other;

[0035] A second ion implantation is performed between two adjacent GR terminal regions to form a plurality of JTE terminal regions in contact with the GR terminal regions, wherein the doping concentration of the GR terminal regions is greater than the doping concentration of the JTE terminal regions, and the depth of the GR terminal regions is greater than the depth of the JTE terminal regions.

[0036] In one embodiment of the present invention, before metal is prepared on the emitter region, the base ohmic contact region and the collector region to form the emitter, base and collector, the following steps are also included:

[0037] Depositing a contact metal on the base ohmic contact region to form a P-type ohmic contact;

[0038] Contact metal is deposited on the emitter region and the collector region to form an N-type ohmic contact.

[0039] In one embodiment of the present invention, before sequentially growing the guide layer and the base region on the drift region, the process further includes the following steps:

[0040] A RESURF region and a drift region are epitaxially grown in sequence on the substrate.

[0041] Compared with the prior art, the present invention has the following beneficial effects:

[0042] 1. In the present invention, a JTE-GR terminal junction is arranged in the drift region between the collector region and the guide layer, and the GR terminal junction is located at both ends of the JTE terminal junction. The GR terminal junction can effectively adjust the end electric field of the JTE terminal junction. The JTE-GR terminal junction combines the advantages of the JTE terminal and the GR terminal, so that the terminal junction can withstand a higher blocking voltage while reducing the sensitivity of the terminal junction to concentration, solving the problem of a strong electric field peak, and improving the stability of the terminal junction;

[0043] 2. The present invention sets a RESURF region on the back of the drift region, which reduces the surface electric field of the device and thus increases the breakdown voltage of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] Figure 1 A schematic structural diagram of a high-voltage BJT device using a SiC BCD process provided by an embodiment of the present invention;

[0045] Figure 2a-2g A schematic flow chart of a method for preparing a high-voltage BJT device using a SiC BCD process is provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0046] The present invention is further described in detail below with reference to specific embodiments, but the embodiments of the present invention are not limited thereto.

[0047] Embodiment 1

[0048] See also Figure 1 , Figure 1 A schematic structural diagram of a high-voltage BJT device using a SiC BCD process is provided in an embodiment of the present invention. The high-voltage BJT device is a lateral BJT device structure, including: a drift region 3; a collector region 4, extending from the surface of the drift region 3 to the inside of the drift region 3; a collector electrode 5, located on the collector region 4; a guide layer 7, located on the drift region 3 and spaced apart from the collector region 4; a JTE-GR terminal junction 6, extending from the surface of the drift region 3 to the inside of the drift region 3, and located between the collector region 4 and the guide layer 7, wherein the JTE-GR terminal junction is formed alternately by the GR terminal region and the JTE terminal region and the GR terminal region is located outside the JTE terminal region; a base region 8, located on the guide layer 7; a base region ohmic contact region 9, extending from the surface of the base region 8 to the inside of the base region 8; a base electrode 10, located on the base region ohmic contact region 9; an emitter region 11, located on the base region 8 and spaced apart from the base region ohmic contact region 9; an emitter electrode 12, located on the emitter region 11, and the base electrode 10 is located between the emitter electrode 12 and the collector electrode 5.

[0049] Specifically, in the vertical direction, the high-voltage BJT device includes from bottom to top: a drift region 3, a guide layer 7 and a base region 8 epitaxially grown in sequence on the surface of one side of the drift region 3, and an emitter region 11 epitaxially grown on the surface of one side of the base region 8; in the planar direction, a collector region 4 and a JTE-GR terminal junction 6 are formed by ion implantation on the surface of the drift region 3, and the JTE-GR terminal junction 6 is spaced between the guide layer 7 and the collector region 4; a base ohmic contact region 9 is formed by ion implantation on the surface of the base region 8, and the base ohmic contact region 9 is spaced from the emitter region 11, and the emitter 12, the base 10, and the collector 5 are arranged in sequence along the horizontal direction.

[0050] Specifically, the JTE-GR terminal junction 6 is formed by the alternating distribution of the junction termination extension (JTE) terminal region and the guard ring (GR) terminal region, and the GR terminal region is located on the outside of the JTE terminal region to form a GR ring, surrounding the JTE terminal region, that is, the two ends of the JTE-GR terminal junction 6 are GR terminal regions, and between the two GR terminal regions, the JTE terminal region and the GR terminal region are alternately distributed.

[0051] In this embodiment, a JTE-GR terminal junction is arranged in the drift region between the collector region and the guide layer, and the GR terminal region is located at both ends of the JTE terminal region. The GR terminal region can effectively adjust the end electric field of the JTE terminal region. The JTE-GR terminal junction combines the advantages of the JTE terminal and the GR terminal, so that the terminal junction can withstand a higher blocking voltage while reducing the sensitivity of the terminal junction to concentration. While maintaining a high breakdown voltage, it can solve the problem of the electric field peak to a certain extent, thereby improving the stability of the terminal junction.

[0052] In a specific embodiment, the JTE-GR terminal junction 6 includes a plurality of GR terminal regions 61 and a plurality of JTE terminal regions 62, wherein the plurality of GR terminal regions 61 are distributed at intervals; the plurality of JTE terminal regions 62 are distributed between two adjacent GR terminal regions 61 and are in contact with the GR terminal regions 61; the doping concentration of the GR terminal region 61 is greater than the doping concentration of the JTE terminal region 62, and the depth of the GR terminal region 61 is greater than the depth of the JTE terminal region 62.

[0053] Specifically, the GR terminal regions 61 and the JTE terminal regions 62 are all P-type doping regions, and the doping concentration of the GR terminal region 61 is greater than the doping concentration of the JTE terminal region 62, that is, the GR terminal region 61 is a P+ implantation region, and the JTE terminal region 62 is a P- implantation region. Furthermore, the ion implantation depth of the GR terminal region 61 is greater than the implantation depth of the JTE terminal region 62, forming a terminal junction with a high depth and a low depth alternately arranged.

[0054] Compared with the traditional JTE terminal junction structure, this embodiment combines the advantages of the JTE terminal and the GR terminal to improve the stability of the terminal junction. The two ends of the traditional JTE terminal junction are prone to electric field peaks, while in the JTE-GR terminal junction structure of this embodiment, when the concentration of the first P-type region, i.e., the JTE terminal junction, is low, the front end of the JTE is partially depleted, but the GR part in the JTE-GR terminal is not depleted due to high concentration doping, so the high concentration of the GR terminal junction can effectively adjust the electric field distribution of the depletion region of the JTE terminal junction, and to a certain extent avoid the possibility of breakdown at the front end of the JTE terminal junction; and when the JTE concentration is high, the end of the JTE terminal junction is prone to electric field peaks, but the GR terminal junction can extend the depletion layer outward, optimize the electric field distribution, and share the voltage of the JTE part.

[0055] In a specific embodiment, the drift region 3 is an N-type drift region, the guide layer 7 is a P-type guide layer, the base region 8 is a P-type base region, and the emitter region 11 is an N-type emitter region.

[0056] In a specific embodiment, an N-type ohmic contact is formed between the collector 5 and the collector region 4 ; a P-type ohmic contact is formed between the base 10 and the base ohmic contact region 9 ; and an N-type ohmic contact is formed between the emitter 12 and the emitter region 11 .

[0057] It can be understood that an N-type ohmic contact metal is deposited between the collector 5 and the collector region 4 , a P-type ohmic contact metal is deposited between the base 10 and the base ohmic contact region 9 , and an N-type ohmic contact metal is deposited between the emitter 12 and the emitter region 11 .

[0058] In a specific embodiment, the high voltage BJT device further includes a RESURF region 2 and a substrate 1 , wherein the RESURF region 2 is located on a surface of the drift region 3 away from the collector region 4 ; and the substrate 1 is located on a surface of the RESURF region 2 away from the drift region 3 .

[0059] Specifically, the RESURF region 2 is a P-type epitaxial layer.

[0060] In this embodiment, a RESURF region is disposed on the back side of the drift region, which reduces the surface electric field of the device and thus improves the breakdown voltage of the device.

[0061] Embodiment 2

[0062] See also Figure 2a-2g , Figure 2a-2g A schematic flow chart of a method for preparing a high-voltage BJT device using a SiC BCD process is provided in an embodiment of the present invention.

[0063] The method for preparing a high voltage BJT device using the SiC BCD process in this embodiment includes the following steps:

[0064] S1, epitaxially growing a RESURF region 2 and a drift region 3 on a substrate 1 in sequence, as shown in Figure 2a shown.

[0065] First, a SiC single crystal substrate 1 is prepared.

[0066] Then, the SiC single crystal substrate 1 is finely processed, including cutting, grinding and polishing, to obtain a flat and defect-free surface. Before growing the epitaxial layer, the substrate surface needs to be thoroughly cleaned to remove the oxide layer and impurities on the surface to ensure good bonding between the epitaxial layer and the substrate 1.

[0067] Next, the RESURF region 2 is first epitaxially grown using the MOCVD process, and P-type epitaxial doping is performed at the same time; then the drift region 3 is epitaxially grown on the RESURF region 2, and N-type epitaxial doping is performed at the same time. The materials of the RESURF region 2 and the drift region 3 both include SiC. By controlling the gas flow rate and the reaction chamber conditions, the molar flow rate of the dopant entering the reaction chamber is accurately controlled, thereby controlling the doping concentration in the SiC. The RESURF region 2 has P-type doping, which can use titanium tetrachloride (TiCl4) as a P-type dopant. The drift region 3 is an N-type doping region, which can use nitrogen (N2) as an N-type dopant.

[0068] S2, sequentially growing the guide layer 7 and the base region 8 on the drift region 3, and growing the emitter region 11 on the base region 8, as shown in FIG. Figure 2b shown.

[0069] Specifically, the guide layer 7 and the base region 8 are epitaxially grown on the drift region 3 in sequence by using the MOCVD process, and P-type epitaxial doping is performed during the epitaxy; then the emitter region 11 is epitaxially grown on the base region 8, and N-type epitaxial doping is performed during the epitaxy. The materials of the guide layer 7, the base region 8, and the emitter region 11 all include SiC, and the molar flow rate of the dopant entering the reaction chamber is precisely controlled by controlling the gas flow rate and the reaction chamber conditions, thereby controlling the doping concentration in the SiC. The guide layer 7 is a P-type guide layer, and the base region 8 is a P-type base region, and titanium tetrachloride (TiCl4) can be used as a P-type dopant. The emitter region 11 is an N-type emitter region, which can use nitrogen (N2) as an N-type dopant.

[0070] S3, ion implantation is performed in the base region 8 to form a base region ohmic contact region 9 spaced apart from the emitter region 11, such as Figure 2c shown.

[0071] Specifically, a layer of metal or other material is deposited on the surface of the wafer as an ion implantation barrier layer, and then the window pattern of the P-type base region 8 for ion implantation is obtained through mask photolithography transfer, and then the excess mask barrier material is etched away to form an ion implantation barrier window, and then ion implantation is performed, using aluminum (Al) as the donor element of the P-type region to form a P-type base region ohmic contact region 9 with a higher doping concentration, which facilitates the formation of ohmic contact and reduces contact resistance.

[0072] S4, performing ion implantation in the drift region 3 to form a JTE-GR terminal junction 6 spaced apart from the guide layer 7. Specifically comprising:

[0073] S41, perform the first ion implantation in the drift region 3 to form a plurality of GR terminal regions 61 arranged at intervals, such as Figure 2d shown.

[0074] Specifically, a layer of metal or other material is deposited on the surface of the wafer as an ion implantation barrier layer, and then the window pattern of the drift region 3 for ion implantation is obtained by mask photolithography transfer, and then the excess mask barrier material is etched away to form the first ion implantation barrier window, and then ion implantation is performed, using aluminum (Al) as the donor element of the P-type region to form a heavily doped GR terminal region 61.

[0075] S42, performing a second ion implantation between two adjacent GR terminal regions 61 to form a plurality of JTE terminal regions 62 in contact with the GR terminal regions 61, wherein the doping concentration of the GR terminal regions 61 is greater than the doping concentration of the JTE terminal regions 62, and the depth of the GR terminal regions 61 is greater than the depth of the JTE terminal regions 62, such as Figure 2e shown.

[0076] Specifically, a layer of metal or other material is deposited on the surface of the wafer as an ion implantation barrier layer, and then the window pattern of the drift region 3 for ion implantation is obtained by mask photolithography transfer, and then the excess mask barrier material is etched away to form a second ion implantation barrier window, and then ion implantation is performed, using aluminum (Al) as the donor element of the P-type region to form a lightly doped and shallow JTE terminal region 62, and the GR terminal region 61 and the JTE terminal region 62 form a JTE-GR terminal junction 6 with a high and a low implantation depth and arranged at intervals.

[0077] S5, ion implantation is performed in the drift region 3 to form a collector region 4 spaced apart from the JTE-GR terminal junction 6, wherein the JTE-GR terminal junction 6 is located between the collector region 4 and the guide layer 7, such as Figure 2f shown.

[0078] Specifically, a layer of metal or other material is deposited on the surface of the wafer as an ion implantation barrier layer, and then the window pattern of the collector region 4 for ion implantation is obtained by mask photolithography transfer, and then the excess mask barrier material is etched away to form an ion implantation barrier window, and then ion implantation is performed, using phosphorus (P) as the donor element of the N-type region to form an N-type collector region 4.

[0079] Furthermore, after ion implantation, since the high-energy implanted ions form many tiny defects in the crystal, the implanted atoms do not properly occupy the lattice position, so the resistance of the implanted area is high. For SiC wafers that undergo ion implantation, high-temperature (usually above 1700°C) activation annealing is performed in an inert gas atmosphere to form P-type and N-type low-resistance areas.

[0080] S6, preparing metal on the emitter region 11, the base ohmic contact region 9 and the collector region 4 to form an emitter 12, a base 10 and a collector 5, such as Figure 2g shown.

[0081] First, a contact metal is deposited on the base ohmic contact region 9 to form a P-type ohmic contact. Specifically, a front P-type ohmic contact window pattern is first transferred on the base ohmic contact region 9 by mask lithography, and then the excess sacrificial oxide layer is etched away to form a P-type ohmic contact window, and then a contact metal is deposited on the surface of the wafer, and then the photoresist and excess metal are removed by a stripping process, and then the wafer is cleaned and dried, and metallization annealing is performed to form a P-type ohmic contact on the base ohmic contact region 9.

[0082] Then, a contact metal is deposited on the emitter region 11 and the collector region 4 to form an N-type ohmic contact. Specifically, first, a front N-type ohmic contact window pattern is transferred on the emitter region 11 and the collector region 4 by mask lithography, and then the excess sacrificial oxide layer and passivation layer are etched away to form an N-type ohmic contact window, and then a contact metal is deposited on the wafer surface, and then the photoresist and excess metal are removed by a stripping process, and then the wafer is cleaned and dried, and metallization annealing is performed to form an N-type ohmic contact on the emitter region 11 and the collector region 4.

[0083] Next, a layer of metal (such as metal Al) is deposited on the front of the wafer as a whole. Then, the electrode patterns of the front emitter 12, base 10 and collector 5 are obtained by mask photolithography transfer, and then the electrodes of the emitter 12, base 10 and collector 5 are separated by etching to form the outermost metal electrode of the device.

[0084] Finally, the photoresist is removed and the device surface is cleaned to complete the device preparation.

[0085] The high-voltage BJT device of this embodiment adopts the JTE-GR terminal junction, which can solve the problem of electric field peak to a certain extent while maintaining a high breakdown voltage, thereby improving the stability of the terminal junction.

[0086] The above contents are further detailed descriptions of the present invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is limited to these descriptions. For ordinary technicians in the technical field to which the present invention belongs, several simple deductions or substitutions can be made without departing from the concept of the present invention, which should be regarded as falling within the protection scope of the present invention.

Claims

1. A high voltage BJT device using SiC BCD technology, characterized in that: include: Drift zone; A collector region extending from a surface of the drift region to an interior of the drift region; A collector electrode, located on the collector region; A guide layer, located on the drift region and spaced apart from the collector region; A JTE-GR terminal junction extends from the surface of the drift region to the interior of the drift region and is located between the collector region and the guide layer, wherein the JTE-GR terminal junction is formed by alternating distribution of the GR terminal region and the JTE terminal region and the GR terminal region is located outside the JTE terminal region; A base region, located on the guide layer; A base region ohmic contact region extending from the surface of the base region to the interior of the base region; A base electrode, located on the base ohmic contact region; An emitter region, located on the base region and spaced apart from the base region ohmic contact region; The emitter is located on the emitter region, and the base is located between the emitter and the collector.

2. The high voltage BJT device using SiC BCD process according to claim 1, characterized in that: The JTE-GR terminal junction includes a plurality of GR terminal regions and a plurality of JTE terminal regions, wherein: The plurality of GR terminal areas are distributed at intervals; the plurality of JTE terminal areas are distributed between two adjacent GR terminal areas and are in contact with the GR terminal areas; The doping concentration of the GR terminal region is greater than the doping concentration of the JTE terminal region, and the depth of the GR terminal region is greater than the depth of the JTE terminal region.

3. The high voltage BJT device using SiC BCD process according to claim 1, characterized in that: The drift region is an N-type drift region, the guide layer is a P-type guide layer, the base region is a P-type base region, and the emitter region is an N-type emitter region.

4. The high voltage BJT device using SiC BCD process according to claim 1, characterized in that: An N-type ohmic contact is formed between the collector electrode and the collector region; A P-type ohmic contact is formed between the base electrode and the base ohmic contact region; An N-type ohmic contact is formed between the emitter and the emitter region.

5. The high voltage BJT device using SiC BCD process according to claim 1, characterized in that: Also included is a RESURF region and a substrate, wherein The RESURF region is located on a surface of the drift region away from the collector region; The substrate is located on a surface of the RESURF region away from the drift region.

6. The high voltage BJT device using SiC BCD process according to claim 5, characterized in that: The RESURF region is a P-type epitaxial layer.

7. A method for preparing a high voltage BJT device using SiC BCD technology, characterized in that: Includes steps: sequentially growing a guide layer and a base region on the drift region, and growing an emitter region on the base region; Performing ion implantation in the base region to form a base region ohmic contact region spaced apart from the emitter region; Performing ion implantation in the drift region to form a JTE-GR terminal junction spaced apart from the guide layer; Performing ion implantation in the drift region to form a collector region spaced apart from the JTE-GR terminal junction, wherein the JTE-GR terminal junction is located between the collector region and the guide layer; Metal is prepared on the emitter region, the base ohmic contact region and the collector region to form an emitter, a base and a collector.

8. The method for preparing a high voltage BJT device using SiC BCD technology according to claim 7, characterized in that: Ion implantation is performed in the drift region to form a JTE-GR terminal junction spaced apart from the guide layer, including: Performing a first ion implantation in the drift region to form a plurality of GR terminal regions spaced apart from each other; A second ion implantation is performed between two adjacent GR terminal regions to form a plurality of JTE terminal regions in contact with the GR terminal regions, wherein the doping concentration of the GR terminal regions is greater than the doping concentration of the JTE terminal regions, and the depth of the GR terminal regions is greater than the depth of the JTE terminal regions.

9. The method for preparing a high voltage BJT device using SiC BCD technology according to claim 7, characterized in that: Before metal is prepared on the emitter region, the base ohmic contact region and the collector region to form the emitter, base and collector, the following steps are also included: Depositing a contact metal on the base ohmic contact region to form a P-type ohmic contact; Contact metal is deposited on the emitter region and the collector region to form an N-type ohmic contact.

10. The method for preparing a high voltage BJT device using SiC BCD technology according to claim 7, characterized in that: Before the guide layer and the base region are sequentially grown on the drift region, the steps include: A RESURF region and a drift region are epitaxially grown in sequence on the substrate.

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