IGBT device and preparation method thereof

Abstract

The invention provides an IGBT (Insulated Gate Bipolar Translator) device and a preparation method thereof. The IGBT device comprises a semiconductor substrate with a first conductive type; the plurality of column regions of the second conduction type are transversely arranged in the semiconductor substrate at intervals; the epitaxial layer is formed on the semiconductor substrate; the body region is formed on the top of the epitaxial layer; the carrier storage layer has a first conduction type and is formed in the epitaxial layer below the body region; the first trench and the second trench penetrate through the body region and the carrier storage layer from the top surface of the body region and abut against the top surface of the column region; the gate region is formed in the first groove, is positioned at the upper part of the groove and is isolated by a gate dielectric layer; the first split gate is formed in the first groove, is positioned at the lower part of the groove and is isolated through an interlayer dielectric layer; and the second split gate is formed in the second groove and is isolated by the interlayer dielectric layer. The structure can improve the compromise relationship between the forward conduction voltage drop and the turn-off loss of the device.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to an insulated gate bipolar transistor (IGBT) device and a preparation method thereof. Background Art

[0002] IGBT is a new type of power semiconductor device that combines the gate voltage control characteristics of MOSFET and the low on-resistance characteristics of BJT, improving the device characteristics. It has broad market development space and application prospects in white appliances, industrial control, automotive electronics, new energy and other fields.

[0003] In IGBT, there is often a trade-off between forward voltage drop and turn-off loss. In order to reduce the forward voltage drop, researchers often sacrifice the larger turn-off loss, resulting in larger switching losses under high switching frequency conditions. Therefore, improving the trade-off between the forward voltage drop and turn-off loss of IGBT has always been a difficult problem that researchers urgently need to solve. Summary of the invention

[0004] The purpose of the present application is to provide an IGBT device and a method for manufacturing the same, which improves the trade-off relationship between the forward conduction voltage drop and the turn-off loss of the device.

[0005] In a first aspect, the present application provides an IGBT device, which includes: a semiconductor substrate having a first conductivity type; a plurality of column regions of a second conductivity type, wherein the plurality of column regions of the second conductivity type are laterally spaced apart in the semiconductor substrate; an epitaxial layer formed on the semiconductor substrate; a body region formed on the top of the epitaxial layer; a carrier storage layer having the first conductivity type, formed in the epitaxial layer below the body region; a first trench and a second trench, extending from the top surface of the body region through the body region and the carrier storage layer to the top surface of the column region; a gate region formed in the first trench and located in the upper part of the trench, wherein a gate dielectric layer isolates the gate region from the body region and the emitter region; a first split gate formed in the first trench and located in the lower part of the trench, wherein an interlayer dielectric layer isolates the first split gate from the gate region, the carrier storage layer and the column region, respectively; a second split gate formed in the second trench, wherein the interlayer dielectric layer isolates the second split gate from the body region, the carrier storage layer and the column region, respectively.

[0006] In a second aspect, the present application also provides a method for preparing an IGBT device, the method comprising: forming a column region having a second conductivity type on a semiconductor substrate of a first conductivity type; growing an epitaxial layer on the top surface of the semiconductor substrate and the column region; digging grooves on the epitaxial layer from top to bottom to form a first groove and a second groove; filling polysilicon after forming a dielectric layer at the bottom and sidewalls of the first groove and the second groove to form a second split gate in the second groove; etching the polysilicon in the first groove to form a first split gate; forming a dielectric layer in the first groove for a second time and then filling polysilicon to form a gate region; performing ion implantation on the top of the epitaxial layer to form a carrier storage layer, a body region and an emitter region respectively; performing ion implantation on the bottom of the semiconductor substrate to form a field stop layer of the first conductivity type and a collector region of the second conductivity type.

[0007] In a third aspect, the present application also provides a method for preparing an IGBT device, the method comprising: growing a first epitaxial layer of a first conductivity type on a substrate of a first conductivity type; forming a column region of a second conductivity type on the first epitaxial layer; growing a second epitaxial layer on the top surface of the first epitaxial layer and the column region; digging grooves in the second epitaxial layer from top to bottom to form a first groove and a second groove; filling polysilicon after forming a dielectric layer at the bottom and sidewalls of the first groove and the second groove to form a second split gate in the second groove; etching the polysilicon in the first groove to form a first split gate; forming a dielectric layer in the first groove for a second time and then filling polysilicon to form a gate region; performing ion implantation on the top of the second epitaxial layer to form a carrier storage layer, a body region and an emitter region respectively; removing the substrate, and performing ion implantation at the bottom of the first epitaxial layer to form a field stop layer of the first conductivity type and a collector region of the second conductivity type.

[0008] The present application provides an IGBT device and a preparation method thereof, in which the lower part of the device has multiple column regions and semiconductor substrates interlaced to form a super junction region, which can increase the breakdown voltage BV of the IGBT device. Since the super junction region will form a lateral electric field, the longitudinal electric field in the lower part of the device will be changed from the triangular distribution of the traditional structure to an approximately rectangular distribution. In the upper part of the device, the first split gate, the interlayer dielectric layer, the carrier storage layer and the second split gate form a capacitive depletion region, which can also realize the change of the longitudinal electric field from the triangular distribution of the traditional structure to an approximately rectangular distribution. Therefore, the IGBT device structure will have a thinner chip thickness at the same breakdown voltage, thereby reducing the forward conduction voltage drop. The thinner chip thickness will in turn make the IGBT have a faster turn-off speed when it is turned off, thereby reducing the switching loss, and then improving the compromise relationship between the forward conduction voltage drop and the turn-off loss. In addition, when the IGBT device is forward-conducted, the auxiliary depletion effect of the first split gate and the second split gate can ensure that the doping concentration of the carrier storage layer is greatly increased under the premise that the breakdown voltage is not attenuated, so that the hole barrier height in the first conductive type conductive column of the carrier storage layer and the super junction region is further increased, thereby enhancing the conductivity modulation effect when the device is forward-conducted, and reducing the forward conduction voltage drop and conduction loss of the device. In addition, the first split gate and the second split gate can select one or all of the negative voltage to establish a minority current channel, thereby improving the turn-off speed of the IGBT device and reducing the turn-off loss. The first split gate and the second split gate also further reduce the parasitic capacitance of the device. Therefore, the structure can improve the trade-off relationship between the forward conduction voltage drop and the turn-off loss of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] In order to more clearly illustrate the specific implementation methods of the present application or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0010] Figure 1 A cross-sectional schematic diagram of an IGBT device provided in an embodiment of the present application;

[0011] Figure 2 A cross-sectional schematic diagram of another IGBT device provided in an embodiment of the present application;

[0012] Figure 3 A flow chart of a method for preparing an IGBT device provided in an embodiment of the present application;

[0013] Figures 4A-4H A schematic cross-sectional view of a method for preparing an IGBT device provided in an embodiment of the present application;

[0014] Figure 5 A flow chart of another method for preparing an IGBT device provided in an embodiment of the present application.

[0015] As shown in the accompanying drawings, the same reference numerals refer to the same parts in all the different views. The accompanying drawings provided herein are for the purpose of illustrating embodiments, principles, concepts, etc., and are not drawn to scale.

[0016] In the above drawings, the meanings of the reference numerals are as follows: 1 is the emitter metal; 2 is the gate dielectric layer; 3 is the gate region; 4 is the interlayer dielectric layer; 4-1 is the interlayer dielectric layer between the sidewall grown on the lower sidewall of the first trench and the first split gate; 4-2 is the interlayer dielectric layer grown between the gate region and the first split gate, and between the sidewall grown on the sidewall of the second trench and the second split gate; 4-3 is the interlayer dielectric layer covering the top of the gate region; 5 is the first split gate; 6 is the body region; 7 is the emitter region; 8 is the body contact region; 9 is the second split gate; 10 is the carrier storage layer; 11 is the column region; 12 is the field stop layer; 13 is the collector region; 14 is the collector metal; 15 is the epitaxial layer; 16 is the first trench; and 17 is the second trench. DETAILED DESCRIPTION

[0017] The technical solution of the present application will be described clearly and completely below in conjunction with the embodiments. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present application.

[0018] Since a relatively good transistor structure has not yet been proposed, which can handle the compromise relationship between the forward conduction voltage drop and the switching loss. The embodiment of the present application provides an IGBT device and a preparation method thereof, which improves the compromise relationship between the forward conduction voltage drop and the turn-off loss of the device. To facilitate understanding of the present embodiment, an IGBT device disclosed in the embodiment of the present application is first introduced in detail.

[0019] It should be noted that the letter "N" as used herein refers to an N-type dopant, and the letter "P" refers to a P-type dopant. The plus sign "+" or the minus sign "-" is used to indicate a relatively high dopant concentration and a relatively low dopant concentration, respectively. The term "channel" is used herein in a generally recognized manner. That is, the movement of current within the FET is from the source connection to the drain connection in the channel. The channel can be made of an N-type semiconductor material or a P-type semiconductor material. Therefore, the FET is designated as an N-channel device or a P-channel device. The following embodiments are described using an N-channel device as an example, but the embodiments of the present invention are not limited thereto. That is, the various features described herein can be used for P-channel devices. The content disclosed in the present invention can form a corresponding P-channel device by replacing N-type dopants and materials with corresponding P-type dopants and materials, and vice versa.

[0020] Figure 1 A cross-sectional view of an IGBT device provided in an embodiment of the present invention includes a semiconductor substrate of a first conductivity type (e.g., N-type). A plurality of column regions 11 of a second conductivity type (e.g., P-type) are arranged in the semiconductor substrate in a transversely spaced manner. A plurality of P-type column regions 11 are interlaced with the N-type semiconductor substrate to form a super junction region. In other embodiments, N-type ion implantation can be continued in the N-type semiconductor substrate to form a super junction region interlaced with the P-type column region 11 having a higher concentration. Since the P-type column region 11 is provided, a transverse electric field is formed in the super junction region, and the longitudinal electric field is changed from a triangular distribution of the traditional structure to an approximately rectangular distribution. When achieving the same BV, the inventive structure has a thinner chip thickness, thereby reducing the forward conduction voltage drop. The thinner chip thickness in turn allows the IGBT to have a faster turn-off speed when turned off, thereby reducing the switching loss, and further improving the trade-off relationship between the forward conduction voltage drop and the turn-off loss.

[0021] Continue to see Figure 1 , forming an epitaxial layer on a semiconductor substrate. In one embodiment, the epitaxial layer may be a part of the semiconductor substrate; in another embodiment, a structure of the same first conductivity type may also be grown on top of the semiconductor substrate as the epitaxial layer. In one embodiment, the epitaxial layer and the semiconductor substrate have the same doping concentration; in another embodiment, the doping concentration of the epitaxial layer may be greater than the doping concentration of the semiconductor substrate.

[0022] A body region 6 of the second conductivity type (e.g., P type) is formed on the top of the epitaxial layer, and a carrier storage layer 10 of the first conductivity type (e.g., N type) is formed in the epitaxial layer below the body region 6. In one embodiment, the doping concentration of the carrier storage layer 10 is greater than the doping concentration of the semiconductor substrate. In one embodiment, the doping concentration of the carrier storage layer 10 is greater than the doping concentration of the first conductivity type column region.

[0023] Continue to see Figure 1 The IGBT device further includes a first trench and a second trench, which extend from the top surface of the body region 6 through the body region 6 and the carrier storage layer 10 to the top surface of the column region 11 of the second conductivity type in the semiconductor substrate. A gate region 3 is formed in the upper part of the first trench, and the gate region 3 is isolated from the body region 6 and the emitter region 7 by the gate dielectric layer 2; a first split gate 5 is formed in the lower part of the first trench, and the first split gate 5 is isolated from the gate region 3, the carrier storage layer 10 and the column region 11 of the second conductivity type by the interlayer dielectric layer 4. A second split gate 9 is formed in the second trench, and the second split gate 9 is isolated from the body region 6, the carrier storage layer 10 and the column region 11 of the second conductivity type by the interlayer dielectric layer 4. In one embodiment, the depths of the first trench and the second trench are the same, so that the depletion area in the carrier storage layer 10 can be increased as much as possible to increase the breakdown voltage BV, while reducing the forward conduction voltage drop and conduction loss.

[0024] In one embodiment, the thickness of the gate dielectric layer 2 is less than the thickness of the interlayer dielectric layer 4. Figure 2 As shown, the interlayer dielectric layer 4 specifically includes: an interlayer dielectric layer 4-1 between the sidewall grown on the lower sidewall of the first trench and the first split gate 5, an interlayer dielectric layer grown between the gate region 3 and the first split gate 5, an interlayer dielectric layer 4-2 between the sidewall grown on the sidewall of the second trench and the second split gate 9, and an interlayer dielectric layer 4-3 covering the top of the gate region 3.

[0025] In one embodiment, the thickness of each interlayer dielectric layer may be different. In one embodiment, the thickness of the interlayer dielectric layer 4-1 between the sidewall of the lower sidewall of the first trench and the first split gate 5 is not consistent from top to bottom, but gradually thins from top to bottom, showing a characteristic of being thick at the top and thin at the bottom. Preferably, as Figure 2 As shown, the thickness of the interlayer dielectric layer 4-1 on the lower sidewall of the first trench has a step-like thinning characteristic from top to bottom. In the area where the interlayer dielectric layer 4-1 is thinner, the concentration of the N-type carrier storage layer 10 can be made higher to reduce the forward conduction voltage drop. In the area where the interlayer dielectric layer 4-1 is thicker, the concentration of the N-type carrier storage layer 10 can be made lower to prevent the PN junction between the N-type carrier storage layer 10 and the body region 6 from breaking down prematurely. Similarly, in one embodiment, the thickness of the interlayer dielectric layer 4-2 grown on the sidewall of the second trench is not consistent from top to bottom, but gradually thins from top to bottom, showing a thick top and thin bottom characteristic. Preferably, as Figure 2 As shown, the thickness of the interlayer dielectric layer 4-2 decreases in a step-like manner from top to bottom. In the thinner region of the interlayer dielectric layer 4-2, the concentration of the N-type carrier storage layer 10 can be increased to reduce the forward conduction voltage drop.

[0026] In one embodiment, the gate dielectric layer 2 and the interlayer dielectric layer 4 may be thermal oxidation products formed by thermal growth or oxides deposited by chemical vapor deposition (CVD).

[0027] In one embodiment, the first split gate 5 and the second split gate 9 both include doped polysilicon.

[0028] In one embodiment, the first split gate 5 and the second split gate 9 can be independently led out of the electrode to receive a potential different from that of the emitter region 7. In one embodiment, the first split gate 5 and the second split gate 9 are connected to a negative voltage. At this time, minority carrier channels will be established in the carrier storage layer 10 close to the first split gate 5 and the second split gate 9, respectively, and the hole carriers in the N-type conductive column of the super junction region can quickly flow to the emitter region 7 through this channel, thereby reducing the turn-off time and turn-off loss of the IGBT device.

[0029] In one embodiment, one of the first split gate 5 and the second split gate 9 can also receive a negative voltage, and the other can receive the same potential as the emitter region 7 (e.g., ground potential), that is, a minority carrier channel is established only in the carrier storage layer 10 close to the split gate connected to the negative voltage for hole carriers to pass through. In one embodiment, the first split gate 5 and the second split gate 9 can receive negative voltages of different values, or can receive the same negative voltage, which is related to the thickness of the interlayer dielectric layer between the split gate and the carrier storage layer 10.

[0030] In the above structure, the first split gate 5, the interlayer dielectric layer 4, the carrier storage layer 10 and the second split gate 9 at the upper part of the device form a capacitive depletion region, and the multiple column regions and the semiconductor substrate in the lower part of the device are staggered to form a super junction region, thereby increasing the breakdown voltage BV of the device. The IGBT structure can realize the change of the longitudinal electric field from the triangular distribution of the traditional structure to an approximately rectangular distribution, and at the same breakdown voltage, it will have a thinner chip thickness, thereby reducing the forward conduction voltage drop. The thinner chip thickness will in turn make the IGBT have a faster turn-off speed when it is turned off, thereby reducing the switching loss. When the IGBT device is forward-conducting, the auxiliary depletion effect of the first split gate 5 and the second split gate 9 can ensure that the doping concentration of the carrier storage layer 10 is greatly increased without attenuating the breakdown voltage. At this time, the hole barrier height in the carrier storage layer 10 and the N-type conductive column of the super junction region is further increased, thereby enhancing the conductivity modulation effect when the device is forward-conducting, and reducing the forward conduction voltage drop and conduction loss of the device. When the IGBT device is turned off, due to the presence of hole carriers in its epitaxial layer, it is turned off slowly and has a large turn-off loss. After the first split gate and the second split gate receive a negative voltage, a minority current channel can be established, which increases the turn-off speed of the IGBT device and reduces the turn-off loss. Therefore, the IGBT structure improves the trade-off relationship between the forward conduction voltage drop and the switching loss of the device.

[0031] The above-mentioned IGBT device further includes a collector region 13 of the second conductivity type (such as P type), the collector region 13 is located at the bottom of the semiconductor substrate, and the bottom of the collector region 13 is in contact with the collector metal 14. A field stop layer 12 of the first conductivity type is also formed between the collector region 13 and the super junction region. In one embodiment, the doping concentration of the field stop layer 12 is greater than the doping concentration of the semiconductor substrate.

[0032] The above IGBT device further includes an emitter region 7 of the first conductivity type, the emitter region 7 is formed on the top of the body region 6 and is adjacent to the first trench, and the top surface of the emitter region 7 covers and contacts the emitter metal 1. Furthermore, a body contact region 8 is formed in the body region 6 of the IGBT device, and the body contact region 8 is also in contact with the emitter metal 1.

[0033] Based on the above device embodiment, the present application embodiment also provides a method for preparing an IGBT device, see Figure 3 As shown, the method specifically includes steps S1-S8.

[0034] Step S1: forming a column region of a second conductivity type on a semiconductor substrate of a first conductivity type.

[0035] See also Figure 4A As shown, a column region 11 of a second conductivity type (P type) is formed on a semiconductor substrate of a first conductivity type (N type). In one embodiment, a trench can be dug from top to bottom on the semiconductor substrate of the first conductivity type (N type), and the P type column region 11 can be grown in the trench. In another embodiment, the P type column region 11 can be formed on the semiconductor substrate by high energy and high dose P type ion implantation.

[0036] Step S2: growing an epitaxial layer on the top surface of the semiconductor substrate and the pillar region.

[0037] See also Figure 4B As shown, an epitaxial layer 15 is grown on the top surface of the column region 11 , and the epitaxial layer 15 has a first conductivity type.

[0038] Step S3: trenching the epitaxial layer from top to bottom to form a first trench and a second trench. In one embodiment, the openings of the first trench and the second trench can be set by forming a trench mask pattern.

[0039] See also Figure 4C As shown, a first trench 16 and a second trench 17 are formed in the epitaxial layer.

[0040] Step S4: After forming a dielectric layer at the bottom and sidewalls of the first trench and the second trench, polysilicon is filled to form a second split gate in the second trench.

[0041] See also Figure 4D As shown, after depositing the interlayer dielectric layer 4 in the first trench 16 and the second trench 17, polysilicon is filled. After the second trench 17 is filled with polysilicon, a planarization process is performed on its top surface (for example, using a chemical mechanical polishing (CMP) process, etc.) to form a second split gate 9. In one embodiment, a dielectric layer can be formed by deposition or thermal growth at the bottom and sidewalls of the first trench 16 and the second trench 17. The dielectric layer laterally limits the size of the polysilicon region subsequently formed in the first trench 16 and the second trench 17, and prevents doping ions from laterally diffusing from the trenches.

[0042] Step S5: etching the polysilicon in the first trench to form a first split gate 5 .

[0043] See also Figure 4E As shown in FIG. 1 , the polysilicon in the first trench 16 is etched to form the first split gate 5 .

[0044] Step S6: depositing a dielectric layer in the first trench for the second time and then filling the trench with polysilicon to form a gate region.

[0045] See also Figure 4F As shown, after the dielectric layer is deposited for the second time in the first trench 16, polysilicon is filled and the top surface is planarized to form a gate region 3. Between each gate region and the epitaxial layer is a gate dielectric layer 2, and the thickness of the gate dielectric layer 2 is less than the thickness of the interlayer dielectric layer 4.

[0046] Step S7: performing ion implantation on the top of the epitaxial layer to form a carrier storage layer, a body region and an emission region respectively.

[0047] See also Figure 4G As shown, ion implantation is performed on the top of the epitaxial layer to form a carrier storage layer 10, a body region 6 and an emitter region 7 respectively. Further, a body contact region 8 is formed in the body region 6 near the emitter region 7. Ion implantation can also be performed by a photoresist mask process. In one embodiment, step S7 further includes depositing an interlayer dielectric layer 4 and an emitter metal 1 on the top of the epitaxial layer.

[0048] Step S8: performing ion implantation at the bottom of the semiconductor substrate to form a field stop layer of the first conductivity type and a collector region of the second conductivity type, wherein the doping concentration of the field stop layer is higher than the doping concentration of the semiconductor substrate.

[0049] See also Figure 4H As shown, Figure 4G The semiconductor device formed in the process is flipped over, and ions of the first conductivity type (N type) and the second conductivity type (P type) are implanted respectively to form a field stop layer 12 of the first conductivity type (N type) and a collector region 13 of the second conductivity type (P type). In one embodiment, step S8 further includes thinning the semiconductor substrate before performing ion implantation.

[0050] Finally, the collector metal 14 is deposited at the bottom of the collector region 13 to form a Figure 1 The IGBT device structure shown.

[0051] Based on the above device embodiment, the present application embodiment also provides another method for preparing an IGBT device, see Figure 5 As shown, the method includes S51-S59.

[0052] Step S51: growing a first epitaxial layer of a first conductivity type on a substrate of a first conductivity type;

[0053] In one embodiment, the first conductivity type is N type.

[0054] Step S52: forming a column region of the second conductivity type on the first epitaxial layer.

[0055] In one embodiment, a trench can be dug from top to bottom in a semiconductor substrate of the first conductivity type (N type), and a P type column region can be grown in the trench. In another embodiment, the P type column region can be formed on the semiconductor substrate by high energy and high dose P type ion implantation.

[0056] Step S53: growing a second epitaxial layer on the top surfaces of the first epitaxial layer and the pillar region.

[0057] Step S54: trenching the second epitaxial layer from top to bottom to form a first trench and a second trench.

[0058] In one embodiment, the openings of the first trench and the second trench may be set by forming a trench mask pattern.

[0059] Step S55: After forming a dielectric layer at the bottom and sidewalls of the first trench and the second trench, polysilicon is filled to form a second split gate in the second trench.

[0060] In one embodiment, a dielectric layer may be formed by deposition or thermal growth at the bottom and sidewalls of the first trench and the second trench. The dielectric layer laterally limits the size of the polysilicon region subsequently formed in the first trench and the second trench, and prevents doping ions from laterally diffusing from the trench. After the second trench is filled with polysilicon, a planarization process (e.g., using a chemical mechanical polishing (CMP) process, etc.) is performed on its top surface to form a second split gate.

[0061] Step S56: etching the polysilicon in the first trench to form a first split gate.

[0062] Step S57: forming a dielectric layer in the first trench for the second time and then filling the trench with polysilicon to form a gate region;

[0063] After the dielectric layer is deposited in the first trench for the second time, polysilicon is filled to form two gate regions. A gate dielectric layer is formed between each gate region and the epitaxial layer. The thickness of the gate dielectric layer is less than that of the interlayer dielectric layer.

[0064] Step S58: performing ion implantation on the top of the second epitaxial layer to form a carrier storage layer, a body region and an emitter region respectively.

[0065] Ion implantation is performed on the top of the epitaxial layer to form a carrier storage layer, a body region and an emitter region, wherein the body region and the emitter region are next to the body contact region. Ion implantation can also be performed through a photoresist mask process. In one embodiment, step S58 also includes depositing an interlayer dielectric layer and an emitter metal on the top of the epitaxial layer.

[0066] Step S59: removing the substrate and performing ion implantation at the bottom of the first epitaxial layer to form a field stop layer of the first conductivity type and a collector region of the second conductivity type, wherein the doping concentration of the field stop layer is higher than the doping concentration of the first epitaxial layer.

[0067] In one embodiment, step S59 further includes thinning the first epitaxial layer and then performing ion implantation to form a field stop layer of the first conductivity type and a collector region of the second conductivity type. Finally, a collector metal is deposited at the bottom of the collector region to form a Figure 1 The IGBT device structure shown.

[0068] The method provided in the embodiment of the present application has the same implementation principle and technical effects as those in the aforementioned device embodiment. For the sake of brief description, for matters not mentioned in the embodiment of the method, reference may be made to the corresponding contents in the aforementioned device embodiment.

[0069] In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present application. In addition, the terms "first", "second", and "third" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance.

[0070] Finally, it should be noted that the above-described embodiments are only specific implementation methods of the present application, which are used to illustrate the technical solutions of the present application, rather than to limit them. The protection scope of the present application is not limited thereto. Although the present application is described in detail with reference to the above-described embodiments, ordinary technicians in the field should understand that any technician familiar with the technical field can still modify the technical solutions recorded in the above-described embodiments within the technical scope disclosed in the present application, or can easily think of changes, or make equivalent replacements for some of the technical features therein; and these modifications, changes or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application, and should be included in the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. An IGBT device, characterized in that: The IGBT device comprises: A semiconductor substrate having a first conductivity type; A plurality of column regions of the second conductivity type, wherein the plurality of column regions of the second conductivity type are disposed in a laterally spaced manner in the semiconductor substrate; an epitaxial layer formed on the semiconductor substrate; The body region, formed on top of the epitaxial layer; a carrier storage layer having a first conductivity type and formed in the epitaxial layer below the body region; A first trench and a second trench, the first trench and the second trench extending from a top surface of the body region through the body region and the carrier storage layer to a top surface of the pillar region; A gate region is formed in the first trench and is located at an upper portion of the trench, wherein the gate region is isolated from the body region and the emitter region by a gate dielectric layer; A first split gate is formed in the first trench and is located at the lower part of the trench, and the interlayer dielectric layer isolates the first split gate from the gate region, the carrier storage layer and the pillar region respectively; The second split gate is formed in the second trench, and the interlayer dielectric layer isolates the second split gate from the body region, the carrier storage layer and the column region respectively.

2. The IGBT device according to claim 1, characterized in that: The first groove and the second groove have the same depth.

3. The IGBT device according to claim 1, characterized in that: Further including: A collector region of a second conductivity type, the collector region being located at the bottom of the semiconductor substrate; A field stop layer of a first conductivity type is formed between the collector region and the stud region.

4. The IGBT device according to claim 1, characterized in that: The first split gate and the second split gate lead out electrodes respectively, and one or both of them are externally connected to a negative voltage.

5. The IGBT device according to claim 1, characterized in that: The thickness of the gate dielectric layer is smaller than the thickness of the interlayer dielectric layer.

6. The IGBT device according to claim 1, characterized in that: The thickness of the interlayer dielectric layer between the first split gate and the first trench sidewall gradually decreases from top to bottom.

7. The IGBT device according to claim 1, characterized in that: The thickness of the interlayer dielectric layer between the second split gate and the second trench sidewall gradually decreases from top to bottom.

8. The IGBT device according to claim 7, characterized in that: The thickness of the interlayer dielectric layer between the second split gate and the second trench sidewall is a step-like thinning characteristic from top to bottom.

9. A method for preparing an IGBT device, characterized in that: The method comprises: Step 1: forming a column region having a second conductivity type on a semiconductor substrate having a first conductivity type; Step 2: growing an epitaxial layer on the top surface of the semiconductor substrate and the pillar region; Step 3: Digging trenches on the epitaxial layer from top to bottom to form a first trench and a second trench; Step 4: After forming a dielectric layer at the bottom and sidewalls of the first trench and the second trench, polysilicon is filled to form a second split gate in the second trench; Step 5: etching the polysilicon in the first trench to form a first split gate; Step 6: forming a dielectric layer in the first trench for the second time and then filling the trench with polysilicon to form a gate region; Step 7: Perform ion implantation on the top of the epitaxial layer to form a carrier storage layer, a body region and an emitter region respectively; Step eight: perform ion implantation at the bottom of the semiconductor substrate to form a field stop layer of the first conductivity type and a collector region of the second conductivity type.

10. A method for preparing an IGBT device, characterized in that: The method comprises: Step 1: growing a first epitaxial layer of a first conductivity type on a substrate of a first conductivity type; Step 2: forming a column region of a second conductivity type on the first epitaxial layer; Step 3: growing a second epitaxial layer on the top surface of the first epitaxial layer and the pillar region; Step 4: digging a trench from top to bottom on the second epitaxial layer to form a first trench and a second trench; Step 5: After forming a dielectric layer at the bottom and sidewalls of the first trench and the second trench, polysilicon is filled to form a second split gate in the second trench; Step 6: Etching the polysilicon in the first trench to form a first split gate; Step 7: forming a dielectric layer in the first trench for the second time and then filling the trench with polysilicon to form a gate region; Step 8: Perform ion implantation on the top of the second epitaxial layer to form a carrier storage layer, a body region and an emitter region respectively; Step nine: removing the substrate and performing ion implantation at the bottom of the first epitaxial layer to form a field stop layer of the first conductivity type and a collector region of the second conductivity type.

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