Enhanced gallium nitride p-type field effect transistor and preparation method thereof

Abstract

The invention relates to an enhanced gallium nitride p-type field effect transistor and a preparation method thereof, and belongs to the technical field of semiconductor devices. The preparation method comprises the following steps: providing an epitaxial wafer structure of which the outermost layer is a p-type gallium nitride layer, wherein the p-type gallium nitride layer contains two-dimensional hole gas; forming a source electrode and a drain electrode on the surface of the p-type gallium nitride layer at intervals; forming a gate dielectric structure on the surface of the p-type gallium nitride layer, wherein the gate dielectric structure comprises a hole tunneling layer, a hole trapping layer and a barrier layer which are stacked in sequence; and forming a gate on the surface of the gate dielectric structure. By forming the gate dielectric structure with the hole tunneling layer, the hole trapping layer and the barrier layer on the surface of the p-type gallium nitride layer, device enhancement can be realized after negative pressure is applied to the gate and initialization is completed, and an etching process does not need to be introduced, so that the leakage current of the device can be reduced, and the reliability is improved. Moreover, the threshold voltage of the device can be accurately regulated and controlled, the circuit design difficulty is reduced, and the applicable scenarios of the gallium nitride p-type field effect transistor are increased.

Description

Technical Field

[0001] The present application relates to the technical field of semiconductor devices, and in particular to an enhanced gallium nitride p-type field effect transistor and a preparation method thereof. Background Art

[0002] The direct-coupled field effect transistor logic circuit is composed of two devices, depletion-type and enhancement-type gallium nitride high-speed electron mobility transistors, in which the pull-up network is composed of a depletion-type high-speed electron mobility transistor. When the gate voltage of the device is 0V, the source and drain are in the on state. Therefore, when the pull-down network is turned on, the entire circuit will consume a large amount of static power. Compared with the direct-coupled field effect transistor logic circuit, the complementary logic circuit composed of an enhancement-type gallium nitride p-type field effect transistor and an enhancement-type gallium nitride n-type field effect transistor does not need to consume a lot of power. Therefore, in order to reduce power loss, it is very necessary to prepare an enhancement-type gallium nitride p-type field effect transistor with reasonable current density and good suppression of off-state leakage.

[0003] At present, there are three main technologies for enhancing enhancement-mode GaN p-type field effect transistors: (1) recessed gate technology, that is, etching the p-type GaN layer under the gate to form a recess, and then depositing the gate dielectric layer and gate metal in the recess; (2) n-type GaN or AlGaN gate cap layer, that is, depositing an n-type GaN or AlGaN layer under the gate, and then etching away the excess material between the gate and the source, and between the gate and the drain; (3) recessed gate combined with plasma treatment technology, that is, using hydrogen or oxygen plasma to treat the p-type GaN under the recessed gate on the basis of the recessed gate structure. However, the above three technologies all use etching processes, which inevitably cause material lattice damage, reduce hole mobility, and increase interface state density during the etching process, which will in turn lead to a series of performance deteriorations such as increased device leakage current and poor reliability. Therefore, the on-current of the enhancement-mode devices prepared by the above three technologies is smaller than that of the depletion-mode devices with the same structure. Summary of the invention

[0004] To solve the above problems, the purpose of the embodiments of the present application includes providing an enhanced gallium nitride p-type field effect transistor and a preparation method thereof, which can achieve device enhancement without etching and can accurately control the threshold voltage of the device.

[0005] In a first aspect, an embodiment of the present application provides a method for preparing an enhancement mode gallium nitride p-type field effect transistor, comprising the following steps:

[0006] An epitaxial wafer structure is provided, the outermost layer of which is a p-type gallium nitride layer, wherein the p-type gallium nitride layer has two-dimensional hole gas; a source electrode and a drain electrode are formed on the surface of the p-type gallium nitride layer; a gate dielectric structure is formed on the surface of the p-type gallium nitride layer where the source electrode and the drain electrode are not formed, wherein the gate dielectric structure comprises a hole tunneling layer, a hole trapping layer and a blocking layer stacked in sequence; and a gate electrode is formed on the surface of the gate dielectric structure.

[0007] In the above technical solution, a gate dielectric structure is formed on the surface of the p-type gallium nitride layer, and the gate dielectric structure includes a hole tunneling layer, a hole trapping layer and a barrier layer stacked in sequence, and a negative voltage is applied to the gate to complete initialization to achieve device enhancement. The preparation method is simple and reliable, and no etching is required in the preparation process, which will not cause material lattice damage and high interface state density, significantly reducing the leakage current of the device and improving the reliability of the device. In addition, since the thickness of the p-type gallium nitride layer is not reduced, that is, the two-dimensional hole gas density will not be reduced, the on-current of the device will not be reduced.

[0008] In the gate dielectric structure, the hole tunneling layer can assist the two-dimensional hole gas to tunnel to the hole capture layer when the initialization negative pressure is applied to the device, thereby improving the threshold voltage retention characteristics of the device; the hole capture layer can store the two-dimensional hole gas that tunnels during the initialization process and adjust the threshold voltage; the blocking layer can block the leakage of the two-dimensional hole gas, reduce device leakage, and improve the retention characteristics of the device threshold voltage. By changing the negative pressure applied to the gate during initialization, the level of the energy band potential under the gate can be changed, so the density of the two-dimensional hole gas under the gate can be changed, and the threshold voltage of the device can be accurately controlled, reducing the difficulty of circuit design and increasing the application scenarios of gallium nitride p-type field effect transistors.

[0009] In some embodiments of the present application, the hole tunneling layer, the hole trapping layer and the blocking layer are all made of high-k dielectric materials, and the dielectric constant and valence band of the hole trapping layer are higher than those of the hole tunneling layer.

[0010] In some embodiments of the present application, the material of the hole tunneling layer is aluminum oxide, the material of the hole trapping layer is hafnium dioxide and / or zirconium dioxide, and the material of the barrier layer is aluminum oxide.

[0011] In some embodiments of the present application, the gate dielectric structure is formed by atomic layer deposition.

[0012] In some embodiments of the present application, the method for forming a gate dielectric structure includes: using trimethylaluminum as an aluminum source and water as an oxygen source, performing atomic layer deposition on the surface of a p-type gallium nitride layer to form a hole tunneling layer; using tetrakis(dimethylamino)hafnium as a hafnium source and water as an oxygen source, performing atomic layer deposition on the surface of the hole tunneling layer to form a hole trapping layer; using trimethylaluminum as an aluminum source and water as an oxygen source, performing atomic layer deposition on the surface of the hole trapping layer to form a blocking layer.

[0013] In some embodiments of the present application, the thickness of the hole tunneling layer is 10 nm to 20 nm, the thickness of the hole trapping layer is 1 nm to 20 nm, and the thickness of the barrier layer is 10 nm to 20 nm.

[0014] In some embodiments of the present application, after forming a gate on the surface of the gate dielectric structure, the method further includes: forming a passivation layer on the surfaces of the source, the drain, the gate and the gate dielectric structure.

[0015] In some embodiments of the present application, the preparation method further includes: removing a portion of the passivation layer to form an opening to expose at least a portion of the source, the drain and the gate; and forming a metal cap layer in the opening.

[0016] In some embodiments of the present application, before forming the source and the drain, the method further includes: removing a portion of the buffer layer, the gallium nitride layer, the barrier layer and the p-type gallium nitride layer to form a mesa isolation.

[0017] In a second aspect, an embodiment of the present application provides an enhancement-mode gallium nitride p-type field effect transistor, comprising a source, a drain, a gate, a gate dielectric structure, and an epitaxial wafer structure whose outermost layer is a p-type gallium nitride layer, wherein the p-type gallium nitride layer has a two-dimensional hole gas; the source, the drain, and the gate dielectric structure are arranged on the surface of the p-type gallium nitride layer, the gate is arranged on the surface of the gate dielectric structure, and the gate dielectric structure comprises a hole tunneling layer, a hole trapping layer, and a blocking layer stacked in sequence.

[0018] In the above technical solution, by forming a gate dielectric structure on the surface of the p-type gallium nitride layer, and setting the gate dielectric structure including a hole tunneling layer, a hole capture layer and a barrier layer stacked in sequence, the device enhancement can be achieved after applying a negative voltage to the gate to complete the initialization. Among them, the hole tunneling layer can assist the two-dimensional hole gas to tunnel to the hole capture layer when the initialization negative voltage is applied to the device, thereby improving the threshold voltage retention characteristics of the device; the hole capture layer can store the two-dimensional hole gas tunneled during the initialization process to regulate the threshold voltage; the barrier layer can block the leakage of the two-dimensional hole gas, reduce the leakage of the device, and improve the retention characteristics of the threshold voltage of the device. By changing the magnitude of the negative pressure applied to the gate during initialization, the level of the energy band potential under the gate can be changed, so the density of the two-dimensional hole gas under the gate can be changed, and then the threshold voltage of the device can be accurately controlled, reducing the difficulty of circuit design and increasing the applicable scenarios of gallium nitride p-type field effect transistors.

[0019] In some embodiments of the present application, the material of the hole tunneling layer is aluminum oxide, the material of the hole trapping layer is hafnium dioxide and / or zirconium dioxide, and the material of the barrier layer is aluminum oxide.

[0020] In some embodiments of the present application, the thickness of the hole tunneling layer is 10 nm to 20 nm, the thickness of the hole trapping layer is 1 nm to 20 nm, and the thickness of the barrier layer is 10 nm to 20 nm. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0022] Figure 1 A process flow chart of a method for preparing an enhancement mode gallium nitride p-type field effect transistor provided in an embodiment of the present application.

[0023] Figure 2 A cross-sectional schematic diagram of an epitaxial wafer structure provided in an embodiment of the present application.

[0024] Figure 3 For Figure 2 The cross-sectional schematic diagram of the epitaxial wafer structure after mesa isolation is shown.

[0025] Figure 4 For Figure 3 Schematic cross-sectional view of the surface of the p-type gallium nitride layer after the source and drain are formed.

[0026] Figure 5 For Figure 4 The schematic cross-sectional view shows the source, drain and epitaxial wafer structure after a hole tunneling layer is formed on the surface.

[0027] Figure 6 For Figure 5 The cross-sectional schematic diagram shown is after a hole-trapping layer is formed on the surface of the hole tunneling layer.

[0028] Figure 7 For Figure 6 The cross-sectional schematic diagram is shown after a barrier layer is formed on the surface of the hole-trapping layer to obtain a gate dielectric structure.

[0029] Figure 8 For Figure 7 The cross-sectional schematic diagram of the gate dielectric structure surface after a gate is formed is shown.

[0030] Fig. 9 For Figure 8 The cross-sectional schematic diagram of the gate dielectric structure and the gate surface after the passivation layer is formed is shown.

[0031] Fig.10 For Fig. 9 The schematic cross-sectional view shows that openings are formed in the passivation layer to expose at least a portion of the source electrode, the drain electrode and the gate electrode.

[0032] Fig.11For Fig.10 A schematic cross-sectional view of the opening after a metal cap layer is formed in the opening is shown.

[0033] Fig.12 It is a schematic diagram of the principle of achieving enhancement of the enhancement-mode gallium nitride p-type field effect transistor in the embodiment of the present application.

[0034] Description of main component symbols:

[0035] 10-epitaxial wafer structure; 101-substrate; 102-buffer layer; 103-gallium nitride layer; 104-barrier layer; 105-p-type gallium nitride layer; 20-source; 30-drain; 40-gate dielectric structure; 401-hole tunneling layer; 402-hole trapping layer; 403-blocking layer; 50-gate; 60-passivation layer; 701-first opening; 702-second opening; 703-third opening; 71-first metal cap layer; 72-second metal cap layer; 73-third metal cap layer; R-groove. DETAILED DESCRIPTION

[0036] Below, the embodiments of the enhanced gallium nitride p-type field effect transistor and the method for preparing the same are specifically disclosed with appropriate reference to the accompanying drawings. However, there are cases where unnecessary detailed descriptions are omitted. For example, there are cases where detailed descriptions of well-known matters and repeated descriptions of actually the same structures are omitted. This is to avoid the following description from becoming unnecessarily lengthy and to facilitate the understanding of those skilled in the art. In addition, the drawings and the following description are provided for those skilled in the art to fully understand the present application and are not intended to limit the subject matter described in the claims.

[0037] Unless otherwise specified, all embodiments and optional embodiments of the present application can be combined with each other to form a new technical solution.

[0038] Unless otherwise specified, all technical features and optional technical features of this application can be combined with each other to form a new technical solution.

[0039] If there is no special explanation, all steps of the present application can be performed sequentially or randomly, preferably sequentially. For example, the method includes steps (a) and (b), which means that the method may include steps (a) and (b) performed sequentially, or may include steps (b) and (a) performed sequentially. For example, the method may further include step (c), which means that step (c) may be added to the method in any order. For example, the method may include steps (a), (b) and (c), or may include steps (a), (c) and (b), or may include steps (c), (a) and (b), etc.

[0040] As mentioned above, in order to prepare an enhanced-mode GaN p-type field effect transistor device with reasonable current density and good suppression of off-state leakage, and to realize GaN complementary logic electrodes to reduce power loss, the commonly used technologies currently include the following three: (1) Recessed gate technology, that is, etching the p-type GaN layer under the gate to form a groove, and then depositing the gate dielectric layer and gate metal in the groove. As the thickness of the p-type GaN layer decreases, the polarization strength between the p-type GaN / barrier layer heterojunction under the gate is weakened, and the valence band at this location moves downward relative to the Fermi level, so the two-dimensional hole gas density generated is reduced, achieving device enhancement. (2) n-type GaN or AlGaN gate cap layer, that is, depositing an n-type GaN or AlGaN layer under the gate, and then etching away the excess material between the gate and the source, and between the gate and the drain. Due to the significant difference between the electron concentration in the n-type GaN cap layer and the hole concentration in the p-type GaN channel layer, a depletion region will be formed in the p-type GaN channel layer, so that the valence band in the p-type GaN channel layer under the gate is lower than the Fermi level and the two-dimensional hole gas is depleted, achieving enhancement. Positive polarization charges can be generated between the AlGaN gate cap layer and the p-type GaN channel layer. The presence of positive polarization charges increases the downward bending of the energy band of the p-type GaN channel, resulting in the disappearance of the hole quantum well at the interface of the p-type GaN / barrier layer under the gate, depleting the two-dimensional hole gas, achieving enhancement. (3) Recessed gate combined with plasma treatment technology, that is, based on the recessed gate structure, hydrogen or oxygen plasma is used to treat the p-type GaN under the recessed gate, so that the magnesium in the p-type GaN is inactive and converted into high-resistance intrinsic GaN, the polarization strength between the p-type GaN / barrier layer is weakened, and the two-dimensional hole gas in the channel is depleted, achieving enhancement.

[0041] However, the above three technologies all use etching processes, which will inevitably cause material lattice damage, reduce hole mobility, and increase interface state density during the etching process, which will in turn lead to a series of performance deteriorations such as increased device leakage current and poor reliability. In addition, etching of p-type gallium nitride in the recessed gate process will sacrifice some two-dimensional hole gas, which will reduce the on-current of the device. Therefore, the on-current of the enhancement-mode devices prepared by the above three technologies is smaller than that of the depletion-mode devices with the same structure.

[0042] Based on this, the embodiment of the present application provides a method for preparing an enhanced gallium nitride p-type field effect transistor. By designing the gate dielectric structure as a hole tunneling layer, a hole trapping layer and a barrier layer stacked in sequence, there is no need to design a gate groove and an etching process, and an enhanced gallium nitride p-type field effect transistor device is realized without sacrificing the two-dimensional hole gas density. At the same time, it is possible to regulate the threshold voltage of the device, reduce the difficulty of circuit design, and increase the applicable scenarios of gallium nitride p-type field effect transistors. The preparation method is simple and reliable, and no etching is required in the preparation process. It will not cause material lattice damage and high interface state density, significantly reduce the leakage current of the device, and improve the reliability of the device. In addition, since the thickness of the p-type gallium nitride layer is not reduced, the two-dimensional hole gas density will not be reduced, and therefore, the on-current of the device will not be reduced.

[0043] Among them, the hole tunneling layer can assist the two-dimensional hole gas to tunnel to the hole capture layer when the initialization negative pressure is applied to the device, thereby improving the threshold voltage retention characteristics of the device; the hole capture layer can store the two-dimensional hole gas that tunnels during the initialization process and adjust the threshold voltage; the barrier layer can block the leakage of the two-dimensional hole gas, reduce device leakage, and improve the threshold voltage retention characteristics of the device. By changing the negative pressure applied to the gate during initialization, the level of the energy band potential under the gate can be changed, that is, the potential well depth between the p-type gallium nitride / barrier layer can be adjusted, so the density of the two-dimensional hole gas under the gate can be changed, and then the threshold voltage of the device can be accurately controlled, reducing the difficulty of circuit design and increasing the application scenarios of gallium nitride p-type field effect transistors.

[0044] The specific structure and preparation method of the enhancement mode gallium nitride p-type field effect transistor provided by the embodiment of the present application are described in detail below with reference to the accompanying drawings.

[0045] Figure 1 A process flow chart of a method for preparing an enhanced gallium nitride p-type field effect transistor provided in an embodiment of the present application, Figures 2 to 11 This is a schematic diagram of the process of preparing an enhancement mode gallium nitride p-type field effect transistor, see Figures 1 to 11 The method for preparing an enhancement-mode gallium nitride p-type field effect transistor provided in the embodiment of the present application comprises the following steps:

[0046] S10, see Figure 1 , an epitaxial wafer structure 10 is provided, wherein the outermost layer of the epitaxial wafer structure 10 is a p-type gallium nitride layer 105 , and the p-type gallium nitride layer 105 has two-dimensional vacancies.

[0047] In some embodiments, the epitaxial wafer structure 10 includes a substrate 101 , a buffer layer 102 , a gallium nitride layer 103 , a barrier layer 104 , and a p-type gallium nitride layer 105 which are stacked in sequence.

[0048] Among them, the gallium nitride layer 103, the barrier layer 104 and the p-type gallium nitride layer 105 form a double heterojunction design structure, and there is a two-dimensional electron gas (2DEG) at the connection interface of the gallium nitride layer 103 close to the barrier layer 104, and there is a two-dimensional hole gas (2DHG) at the connection interface of the p-type gallium nitride layer 105 close to the barrier layer 104.

[0049] The substrate 101 is a commonly used substrate material for gallium nitride-based devices, and can be a silicon substrate, a sapphire substrate, a diamond substrate, a gallium nitride substrate, a silicon carbide substrate, or a silicon-on-insulator substrate. In the embodiment of the present application, the substrate 101 is a silicon substrate. The thickness of the substrate 101 can be 500 μm to 5000 μm, for example, 500 μm, 1000 μm, 2000 μm, 5000 μm, etc.

[0050] The buffer layer 102 is used to mitigate the phenomenon of lattice mismatch when the gallium nitride material grows on the substrate 101. The buffer layer 102 can be an aluminum nitride layer, an aluminum gallium nitride layer with a gradient aluminum component, a gallium nitride layer doped with carbon or iron, etc. The thickness of the buffer layer 102 can be 1 μm to 20 μm, for example, 1 μm, 5 μm, 10 μm, 20 μm, etc.

[0051] The barrier layer 104 is made of aluminum gallium nitride. The gallium nitride layer 103, the barrier layer 104 (aluminum gallium nitride) and the p-type gallium nitride layer 105 in the epitaxial wafer structure 10 form a double heterostructure. In some embodiments, an aluminum nitride layer may be provided between the barrier layer 104 and the p-type gallium nitride layer 105, and / or between the barrier layer 104 and the gallium nitride layer 103.

[0052] In some embodiments, step S10 further includes: performing surface cleaning on the epitaxial wafer structure 10 to clean surface contamination, oxides, organic matter, etc. For example, an acidic solution (such as diluted hydrofluoric acid, nitric acid, citric acid, etc.) can be used to remove surface oxides, and an organic solvent (such as acetone, isopropanol, etc.) can be used to remove surface organic matter.

[0053] See also Figure 3 , after cleaning the epitaxial wafer structure 10, it also includes mesa isolation of the epitaxial layer of the epitaxial wafer structure 10. Mesa isolation refers to isolating an area for forming transistor devices on the surface of the epitaxial layer of the epitaxial wafer structure 10 to separate different transistor devices on the epitaxial wafer structure 10. It can be understood that mesa isolation is used to remove the barrier layer 104 that connects each independent device so that the devices do not interfere with each other. Exemplarily, mesa isolation can be formed by removing part of the p-type gallium nitride layer 105, the barrier layer 104, the gallium nitride layer 103 and part of the buffer layer 102. Among them, the mesa isolation can be dry-etched to the buffer layer 102 using inductively coupled plasma, and the ion source used in the etching process can be boron chloride and chlorine.

[0054] S20, see Figure 4 A source electrode 20 and a drain electrode 30 are formed on the surface of the p-type gallium nitride layer 105 .

[0055] In some embodiments, patterned photolithography, sputtering and annealing can be used in combination with a metal lift-off process to obtain the source 20 and the drain 30. The source 20 and the drain 30 can be made of at least one of metals such as titanium, aluminum, nickel, and gold, or alloys of these metals. The source 20 and the drain 30 can each independently be a single-layer structure or a multi-layer structure, such as nickel / gold, titanium / aluminum / titanium, etc.

[0056] As an example, after depositing nickel (20nm) / gold (30nm) stacked metal by ultra-high vacuum magnetron sputtering coating machine, annealing treatment is performed at 550°C for 5 minutes in oxygen atmosphere, and the source 20 and the drain 30 are formed by using LOR double-layer glue metal stripping process.

[0057] S30, see Figure 5 , Figure 6 and Figure 7 A gate dielectric structure 40 is formed on the surface of the p-type gallium nitride layer 105 where the source 20 and the drain 30 are not formed. The gate dielectric structure 40 includes a hole tunneling layer 401, a hole trapping layer 402 and a blocking layer 403 stacked in sequence.

[0058] Among them, the hole tunneling layer 401 can assist the two-dimensional hole gas to tunnel to the hole capture layer 402, the hole capture layer 402 can store the two-dimensional hole gas tunneled from the hole tunneling layer 401, and the blocking layer 403 can block the leakage of carriers (two-dimensional hole gas). The materials of the hole tunneling layer 401, the hole capture layer 402 and the blocking layer 403 are all high-k dielectric materials, and the dielectric constant and valence band of the material of the hole capture layer 402 are higher than those of the hole tunneling layer 401, which can effectively promote the tunneling of holes and improve the hole storage performance. The potential well formed by the large valence band difference is conducive to storing holes in the hole capture layer 402, which is not easy to leak.

[0059] In the present application, high-k dielectric material refers to a dielectric material having a dielectric constant greater than that of silicon dioxide (3.9).

[0060] The hole tunneling layer 401 may be made of aluminum oxide. The hole tunneling layer 401 may be a single layer or a multi-layer structure, and the thickness may be 10 nm to 20 nm, such as 10 nm, 12 nm, 15 nm, 20 nm, etc. Preferably, the thickness of the hole tunneling layer 401 is 10 nm.

[0061] The material of the hole capture layer 402 is a material with hole capture capability and preferably a material with a large valence band difference with the hole tunneling layer 401, which can effectively promote the tunneling of holes. In some embodiments, the material of the hole capture layer 402 can be hafnium dioxide and / or zirconium dioxide, and can also be hafnium-based and zirconium-based nitrides, nitride oxides, etc., such as hafnium nitride, hafnium oxynitride, zirconium nitride, zirconium oxynitride, etc. The hole capture layer 402 can be a single-layer or multi-layer structure, and the thickness can be 1nm to 20nm, for example, 1nm, 5nm, 10nm, 20nm, etc. Preferably, the thickness of the hole capture layer 402 is 10nm.

[0062] The material of the barrier layer 403 may be aluminum oxide. The thickness of the barrier layer 403 may be 10 nm to 20 nm, for example, 10 nm, 12 nm, 15 nm, 20 nm, etc. Preferably, the thickness of the barrier layer 403 is 10 nm.

[0063] In some embodiments, the gate dielectric structure 40 may be formed by atomic layer deposition, the temperature of the atomic layer deposition may be 300° C., and the growth rate may be 0.1 nm / cycle.

[0064] As an example, step S30 may include: see Figure 5 , using trimethylaluminum as an aluminum source and water as an oxygen source, atomic layer deposition is performed on the surface of the p-type gallium nitride layer 105 to form a hole tunneling layer 401; see Figure 6 , using tetrakis(dimethylamino)hafnium as a hafnium source and water as an oxygen source, atomic layer deposition is performed on the surface of the hole tunneling layer 401 to form a hole trapping layer 402; see Figure 7 Atomic layer deposition is performed on the surface of the hole trapping layer 402 using trimethylaluminum as an aluminum source and water as an oxygen source to form a blocking layer 403 .

[0065] It can be understood that due to the limitation of the atomic layer deposition process, the gate dielectric structure 40 not only covers the surface of the p-type gallium nitride layer 105 , but also covers the surface of the source 20 , the drain 30 and the epitaxial wafer structure 10 .

[0066] S40, see Figure 8 , a gate 50 is formed on the surface of the gate dielectric structure 40 .

[0067] The gate 50 is disposed between the source 20 and the drain 30 . The source 20 , the drain 30 and the gate dielectric structure 40 are arranged to form a groove R. The gate 50 is formed in the groove R.

[0068] In some embodiments, the electrode pattern can be defined by patterned photolithography, metal sputtering, annealing, and combined with a metal lift-off process to form the gate 50. The material of the gate 50 can be at least one of magnesium, titanium, aluminum, nickel, gold, platinum, palladium, etc. or an alloy of these metals, and the gate 50 can be a single layer or a multi-layer structure stack. As an example, an ultra-high vacuum magnetron sputtering coating machine can be used to deposit a nickel (20nm) / gold (30nm) metal stack sputtered on the surface of the gate dielectric structure 40 to form the gate 50.

[0069] In some embodiments, after step S40, the method further includes: forming a passivation layer 60 on the surfaces of the source 20, the drain 30, the gate 50 and the gate dielectric structure 40. Fig. 9 Since the gate dielectric structure 40 covers the surface of the p-type gallium nitride layer 105 , the source 20 , the drain 30 and the epitaxial wafer structure 10 , the passivation layer 60 can directly cover the surface of the gate dielectric structure 40 .

[0070] In some embodiments, the passivation layer 60 may be formed by plasma enhanced chemical vapor deposition. The material of the passivation layer 60 may be silicon nitride (eg SiN x As an example, in an atmosphere of 350° C., with silane, ammonia and nitrogen as source materials, plasma enhanced chemical vapor deposition is adopted, the deposition rate is 0.5 nm / s, the deposition time is 40 s, and a silicon nitride passivation layer 60 with a thickness of 20 nm is obtained.

[0071] In some embodiments, after forming the passivation layer 60 , the method further includes: removing a portion of the passivation layer 60 to form an opening to expose at least a portion of the source 20 , the drain 30 and the gate 50 ; and forming a metal cap layer in the opening.

[0072] See also Fig.10 , corresponding to the source 20 and the drain 30 , part of the passivation layer 60 and the gate dielectric structure 40 are removed to form a first opening 701 and a second opening 702 respectively, and the first opening 701 and the second opening 702 penetrate the passivation layer 60 and the gate dielectric structure 40 ; corresponding to the gate 50 , part of the passivation layer 60 is removed to form a third opening 703, and the third opening 703 penetrates the passivation layer 60.

[0073] The method for removing part of the passivation layer 60 and the gate dielectric structure 40 may be etching. As an example, a mixed gas of argon and sulfur hexafluoride is used for etching in an inductively coupled plasma system.

[0074] See also Fig.11, metal is deposited in the first opening 701 to form a first metal cap layer 71, and the first metal cap layer 71 is electrically connected to the source 20; metal is deposited in the second opening 702 to form a second metal cap layer 72, and the second metal cap layer 72 is electrically connected to the drain 30; and a third metal cap layer 73 is formed in the third opening 703, and the third metal cap layer 73 is electrically connected to the gate 50.

[0075] The material of the metal cap layer is usually a metal with good conductivity. As an example, nickel (150 nm) / gold (50 nm) can be deposited using an electron beam deposition system to form the first metal cap layer 71, the second metal cap layer 72 and the third metal cap layer 73.

[0076] See also Fig.11 The embodiment of the present application also provides an enhanced gallium nitride p-type field effect transistor prepared by the above preparation method, including a source 20, a drain 30, a gate 50, a gate dielectric structure 40, and an epitaxial wafer structure 10 with a p-type gallium nitride layer 105 as the outermost layer, the p-type gallium nitride layer 105 having a two-dimensional hole gas, the source 20, the drain 30 and the gate dielectric structure 40 are arranged on the surface of the p-type gallium nitride layer 105, the gate 50 is arranged on the surface of the gate dielectric structure 40, and the gate dielectric structure 40 includes a hole tunneling layer 401, a hole trapping layer 402 and a blocking layer 403 stacked in sequence.

[0077] Fig.12 Schematic diagram of the principle of achieving enhancement of the enhanced gallium nitride p-type field effect transistor in the embodiment of the present application, Fig.12 (a), (b) and (c) in the figure correspond to the schematic diagrams of the energy band structure of the enhancement mode GaN p-type field effect transistor before initialization, during initialization and after initialization. Fig.11 and Fig.12 When the enhancement-mode GaN p-type field effect transistor is not initialized, there are many traps in the hole trapping layer 402 of the gate dielectric structure 40. Due to the polarization of the p-type GaN layer 105 and the barrier layer 104, there are a large number of two-dimensional hole gases in the channel of the p-type GaN layer 105. The device works normally but is in a normally-on state, that is, it is a depletion-type device. During the initialization process, since a negative voltage (about -10V) is applied to the gate 50, the barrier of the p-type GaN layer 105 is flattened, and the two-dimensional hole gas is tunneled from the hole tunneling layer 401 to the hole trapping layer 402 and stored. At the same time, due to the existence of the barrier layer 403, the two-dimensional hole gas will not leak out from the gate 50. After initialization, the two-dimensional hole gas is captured by most of the traps in the hole-trapping layer 402 and becomes fixed positive charges. These fixed positive charges can bend the valence band to a lower potential, causing the hole quantum well at the interface between the p-type gallium nitride layer 105 and the barrier layer 104 under the gate to disappear, depleting the two-dimensional hole gas, and converting the device from a depletion mode to an enhancement mode.

[0078] In practical applications, the threshold voltage can be adjusted by changing the negative pressure applied to the gate 50 during initialization. For example, when a lower negative pressure is applied to the gate 50, the energy band potential can be further increased, and more two-dimensional hole gas will be tunneled into the hole trapping layer 402 to be stored, thereby further depleting the two-dimensional hole gas under the gate, and achieving precise adjustment of the threshold voltage.

[0079] The embodiments described above are part of the embodiments of the present application, rather than all of the embodiments. The detailed description of the embodiments of the present application is not intended to limit the scope of the present application for protection, but merely represents the selected embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present application.

Claims

1. A method for preparing an enhancement-mode gallium nitride p-type field effect transistor, characterized in that: The following steps are involved: Providing an epitaxial wafer structure whose outermost layer is a p-type gallium nitride layer, wherein the p-type gallium nitride layer has a two-dimensional hole gas; Forming a source electrode and a drain electrode on the surface of the p-type gallium nitride layer; forming a gate dielectric structure on a surface of the p-type gallium nitride layer where the source and the drain are not formed, wherein the gate dielectric structure comprises a hole tunneling layer, a hole trapping layer and a blocking layer stacked in sequence; A gate is formed on the surface of the gate dielectric structure.

2. The preparation method according to claim 1, characterized in that: The hole tunneling layer, the hole trapping layer and the blocking layer are all made of high-k dielectric materials, and the dielectric constant and valence band of the material of the hole trapping layer are higher than those of the hole tunneling layer.

3. The preparation method according to claim 1, characterized in that: The material of the hole tunneling layer is aluminum oxide, the material of the hole trapping layer is hafnium dioxide and / or zirconium dioxide, and the material of the barrier layer is aluminum oxide.

4. The preparation method according to claim 1, characterized in that: The gate dielectric structure is formed by atomic layer deposition.

5. The preparation method according to claim 4, characterized in that: The method for forming the gate dielectric structure includes: Using trimethylaluminum as an aluminum source and water as an oxygen source, atomic layer deposition is performed on the surface of the p-type gallium nitride layer to form the hole tunneling layer; Using tetrakis(dimethylamino)hafnium as a hafnium source and water as an oxygen source, atomic layer deposition is performed on the surface of the hole tunneling layer to form the hole trapping layer; The blocking layer is formed by atomic layer deposition on the surface of the hole trapping layer using trimethylaluminum as an aluminum source and water as an oxygen source.

6. The preparation method according to any one of claims 1 to 5, characterized in that The thickness of the hole tunneling layer is 10 nm to 20 nm, the thickness of the hole trapping layer is 1 nm to 20 nm, and the thickness of the barrier layer is 10 nm to 20 nm.

7. The preparation method according to claim 1, characterized in that: After forming a gate on the surface of the gate dielectric structure, the method further includes: forming a passivation layer on the surfaces of the source electrode, the drain electrode, the gate electrode and the gate dielectric structure; Removing a portion of the passivation layer to form an opening to expose at least a portion of the source electrode, the drain electrode, and the gate electrode; A metal cap layer is formed in the opening.

8. An enhancement-mode gallium nitride p-type field effect transistor, characterized in that: The invention comprises an epitaxial wafer structure including a source electrode, a drain electrode, a gate electrode, a gate dielectric structure and a p-type gallium nitride layer as the outermost layer, wherein the p-type gallium nitride layer has a two-dimensional hole gas; the source electrode, the drain electrode and the gate dielectric structure are arranged on the surface of the p-type gallium nitride layer, the gate electrode is arranged on the surface of the gate dielectric structure, and the gate dielectric structure comprises a hole tunneling layer, a hole trapping layer and a blocking layer stacked in sequence.

9. The enhancement mode gallium nitride p-type field effect transistor according to claim 8, characterized in that: The material of the hole tunneling layer is aluminum oxide, the material of the hole trapping layer is hafnium dioxide and / or zirconium dioxide, and the material of the barrier layer is aluminum oxide.

10. The enhancement mode gallium nitride p-type field effect transistor according to claim 8, characterized in that: The thickness of the hole tunneling layer is 10 nm to 20 nm, the thickness of the hole trapping layer is 1 nm to 20 nm, and the thickness of the barrier layer is 10 nm to 20 nm.

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