Embedded source / drain MOS (Metal Oxide Semiconductor) tube and preparation method thereof

Abstract

According to the embedded source / drain MOS transistor and the preparation method thereof, the inner side wall structure and the outer side wall structure are arranged in the grid side wall, ion implantation of LDD and a halo region is achieved based on the inner side wall structure, ion implantation of a source / drain is achieved through the outer side wall structure, and the air side wall with the minimum dielectric constant is arranged in the outer side wall structure, so that the embedded source / drain MOS transistor is obtained. The invention aims to reduce the effective dielectric constant of the gate side wall, reduce the parasitic capacitance and reduce the problem of Vbd (breakdown voltage) failure between the gate and the SG. Besides, an inner side wall structure which is in contact with the semiconductor substrate and surrounds the outer side wall of the grid electrode is firstly formed, then when source and drain electrode grooves are formed, an outer side wall structure material layer which is in contact with the semiconductor substrate and surrounds the inner side wall structure is formed, and an air side wall is formed by removing a sacrificial layer. Therefore, the preparation of the grid side wall with the air side wall can be realized in the process of preparing the source and drain electrodes of the MOS tube, the grid side wall is directly formed on the surface of the semiconductor substrate, and the process is simple and easy to realize.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor integrated circuit manufacturing technology, and in particular relates to an embedded source / drain MOS transistor and its fabrication method. Background Technology

[0002] In the field of semiconductor integrated circuit manufacturing technology, with the development of semiconductor technology, the feature sizes of various semiconductor devices are constantly decreasing, and the critical dimensions of CMOS technology are becoming smaller and smaller, leading to increasingly higher performance requirements for semiconductor devices. Stress-channel transistors (SCMTs) are widely studied in the integrated circuit industry. They improve carrier mobility and thus device performance by using embedded epitaxial layers in the source and drain regions of the MOSFET to change the stress in the channel region. For example, for PMOS devices, currently, embedded germanium-silicon epitaxial processes are commonly used to form silicon-germanium epitaxial layers to improve the hole channel mobility of PMOS devices, thereby enhancing their performance.

[0003] In the fabrication of embedded source / drain MOSFETs, silicon nitride (SiN) is typically used as the sidewall material for the gate. The dielectric constant of SiN is approximately 7.4, which leads to larger parasitic capacitances between the MOSFET gate and the interconnect contact, between the gate and the source / drain, and the failure of Vbd (breakdown voltage) between the gate and the embedded source / drain, thus affecting the performance of the MOSFET. Summary of the Invention

[0004] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide an embedded source / drain MOSFET and its fabrication method, which solves the problem that the dielectric constant of the gate sidewall of the embedded source / drain MOSFET in the prior art is large, resulting in large parasitic capacitance caused by the gate sidewall and failure of Vbd (breakdown voltage) between the gate and the embedded source / drain, thus affecting the performance of the MOSFET device.

[0005] To achieve the above and other related objectives, the present invention provides an embedded source / drain MOSFET, the embedded source / drain MOSFET comprising:

[0006] A semiconductor substrate having source trenches and drain trenches for forming the source and drain of a MOS transistor;

[0007] The source and drain are selectively epitaxially filled in the source trench and the drain trench respectively, and protrude from the surface of the semiconductor substrate to a predetermined height.

[0008] A gate structure located on a semiconductor substrate between the source and drain electrodes, the gate structure comprising: a gate composed of a gate dielectric layer and a gate conductive layer, and a gate sidewall located on the surface of the semiconductor substrate and surrounding the outer sidewall of the gate; the gate sidewall comprises an inner sidewall structure and an outer sidewall structure from the inside out, wherein the outer sidewall structure includes an air sidewall exposed on the surface of the semiconductor substrate, and the air sidewall is located on the side closer to the inner sidewall structure; from the inside out is defined as the direction from near the gate to away from the gate.

[0009] Optionally, the inner sidewall structure includes a first dielectric material layer and a second dielectric material layer from the inside out, wherein the etching selectivity ratio of the second dielectric material layer to the first dielectric material layer is greater than 1; the outer sidewall structure further includes a third dielectric material layer, which is connected to the air sidewall and disposed on the side away from the gate, and contacts the source and drain electrodes protruding from the surface of the semiconductor substrate.

[0010] Furthermore, the semiconductor substrate is a silicon substrate.

[0011] Furthermore, the first dielectric material layer is a SiON layer or a SiOC layer, and the second and third dielectric material layers are SiN layers.

[0012] Optionally, the surface of the gate sidewall is provided with an insulating covering layer to seal the top of the air sidewall.

[0013] Optionally, the ratio of the thickness of the air sidewall to the thickness of the gate sidewall is 1:3 to 1:6, including the endpoint values.

[0014] The present invention also provides a method for fabricating an embedded source / drain MOSFET, wherein the method for fabricating the embedded source / drain MOSFET includes the following step of fabricating the gate sidewall:

[0015] A semiconductor substrate is provided, the semiconductor substrate having a source region and a drain region for forming the source and drain of a MOS transistor; a gate composed of a gate dielectric layer and a gate conductive layer is formed on the semiconductor substrate, and the gate is located between the source region and the drain region;

[0016] A hard mask layer is formed on the gate surface;

[0017] An inner sidewall structure is formed on the surface of the semiconductor substrate to surround the outer sidewall of the gate.

[0018] An outer wall structure material layer is formed on the surface and sidewalls of the structure obtained above. The outer wall structure material layer includes a sacrificial layer, and the sacrificial layer is close to the side of the inner wall structure.

[0019] The outer wall structure material layer and the semiconductor substrate are etched, leaving only the outer wall structure material layer formed on the outer wall of the inner wall structure, and a source trench and a drain trench are formed in the semiconductor substrate where the source region and the drain region are located.

[0020] The sacrificial layer is removed from the outer wall structure material layer, leaving only the outer wall of the inner wall structure, to expose the surface of the semiconductor substrate, thereby forming an outer wall structure, and the location of the sacrificial layer forms an air sidewall in the outer wall structure.

[0021] Optionally, the method for forming the inner wall structure includes:

[0022] A first dielectric material layer and a second dielectric material layer are sequentially formed on the surface and sidewalls of the obtained structure;

[0023] A dry etching process is used to etch the first dielectric material layer and the second dielectric material layer, leaving only the first dielectric material layer and the second dielectric material layer formed on the outer wall of the gate and the hard mask layer to form the inner sidewall structure.

[0024] Optionally, after forming the inner sidewall structure, the method further includes the step of forming LDD region and halo region by ion implantation; after forming the source trench and the drain trench, the method further includes the step of forming source and drain by selective epitaxy, wherein the source and drain are respectively filled in the source trench and the drain trench and protrude from the surface of the semiconductor substrate to a preset height, and the source and drain protruding from the surface of the semiconductor substrate are connected to the outermost sidewall of the outer sidewall structure.

[0025] Optionally, after forming the outer sidewall structure, the method further includes the step of forming an insulating covering layer on the surface of the resulting structure to seal the top of the air sidewall.

[0026] As described above, the embedded source / drain MOS transistor and its fabrication method of the present invention, by setting an inner sidewall structure and an outer sidewall structure in the gate sidewall of the outer sidewall of the gate, can realize ion implantation of the LDD region and halo region of the MOS transistor based on the inner sidewall structure, and can realize ion implantation of the source / drain of the MOS transistor through the outer sidewall structure. Furthermore, an air sidewall is set in the outer sidewall structure. The dielectric constant of air is the smallest, approximately equal to 1, which is the smallest dielectric constant value among dielectric materials. Therefore, the air sidewall can effectively reduce the equivalent dielectric constant of the gate sidewall, which is beneficial to reducing parasitic capacitance caused by the gate sidewall, such as the parasitic capacitance between the gate and the source / drain, and the parasitic capacitance between the gate and the interconnect contact hole, etc. It can also reduce the problem of Vbd (breakdown voltage) failure between the gate and the embedded source / drain. In addition, by first forming an inner sidewall structure that contacts the semiconductor substrate and surrounds the outer sidewall of the gate, and then forming the source trench and drain trench by etching the outer sidewall structure material layer, an outer sidewall structure material layer that contacts the semiconductor substrate and surrounds the inner sidewall structure is formed. By removing the sacrificial layer in the outer sidewall structure material layer, an air sidewall is formed. Thus, the gate sidewall with air sidewall can be fabricated during the fabrication of the source and drain of the MOS transistor, and the gate sidewall is formed directly on the surface of the semiconductor substrate. The process is simple and easy to implement. Attached Figure Description

[0027] Figures 1 to 12 The diagram shows a cross-sectional structure after each step in the fabrication method of the embedded source / drain MOS transistor of the present invention.

[0028] Component designation explanation

[0029] 10 Semiconductor substrate

[0030] 100 source region

[0031] 11 Gate

[0032] 110 Gate dielectric layer

[0033] 111 Gate conductive layer

[0034] 12 Hard mask layers

[0035] 13. Inner wall structure

[0036] 130 First dielectric material layer

[0037] 131 Second dielectric material layer

[0038] 14. External wall structure

[0039] 140 Sacrificial Layer

[0040] 141 Air sidewall

[0041] 142 Third dielectric material layer

[0042] 15 Gate sidewalls

[0043] 16 Insulation Covering Layer

[0044] 17 Source

[0045] 170 Source Trench Detailed Implementation

[0046] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0047] Please see Figures 1 to 12 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the illustrations only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0048] Example 1

[0049] like Figure 12 As shown, this embodiment provides an embedded source / drain MOSFET, which includes:

[0050] Semiconductor substrate 10, the semiconductor substrate 10 having source trenches 170 for forming the source and drain of a MOS transistor (e.g., Figure 9 (as shown) and drain trench;

[0051] The source 17 and drain are selectively epitaxially filled in the source trench 170 and the drain trench, respectively, and protrude from the surface of the semiconductor substrate 10 to a predetermined height.

[0052] A gate structure located on a semiconductor substrate 10 between the source 17 and the drain, the gate structure comprising: a gate 11 composed of a gate dielectric layer and a gate conductive layer, and a gate sidewall 15 located on the surface of the semiconductor substrate 10 and surrounding the outer sidewall of the gate 11; the gate sidewall 15 includes an inner sidewall structure 13 and an outer sidewall structure 14 from the inside out, wherein the outer sidewall structure 14 includes an air sidewall 141 exposed on the surface of the semiconductor substrate 10, and the air sidewall 141 is located on the side close to the inner sidewall structure 13; from the inside out is defined as the direction from near the gate 11 to away from the gate 11.

[0053] In this embodiment, the embedded source / drain MOSFET uses an inner and outer sidewall structure in the gate sidewall. The inner sidewall structure enables ion implantation of the LDD and halo regions of the MOSFET, while the outer sidewall structure enables ion implantation of the source / drain. Furthermore, an air sidewall is incorporated within the outer sidewall structure. Air has the lowest dielectric constant, approximately 1, which is the smallest among dielectric materials. Therefore, the air sidewall effectively reduces the equivalent dielectric constant of the gate sidewall, thus mitigating parasitic capacitances caused by the gate sidewall, such as the parasitic capacitance between the gate and the source / drain, and the parasitic capacitance between the gate and interconnect contact holes. Additionally, it reduces the Vbd (breakdown voltage) failure problem between the gate and the embedded source / drain.

[0054] like Figure 2 As shown, to... Figure 11 , 12 The enlarged cross-sectional diagram of the gate 11 shows a gate dielectric layer 110 below and a gate conductive layer 111 above the gate dielectric layer 110. The gate dielectric layer 110 is generally located above the MOS channel, providing electrical isolation between the gate conductive layer 111 and the channel layer. Applying a voltage to the gate conductive layer 111 controls the switching of the MOS channel. The gate 11 can be a metal-dielectric layer structure or a semiconductor-dielectric layer structure, such as a metal layer-SiON dielectric layer structure (e.g., aluminum, copper, silver, tungsten, etc.) or a polysilicon semiconductor layer-silicon oxide dielectric layer structure, depending on the specific requirements.

[0055] It should be noted here that, since the focus of this embodiment is on the gate sidewall structure on the outer sidewall of the gate, Figure 1 , Figures 3 to 12 Only a portion of the MOSFET structure related to the gate sidewall is shown for ease of understanding. However, in practice... Figure 1 , Figures 3 to 12The embedded source / drain MOSFETs illustrated should also include other conventional MOSFET structures, such as the interconnection structure of the drain, source, drain and gate, etc., which are well known in the art and will not be described in detail here.

[0056] As a preferred example, the inner wall structure 13 is composed of a stack of two dielectric material layers, such as... Figure 12 The inner wall structure 13 consists of a first dielectric material layer 130 and a second dielectric material layer 131 arranged from the inside out. The etching selectivity ratio of the second dielectric material layer 131 to the first dielectric material layer 130 is greater than 1. This is to ensure that during the fabrication of the inner wall structure 13, etching the second dielectric material layer 131 does not cause significant etching damage to the first dielectric material layer 130. In this concept, a higher etching selectivity ratio between the second dielectric layer 131 and the first dielectric layer 130 is preferable. Furthermore, the outer wall structure 14 is also composed of a stack of two dielectric material layers, such as... Figure 12 The semiconductor substrate 10 has an air sidewall 141 and a third dielectric material layer 142 extending from the inside out. The third dielectric material layer 142 contacts the source electrode 17 and the drain electrode protruding from the surface of the semiconductor substrate 10. Further, when the semiconductor substrate 10 is made of silicon-based material, such as single-crystal silicon, preferably, the first dielectric material layer 130 is made of SiON or SiOC, obtained by nitriding or carburizing silicon oxide; the second dielectric material layer 131 and the third dielectric layer 142 are made of SiN.

[0057] However, it is not limited to the above limitations. The inner wall structure 13 can also be other single-layer, three-layer, four-layer, or more-layer structures, and the outer wall structure 14 can also be other three-layer, four-layer, or more-layer structures. The specific configuration is determined according to actual needs, and the materials used for each layer are also selected according to actual needs. In addition, the material of the semiconductor substrate 10 can also be other semiconductor materials suitable for fabricating MOS transistors, such as silicon-on-insulator (SOI) substrates, bulk silicon substrates, germanium substrates, germanium-silicon substrates, indium phosphide substrates, sapphire substrates, silicon carbide substrates, gallium arsenide substrates, germanium-on-insulator substrates, etc.

[0058] As a better example, such as Figure 12 As shown, an insulating cladding layer 16 is provided on the surface of the gate sidewall 15 to seal the air sidewall 141. Of course, for ease of fabrication and to serve as a buffer layer or bonding layer for subsequent MOS structure fabrication, this insulating cladding layer 16 can be formed on the entire exposed surface of the resulting structure.

[0059] As another preferred example, the ratio of the thickness of the air sidewall 141 to the thickness of the gate sidewall 15 is 1:3 to 1:6, including endpoint values ​​such as 1:3, 1:4, 1:5 or 1:6, to ensure the robustness of the gate sidewall 15 while reducing the dielectric constant of the gate sidewall 15.

[0060] As an example, the embedded source / drain MOSFET in this embodiment can be either an NMOS or a PMOS. When an NMOS is selected, the source 17 and drain material formed by selective epitaxy can be SiC; when a PMOS is selected, the source 17 and drain material formed by selective epitaxy can be SiGe. However, it is not limited to these, and other suitable selective epitaxial source / drain materials can also be used. In addition, the source 17 and drain formed by embedded epitaxy protrude from the surface of the semiconductor substrate 10 by a predetermined height. The source 17 and drain protruding from the surface of the semiconductor substrate 10 by a predetermined height are used to attach to the outer wall to ensure that they do not tip over. For example, the ratio of the height of the source 17 and drain protruding from the surface of the semiconductor substrate 10 by a predetermined height to the height of the gate 11 is approximately 1 / 2.

[0061] Example 2

[0062] This embodiment provides a method for fabricating an embedded source / drain MOSFET, used to fabricate the embedded source / drain MOSFET described in Embodiment 1 above. However, it is not limited to this method; other fabrication methods can also be used to fabricate the embedded source / drain MOSFET of Embodiment 1. Relatively speaking, the fabrication method of this embodiment is a preferred fabrication scheme. The fabrication method includes the following steps for fabricating the gate sidewall:

[0063] S1. A semiconductor substrate is provided, the semiconductor substrate having a source region and a drain region for forming the source and drain of a MOS transistor; a gate composed of a gate dielectric layer and a gate conductive layer is formed on the semiconductor substrate, and the gate is located between the source region and the drain region;

[0064] S2. A hard mask layer is formed on the gate surface;

[0065] S3. An inner sidewall structure surrounding the outer sidewall of the gate is formed on the surface of the semiconductor substrate;

[0066] S4. An outer wall structure material layer is formed on the surface and sidewall of the structure obtained above. The outer wall structure material layer includes a sacrificial layer, and the sacrificial layer is close to the side of the inner wall structure.

[0067] S5. Etch the outer wall structure material layer and the semiconductor substrate, retaining only the outer wall structure material layer formed on the outer wall of the inner wall structure, and form source trenches and drain trenches in the semiconductor substrate where the source region and the drain region are located.

[0068] S6. Remove the sacrificial layer from the outer wall structure material layer, leaving only the outer wall of the inner wall structure, to expose the surface of the semiconductor substrate, thereby forming an outer wall structure, and the location of the sacrificial layer forms an air sidewall in the outer wall structure.

[0069] It should be noted that the fabrication method in this embodiment focuses on the fabrication process of the gate sidewall. In practice, it also includes the fabrication process of other structures of the MOS transistor, such as the source, drain, LDD region, halo region, and interconnection lead-out structures that expose the surface of the semiconductor substrate. These can all be fabricated using methods known in the art, and will not be described in detail here.

[0070] The gate sidewall fabrication method proposed in this embodiment first forms an inner sidewall structure that contacts the semiconductor substrate and surrounds the outer sidewall of the gate. Then, when etching the outer sidewall structure material layer to form source trenches and drain trenches, an outer sidewall structure material layer that contacts the semiconductor substrate and surrounds the inner sidewall structure is formed. By removing the sacrificial layer in the outer sidewall structure material layer, an air sidewall is formed. Thus, the gate sidewall with air sidewall can be fabricated during the fabrication of the source and drain of the MOSFET, and the gate sidewall is directly formed on the surface of the semiconductor substrate. The process is simple and easy to implement, and it can reduce the parasitic capacitance of the MOSFET and reduce the Vbd (breakdown voltage) failure problem between the gate and the embedded source / drain.

[0071] The preparation method of this embodiment will be described in detail below with reference to the specific accompanying drawings.

[0072] like Figure 1 As shown, step S1 is performed first, providing a semiconductor substrate 10, which has a source region 100 and a drain region for forming the source and drain of a MOS transistor. Figure 1 Only one source region 100 is shown in the diagram; in reality, the semiconductor substrate 10 has several source regions 100 and several drain regions; for example... Figure 2 As shown, a gate 11 composed of a gate dielectric layer 110 and a gate conductive layer 111 is formed on the semiconductor substrate 10, and the gate 11 is located between the source region 100 and the drain region.

[0073] It should be noted that the gate 11 is located between the source region 100 and the drain region, and has a certain gap. Generally, this gap is used to form the LDD region and halo region of the MOS transistor.

[0074] As an example, the material of the semiconductor substrate 10 can be any semiconductor material suitable for fabricating MOS transistors, such as silicon-on-insulator (SOI) substrate, bulk silicon substrate, germanium substrate, germanium-silicon substrate, indium phosphide substrate, sapphire substrate, silicon carbide substrate, gallium arsenide substrate, germanium-on-insulator substrate, etc. In this embodiment, a single-crystal silicon substrate is preferred.

[0075] like Figure 1 As shown, step S2 is then performed to form a hard mask layer 12 on the surface of the gate 11.

[0076] As an example, the material of the hard mask layer 12 can be silicon nitride.

[0077] like Figure 5 As shown, step S3 is then performed, in which an inner wall structure 13 is formed on the surface of the semiconductor substrate 10 to surround the outer wall of the gate 11.

[0078] The inner wall structure 13 can be a single dielectric material layer or a stack of two or more dielectric material layers. Preferably, the dielectric material layers of adjacent layers have a large etching selectivity to ensure that etching one dielectric material layer does not cause significant etching damage to the other. The thickness of the inner wall structure 13 is determined by the boundary positions of the LDD region and halo region to be formed in the MOSFET, and is selected according to actual needs, without excessive restrictions here.

[0079] The following example, using the inner wall structure 13 as a two-layer dielectric material structure, illustrates a specific method for forming the inner wall structure 13: First, as... Figure 3 and Figure 4 As shown, the exposed surface of the structure obtained after step S2, including the front surface and sidewalls, is sequentially formed with a first dielectric material layer 130 and a second dielectric material layer 131. Preferably, the material of the first dielectric material layer 130 is SiON, and the material of the second dielectric layer 131 is SiN. Deposition processes such as CVD and ALD can be used to form the first dielectric material layer 130 and the second dielectric layer 131. Figure 5 As shown, a dry etching process is then used to etch the first dielectric material layer 130 and the second dielectric material layer 131, leaving only the first dielectric material layer 130 and the second dielectric material layer 131 formed on the outer wall of the gate 11 and the hard mask layer 12, so that this part of the first dielectric material layer 130 and the second dielectric material layer 131 forms the inner sidewall structure 13.

[0080] like Figure 6As shown, as an example, after forming the inner wall structure 13, the process further includes forming the LDD region and halo region of the MOS transistor using an ion implantation process. Figure 6 In this process, the inner wall structure 13 and the gate 11 are self-aligned structures, and ion implantation is performed within a preset area of ​​the semiconductor substrate 10 on their sides. Generally, vertical ion implantation is used to form LDD regions, and tilted ion implantation is used to form halo regions.

[0081] like Figure 7 and Figure 8 As shown, step S4 is then performed, forming an outer wall structure material layer on the exposed surface of the structure obtained above, i.e. the structure obtained after step S3, including the front surface and the sidewalls. The outer wall structure material layer includes a sacrificial layer 140, and the sacrificial layer 140 is located on the side close to the inner wall structure 13.

[0082] Generally, the outer wall structure material layer is selected as a stack of two or more multilayer dielectric material layers. Preferably, adjacent dielectric material layers have a large etching selectivity to ensure that etching one dielectric material layer does not cause significant etching damage to the other. The thickness of the outer wall structure material layer is determined by the boundary positions of the source and drain regions to be formed in the MOSFET, and is selected according to actual needs, without excessive restrictions here. Figure 8 As shown, the outer wall structure material layer consists of two layers, including a sacrificial layer 140 and a third dielectric material layer 142 from the inside out. Preferably, the material of the sacrificial layer 140 is SiO2 and the material of the third dielectric layer 142 is SiN. The sacrificial layer 140 and the third dielectric layer 142 can be formed by deposition processes such as CVD or ALD.

[0083] like Figure 9 As shown, step S5 is then performed, etching the outer wall structure material layer and the semiconductor substrate 10, retaining only the outer wall structure material layer formed on the outer wall of the inner wall structure 13, and forming source trench 170 and drain trench in the semiconductor substrate 10 where the source region 100 and the drain region are located. Here, when etching to form the source trench 170 and drain trench, the hard mask layer 12 serves as a protective layer for the gate 11.

[0084] The outer wall structure material layer and the semiconductor substrate 10 are generally etched using a dry etching process.

[0085] like Figure 10As shown in the illustration, as an example, after forming the source trench 170 and the drain trench, the process further includes forming a source 17 and a drain using selective epitaxy. The source 17 and the drain are respectively filled in the source trench 170 and the drain trench and protrude from the surface of the semiconductor substrate 10. Here, the selective epitaxy technique uses existing conventional process parameters, which are selected according to actual needs and are not excessively restricted here.

[0086] like Figure 11 As shown, the final step S6 is performed to remove the sacrificial layer 140 from the outer wall structure material layer that is only retained on the outer wall of the inner wall structure 13 until the surface of the semiconductor substrate 10 is exposed, so as to form the outer wall structure 14, and the location of the sacrificial layer 140 is formed as the air sidewall 141 in the outer wall structure 14.

[0087] As an example, the sacrificial layer 140 is removed using a wet etching process.

[0088] like Figure 12 As shown, after forming the outer sidewall structure 14, the method further includes forming an insulating covering layer 16 on the surface of the resulting structure to seal the air sidewall 141.

[0089] As an example, the insulating coating layer 16 is made of SiO2 and can be formed using a CVD process.

[0090] In summary, this invention provides an embedded source / drain MOSFET and its fabrication method. By setting an inner sidewall structure and an outer sidewall structure in the gate sidewall, ion implantation of the LDD region and halo region of the MOSFET can be achieved based on the inner sidewall structure. Ion implantation of the source / drain of the MOSFET can be achieved through the outer sidewall structure. Furthermore, an air sidewall is set in the outer sidewall structure. Air has the smallest dielectric constant, approximately equal to 1, which is the smallest dielectric constant among dielectric materials. Therefore, the air sidewall can effectively reduce the equivalent dielectric constant of the gate sidewall, which is beneficial for reducing parasitic capacitance caused by the gate sidewall, such as the parasitic capacitance between the gate and the source / drain, and the parasitic capacitance between the gate and the interconnect contact hole, etc. It can also reduce the problem of Vbd (breakdown voltage) failure between the gate and the embedded source / drain. Furthermore, by first forming an inner sidewall structure that contacts the semiconductor substrate and surrounds the outer sidewall of the gate, and then forming the source and drain trenches during the etching of the outer sidewall structure material layer, an outer sidewall structure material layer that contacts the semiconductor substrate and surrounds the inner sidewall structure is formed. By removing the sacrificial layer in the outer sidewall structure material layer, an air sidewall is formed. Thus, the gate sidewall with an air sidewall can be fabricated during the fabrication of the source and drain of a MOS transistor, and the gate sidewall is directly formed on the surface of the semiconductor substrate, making the process simple and easy to implement. Therefore, this invention effectively overcomes the various shortcomings of the prior art and has high industrial applicability.

[0091] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. An embedded source / drain MOS tube, characterized in that: The embedded source / drain MOS tube comprises: A semiconductor substrate having a source trench and a drain trench for forming a source and a drain of a MOS tube; A source electrode and a drain electrode are respectively filled in the source electrode trench and the drain electrode trench by using a selective epitaxial technology and protrude from the surface of the semiconductor substrate to a preset height; A gate structure located on a semiconductor substrate between the source and the drain, the gate structure comprising: a gate composed of a gate dielectric layer and a gate conductive layer, a gate sidewall located on the surface of the semiconductor substrate and surrounding the outer sidewall of the gate; the gate sidewall comprises an inner sidewall structure and an outer sidewall structure from the inside to the outside, wherein the outer sidewall structure comprises a layer of air sidewall exposing the surface of the semiconductor substrate, and the air sidewall is close to one side of the inner sidewall structure; from the inside to the outside is defined as a direction from close to the gate to away from the gate.

2. The embedded source / drain MOS transistor according to claim 1, characterized in that: The inner sidewall structure includes a first dielectric material layer and a second dielectric material layer from the inside to the outside, wherein the etching selectivity ratio of the second dielectric material layer to the first dielectric material layer is greater than 1; the outer sidewall structure also includes a third dielectric material layer, the third dielectric material layer is connected to the air sidewall and is arranged on a side away from the gate, and is in contact with the source and the drain protruding from the surface of the semiconductor substrate.

3. The embedded source / drain MOS transistor according to claim 2, characterized in that: The semiconductor substrate is a silicon substrate.

4. The embedded source / drain MOS transistor according to claim 3, characterized in that: The first dielectric material layer is a SiON layer or a SiOC layer, and the second dielectric material layer and the third dielectric material layer are SiN layers.

5. The embedded source / drain MOS transistor according to claim 1, characterized in that: An insulating coating layer is provided on the surface of the gate sidewall to seal the top of the air sidewall.

6. The embedded source / drain MOS transistor according to claim 1, characterized in that: The ratio of the thickness of the air sidewall to the thickness of the gate sidewall is 1:3-1:6, including endpoint values.

7. A method for preparing an embedded source / drain MOS tube, characterized in that: The method for preparing the embedded source / drain MOS tube includes the following steps of preparing the gate sidewall: A semiconductor substrate is provided, wherein the semiconductor substrate has a source region and a drain region for forming a source and a drain of a MOS tube; a gate composed of a gate dielectric layer and a gate conductive layer is formed on the semiconductor substrate, and the gate is located between the source region and the drain region; forming a hard mask layer on the surface of the gate; Forming an inner sidewall structure surrounding the outer sidewall of the gate on the surface of the semiconductor substrate; Forming an outer wall structure material layer on the surface and sidewall of the obtained structure, wherein the outer wall structure material layer includes a sacrificial layer, and the sacrificial layer is close to one side of the inner wall structure; Etching the outer sidewall structure material layer and the semiconductor substrate, retaining only the outer sidewall structure material layer formed on the outer sidewall of the inner sidewall structure, and forming a source trench and a drain trench in the semiconductor substrate where the source region and the drain region are located; The sacrificial layer in the outer wall structure material layer is removed to expose the surface of the semiconductor substrate, so as to form an outer wall structure, and the location of the sacrificial layer forms an air sidewall in the outer wall structure.

8. The method for preparing an embedded source / drain MOS transistor according to claim 7, characterized in that: The method for forming the inner side wall structure includes: Sequentially forming a first dielectric material layer and a second dielectric material layer on the surface and sidewall of the obtained structure; The first dielectric material layer and the second dielectric material layer are etched by dry etching process, and only the first dielectric material layer and the second dielectric material layer formed on the outer sidewalls of the gate and the hard mask layer are retained to form the inner sidewall structure.

9. The method for preparing an embedded source / drain MOS transistor according to claim 7, characterized in that: After forming the inner sidewall structure, the step of ion implantation to form an LDD region and a halo region is also included; after forming the source trench and the drain trench, the step of using selective epitaxial technology to form a source and a drain is also included, the source and the drain are respectively filled in the source trench and the drain trench and protrude from the surface of the semiconductor substrate to a preset height, and the source and the drain protruding from the surface of the semiconductor substrate are connected to the outermost sidewall of the outer sidewall structure.

10. The method for preparing an embedded source / drain MOS transistor according to claim 7, characterized in that: After forming the outer side wall structure, the method further includes forming an insulating coating layer on the surface of the obtained structure to seal the top of the air side wall.

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