MOSFET device and preparation method thereof

Abstract

The invention provides an MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) device and a preparation method thereof. The device comprises a substrate of a first conduction type and an epitaxial layer on the substrate; the plurality of column regions of the second conduction type are formed in the epitaxial layer and are transversely staggered with the epitaxial layer; the first groove and the second groove extend downwards from the top surfaces of the left side and the right side of the epitaxial layer to the top of the column region; the first gate region and the first split gate are formed in the first trench; the second gate region and the second split gate are symmetrically formed in the second trench; the first gate region and the second gate region respectively comprise an upper part and a lower part, the transverse width of the upper part is greater than that of the lower part, and an inverted L-shaped structure is formed; the first gate region covers the first split gate, the second gate region covers the second split gate, and the first gate region and the second gate region are isolated through an interlayer dielectric layer. According to the structure, a super junction, a split gate and two transverse channels are introduced, so that an electric field is in approximately rectangular distribution when the device is in forward withstand voltage, the compromise relation between specific on-resistance and breakdown voltage is optimized, and an FOM value is reduced.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a metal-oxide-semiconductor field-effect transistor (MOSFET) device and a preparation method thereof. Background Art

[0002] MOSFET devices are field-effect transistors that can be widely used in analog and digital circuits. Field-effect transistors play many important roles in electronic circuits, including signal amplification, switch control, power management, analog circuit applications, and high-frequency applications.

[0003] However, in MOSFET devices, there is a trade-off relationship between on-resistance and breakdown voltage. Increasing the breakdown voltage BV and reducing the specific on-resistance often cannot be achieved at the same time, resulting in large conduction losses when the device works under high voltage. At present, some transistor structures still need to be proposed in the hope of better improving the trade-off relationship between specific on-resistance and breakdown voltage. Summary of the invention

[0004] The purpose of the present application is to provide a MOSFET device and a preparation method thereof, which optimizes the trade-off relationship between specific on-resistance and breakdown voltage and reduces the quality factor FOM value.

[0005] In a first aspect, the present application provides a MOSFET device, which includes: a substrate having a first conductivity type; an epitaxial layer having the first conductivity type and formed on the substrate; a plurality of column regions of a second conductivity type formed in the epitaxial layer, wherein the plurality of column regions of the second conductivity type and the epitaxial layer of the first conductivity type are laterally staggered; a first trench and a second trench extend downward from the top surfaces on the left and right sides of the epitaxial layer to the top of the column region; wherein a first gate region and a first split gate are formed in the first trench; a second gate region and a second split gate are symmetrically formed in the second trench with respect to the first gate region and the first split gate, respectively; the first gate region and the second gate region respectively include an upper portion and a lower portion, wherein the lateral width of the upper portion is greater than the lateral width of the lower portion, and the upper portion and the lower portion form an inverted L-shaped structure; the first gate region covers the first split gate, and the first gate region and the first split gate are isolated by an interlayer dielectric layer; the second gate region covers the second split gate, and the second gate region and the second split gate are isolated by an interlayer dielectric layer.

[0006] In a second aspect, the present application also provides a method for preparing a MOSFET device, the method comprising: growing a first epitaxial layer of a first conductivity type on a substrate; forming a column region of a second conductivity type on the first epitaxial layer; epitaxially growing a second epitaxial layer of the first conductivity type on the column region and on top of the first epitaxial layer; digging grooves from top to bottom on the left and right sides of the second epitaxial layer to the top surface of the column region; filling polysilicon after forming a dielectric layer at the bottom and side walls of the grooves on both sides; etching the polysilicon to form a first split gate and a second split gate; forming a dielectric layer in the grooves on both sides for a second time and then filling polysilicon; etching the polysilicon to form a first gate region and a second gate region; after forming a dielectric layer for a third time on the top and side walls of the first gate region and the second gate region, growing a source metal on the dielectric layer and in the grooves on both sides.

[0007] In the MOSFET device and preparation method provided by the present application, a longitudinal polysilicon gate is introduced as a split gate in the body in the upper half of the device to form a capacitive depletion region; the superjunction structure formed by the P-type column region and the N-type column region introduced in the middle and lower part of the device can introduce a lateral electric field to assist in depleting the positively charged ionized donor charge in the N-type column. The device structure makes the electric field change from a normal triangular distribution to a nearly rectangular distribution, which improves the breakdown voltage, and can further increase the doping concentration in the drift region, thereby reducing the specific on-resistance of the device, improving the trade-off relationship between the specific on-resistance and the breakdown voltage, and this structure reduces the gate charge, thereby also reducing the FOM value, reducing the conduction loss and switching loss of the device, and improving the system efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] In order to more clearly illustrate the specific implementation methods of the present application or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0009] Figure 1 A cross-sectional schematic diagram of a MOSFET device provided in an embodiment of the present application;

[0010] Figure 2 A cross-sectional schematic diagram of another MOSFET device provided in an embodiment of the present application;

[0011] Figure 3 A cross-sectional schematic diagram of another MOSFET device provided in an embodiment of the present application;

[0012] Figure 4 A cross-sectional schematic diagram of another MOSFET device provided in an embodiment of the present application;

[0013] Figures 5A-5K A schematic cross-sectional view of a device involved in the preparation process of a MOSFET device provided in an embodiment of the present application.

[0014] As shown in the accompanying drawings, the same reference numerals refer to the same parts in all the different views. The accompanying drawings provided herein are for the purpose of illustrating embodiments, principles, concepts, etc., and are not drawn to scale.

[0015] In the above drawings, the meanings of the reference numerals are as follows: 1 is the source metal; 2 is the gate dielectric layer; 3-1 is the first gate region; 3-2 is the second gate region; 4 is the interlayer dielectric layer; 5-1 is the first split gate; 5-2 is the second split gate; 5-3 is the third split gate; 6 is the first body region; 7-1 is the first source region; 7-2 is the second source region; 8 is the body contact region; 9-1 is the first column region, 9-2 is the second column region; 10 is the third column region; 11 is the epitaxial layer; 12 is the substrate; 13 is the drain metal; 14-1 is the third source region, 14-2 is the fourth source region; 15-1 is the second body region; 15-2 is the third body region; 17, 18, 24 are trenches at different process stages; 19, 21 are dielectric layers at different process stages; 20, 22 are polysilicon at different process stages. DETAILED DESCRIPTION

[0016] The technical solution of the present application will be described clearly and completely below in conjunction with the embodiments. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present application.

[0017] The embodiment of the present application provides a MOSFET device and a preparation method thereof, so that when the device is in a forward withstand voltage, the electric field is distributed in an approximately rectangular manner, and two vertical channels are introduced at the same time, thereby optimizing the trade-off relationship between the specific on-resistance and the breakdown voltage, and reducing the quality factor FOM value, wherein FOM=Qg×Rsp, Qg is the gate charge, and Rsp is the device specific on-resistance. To facilitate understanding of the present embodiment, a MOSFET device disclosed in the embodiment of the present application is first introduced in detail.

[0018] It should be noted that the letter "N" as used herein refers to an N-type dopant, and the letter "P" refers to a P-type dopant. The plus sign "+" or the minus sign "-" is used to indicate a relatively high dopant concentration and a relatively low dopant concentration, respectively. The term "channel" is used herein in a generally recognized manner. That is, the movement of current within the FET is from the source connection to the drain connection in the channel. The channel can be made of an N-type semiconductor material or a P-type semiconductor material. Therefore, the FET is designated as an N-channel device or a P-channel device. The following embodiments are described using an N-channel device as an example, but the embodiments of the present invention are not limited thereto. That is, the various features described herein can be used for P-channel devices. The content disclosed in the present invention can form a corresponding P-channel device by replacing N-type dopants and materials with corresponding P-type dopants and materials, and vice versa.

[0019] Figure 1 The cross-sectional view of a MOSFET device 100 provided in an embodiment of the present application includes a substrate 12 having a first conductivity type. An epitaxial layer 11 is formed on the substrate 12, wherein the doping concentration of the epitaxial layer 11 is lower than the doping concentration of the substrate 12. Figure 1 In the embodiment shown, N and N+ are used for distinction. In the epitaxial layer 11, a plurality of column regions of the second conductivity type are formed, such as Figure 1 The first column region 9-1 and the second column region 9-2 shown in the figure, the plurality of column regions of the second conductivity type and the epitaxial layer of the first conductivity type are arranged in a transversely staggered manner. In one embodiment, ion implantation can be further performed in the epitaxial layer 11 between the plurality of column regions of the second conductivity type to obtain a third column region 10 of the first conductivity type with a higher doping concentration, and the plurality of column regions of the second conductivity type and the epitaxial layer of the first conductivity type (or the third column region 10 of the first conductivity type) are arranged in a transversely staggered manner to form a super junction region. The MOSFET device 100 also includes a first trench and a second trench, the first trench and the second trench extending downward from the top surface of the left and right sides of the epitaxial layer to the top of the column region, wherein a first gate region 3-1 and a first split gate 5-1 are formed in the first trench, and a second gate region 3-2 and a second split gate 5-2 symmetrical to the first gate region and the first split gate are formed in the second trench. The first gate region 3-1 and the second gate region 3-2 include an upper part and a lower part respectively, the lateral width of the upper part is greater than the lateral width of the lower part, and the upper part and the lower part form an inverted L-shaped structure. The first gate region 3-1 covers the first split gate 5-1, and the first gate region 3-1 and the first split gate 5-1 are isolated by the interlayer dielectric layer 4. The second gate region 3-2 covers the second split gate 5-2, and the second gate region 3-2 and the second split gate 5-2 are isolated by the interlayer dielectric layer 4.

[0020] Furthermore, the MOSFET device 100 further includes a first body region 6 formed in the epitaxial layer 11 between the first trench and the second trench. Figure 1 In the illustrated embodiment, the depth of the first body region 6 is shown as being equal to the height of the upper portions of the first gate region 3-1 and the second gate region 3-2, but it is understood that in other embodiments, the depth of the first body region 6 may be less than or equal to the height of the upper portions of the first gate region 3-1 and the second gate region 3-2, so as to form a channel in the first body region 6. The first gate region 3-1 and the second gate region 3-2 are isolated from the first body region 6 and the pillar region (9-1 and 9-2) by the gate region dielectric layer 2, respectively.

[0021] The MOSFET device 100 further includes a first source region 7-1 and a second source region 7-2, wherein the first source region 7-1 is formed at the top of the first body region 6 adjacent to the sidewall of the first trench, and the second source region 7-2 is formed at the top of the first body region 6 adjacent to the sidewall of the second trench. A body contact region 8 is also provided between the first source region 7-1 and the second source region 7-2, and is also formed at the top of the first body region 6.

[0022] The MOSFET device 100 also includes a source metal 1, which covers the top surfaces of the first gate region 3-1, the second gate region 3-2, the first source region 7-1, and the second source region 7-2. In addition, the source metal 1 will extend downward to fill part of the space of the first trench and the second trench. In one embodiment, the source metal 1 extends downward to the bottom of the first trench to contact the first column region 9-1, and extends downward to the bottom of the second trench to contact the second column region 9-2, and covers the side walls of the first gate region 3-1 and the side walls of the second gate region 3-2 respectively, wherein the source metal 1 is isolated from the first gate region 3-1 and the second gate region 3-2 respectively by the interlayer dielectric layer 4. The MOSFET device 100 also includes a drain region and a drain metal 13, and the first conductive type substrate 12 is thinned as a drain region, and the drain metal 13 covers the drain region.

[0023] At the top of the MOSFET device 100, the first split gate 5-1, the interlayer dielectric layer 4, the epitaxial layer 11 and the second split gate 5-2 form a capacitive depletion region. During forward withstand voltage, the first split gate 5-1 and the second split gate 5-2 at the top of the MOSFET device 100 assist in depleting the positively charged ionized donor charge in the nearby N-type epitaxial layer; the super junction structure formed by the P-type column region and the N-type column region introduced in the middle and lower part of the MOSFET device 100 can introduce a lateral electric field to assist in depleting the positively charged ionized donor charge in the N-type column. The above structure makes the electric field change from a normal triangular distribution to a nearly rectangular distribution, thereby increasing the breakdown voltage BV, and ensuring that the thickness of the epitaxial layer of the inventive structure can be made thinner and the doping concentration of the epitaxial layer can be made higher under the premise that the breakdown voltage does not decay, thereby reducing the on-resistance of the MOSFET device 100, improving the trade-off relationship between the on-resistance and the breakdown voltage, and this structure reduces the gate charge, thereby also reducing the quality factor FOM value, reducing the conduction loss and switching loss of the device, and improving the system efficiency.

[0024] Figure 2 A cross-sectional schematic diagram of another MOSFET device 200 provided in an embodiment of the present application, compared with the MOSFET device 100, the MOSFET device 200 further includes a second body region 15-1, a third body region 15-2, a third source region 14-1 and a fourth source region 14-2.

[0025] The second body region 15-1 is formed at the top of the first column region 9-1 corresponding to the bottom of the first gate region 3-1; the third body region 15-2 is formed at the top of the second column region 9-2 corresponding to the bottom of the second gate region 3-2; the third source region 14-1 is formed at the top of the first column region 9-1 adjacent to the second body region 15-1; the fourth source region 14-2 is formed at the top of the second column region 9-2 adjacent to the third body region 15-2.

[0026] Although the conductivity type and doping concentration of the third source region 14 - 1 and the fourth source region 14 - 2 , as well as the substrate 12 are all represented by N+, in one embodiment, the doping concentration of the third source region 14 - 1 and the fourth source region 14 - 2 is higher than the doping concentration of the substrate 12 .

[0027] In this embodiment, the source metal 1 extends downward to the bottom of the first trench and contacts the third source region 14-1, and extends downward to the bottom of the second trench and contacts the fourth source region 14-2, and covers the side walls of the first gate region 3-1 and the second gate region 3-2 respectively, wherein the source metal 1 is isolated from the first gate region 3-1 and the second gate region 3-2 by the interlayer dielectric layer 4.

[0028] In the MOSFET device 200, a lateral channel may be added in each of the second body region 15-1 and the third body region 15-2 to form a four-channel structure, thereby increasing the channel density of the device and further reducing the on-resistance of the device.

[0029] Figure 3 A cross-sectional schematic diagram of another MOSFET device 300 provided in an embodiment of the present application is shown in FIG. Figure 3 Compared with the MOSFET device 200, the MOSFET device 300 further includes a third trench, which extends downward from the top surface of the first body region 6 into the epitaxial layer and reaches the top of the N-type column region 10. The third split gate 5-3 is formed in the third trench, and the interlayer dielectric layer 4 isolates the third split gate 5-3 and the first body region 6 from the epitaxial layer.

[0030] In the above structure, the third split gate 5-3, the interlayer dielectric layer 4, the epitaxial layer 11, the first split gate 5-1 and the second split gate 5-2 form a capacitive depletion region, further optimizing the electric field distribution, increasing the doping concentration of the epitaxial layer 11, thereby further reducing the on-resistance of the MOSFET device 600, reducing the conduction loss and switching loss of the device, and improving the system efficiency. Similar to the first split gate 5-1 and the second split gate 5-2, in one embodiment, the third split gate includes doped polysilicon.

[0031] In one embodiment, the thickness of the gate region dielectric layer is less than the thickness of the interlayer dielectric layer. Wherein, the gate region dielectric layer 2 includes: a dielectric layer between the first gate region 3-1 and the first body region 6, a dielectric layer between the second gate region 3-2 and the first body region 6, a dielectric layer between the first gate region 3-1 and the P-type column region, and a dielectric layer between the second gate region 3-2 and the P-type column region. The interlayer dielectric layer 4 specifically includes: an interlayer dielectric layer between the first gate region 3-1 and the source metal, an interlayer dielectric layer between the second gate region 3-2 and the source metal, an interlayer dielectric layer grown between the first gate region 3-1 and the first split gate 5-1, and an interlayer dielectric layer grown between the second gate region 3-2 and the first split gate 5-2. In one embodiment, the thicknesses of the above-mentioned interlayer dielectric layers may not be equal.

[0032] Further, in one embodiment, in the above Figure 1-Figure 3In the illustrated embodiment, the thickness of the interlayer dielectric layer on both lateral sides of the first split gate 5-1 gradually decreases from top to bottom, and the thickness of the interlayer dielectric layer on both lateral sides of the second split gate 5-2 gradually decreases from top to bottom. Preferably, the thickness of the interlayer dielectric layer on both lateral sides of the first split gate 5-1 has a step-like thinning characteristic from top to bottom, and the thickness of the interlayer dielectric layer on both lateral sides of the second split gate 5-2 has a step-like thinning characteristic from top to bottom. In another embodiment, the thickness of the interlayer dielectric layer on both lateral sides of the third split gate 5-3 also gradually decreases from top to bottom. Preferably, the thickness of the interlayer dielectric layer on both lateral sides of the third split gate 5-3 has a step-like thinning characteristic from top to bottom. See Figure 4 A MOSFET device 400 is shown in the embodiment.

[0033] It should be noted that in Figures 1 to 4 In the illustrated MOSFET devices 100-400, the lower super junction region illustrates two P-type column regions and one N-type column region forming two PN junctions. In other embodiments, the device may include more P-type column regions and N-type column regions to form more PN junctions.

[0034] The MOSFET device provided in the embodiment of the present application combines the advantages of the split gate and the super structure, forms a depletion region in the upper half of the device, optimizes the electric field distribution, introduces P columns (such as 9-1 and 9-2) and N columns (10) in the middle and lower parts of the device to form a super junction structure, thereby increasing the device breakdown voltage, reducing the specific on-resistance, and improving the trade-off relationship between the specific on-resistance and the breakdown voltage. In addition, two additional channels are introduced in the middle of the left and right sides of the device to form a four-channel structure, thereby increasing the channel density of the device and further reducing the specific on-resistance of the device.

[0035] Based on the above device embodiment, the embodiment of the present application also provides a method for preparing a MOSFET device, which specifically includes the following steps one to nine.

[0036] Step 1: growing a first epitaxial layer of a first conductivity type on a substrate. Figure 5A In the process step diagram, the conductivity type of the substrate 12 is indicated as N, the conductivity type of the first epitaxial layer 11 is also indicated as N, and the doping concentration N+ of the substrate 12 is higher than the doping concentration N of the first epitaxial layer 11 .

[0037] Step 2: Forming a column region of the second conductivity type in the first epitaxial layer. In one embodiment, a trench can be dug from top to bottom in the first epitaxial layer of the first conductivity type (N type), and P-type column regions 9-1 and 9-2 can be grown in the trench. In this case, step 2 includes the following steps: Figure 5B and Figure 5CIn yet another embodiment, the P-type column regions 9-1 and 9-2 can be formed on the first epitaxial layer by high-energy and high-dose P-type ion implantation.

[0038] exist Figure 5B In the process steps shown, a trench is dug from the top surface of the first epitaxial layer 11 downward to form the trench 17. In one embodiment, the openings of the first trench and the second trench can be set by forming a trench mask pattern.

[0039] exist Figure 5C In the process steps shown, a column region having a second conductivity type (such as a first column region 9-1 and a second column region 9-2) is grown in the trench 17, and the conductivity type and doping concentration of the first column region 9-1 and the second column region 9-2 can be represented by P+.

[0040] In one embodiment, the first column region 9-1 and the second column region 9-2 are separated by the first epitaxial layer 11 of the first conductivity type in the middle. In some embodiments, N ions may be further implanted into the first epitaxial layer 11 between the two trenches 17 to increase the doping concentration of the epitaxial layer, thereby forming a third column region 10 of the first conductivity type (N type), the doping concentration of which is represented by N+.

[0041] In a preferred embodiment, after forming the column region of the second conductivity type, step 2 further includes: performing ion implantation on the top of the column region of the second conductivity type to form a second body region, a third body region, a third source region and a fourth source region. Figure 5D As shown in FIG. 1 , the tops of the two P-type column regions 9 - 1 and 9 - 2 are respectively formed into a body region (including 15 - 1 and 15 - 2 ) and a source region ( 14 - 1 and 14 - 2 ) by ion implantation.

[0042] Step 3: epitaxially grow a second epitaxial layer 11 having the first conductivity type on the pillar region and the top of the first epitaxial layer. In one embodiment, the doping concentration of the second epitaxial layer 11 is lower than the doping concentration of the first epitaxial layer; in another embodiment, the doping concentration of the second epitaxial layer 11 may be the same as the doping concentration of the first epitaxial layer. Figure 5E In the process steps shown, a second epitaxial layer 11 having a first conductivity type (N) is epitaxially grown on the two column regions 9 - 1 and 9 - 2 and on top of the first epitaxial layer 11 .

[0043] Step 4: Dig trenches from top to bottom on the left and right sides of the second epitaxial layer to the top surface of the pillar region. Fig. 5F In the process steps shown, trenches are dug from top to bottom on the left and right sides of the second epitaxial layer 11 until they reach the top surfaces of the column regions 9 - 1 and 9 - 2 , thereby obtaining two trenches 18 .

[0044] Step 5: After forming a dielectric layer at the bottom and sidewalls of the trenches on both sides, fill them with polysilicon. Figure 5GIn the process steps shown, a dielectric layer 19 is deposited at the bottom and sidewalls of the trenches 18 on both sides and then filled with polysilicon 20. In one embodiment, the dielectric layer 19 can be formed by deposition or thermal growth at the bottom and sidewalls of the trenches 18 on both sides. The dielectric layer laterally limits the size of the polysilicon region subsequently formed in the trenches 18 on both sides and prevents doping ions from laterally diffusing from the trenches.

[0045] Step 6: Etch the polysilicon to form a first split gate and a second split gate. Figure 5H In the process steps shown, after the grooves 18 on both sides are filled with polysilicon 20, the polysilicon 20 is etched and its top surface is planarized (for example, using a chemical mechanical polishing (CMP) process, etc.) to form an interlayer dielectric layer 4, a first split gate 5-1 and a second split gate 5-2.

[0046] Step 7: After forming a dielectric layer in the trenches on both sides for the second time, fill it with polysilicon. The dielectric layer deposited here includes interlayer dielectric and gate dielectric. Fig.5I In the process steps shown, a dielectric layer 21 is deposited for the second time in the trenches on both sides and polysilicon 22 is filled.

[0047] Step 8: Etch the polysilicon to form a first gate region and a second gate region. Figure 5J In the process steps shown, the polysilicon 22 is etched to form the first gate region 3-1 and the second gate region 3-2. In one embodiment, after step eight, the second epitaxial layer 11 may be ion implanted to form the first body region 6, the body contact region 8, the first source region 7-1 and the second source region 7-2.

[0048] Step 9: After forming the dielectric layer for the third time on the top and sidewalls of the first gate region and the second gate region, grow the source metal on the dielectric layer and in the grooves on both sides. Figure 5J and 5K The process steps are shown in Figure 1. Figure 5J As shown, after a dielectric layer 23 is deposited for the third time on the top and sidewalls of the first gate region 3-1 and the second gate region 3-2, etching is performed to obtain two trenches 24. Figure 5K As shown, source metal is deposited on the entire dielectric layer 23 and in the trenches 24 on both sides to obtain source metal 1. In other embodiments, metal is deposited on the other side of the device to form a drain metal layer 13.

[0049] The method provided in the embodiment of the present application has the same implementation principle and technical effects as those in the aforementioned device embodiment. For the sake of brief description, for matters not mentioned in the embodiment of the method, reference may be made to the corresponding contents in the aforementioned device embodiment.

[0050] In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present application. In addition, the terms "first", "second", and "third" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance.

[0051] Finally, it should be noted that the above-described embodiments are only specific implementation methods of the present application, which are used to illustrate the technical solutions of the present application, rather than to limit them. The protection scope of the present application is not limited thereto. Although the present application is described in detail with reference to the above-described embodiments, ordinary technicians in the field should understand that any technician familiar with the technical field can still modify the technical solutions recorded in the above-described embodiments within the technical scope disclosed in the present application, or can easily think of changes, or make equivalent replacements for some of the technical features therein; and these modifications, changes or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application, and should be included in the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. A MOSFET device, characterized in that: The MOSFET device comprises: a substrate having a first conductivity type; an epitaxial layer having a first conductivity type and formed on the substrate; A plurality of column regions of the second conductivity type are formed in the epitaxial layer, and the plurality of column regions of the second conductivity type and the epitaxial layer are laterally staggered; A first trench and a second trench, the first trench and the second trench extending downward from the top surfaces of the left and right sides of the epitaxial layer to the top of the pillar region; Among them, the first gate region and the first split gate are formed in the first trench; the second gate region and the second split gate are symmetrically formed in the second trench with the first gate region and the first split gate respectively; the first gate region and the second gate region include an upper part and a lower part, the lateral width of the upper part is greater than the lateral width of the lower part, and the upper part and the lower part form an inverted L-shaped structure; the first gate region covers the first split gate, and the first gate region and the first split gate are isolated by an interlayer dielectric layer; the second gate region covers the second split gate, and the second gate region and the second split gate are isolated by an interlayer dielectric layer.

2. The MOSFET device according to claim 1, characterized in that Further including: A first body region is formed in the epitaxial layer between the first trench and the second trench, the depth of the first body region is less than or equal to the height of the upper parts of the first gate region and the second gate region, wherein the first gate region and the second gate region are respectively isolated from the first body region and the column region by a gate region dielectric layer; A first source region and a second source region, wherein the first source region is formed on a top portion of the first body region adjacent to a sidewall of the first trench, and the second source region is formed on a top portion of the first body region adjacent to a sidewall of the second trench.

3. The MOSFET device according to claim 2, characterized in that: Further including: A second body region formed at the top of the column region corresponding to the bottom of the first gate region; A third body region is formed at the top of the column region corresponding to the bottom of the second gate region; a third source region formed on top of a pillar region adjacent to the second body region; A fourth source region is formed on the top of the pillar region adjacent to the third body region.

4. The MOSFET device according to claim 3, characterized in that: Further including: A source metal covers the top surfaces of the first gate region, the second gate region, the first source region, and the second source region, and extends downward to the bottom of the first trench to contact the third source region, and extends downward to the bottom of the second trench to contact the fourth source region, and laterally covers the side walls of the first gate region and the side walls of the second gate region, wherein the source metal is isolated from the first gate region and the second gate region by an interlayer dielectric layer.

5. The MOSFET device according to claim 2, characterized in that: Further including: A third trench extends downward from the top surface of the first body region into the epitaxial layer and reaches the top of the pillar region; The third split gate is formed in the third trench, and the interlayer dielectric layer isolates the third split gate from the first body region and the epitaxial layer respectively.

6. The MOSFET device according to claim 2, characterized in that: The thickness of the gate dielectric layer is smaller than the thickness of the interlayer dielectric layer.

7. The MOSFET device according to claim 1, characterized in that: The thickness of the interlayer dielectric layer on both sides of the first split gate gradually decreases from top to bottom, and the thickness of the interlayer dielectric layer on both sides of the second split gate gradually decreases from top to bottom.

8. The MOSFET device according to claim 5, characterized in that: The thickness of the interlayer dielectric layer on both sides of the third split gate gradually decreases from top to bottom.

9. A method for preparing a MOSFET device, characterized in that: The method comprises: Step 1: growing a first epitaxial layer having a first conductivity type on a substrate; Step 2: forming a column region having a second conductivity type in the first epitaxial layer; Step 3: epitaxially growing a second epitaxial layer having a first conductivity type on the pillar region and on top of the first epitaxial layer; Step 4: digging trenches from top to bottom on the left and right sides of the second epitaxial layer to the top surface of the pillar region; Step 5: After forming a dielectric layer at the bottom and sidewalls of the trenches on both sides, polysilicon is filled; Step 6: Etching the polysilicon to form a first split gate and a second split gate; Step 7: forming a dielectric layer in the trenches on both sides for the second time and then filling with polysilicon; Step 8: etching the polysilicon to form a first gate region and a second gate region; Step 9: After forming a dielectric layer for the third time on the top and sidewalls of the first gate region and the second gate region, a source metal is formed on the dielectric layer and in the trenches on both sides.

10. The method for preparing a MOSFET device according to claim 9, characterized in that: The method further comprises: Between the above steps 2 and 3, ion implantation is performed on the top of the column region to form a body region and a source region, wherein the source metal is in electrical contact with the source region.

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