LDMOS device and preparation method thereof

Abstract

According to the LDMOS device and the preparation method thereof provided by the invention, the first doped region and the second doped region in the drift region respectively form the first depletion region and the second depletion region with the drift region, so that the voltage resistance of the LDMOS device is improved. On the basis, the first doped regions and the second doped regions are sequentially arranged at intervals in the direction perpendicular to the surface of the substrate, and the first distance between the first doped regions and the surface of the substrate is smaller than the second distance between the second doped regions and the surface of the substrate; the first ion doping concentration of the first doped region is larger than the second ion doping concentration of the second doped region, the thickness of the first doped region is smaller than the thickness of the second doped region, the positions and the ion doping concentrations of the doped regions are reasonably set, so that the first depletion region and the second depletion region are far away from a channel, and a current channel is reserved; and the total area of the first depletion region and the second depletion region of the LDMOS device is increased, so that the LDMOS device is relatively low in on resistance and relatively good in integration level while the voltage resistance of the LDMOS device is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to an LDMOS device and a preparation method thereof. Background Art

[0002] Lateral Diffused Medal Oxide Semiconductor (LDMOS) is widely used as a power MOS tube because it is more compatible with CMOS process.

[0003] As the performance requirements for LDMOS devices increase, LDMOS devices are required to have higher voltage resistance and lower on-resistance.

[0004] In order to improve the voltage resistance performance of the LDMOS device, one existing method is to reduce the concentration of the drift region inside the LDMOS device. This method has the problem of increasing the on-resistance of the LDMOS device. Another method is to increase the width of the LDMOS device to increase the N-type drift region of the LDMOS device. This approach will lead to an increase in the area of ​​the LDMOS device, which is not conducive to integration.

[0005] Therefore, solving the technical problem that although the existing LDMOS device has improved the withstand voltage performance, it leads to high on-resistance and low integration of the LDMOS device has become a technical problem that needs to be solved urgently. Summary of the invention

[0006] The present invention provides an LDMOS device and a preparation method thereof, aiming to improve the voltage resistance performance of the LDMOS while making the LDMOS have lower on-resistance and better integration.

[0007] According to a first aspect of the present invention, the present invention provides an LDMOS device, comprising: a substrate, and a gate structure located on a surface of the substrate;

[0008] The substrate includes a source region, a drain region, and a drift region, wherein the source region and the drift region are respectively located on both sides of the gate structure, and the drift region also extends to a portion below the gate structure, and the drain region is located in the drift region; the drift region includes a first doping region and a second doping region, wherein the first doping region and the second doping region are located between the drain region and the source region, and the first doping region and the second doping region are arranged in sequence and spaced apart in a direction perpendicular to the surface of the substrate, a first distance between an upper surface of the first doping region and a surface of the substrate is smaller than a second distance between an upper surface of the second doping region and a surface of the substrate, a thickness of the first doping region is smaller than a thickness of the second doping region, and a first ion doping concentration of the first doping region is greater than a second ion doping concentration of the second doping region.

[0009] Optionally, a ratio of the thickness of the drift region to the first spacing is in a range of 11.0 to 11.4;

[0010] The ratio of the second spacing to the first spacing is in a range of 4.0 to 4.4.

[0011] Optionally, a ratio of a thickness of the drift region to a thickness of the first doping region is in a range of 11.0 to 11.4;

[0012] The ratio of the thickness of the second doping region to the thickness of the first doping region is in a range of 1.9 to 2.1.

[0013] Optionally, a ratio of the first ion doping concentration to the second ion doping concentration ranges from 1.9 to 2.1.

[0014] Optionally, along a direction from the source region to the drain region, the first doped region has a first length, the drift region has a second length, and a ratio of the second length to the first length is in a range of 1.4 to 1.6.

[0015] Optionally, the method further includes: a field oxide layer, wherein the field oxide layer is located between the gate structure and the drain region above the drift region.

[0016] Optionally, the number of the second doping region is 1.

[0017] Optionally, the number of the second doping regions is more than 2, and the more than 2 second doping regions are arranged in sequence and spaced apart in a direction perpendicular to the surface of the substrate.

[0018] Optionally, the LDMOS device is an N-channel LDMOS device, and the doping ions in the first doping region and the second doping region are both P-type doping ions.

[0019] According to a second aspect of the present invention, a method for preparing an LDMOS device is provided, the method comprising:

[0020] providing a substrate and forming a drift region in the substrate;

[0021] A first doping region and a second doping region are formed in the drift region and are arranged in sequence and spaced apart in a direction perpendicular to the surface of the substrate; wherein a first distance between the upper surface of the first doping region and the surface of the substrate is smaller than a second distance between the upper surface of the second doping region and the surface of the substrate, a thickness of the first doping region is smaller than a thickness of the second doping region, and a first ion doping concentration of the first doping region is greater than a second ion doping concentration of the second doping region;

[0022] forming a source region and a drain region in the substrate, wherein the drain region is located in the drift region, and the source region and the drain region are located on both sides of the first doped region; and

[0023] A gate structure is formed on the surface of the substrate, and the gate structure is located between the source region and the drain region.

[0024] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0025] The present invention provides an LDMOS device and a preparation method thereof. Since the first doping region and the second doping region in the drift region respectively form the first depletion region and the second depletion region with the drift region, the withstand voltage performance of the LDMOS device is improved. On this basis, the first doping region and the second doping region are sequentially arranged in a direction perpendicular to the surface of the substrate, the first spacing between the first doping region and the surface of the substrate is smaller than the second spacing between the second doping region and the surface of the substrate, the first ion doping concentration of the first doping region is greater than the second ion doping concentration of the second doping region, the thickness of the first doping region is smaller than the thickness of the second doping region, etc., the position of the doping region and its ion doping concentration are reasonably set, so that the first depletion region and the second depletion region are far away from the channel, the current channel is reserved, and the total area of ​​the first depletion region and the second depletion region of the LDMOS device is increased, so that the withstand voltage performance of the LDMOS device is improved, and the LDMOS device also takes into account low on-resistance and good integration. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0027] Figure 1 A schematic diagram of the structure of an LDMOS device in one embodiment of the present invention;

[0028] Figure 2 A schematic diagram of the structure of an LDMOS device in another embodiment of the present invention;

[0029] Figure 3 A schematic diagram of the structure of an LDMOS device in another embodiment of the present invention;

[0030] Figure 4 It is a schematic diagram of the simulation waveform of the withstand voltage performance and driving current of the undoped region in the drift region;

[0031] Figure 5A schematic diagram of a simulation waveform showing the relationship between the withstand voltage performance of the drift region containing the first doping region and the driving current;

[0032] Figure 6 A schematic diagram of simulation waveform comparison of the relationship between the withstand voltage performance and the driving current of the drift region containing the first doping region and the relationship between the withstand voltage performance and the driving current of the drift region containing the first doping region and the second doping region;

[0033] Figure 7 to Figure 10 It is a schematic structural diagram corresponding to each step of the method for preparing an LDMOS device in an embodiment of the present invention. DETAILED DESCRIPTION

[0034] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0035] The terms "first", "second", "third", "fourth", etc. (if any) in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0036] The technical solution of the present invention is described in detail with specific embodiments below. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described in detail in some embodiments.

[0037] As described in the background art, the present invention aims to solve the technical problem of improving the withstand voltage performance of the LDMOS device while making the LDMOS device have a lower on-resistance and a better integration.

[0038] In the prior art, in order to improve the voltage resistance performance of the LDMOS device, one implementation method is to reduce the concentration of the drift region inside the LDMOS device. This method has the technical problem of increasing the on-resistance of the LDMOS device. Another implementation method is to increase the width of the LDMOS device to increase the drift region of the LDMOS device. This method will cause the area of ​​the LDMOS device to increase, which is not conducive to integration.

[0039] In view of this, the present invention provides an LDMOS device, because the first doping region and the second doping region in the drift region respectively form the first depletion region and the second depletion region with the drift region, thereby improving the withstand voltage performance of the LDMOS device. On this basis, the first doping region and the second doping region are arranged in sequence in a direction perpendicular to the surface of the substrate, the first spacing between the first doping region and the surface of the substrate is smaller than the second spacing between the second doping region and the surface of the substrate, the first ion doping concentration of the first doping region is greater than the second ion doping concentration of the second doping region, the thickness of the first doping region is smaller than the thickness of the second doping region, etc., the position of the doping region and its ion doping concentration are reasonably set, so that the first depletion region and the second depletion region are far away from the channel, the current channel is reserved, and the total area of ​​the first depletion region and the second depletion region of the LDMOS device is increased, so that the withstand voltage performance of the LDMOS device is improved, and the LDMOS device also takes into account lower on-resistance and better integration.

[0040] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and understandable, specific embodiments of the present invention are described in detail below in conjunction with the accompanying drawings.

[0041] Please refer to Figure 1 In one embodiment of the present invention, an LDMOS device is provided, which may include: a substrate 100 , and a gate structure 130 located on the surface of the substrate 100 .

[0042] In this embodiment, the substrate 100 may include a source region 121, a drain region 122, and a drift region 110. The source region 121 and the drift region 110 are respectively located on both sides of the gate structure 130. The drift region 110 also extends to a portion below the gate structure 130. The drain region 122 is located in the drift region 110. The drift region 110 has a first doping region 111 and a second doping region 112. The first doping region 111 and the second doping region 112 are also located between the drain region 122 and the source region. 121, the first doping region 111 and the second doping region 112 are arranged in sequence in a direction perpendicular to the surface of the substrate 100, a first distance D1 between the first doping region 111 and the surface of the substrate 100 is smaller than a second distance D2 between the second doping region 112 and the surface of the substrate 100, a thickness H1 of the first doping region 111 is smaller than a thickness H2 of the second doping region 112, and a first ion doping concentration of the first doping region 111 is greater than a second ion doping concentration of the second doping region 112.

[0043] As an example, the substrate 100 may be Si or SOI (Silicon On Insulator in English and Silicon on Insulator in Chinese).

[0044] As an implementation manner, the LDMOS device may be an N-channel LDMOS device, and the doping ions in the first doping region 111 and the second doping region 112 are both P-type doping ions.

[0045] Of course, it should be understood that the present invention is not limited thereto, and the LDMOS device may also be a P-channel LDMOS device. In this case, the doping ions in the first doping region 111 and the second doping region 112 are both N-type doping ions.

[0046] In the above embodiment, since the first doping region 111 and the second doping region 112 in the drift region 110 form the first depletion region and the second depletion region with the drift region 110 respectively, the withstand voltage performance of the LDMOS device can be improved. On this basis, by sequentially arranging the first doping region 111 and the second doping region 112 in a direction perpendicular to the surface of the substrate 100, the first ion doping concentration of the first doping region 111 close to the surface of the substrate 100 is greater than the second ion doping concentration of the second doping region 112 far from the surface of the substrate 100, and the thickness of the first doping region 111 is less than the thickness of the second doping region 112, so that the width of the first depletion region corresponding to the first doping region 111 is narrower than the width of the second depletion region corresponding to the second doping region 112, that is, the on-resistance close to the device surface is lower than the on-resistance far from the device surface, and a current channel is reserved on the device surface, which can improve the lateral drive current density on the surface of the LDMOS device, thereby achieving the improvement of the withstand voltage performance of the LDMOS device while making the LDMOS device have a low on-resistance and a good integration.

[0047] In another specific embodiment, please refer to Figure 2 The LDMOS device may further include: a field oxide layer 140 , wherein the field oxide layer 140 is located above the drift region 110 and between the gate structure 130 and the drain region 122 .

[0048] In this embodiment, the field oxide layer 140 can electrically isolate the drift region 110 from other regions to prevent current from flowing along a path that should not flow. At the same time, the field oxide layer 140 can also provide a protective layer for the surface of the substrate 100 to prevent the surface of the substrate 100 from being damaged in subsequent process steps.

[0049] In a specific embodiment, the number of the second doping region 112 may be one.

[0050] Taking the case where the number of the second doping region 112 is one as an example, the specific configuration of the LDMOS device is described below.

[0051] As an embodiment, the ratio of the thickness H3 of the drift region 110 to the first distance D1 is in a range of 11.0 to 11.4.

[0052] The ratio of the second distance D2 to the first distance D1 is in a range of 4.0 to 4.4.

[0053] If the ratio of the thickness H3 of the drift region 110 to the first spacing D1 is too large, and the first spacing D1 is small, the first depletion region formed by the first doping region 111 and the drift region 110 seriously blocks the driving current path, causing the driving current to drop sharply (i.e., the on-resistance increases too much). If the ratio of the thickness H3 of the drift region 110 to the first spacing D1 is too small, and the first spacing D1 is large, the first depletion region is too far away from the steep electric field of the LDMOS device, making it difficult to significantly improve the withstand voltage performance of the LDMOS device.

[0054] In this embodiment, by setting the ratio range of the thickness of the drift region 110 to the first spacing D1 to 11.0-11.4, the voltage resistance performance of the LDMOS device can be effectively improved without reducing the driving current of the LDMOS device too much (that is, the on-resistance of the LDMOS device will not be increased too much).

[0055] On this basis, the ratio of the second spacing D2 to the first spacing D1 is in the range of 4.0 to 4.4, so that the second depletion region formed by the second doping region 112 and the drift region 110 can be far away from the current path and will not affect the driving current (i.e., will not affect the on-resistance), and can also improve the withstand voltage performance of the LDMOS device.

[0056] As an example, when the thickness of the drift region 110 is in the range of 11.3um to 11.8um, the first distance D1 between the first doping region 111 and the surface of the substrate 100 is set to be in the range of 1.0um to 1.4um, and the second distance D2 between the upper surface of the second doping region 112 and the surface of the substrate 100 is set to be in the range of 5.3um to 5.7um.

[0057] Of course, it should be understood that the present invention is not limited thereto.

[0058] In this embodiment, for the LDMOS device in which the thickness of the drift region 110 ranges from 11.3um to 11.8um, if the first spacing D1 is too close, the first depletion region formed by the first doping region 111 and the drift region 110 seriously blocks the current path, causing the drive current to drop sharply (i.e., the on-resistance increases too much), and if the first spacing D1 is too far, the first depletion region is far away from the steep electric field of the LDMOS device, making it difficult to significantly improve the withstand voltage performance of the LDMOS device. Therefore, setting the first spacing D1 between the first doping region 111 and the surface of the substrate 100 in the range of 1.0um to 1.4um can effectively improve the withstand voltage performance of the device without reducing the drive current of the device too much (i.e., the on-resistance of the device will not increase too much).

[0059] On this basis, the second distance D2 between the upper surface of the second doping region 112 and the surface of the substrate 100 is set to a range of 5.3um to 5.7um, so that the second depletion region formed by the second doping region 112 and the drift region 110 is away from the current path (i.e., where the electric field is steeper). The thickness of the second doping region 112 and the second ion doping concentration can be set larger, so that the area of ​​the second depletion region is larger, which can play a role in reducing the withstand voltage of the LDMOS device.

[0060] As a specific implementation manner, the ratio of the thickness H3 of the drift region 110 to the thickness H1 of the first doping region 111 is in a range of 11.0 to 11.4.

[0061] The ratio of the thickness H2 of the second doping region 112 to the thickness H1 of the first doping region 111 is in a range of 1.9 to 2.1.

[0062] The ratio of the thickness H3 of the drift region 110 to the thickness of the first doping region 111 is set in the range of 11.0 to 11.3, so that the first depletion region can significantly improve the withstand voltage performance of the LDMOS device without causing excessive reduction in on-resistance. On this basis, the ratio of the thickness of the second doping region 112 to the thickness of the first doping region 111 is set in the range of 1.9 to 2.1, so that the withstand voltage performance of the LDMOS device can be improved through the second depletion region.

[0063] For example, when the thickness H3 of the drift region 110 is in the range of 11.3um to 11.8um, the thickness H1 of the first doping region 111 is set in the range of 0.9um to 1.1um, and the thickness H2 of the second doping region 112 is set in the range of 1.8um to 2.2um.

[0064] In this embodiment, when the thickness H3 of the drift region 110 ranges from 11.3um to 11.8um, if the thickness H1 of the first doping region 111 is too small, the area of ​​the first depletion region is large, and the first depletion region will seriously hinder the current flow of the current path, causing the drive current to decrease sharply (i.e., the on-resistance increases greatly). If the thickness of the first doping region 111 is too small, the area of ​​the first depletion region is small, and the first depletion region is far away from the steep electric field of the LDMOS device, making it difficult to significantly improve the withstand voltage performance of the LDMOS device. The thickness H1 of the first doping region 111 is set to range from 0.9um to 1.1um. While the first depletion region can significantly improve the withstand voltage performance of the LDMOS device, it will not cause the on-resistance to decrease too much.

[0065] On this basis, the thickness H2 of the second doping region 112 is set to range from 1.8um to 2.2um, so that the second depletion region formed by the second doping region 112 and the drift region 110 is far away from the current path. Therefore, the thickness H2 of the second doping region 112 can be set to a larger range. Setting the thickness H2 of the second doping region 112 to range from 1.8um to 2.2um can significantly improve the voltage resistance performance of the LDMOS device.

[0066] As a specific implementation, the ratio of the first ion doping concentration to the second ion doping concentration ranges from 1.9 to 2.1.

[0067] As an example, the first ion doping concentration range of the first doping region 111 is set to 2.8×10 12 cm -2 ~3.2×10 12 cm -2 The second ion doping concentration of the second doping region 112 is in the range of 1.4×10 12 cm -2 ~1.6×10 12 cm -2 .

[0068] If the first ion doping concentration is too high, the first depletion region will be small in area, and it will be difficult for the first depletion region to improve the withstand voltage performance of the LDMOS device. If the first ion doping concentration is too low, the first depletion region will be large in area, and the first depletion region will seriously hinder the current flow in the current path, causing the drive current to decrease sharply (i.e., the on-resistance increases greatly). Therefore, the first ion doping concentration range of the first doping region 111 is set to 2.8×10 12 cm -2 ~3.2×10 12 cm -2 , that is, the withstand voltage performance of the LDMOS device can be effectively improved without reducing the driving current of the LDMOS device too much (that is, the on-resistance of the LDMOS device will not be increased too much).

[0069] On this basis, in order to make the second depletion region formed by the second doping region 112 and the drift region 110 away from the current path, the range of the second ion doping concentration can be set to be smaller, and the range of the second ion doping concentration is set to 1.4×10 12 cm -2 ~1.6×10 12 cm -2 , which can significantly improve the voltage resistance performance of LDMOS devices.

[0070] In some specific embodiments, along the direction from the source region 121 to the drain region 122 , the first doped region 111 has a first length L1 , the drift region 110 has a second length L2 , and a ratio of the second length L2 to the first length L1 ranges from 1.4 to 1.6.

[0071] In a specific embodiment, along the direction from the source region 121 to the drain region 122 , the first doped region 111 has a first boundary (not shown) and a second boundary (not shown) opposite to each other, the first boundary is close to the source region 121 , and the second boundary is close to the drain region 122 .

[0072] In this embodiment, there is a first distance between the first boundary and a third boundary (not shown) of the drift region 110 close to the source region 121 , and there is a second distance between the second boundary and the drain region 122 . Both the first distance and the second distance are greater than 0.

[0073] In the above embodiment, by setting the length ratio of the drift region 110 to the first doping region 111 in the range of 1.4 to 1.6, the first length L1 of the first doping region 111 is longer, and thus a longer first depletion region can be obtained, which is beneficial to improving the voltage resistance performance of the LDMOS device. At the same time, the length of the drift region 110 is greater than the length of the first doping region 111, ensuring that the first doping region 111 is located in the drift region 110 and between the source region 121 and the drain region 122, and there can be a second distance between the first doping region 111 and the drain region 122, which can avoid the risk of the first doping region 111 being too close to the drain region 122.

[0074] In one embodiment, along the direction from the source region 121 to the drain region 122 , the second doping region 112 and the first doping region 111 have the same first length L1 .

[0075] In another embodiment, along the direction from the source region 121 to the drain region 122 , the length of the second doping region 112 may be different from that of the first doping region 111 , for example, the length of the second doping region 112 may be longer or shorter than that of the first doping region 111 .

[0076] In another embodiment, please refer to Figure 3 The number of the second doping regions 112 is greater than or equal to 2, and the greater than or equal to 2 second doping regions 112 are arranged in sequence and spaced apart in a direction perpendicular to the surface of the substrate 100.

[0077] As an example, when the thickness H3 of the drift region 110 is in the range of 11.3um to 11.8um, the thickness H2 of each of the second doping regions 112 of the present invention is greater than the thickness H1 of the first doping region 111, and the thickness H2 of each of the second doping regions 112 may be the same or different, which is not limited in the present invention. The second ion doping concentration of each of the second doping regions 112 is greater than the first ion doping concentration of the first doping region 111, and the second ion doping concentration of each of the second doping regions 112 may be the same or different, which is not limited in the present invention.

[0078] In this embodiment, the spacing between each second doping region 112 can be set by a person skilled in the art according to the requirements, and the present invention does not impose any specific restrictions here. Among them, each second doping region 112 only needs to meet the following requirements: the distance between the upper surface of the second doping region 112 with the smallest second spacing D2 from the surface of the substrate 100 and the surface of the substrate 100 is set between 5.3um and 5.7um, and the distance between the lower surface of the second doping region 112 with the largest second spacing D2 from the surface of the substrate 100 and the surface of the substrate 100 is set between 5.3um and 11.0um.

[0079] In the above embodiment, by ensuring that the second doped region 112 does not exceed the drift region 110 and under the premise of ensuring that the second depletion region formed by the second doped region 112 and the drift region 110 is far away from the channel, the area of ​​the second doped region can be set larger to increase the area of ​​the second depletion region, thereby improving the voltage resistance performance of the LDMOS device.

[0080] Now combined Figures 4 to 6 The effects of the LDMOS device of the present invention will be described.

[0081] Please refer to Figure 4 ,exist Figure 4 In the example: the horizontal axis BV can be understood as the withstand voltage of the LDMOS device, and the vertical axis I can be understood as the driving current of the LDMOS device.

[0082] Please refer to Figure 4 as well as Figure 5 ,exist Figure 4 and Figure 5 In the example, the horizontal axis BV can be understood as the withstand voltage of the N-channel LDMOS device, and the vertical axis I can be understood as the driving current of the N-channel LDMOS device.

[0083] Figure 4 The LDMOS device with no doping in the mid-drift region has a withstand voltage of 150V to 155V and a drive current of 1.15×10 -8 A~1.20×10-8 A, and Figure 5 The LDMOS device with the first doping region in the drift region has a withstand voltage of 630V to 660V and a drive current of 1.15×10 -8 A~1.20×10 -8 A, from the drift region without doping to the drift region containing the first doping region, the withstand voltage of the LDMOS device increases from 150V to 155V to 630V to 660V, and the drive current increases from 1.15×10 -8 A~1.20×10 -8 A, increased to 1.15×10 -8 A~1.20×10 -8 A. Thus, it can be seen that the withstand voltage performance of the LDMOS device is significantly improved from the drift region without doping to the drift region containing the first doping region, while the driving current is not reduced.

[0084] Please refer to Figure 6 ,exist Figure 6 In the example, the horizontal axis BV can be understood as the withstand voltage of the LDMOS device, the vertical axis I can be understood as the driving current of the LDMOS device, the red line is the relationship between the withstand voltage performance and the driving current of the drift region of the LDMOS device containing the first doped region, and the green line is the relationship between the withstand voltage performance and the driving current of the drift region of the LDMOS device containing the first doped region and the second doped region.

[0085] Depend on Figure 6 It can be seen that, from the LDMOS device in which the drift region contains the first doping region to the LDMOS device in which the drift region contains the first doping region and the second doping region, the withstand voltage performance of the LDMOS device increases from 620V to 640V to 760V to 780V, and the driving current of the LDMOS device increases from 1.25×10 -8 A~1.30×10 -8 A is reduced to 1.10×10 -8 A~1.15×10 -8 A, it can be seen that the withstand voltage of the LDMOS device is significantly increased from the LDMOS device in which the drift region contains the first doping region to the LDMOS device in which the drift region contains the first doping region and the second doping region, and although the driving current of the LDMOS device is reduced, the reduction is small.

[0086] It can be seen that the present invention increases the depletion region area of ​​the LDMOS device by reasonably setting the positions of the first doping region and the second doping region and their ion doping concentrations, while sacrificing only a small driving current of the LDMOS device, thereby improving the voltage resistance performance of the LDMOS device while also enabling the LDMOS device to have a lower on-resistance and a better integration.

[0087] Figure 7 to Figure 10 It is a schematic diagram of an LDMOS device corresponding to each step of the method for preparing an N-channel LDMOS device of the present invention.

[0088] An embodiment of the present invention further provides a method for preparing an LDMOS device, which is used to prepare the LDMOS device in the above embodiment.

[0089] Please refer to Figure 7 , a substrate 100 is provided, and a drift region 110 is formed in the substrate 100 .

[0090] As an example, the substrate 100 may be Si or SOI (Silicon On Insulator in English and Silicon on Insulator in Chinese).

[0091] Please refer to Figure 8 , a second doping region 112 and a first doping region 111 are sequentially formed in the drift region 110 and are arranged in sequence in a direction perpendicular to the surface of the substrate 100; wherein a first distance D1 between the upper surface of the first doping region 111 and the surface of the substrate 100 is smaller than a second distance D2 between the upper surface of the second doping region 112 and the surface of the substrate 100, a thickness H1 of the first doping region 111 is smaller than a thickness H2 of the second doping region 112, and a first ion doping concentration of the first doping region 111 is greater than a second ion doping concentration of the second doping region 112.

[0092] As an example, the step of sequentially forming the second doping regions 112 and the first doping regions 111 sequentially arranged at intervals in a direction perpendicular to the surface of the substrate 100 in the drift region 110 may include:

[0093] A patterned first mask layer is formed on the surface of the substrate 100 .

[0094] With the first mask layer as a mask, doping ions are implanted into the drift region 110 to sequentially form the second doping regions 112 and the first doping regions 111 which are sequentially arranged at intervals in a direction perpendicular to the surface of the substrate 100 .

[0095] As an implementation manner, in the process of forming the first doping region 111 and the second doping region 112 , a ratio of a first ion doping concentration of the first doping region 111 to a second ion doping concentration of the second doping region 112 is in a range of 1.9 to 2.1.

[0096] As an implementation manner, a ratio of the ion implantation energy of the second doping region 112 to the ion implantation energy of the first doping region 1111 is in a range of 3.9 to 4.1.

[0097] The second doping region 112 and the first doping region 111 are formed in sequence, and the patterned first mask layer only needs to be formed once on the surface of the substrate 100 , thereby reducing the process flow.

[0098] In another embodiment, different mask layers may be used as barrier layers and ion implantation may be performed separately to form a first doping region and a second doping region with different lengths along a direction from the source region to the drain region.

[0099] In this embodiment, after the first doping region 111 and the second doping region 112 are formed, the patterned first mask layer is removed.

[0100] Please refer to Fig. 9 , a source region 121 and a drain region 122 are formed in the substrate 100 , the drain region 122 is located in the drift region 110 , and the source region 121 and the drain region 122 are located on both sides of the first doping region 111 .

[0101] Please refer to Fig.10 A gate structure 130 is formed on the surface of the substrate 100 , and the gate structure 130 is located between the source region 121 and the drain region 122 .

[0102] In summary, the embodiment of the present invention provides a method for preparing an LDMOS device, because the first doping region 111 and the second doping region 112 in the drift region 110 form the first depletion region and the second depletion region with the drift region 110 respectively, the withstand voltage performance of the LDMOS device is improved. On this basis, the first doping region 111 and the second doping region 112 are sequentially arranged in a direction perpendicular to the surface of the substrate 100, the first spacing D1 between the first doping region 111 and the surface of the substrate 100 is smaller than the second spacing D2 between the second doping region 112 and the surface of the substrate 100, the first ion doping concentration of the first doping region 111 is greater than the second ion doping concentration of the second doping region 112, the thickness of the first doping region 111 is smaller than the thickness of the second doping region 112, etc., the position of the doping region and its ion doping concentration are reasonably set, so that the first depletion region and the second depletion region are far away from the channel, the current channel is reserved, and the total area of ​​the first depletion region and the second depletion region of the LDMOS device is increased, so that the withstand voltage performance of the LDMOS device is improved, and the LDMOS device also takes into account low on-resistance and good integration.

[0103] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. An LDMOS device, characterized in that: include: A substrate, and a gate structure located on a surface of the substrate; The substrate includes a source region, a drain region, and a drift region, wherein the source region and the drift region are respectively located on both sides of the gate structure, and the drift region also extends to a portion below the gate structure, and the drain region is located in the drift region; the drift region includes a first doping region and a second doping region, wherein the first doping region and the second doping region are located between the drain region and the source region, and the first doping region and the second doping region are arranged in sequence and spaced apart in a direction perpendicular to the surface of the substrate, a first distance between an upper surface of the first doping region and a surface of the substrate is smaller than a second distance between an upper surface of the second doping region and a surface of the substrate, a thickness of the first doping region is smaller than a thickness of the second doping region, and a first ion doping concentration of the first doping region is greater than a second ion doping concentration of the second doping region.

2. The LDMOS device according to claim 1, characterized in that The ratio of the thickness of the drift region to the first spacing is in the range of 11.0 to 11.4; The ratio of the second spacing to the first spacing is in a range of 4.0 to 4.

4.

3. The LDMOS device according to claim 1, characterized in that: The ratio of the thickness of the drift region to the thickness of the first doping region is in the range of 11.0 to 11.4; The ratio of the thickness of the second doping region to the thickness of the first doping region is in a range of 1.9 to 2.

1.

4. The LDMOS device according to claim 1, wherein: The ratio of the first ion doping concentration to the second ion doping concentration is in a range of 1.9 to 2.

1.

5. The LDMOS device according to claim 1, wherein: Along the direction from the source region to the drain region, the first doped region has a first length, the drift region has a second length, and a ratio of the second length to the first length ranges from 1.4 to 1.

6.

6. The LDMOS device according to any one of claims 1 to 4, characterized in that: Also includes: A field oxide layer is located between the gate structure and the drain region above the drift region.

7. The LDMOS device according to claim 1, characterized in that: The number of the second doping region is one.

8. The LDMOS device according to claim 1, wherein: The number of the second doping regions is more than 2, and the more than 2 second doping regions are arranged in sequence and spaced apart in a direction perpendicular to the surface of the substrate.

9. The LDMOS device according to claim 1, wherein: The LDMOS device is an N-channel LDMOS device, and the doping ions in the first doping region and the second doping region are both P-type doping ions.

10. A method for preparing an LDMOS device, characterized in that: The method comprises: providing a substrate and forming a drift region in the substrate; A first doping region and a second doping region are formed in the drift region and are arranged in sequence and spaced apart in a direction perpendicular to the surface of the substrate; wherein a first distance between the upper surface of the first doping region and the surface of the substrate is smaller than a second distance between the upper surface of the second doping region and the surface of the substrate, a thickness of the first doping region is smaller than a thickness of the second doping region, and a first ion doping concentration of the first doping region is greater than a second ion doping concentration of the second doping region; forming a source region and a drain region in the substrate, wherein the drain region is located in the drift region, and the source region and the drain region are located on both sides of the first doped region; and A gate structure is formed on the surface of the substrate, and the gate structure is located between the source region and the drain region.

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