Semiconductor structure and manufacturing method thereof

Abstract

The invention relates to a semiconductor structure and a manufacturing method thereof. The semiconductor structure comprises a substrate, a capacitance adjusting layer, a gate structure and a drain structure, the capacitance adjusting layer is located at the central position of one side of the substrate; the gate structure is located on the side, away from the substrate, of the capacitance adjusting layer; the gate structure covers the top and the side wall of the capacitance adjusting layer and at least part of the surface of the substrate; the drain electrode structure is located on the side, away from the gate electrode structure, of the substrate. According to the semiconductor power device, the gate-drain capacitance of the semiconductor power device can be effectively reduced under the condition that the gate-source capacitance is not influenced, so that the conversion speed is effectively improved, the power loss of the device in the on-state is reduced, and the working efficiency of the semiconductor power device is effectively improved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for manufacturing the same. Background Art

[0002] Power Electronic Device (PED), also known as semiconductor power device, is a high-power (usually refers to currents of tens to thousands of amperes and voltages of hundreds of volts or more) electronic device used in power conversion and power control circuits. As power electronics technology tends to develop in the direction of high power, high frequency, and integration, in order to meet production and work needs, it is necessary to improve the working efficiency of semiconductor power devices. Among them, the working efficiency of semiconductor power devices usually depends on the recombination speed of minority carriers (referred to as minority carriers) in the base region during the device shutdown period and the amount of carriers extracted by the gate.

[0003] In the related art, in order to improve the working efficiency of semiconductor power devices, a method of reducing the minority carrier lifetime is usually adopted. However, although this method can shorten the process of turning off the current of the semiconductor power device, it is easy to increase the forward voltage drop of the semiconductor power device during the conduction period, thereby causing the problem of increased on-state power loss of the device. Summary of the invention

[0004] Based on this, the embodiments of the present application provide a semiconductor structure and a manufacturing method thereof, which can effectively reduce the gate-drain capacitance of a semiconductor power device without affecting the gate-source capacitance, so as to achieve both an effective increase in conversion speed and a reduction in device on-state power loss, thereby effectively improving the working efficiency of the semiconductor power device.

[0005] In order to achieve the above-mentioned purpose, on the one hand, some embodiments of the present application provide a semiconductor structure. The semiconductor structure includes a substrate, a capacitance adjustment layer, a gate structure and a drain structure; the capacitance adjustment layer is located at the central position of one side of the substrate; the gate structure is located on the side of the capacitance adjustment layer away from the substrate; the gate structure covers the top and sidewalls of the capacitance adjustment layer and at least part of the surface of the substrate; the drain structure is located on the side of the substrate away from the gate structure.

[0006] In some embodiments, the orthographic projection of the capacitance adjustment layer on the substrate is located inside the orthographic projection of the gate structure on the substrate.

[0007] In some embodiments, the orthographic projection of the capacitance adjustment layer on the substrate is located at a central position of the orthographic projection of the gate structure on the substrate.

[0008] In some embodiments, the thickness of the gate structure on the substrate is greater than its thickness on the capacitance adjustment layer; wherein the thickness of the gate structure is the dimension of the gate structure in a direction perpendicular to the substrate.

[0009] In some embodiments, the base includes a substrate and an epitaxial layer stacked in sequence from bottom to top; wherein the drain structure is located on a side of the substrate away from the epitaxial layer; the capacitance adjustment layer and the gate structure are both located on a side of the epitaxial layer away from the substrate.

[0010] In some embodiments, the semiconductor structure also includes at least two well regions and at least two source regions; at least two well regions are located inside the epitaxial layer on one side close to the gate structure, and are distributed on both sides of the gate structure in a direction parallel to the surface of the epitaxial layer; at least two source regions are respectively located inside each of the well regions.

[0011] In some embodiments, the gate structure includes a gate dielectric layer and a gate conductive layer stacked in sequence from bottom to top; wherein the gate dielectric layer conformally covers the top and side walls of the capacitance adjustment layer and at least a portion of the surface of the substrate; and the gate conductive layer covers the gate dielectric layer.

[0012] In some embodiments, a surface of the gate conductive layer facing away from the substrate is flush.

[0013] On the other hand, the present application also provides a method for manufacturing a semiconductor structure according to some embodiments, which is used to prepare the semiconductor structure in some of the above embodiments. The method for manufacturing the semiconductor structure includes: forming a substrate; forming a drain structure on one side of the substrate; forming a capacitance adjustment layer at the central position of a side of the substrate away from the drain structure; forming a gate structure on a side of the capacitance adjustment layer away from the substrate; the gate structure covers the top and sidewalls of the capacitance adjustment layer and at least a portion of the surface of the substrate.

[0014] In some embodiments, the forming of the substrate includes: providing a substrate; forming an epitaxial layer on one side of the substrate; before forming a capacitance adjustment layer at a central position on a side of the substrate away from the drain structure, the manufacturing method also includes: forming at least two well regions spaced apart and distributed in a direction parallel to the surface of the epitaxial layer inside the side of the epitaxial layer away from the substrate; forming a source region inside each of the well regions; wherein the capacitance adjustment layer is formed on the surface of the epitaxial layer between any two adjacent well regions.

[0015] The embodiments of the present application may or at least have the following advantages:

[0016] In the embodiment of the present application, a capacitance adjustment layer is formed at the central position of one side of the substrate; and the gate structure covers the top and sidewalls of the capacitance adjustment layer, so that the capacitance adjustment layer is located between the gate structure and the substrate and is accommodated inside the gate structure. The embodiment of the present application increases the distance between the central position of the gate structure and the drain structure in the direction perpendicular to the substrate by forming a capacitance adjustment layer, so as to effectively reduce the gate-drain capacitance and increase the switching ratio, thereby improving the response speed of the semiconductor power device and improving the device frequency. In addition, since the two sides of the gate structure close to the source region in the direction parallel to the substrate are the main positions for controlling the P well, its central position has almost no effect on the on and off of the P well; therefore, forming the capacitance adjustment layer at the central position of the gate structure can hardly affect the gate-source capacitance, ensure the control ability of the P well, and thus reduce the power consumption of the semiconductor power device. In this way, the present application can effectively reduce the gate-drain capacitance of the semiconductor power device without affecting the gate-source capacitance, so as to take into account the effective improvement of the conversion speed and the reduction of the power loss of the device in the on state, thereby effectively improving the working efficiency of the semiconductor power device.

[0017] The details of one or more embodiments of the present application are set forth in the following drawings and description. Other features, objects, and advantages of the present application will become apparent from the description, drawings, and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0019] Figure 1 A schematic diagram of a semiconductor structure provided in some embodiments;

[0020] Figure 2 A schematic flow chart of a method for manufacturing a semiconductor structure provided in some embodiments;

[0021] Figure 3 A schematic flow chart of another method for manufacturing a semiconductor structure provided in some embodiments;

[0022] Figure 4 A schematic diagram of a flow chart of step S300 provided in some embodiments;

[0023] Figure 5 A schematic diagram of a flow chart of step S400 provided in some embodiments;

[0024] Figure 6is a schematic structural diagram of a substrate provided in some embodiments;

[0025] Figure 7 A schematic diagram of a structure obtained after forming a capacitance adjustment material layer provided in some embodiments;

[0026] Figure 8 A schematic diagram of a structure obtained after forming a capacitance adjustment layer provided in some embodiments;

[0027] Fig. 9 A schematic diagram of a structure obtained after forming a gate dielectric material layer provided in some embodiments;

[0028] Fig.10 A schematic diagram of a structure obtained after a gate conductive material layer is provided in some embodiments.

[0029] Description of reference numerals:

[0030] 1-base, 11-substrate, 12-epitaxial layer, 2-capacitance adjustment layer, 21-capacitance adjustment material layer, 3-gate structure, 31-gate dielectric layer, 311-gate dielectric material layer, 32-gate conductive layer, 321-gate conductive material layer, 4-drain structure, 5-well region, 6-source region. DETAILED DESCRIPTION

[0031] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present application are given in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0032] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0033] It should be understood that when an element or layer is referred to as being "on," "adjacent to," or "connected to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. It should be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types, and / or portions, these elements, components, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion. Therefore, without departing from the teachings of the present application, the first element, component, region, layer, doping type, or portion discussed below may be represented as a second element, component, region, layer, or portion.

[0034] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that when the terms "consisting of" and / or "comprising" are used in this specification, the presence of the features, integers, steps, operations, elements and / or parts can be determined, but the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups is not excluded. At the same time, when used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0035] Embodiments of the invention are described herein with reference to cross-sectional views that are schematic representations of idealized embodiments (and intermediate structures) of the present application, such that variations in the shapes shown due to, for example, manufacturing techniques and / or tolerances are anticipated. Embodiments of the present application should not be limited to the specific shapes of the regions shown herein, but include deviations in shapes due to, for example, manufacturing techniques. Therefore, the regions shown in the figures are schematic in nature, their shapes do not represent the actual shapes of the regions of the device, and do not limit the scope of the present application.

[0036] The embodiments of the present application provide a semiconductor structure and a method for manufacturing the same, which can effectively reduce the gate-drain capacitance of a semiconductor power device without affecting the gate-source capacitance, so as to achieve both an effective increase in conversion speed and a reduction in device on-state power loss, thereby effectively improving the working efficiency of the semiconductor power device.

[0037] In some embodiments, see Figure 1 The semiconductor structure includes a substrate 1, a capacitance adjustment layer 2, a gate structure 3 and a drain structure 4; the capacitance adjustment layer 2 is located at the central position of one side of the substrate 1; the gate structure 3 is located on the side of the capacitance adjustment layer 2 away from the substrate 1; the gate structure 3 covers the top and sidewalls of the capacitance adjustment layer 2 and at least a portion of the surface of the substrate 1; the drain structure 4 is located on the side of the substrate 1 away from the gate structure 3.

[0038] Illustratively, the semiconductor structure includes, but is not limited to, a silicon carbide (SiC) power device.

[0039] For some examples, see Figure 1 The semiconductor structure includes a drain structure 4, a substrate 1, a capacitance adjustment layer 2 and a gate structure 3 which are sequentially stacked from bottom to top along a first direction (eg, a Y direction).

[0040] By way of example, the material of the capacitance adjustment layer 2 includes, but is not limited to, an insulating material; the material of the capacitance adjustment layer 2 may be, for example, an oxide.

[0041] For example, the size of the capacitance adjustment layer 2 in the second direction (eg, X direction) is smaller than the size of the gate structure 3 in the second direction (eg, X direction).

[0042] Illustratively, the second direction (eg, X direction) intersects the first direction (eg, Y direction).

[0043] Illustratively, the second direction (eg, X direction) is orthogonal to the first direction (eg, Y direction).

[0044] For example, the size of the drain structure 4 in the second direction (eg, X direction) is the same as the size of the substrate 1 in the second direction (eg, X direction).

[0045] For example, the drain structure 4 may cover a surface of the substrate 1 facing away from the gate structure 3 .

[0046] By way of example, the material of the drain structure 4 includes, but is not limited to, a conductive material; the material of the drain structure 4 may be, for example, a conductive metal.

[0047] In the embodiment of the present application, a capacitance adjustment layer 2 is formed at the central position of one side of the substrate 1; and the gate structure 3 covers the top and sidewalls of the capacitance adjustment layer 2, so that the capacitance adjustment layer 2 is located between the gate structure 3 and the substrate 1 and is accommodated inside the gate structure 3. The embodiment of the present application increases the distance between the central position of the gate structure 3 and the drain structure 4 in the direction perpendicular to the substrate 1 by forming the capacitance adjustment layer 2, so as to effectively reduce the gate-drain capacitance and increase the switching ratio, thereby improving the response speed of the semiconductor power device and improving the device frequency. In addition, since the two sides of the gate structure 3 close to the source region 6 in the direction parallel to the substrate 1 are the main positions for controlling the P well, its central position has almost no effect on the on and off of the P well; therefore, the capacitance adjustment layer 2 is formed at the central position of the gate structure 3, which can hardly affect the gate-source capacitance, ensure the control ability of the P well, and thus reduce the power consumption of the semiconductor power device. In this way, the present application can effectively reduce the gate-drain capacitance of the semiconductor power device without affecting the gate-source capacitance, so as to take into account the effective improvement of the conversion speed and the reduction of the power loss of the device in the on state, thereby effectively improving the working efficiency of the semiconductor power device.

[0048] In some embodiments, please refer to Figure 1 , the orthographic projection of the capacitance adjustment layer 2 on the substrate 1 is located inside the orthographic projection of the gate structure 3 on the substrate 1 .

[0049] It should be noted that the orthographic projection of the capacitance adjustment layer 2 on the substrate 1 is the orthographic projection of the capacitance adjustment layer 2 on the substrate 1 along the first direction (for example, the Y direction); the orthographic projection of the gate structure 3 on the substrate 1 is the orthographic projection of the gate structure 3 on the substrate 1 along the first direction (for example, the Y direction).

[0050] In some embodiments, please refer to Figure 1 , the orthographic projection of the capacitance adjustment layer 2 on the substrate 1 is located at the center of the orthographic projection of the gate structure 3 on the substrate 1 .

[0051] In the embodiment of the present application, since the two sides of the gate structure 3 close to the source region 6 in the direction parallel to the substrate 1 are the main positions for controlling the P-well, the central position has almost no effect on the on and off of the P-well; therefore, the capacitance adjustment layer 2 is formed at the central position of the gate structure 3, which can hardly affect the gate-source capacitance, ensure the control ability of the P-well, and thus reduce the power consumption of the semiconductor power device. In this way, the present application can effectively reduce the gate-drain capacitance of the semiconductor power device without affecting the gate-source capacitance, so as to take into account the effective improvement of the conversion speed and the reduction of the power loss of the device in the on state, thereby effectively improving the working efficiency of the semiconductor power device.

[0052] In some embodiments, please refer to Figure 1 , the thickness of the gate structure 3 on the substrate 1 is greater than its thickness on the capacitance adjustment layer 2; wherein the thickness of the gate structure 3 is the dimension of the gate structure 3 in a direction perpendicular to the substrate 1.

[0053] By way of example, the thickness of the gate structure 3 is a dimension of the gate structure 3 in a first direction (eg, the Y direction).

[0054] In some embodiments, please refer to Figure 1 The base 1 includes a substrate 11 and an epitaxial layer 12 stacked in sequence from bottom to top; wherein the drain structure 4 is located on the side of the substrate 11 away from the epitaxial layer 12; the capacitance adjustment layer 2 and the gate structure 3 are both located on the side of the epitaxial layer 12 away from the substrate 11.

[0055] For example, please refer to Figure 1 The base 1 includes a substrate 11 and an epitaxial layer 12 which are stacked in sequence from bottom to top along a first direction (eg, the Y direction).

[0056] For example, the substrate 11 can be made of semiconductor material, insulating material, conductor material or any combination thereof. The substrate 11 can be a single-layer structure or a multi-layer structure. For example, the substrate 11 can be a silicon (Si) substrate, a silicon germanium (SiGe) substrate, a silicon germanium carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate or other III / V semiconductor substrates or II / VI semiconductor substrates. Or, for example, the substrate 11 can be a layered substrate including Si / SiGe, Si / SiC, silicon on insulator (SOI) or silicon germanium on insulator. Therefore, the type of substrate 11 should not limit the scope of protection of the present application.

[0057] By way of example, the material of the epitaxial layer 12 includes, but is not limited to, silicon carbide (SiC).

[0058] Illustratively, the crystal orientation of the epitaxial layer 12 is the same as that of the substrate 11 .

[0059] Illustratively, the epitaxial layer 12 includes, but is not limited to, a single crystal layer.

[0060] Illustratively, the conductivity type of the substrate 11 is the same as that of the epitaxial layer 12 ; for example, the conductivity type of the substrate 11 and the conductivity type of the epitaxial layer 12 are both P-type, or the conductivity type of the substrate 11 and the conductivity type of the epitaxial layer 12 are both N-type.

[0061] Illustratively, the conductive strength of the substrate 11 is greater than the conductive strength of the epitaxial layer 12 .

[0062] For example, a size of the epitaxial layer 12 in a first direction (eg, Y direction) is greater than a size of the substrate 11 in the first direction (eg, Y direction).

[0063] In some embodiments, please refer to Figure 1 The semiconductor structure also includes at least two well regions 5 and at least two source regions 6; at least two well regions 5 are located inside the epitaxial layer 12 on one side close to the gate structure 3, and are distributed on both sides of the gate structure 3 along a direction parallel to the surface of the epitaxial layer 12; at least two source regions 6 are respectively located inside each well region 5.

[0064] For example, please refer to Figure 1 , at least a portion of the gate structure 3 is in contact with a portion of the surface of the well region 5 .

[0065] In some embodiments, please refer to Figure 1 The gate structure 3 includes a gate dielectric layer 31 and a gate conductive layer 32 stacked in sequence from bottom to top; wherein the gate dielectric layer 31 conformally covers the top and sidewalls of the capacitance adjustment layer 2 and at least a portion of the surface of the substrate 1; and the gate conductive layer 32 covers the gate dielectric layer 31.

[0066] For example, the material of the gate dielectric layer 31 includes, but is not limited to, an insulating material; the material of the gate dielectric layer 31 may be, for example, an oxide.

[0067] By way of example, the material of the gate conductive layer 32 may be polysilicon (Poly).

[0068] By way of example, at least a portion of the gate dielectric layer 31 contacts a portion of the surface of the well region 5 .

[0069] In some embodiments, please refer to Figure 1 , the surface of the gate conductive layer 32 facing away from the substrate 1 is flush.

[0070] For example, a surface of the gate conductive layer 32 that is away from the substrate 1 in the first direction (eg, the Y direction) is a plane.

[0071] The present application also provides a method for manufacturing a semiconductor structure according to some embodiments; the method for manufacturing a semiconductor structure can be used to prepare the semiconductor structures in some of the above embodiments. The method for manufacturing the semiconductor structure also possesses the technical advantages of the above semiconductor structure. It should be noted that for the parts that are the same or corresponding to the above embodiments, reference can be made to the corresponding description of the above embodiments, and will not be described in detail below.

[0072] In some embodiments, see Figure 2 , the manufacturing method of the semiconductor structure includes the following steps S100~S400.

[0073] S100, forming a substrate.

[0074] S200 , forming a drain structure on one side of the substrate.

[0075] S300 , forming a capacitance adjustment layer at a central position of a side of the substrate away from the drain structure.

[0076] S400, forming a gate structure on a side of the capacitance adjustment layer away from the substrate; the gate structure covers the top and sidewall of the capacitance adjustment layer and at least a portion of the surface of the substrate.

[0077] In the embodiment of the present application, a capacitance adjustment layer is formed at the central position of one side of the substrate; and the gate structure covers the top and sidewalls of the capacitance adjustment layer, so that the capacitance adjustment layer is located between the gate structure and the substrate and is accommodated inside the gate structure. The embodiment of the present application increases the distance between the central position of the gate structure and the drain structure in the direction perpendicular to the substrate by forming a capacitance adjustment layer, so as to effectively reduce the gate-drain capacitance and increase the switching ratio, thereby improving the response speed of the semiconductor power device and improving the device frequency. In addition, since the two sides of the gate structure close to the source region in the direction parallel to the substrate are the main positions for controlling the P well, its central position has almost no effect on the on and off of the P well; therefore, forming the capacitance adjustment layer at the central position of the gate structure can hardly affect the gate-source capacitance, ensure the control ability of the P well, and thus reduce the power consumption of the semiconductor power device. In this way, the present application can effectively reduce the gate-drain capacitance of the semiconductor power device without affecting the gate-source capacitance, so as to take into account the effective improvement of the conversion speed and the reduction of the power loss of the device in the on state, thereby effectively improving the working efficiency of the semiconductor power device.

[0078] In some embodiments, see Figure 3 , step S100 includes the following steps S110~S120.

[0079] S110, providing a substrate.

[0080] S120, forming an epitaxial layer on one side of the substrate.

[0081] For some examples, see Figure 3 Before step S300, the manufacturing method further includes the following steps S510~S520.

[0082] S510, forming at least two well regions spaced apart and distributed in a direction parallel to a surface of the epitaxial layer inside a side of the epitaxial layer facing away from the substrate.

[0083] S520 , forming source regions inside each well region.

[0084] In some examples, the capacitance adjustment layer is formed on the surface of the epitaxial layer between any two adjacent well regions.

[0085] In some embodiments, see Figure 4 , step S300 may include the following steps S310~S320.

[0086] S310 , forming a capacitance adjustment material layer on a side of the substrate away from the drain structure.

[0087] S320, etching the capacitance adjustment material layer to remove the capacitance adjustment material layer on the surface of the well region, the surface of the source region and at least a portion of the surface of the epitaxial layer, so that the capacitance adjustment material layer retained between any two adjacent well regions constitutes a capacitance adjustment layer.

[0088] In some embodiments, see Figure 5 , step S400 may include the following steps S410~S430.

[0089] S410, forming a gate dielectric material layer that conformally covers the top and sidewalls of the capacitance adjustment layer, the surface of the epitaxial layer, the surface of the well region, and the surface of the source region.

[0090] S420, forming a gate conductive material layer covering the gate dielectric material layer.

[0091] S430, etching the gate dielectric material layer and the gate conductive material layer to remove the gate dielectric material layer and the gate conductive material layer on the surface of the source region and at least a portion of the surface of the well region, so that the remaining portions of the gate dielectric material layer and the gate conductive material layer correspond to form a gate structure.

[0092] It should be understood that although Figure 2~Figure 5 The steps in the flowchart are shown in sequence as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. Moreover, Figure 2~Figure 5 At least part of the steps may include multiple steps or multiple stages. These steps or stages are not necessarily performed at the same time, but can be performed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed in turn or alternately with other steps or at least part of the steps or stages in other steps.

[0093] In order to more clearly illustrate the manufacturing method of the semiconductor structure in some of the above embodiments, the following embodiments are combined with Figure 1 and Figure 6~Figure 10 Understand.

[0094] In some embodiments, the method for manufacturing a semiconductor structure includes the following steps S100 - S400 .

[0095] In step S100, refer to Figure 6 , forming a base 1.

[0096] In some embodiments, step S100 includes the following steps S110 to S120.

[0097] In step S110 , a substrate 11 is provided.

[0098] For example, the substrate 11 can be made of semiconductor material, insulating material, conductor material or any combination thereof. The substrate 11 can be a single-layer structure or a multi-layer structure. For example, the substrate 11 can be a silicon (Si) substrate, a silicon germanium (SiGe) substrate, a silicon germanium carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate or other III / V semiconductor substrates or II / VI semiconductor substrates. Or, for example, the substrate 11 can be a layered substrate including Si / SiGe, Si / SiC, silicon on insulator (SOI) or silicon germanium on insulator. Therefore, the type of substrate 11 should not limit the scope of protection of the present application.

[0099] In step S120, please continue to refer to Figure 6 , an epitaxial layer 12 is formed on one side of the substrate 11.

[0100] By way of example, the material of the epitaxial layer 12 includes, but is not limited to, silicon carbide (SiC).

[0101] By way of example, the process for forming the epitaxial layer 12 includes, but is not limited to, an epitaxial growth process.

[0102] Illustratively, the conductivity type of the substrate 11 is the same as that of the epitaxial layer 12 ; for example, the conductivity type of the substrate 11 and the conductivity type of the epitaxial layer 12 are both P-type, or the conductivity type of the substrate 11 and the conductivity type of the epitaxial layer 12 are both N-type.

[0103] Illustratively, the conductive strength of the substrate 11 is greater than the conductive strength of the epitaxial layer 12 .

[0104] In step S200, please continue to refer to Figure 6 , a drain structure 4 is formed on one side of the substrate 1 .

[0105] By way of example, the material of the drain structure 4 includes, but is not limited to, a conductive material; the material of the drain structure 4 may be, for example, a conductive metal.

[0106] In some examples, before step S300, the manufacturing method further includes the following steps S510-S520.

[0107] In step S510, please continue to refer to Figure 6 At least two well regions 5 are formed inside the epitaxial layer 12 on the side facing away from the substrate 11 and are spaced apart from each other in a direction parallel to the surface of the epitaxial layer 12 .

[0108] By way of example, the process for forming the well region 5 includes, but is not limited to, an ion implantation (IMP) process.

[0109] In step S520, please continue to refer to Figure 6 , a source region 6 is formed inside each well region 5.

[0110] By way of example, the process for forming the source region 6 includes, but is not limited to, an ion implantation (IMP) process.

[0111] In step S300, refer to Figure 8 , a capacitance adjustment layer 2 is formed at a central position of a side of the substrate 1 away from the drain structure 4 .

[0112] For some examples, see Figure 8 The capacitance adjustment layer 2 is formed on the surface of the epitaxial layer 12 between any two adjacent well regions 5 in the second direction (eg, the X direction).

[0113] In some embodiments, step S300 may include the following steps S310 to S320.

[0114] In step S310, refer to Figure 7 , a capacitance adjustment material layer 21 is formed on a side of the substrate 1 away from the drain structure 4 .

[0115] By way of example, the material of the capacitance adjustment material layer 21 includes, but is not limited to, an insulating material; the material of the capacitance adjustment material layer 21 may be, for example, an oxide.

[0116] In step S320, refer to Figure 8 , etching the capacitance adjustment material layer 21, removing the capacitance adjustment material layer 21 on the surface of the well region 5, the surface of the source region 6 and at least part of the surface of the epitaxial layer 12, so that the capacitance adjustment material layer 21 retained between any two adjacent well regions 5 corresponds to forming a capacitance adjustment layer 2.

[0117] For example, the etching process of the capacitance adjustment material layer 21 includes but is not limited to a dry etching process; the etching process of the capacitance adjustment material layer 21 may be, for example, a photolithography process.

[0118] In step S400 , a gate structure 3 is formed on a side of the capacitance adjustment layer 2 facing away from the substrate 1 ; the gate structure 3 covers the top and sidewalls of the capacitance adjustment layer 2 and at least a portion of the surface of the substrate 1 .

[0119] In some embodiments, step S400 may include the following steps S410 to S430.

[0120] In step S410, refer to Fig. 9, forming a gate dielectric material layer 311 that conformally covers the top and sidewalls of the capacitance adjustment layer 2 , the surface of the epitaxial layer 12 , the surface of the well region 5 , and the surface of the source region 6 .

[0121] By way of example, the material of the gate dielectric material layer 311 includes, but is not limited to, an insulating material; the material of the gate dielectric material layer 311 may be, for example, an oxide.

[0122] In step S420, refer to Fig.10 , forming a gate conductive material layer 321 covering the gate dielectric material layer 311.

[0123] By way of example, the material of the gate conductive material layer 321 may be polysilicon (Poly).

[0124] In step S430, refer to Figure 1 , the gate dielectric material layer 311 and the gate conductive material layer 321 are etched to remove the gate dielectric material layer 311 and the gate conductive material layer 321 on the surface of the source region 6 and at least part of the surface of the well region 5, so that the retained parts of the gate dielectric material layer 311 and the gate conductive material layer 321 correspond to form the gate structure 3.

[0125] For example, the size of the capacitance adjustment layer 2 in the second direction (eg, X direction) is smaller than the size of the gate structure 3 in the second direction (eg, X direction).

[0126] By way of example, the orthographic projection of the capacitance adjustment layer 2 on the substrate 1 is located inside the orthographic projection of the gate structure 3 on the substrate 1 .

[0127] By way of example, the orthographic projection of the capacitance adjustment layer 2 on the substrate 1 is located at the center of the orthographic projection of the gate structure 3 on the substrate 1 .

[0128] In the description of this specification, the description with reference to the terms "some embodiments", "some examples", "exemplarily", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.

[0129] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0130] The above-mentioned embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for ordinary technicians in this field, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application.

Claims

1. A semiconductor structure, characterized in that: include: substrate; A capacitance adjustment layer is located at a central position of one side of the substrate; A gate structure, located on a side of the capacitance adjustment layer away from the substrate; The gate structure covers the top and sidewalls of the capacitance adjustment layer and at least a portion of the surface of the substrate; The drain structure is located on a side of the substrate away from the gate structure.

2. The semiconductor structure according to claim 1, characterized in that: The orthographic projection of the capacitance adjustment layer on the substrate is located inside the orthographic projection of the gate structure on the substrate.

3. The semiconductor structure according to claim 1, characterized in that: The orthographic projection of the capacitance adjustment layer on the substrate is located at a central position of the orthographic projection of the gate structure on the substrate.

4. The semiconductor structure according to claim 1, characterized in that: The thickness of the gate structure on the substrate is greater than its thickness on the capacitance adjustment layer; wherein the thickness of the gate structure is the dimension of the gate structure in a direction perpendicular to the substrate.

5. The semiconductor structure according to claim 1, characterized in that: The base comprises a substrate and an epitaxial layer stacked in sequence from bottom to top; wherein, The drain structure is located on a side of the substrate away from the epitaxial layer; The capacitance adjustment layer and the gate structure are both located on a side of the epitaxial layer away from the substrate.

6. The semiconductor structure according to claim 5, characterized in that: Also includes: At least two well regions are located inside the epitaxial layer on one side close to the gate structure and are distributed on both sides of the gate structure in a direction parallel to the surface of the epitaxial layer; At least two source regions are respectively located inside the well regions.

7. The semiconductor structure according to claim 1, characterized in that: The gate structure includes a gate dielectric layer and a gate conductive layer stacked in sequence from bottom to top; wherein, The gate dielectric layer conformally covers the top and sidewalls of the capacitance adjustment layer and at least a portion of the surface of the substrate; The gate conductive layer covers the gate dielectric layer.

8. The semiconductor structure according to claim 7, characterized in that: The surface of the gate conductive layer facing away from the substrate is flush.

9. A method for manufacturing a semiconductor structure, characterized in that: include: forming a base; forming a drain structure on one side of the substrate; forming a capacitance adjustment layer at a central position of a side of the substrate away from the drain structure; A gate structure is formed on a side of the capacitance adjustment layer away from the substrate; the gate structure covers the top and sidewalls of the capacitance adjustment layer and at least a portion of the surface of the substrate.

10. The method for manufacturing a semiconductor structure according to claim 9, characterized in that: The forming substrate comprises: providing a substrate; forming an epitaxial layer on one side of the substrate; Before forming the capacitance adjustment layer at the central position of the side of the substrate away from the drain structure, the manufacturing method further includes: forming at least two well regions spaced apart and distributed in a direction parallel to a surface of the epitaxial layer inside the epitaxial layer on a side facing away from the substrate; forming source regions inside each of the well regions; Wherein, the capacitance adjustment layer is formed on the surface of the epitaxial layer between any two adjacent well regions.

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