Semiconductor structure and forming method
By forming trenches on the substrate of the semiconductor structure and filling the support layer, the interfacial traps and planarized depressions that exist in the formation of high-voltage operating devices in the existing semiconductor structure are solved, and performance improvement and cost savings are achieved.
Patent Information
- Application Number
- CN202311482074.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-11-08
- Publication Date
- 2025-05-16
AI Technical Summary
The existing semiconductor structures with 28nm and below have poor performance in the combined or combined processes, especially in the formation of high-voltage operating devices, there are problems of trench bottom interfacial traps and concave during planarization.
By forming a first gate on a substrate of a semiconductor structure and forming a trench in the first gate in a direction perpendicular to the substrate surface, the bottom of the trench exposes the substrate surface and fills the support layer in the trench. This method does not require an additional mask, saves costs, and avoids depression problems during planarization by filling the support layer.
The performance and uniformity of the semiconductor structure are improved, process costs are reduced, and the yield of the formed semiconductor structure is improved.
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Figure CN120018567A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure and a forming method thereof. Background Art
[0002] In current semiconductor processes, controllers, memories, circuits operating at low voltages, and power devices operating at high voltages are mostly integrated into a single chip to realize a single-chip system. Power devices or high-voltage (HV) devices, such as vertical double-diffused metal oxide semiconductors (VDMOS), insulated gate bipolar transistors (IGBTs), and lateral diffused MOS (LDMOS), are used to improve power switching efficiency and reduce the loss of energy resources. Switching transistors are usually required to withstand high breakdown voltages and operate at low on-resistance.
[0003] In addition, in semiconductor manufacturing processes of 28nm and below, a high voltage (HV) semiconductor structure may include a low voltage (LV) device as a core device and a medium voltage (MV) device providing source drive. Recently, a single-chip solution for mobile communication systems has been developed, so advanced manufacturing methods for merging or combining processes can simultaneously form semiconductor devices for high voltage (HV) operation, for medium voltage (MV) operation, and for low voltage (LV) operation is necessary and / or desired.
[0004] In the current semiconductor process level, conventional processes for logic devices and conventional processes for high voltage operating devices are performed separately in a merged or combined process, so the number of masks for the integrated solution (i.e., containing HV, MV, and LV devices) is the same or greater. That is, although the junctions used for HV devices are the same type as those for logic devices (MV or LV devices), separate lithography processes are performed to form those junctions.
[0005] However, there are still many problems with existing semiconductor structures of 28nm and below. Summary of the invention
[0006] The technical problem solved by the present invention is to provide a semiconductor structure and a forming method thereof, so as to improve the performance of the semiconductor structure.
[0007] To solve the above problems, the present invention also provides a semiconductor structure, including: a substrate, the substrate including a first region; a first gate located on the first region, the first gate having a plurality of grooves penetrating the first gate in a direction perpendicular to the substrate surface; and a support layer located in the grooves.
[0008] Optionally, it also includes: a first source and a drain respectively located in the substrate on both sides of the first gate.
[0009] Optionally, the extending direction of the trench is parallel to the extending direction of the first source and drain, or the extending direction of the trench is perpendicular to the extending direction of the first source and drain.
[0010] Optionally, a length of the first gate in a direction parallel to an extension of the trench is greater than a length of the trench in the extension direction, and a width of the first gate in a direction perpendicular to an extension of the trench is greater than a width of the trench in the extension direction.
[0011] Optionally, the substrate further includes: a second region adjacent to the first region, a second gate located on the second region, and a second source and drain located in the substrate at both sides of the second gate.
[0012] Optionally, it also includes a shallow trench isolation structure located in the substrate, wherein the shallow trench isolation structure isolates the first region and the second region.
[0013] Optionally, it also includes: a first gate dielectric layer located on the surface of the first region, a second gate dielectric layer located on the surface of the first gate dielectric layer, and the first gate is located on the surface of the second gate dielectric layer; the material of the first gate dielectric layer includes hafnium dioxide, and the material of the second gate dielectric layer includes titanium nitride.
[0014] Optionally, the second gate is located on the surface of the second gate dielectric layer on the second region, and the material of the second gate is metal.
[0015] Optionally, the material of the first gate is polysilicon, the polysilicon contains doping ions, the type of doping ions includes phosphorus or boron, and the concentration of the doping ions is 2·10 15 / cm 2 .
[0016] Correspondingly, the present invention also provides a method for forming a semiconductor structure, comprising: providing a substrate, the substrate comprising a first region; forming a first gate on the substrate in the first region; forming a plurality of grooves in the first gate that penetrate the first gate in a direction perpendicular to the surface of the substrate; and forming a supporting layer in the grooves.
[0017] Optionally, the method further includes forming a first source and a drain in the substrate on both sides of the first gate in the first region.
[0018] Optionally, the extending direction of the trench is parallel to the extending direction of the first source and drain, or the extending direction of the trench is perpendicular to the extending direction of the first source and drain.
[0019] Optionally, a length of the first gate in a direction parallel to an extension of the trench is greater than a length of the trench in the extension direction, and a width of the first gate in a direction perpendicular to an extension of the trench is greater than a width of the trench in the extension direction.
[0020] Optionally, the substrate further includes a second region adjacent to the first region, the length of the first region is greater than the length of the second region, a second gate is formed on the second region, and a second source and drain are formed in the substrate on both sides of the second gate.
[0021] Optionally, before forming the first gate, the method further includes: forming an initial first gate dielectric layer on the surface of the substrate; forming an initial second gate dielectric layer on the surface of the initial first gate dielectric layer; and forming an initial gate layer on the surface of the initial second gate dielectric layer.
[0022] Optionally, the step of forming a groove includes: forming a patterned layer on the surface of the initial gate layer; using the patterned layer as a mask, etching the initial gate layer, the initial second gate dielectric layer and the initial first gate dielectric layer in sequence, forming a first gate dielectric layer, a second gate dielectric layer and a first gate in sequence on the first region, and forming a groove passing through the first gate in a direction perpendicular to the substrate surface; forming a first gate dielectric layer, a second gate dielectric layer and a first gate in sequence on the second region.
[0023] Optionally, the method further includes forming a second source and drain in the substrate on both sides of the first gate in the second region, and forming a silicide layer on the surface of the first source and drain and the surface of the second source and drain.
[0024] Optionally, the method further includes removing the first gate on the second region to form a gate opening, exposing the surface of the second gate dielectric layer on the second region at the bottom of the gate opening; and forming a second gate in the gate opening, wherein the material of the second gate is a metal material.
[0025] Optionally, the material of the support layer includes one or more of silicon nitride, silicon oxide, silicon carbide, and silicon carbide nitride.
[0026] Optionally, the material of the first gate is polysilicon, the polysilicon contains doping ions, the types of doping ions include phosphorus or boron, and the concentration of doping ions is 2·10 15 / cm 2 .
[0027] Compared with the prior art, the technical solution of the present invention has the following advantages:
[0028] In the technical solution of the semiconductor structure of the present invention, the substrate includes a first region, the first region has a first gate, the first gate has a plurality of grooves penetrating the first gate in a direction perpendicular to the surface of the substrate, and the grooves are filled with a supporting layer. On the one hand, the bottom of the groove exposes the surface of the substrate to avoid the generation of interface state traps at the bottom of the groove, thereby improving the performance and uniformity of the device containing the groove; on the other hand, the supporting layer fills the groove. In the subsequent planarization process, the supporting effect of the supporting layer can avoid the depression problem in the first region during the planarization process, thereby greatly improving the yield of the formed semiconductor structure.
[0029] In the technical solution of the formation method of the present invention, a first gate is formed on a substrate in a first region, and a plurality of grooves are formed in the first gate that penetrate the first gate in a direction perpendicular to the surface of the substrate, the bottom of the grooves exposes a portion of the surface of the substrate, and a supporting layer is formed in the grooves; on the one hand, in the process of forming the grooves in the first gate, no additional mask is required, which saves costs; on the other hand, the supporting layer fills the grooves, and in the subsequent planarization process, the supporting effect of the supporting layer can avoid the problem of depression in the first region during the planarization process.
[0030] Furthermore, a patterned layer is formed on the surface of the initial gate layer; the patterned layer is used as a mask to sequentially etch the initial gate layer, the initial second gate dielectric layer and the initial first gate dielectric layer to form a first gate dielectric layer located on the substrate, a second gate dielectric layer located on the surface of the first gate dielectric layer, and a first gate located on the surface of the second gate dielectric layer on the first region, and a groove is formed that penetrates the first gate in a direction perpendicular to the substrate surface, thereby completely cutting off the initial gate layer from the initial second gate dielectric layer, eliminating the problem of electric traps generated at the interface at the bottom of the trench due to the contact between the initial gate layer and the initial second gate dielectric layer, thereby improving the performance and uniformity of devices containing trenches. BRIEF DESCRIPTION OF THE DRAWINGS
[0031] Figures 1 to 4 It is a schematic diagram of the structure of each step of a method for forming a semiconductor structure;
[0032] Figures 5 to 12 It is a schematic structural diagram of each step of a method for forming a semiconductor structure in one embodiment of the present invention. DETAILED DESCRIPTION
[0033] As the background technology, the performance of the existing semiconductor structure is poor.
[0034] Please refer to Figure 1 , providing a substrate, on the substrate 100, the substrate includes a first region I and a second region II, the first region I is used to form a high voltage or medium voltage device, and the second region II is used to form a central device; forming a shallow trench isolation structure 101 in the substrate 100, the shallow trench isolation structure 101 isolating the first region I from the second region II; forming an oxide layer 102 on the surface of the substrate 100 and the surface of the shallow trench isolation structure 101; forming a barrier layer 103 on the surface of the oxide layer 102, and forming a gate layer 104 on the surface of the barrier layer 103; forming a patterned layer 105 on the surface of the gate layer 104, using the patterned layer 105 as a mask, etching and removing a portion of the thickness of the gate layer 104 on the first region, and forming a trench 106 ( Figure 1 Only one trench is shown, and there will be multiple trenches in the actual process).
[0035] Please refer to Figure 2 , remove the patterned layer 105 and form a hard mask layer 107 on the surface of the gate layer 104.
[0036] Please refer to Figure 3 , patterning the hard mask layer 107 , forming a first device 108 including a trench 106 on the first region I and forming a second device 109 on the second region II, the sidewall of the trench 106 having the hard mask layer 107 .
[0037] Please refer to Figure 4 A first sidewall 110 is formed on the sidewall of the first device 108, a second sidewall 111 is formed on the sidewall of the second device 109, a first source and drain 112 is formed in the substrate 100 on both sides of the first sidewall 110, a first silicide layer 113 is formed on the first source and drain 112, a second source and drain 114 is formed in the substrate on both sides of the second sidewall 111, and a second silicide layer 115 is formed on the second source and drain 114.
[0038] However, during the formation of the above-mentioned semiconductor structure, an additional patterned layer (mask) is required to form grooves in the first area in advance, which increases the cost on the one hand, and on the other hand, according to the test structure analysis, multi-groove etching will produce electrical traps at the interface between the barrier layer and the gate layer, resulting in the uniformity of high-voltage or medium-voltage devices being worse than that of devices without grooves.
[0039] On this basis, the present invention provides a method for forming a semiconductor structure, forming a first gate on a substrate in a first region, forming a plurality of grooves in the first gate that penetrate the first gate in a direction perpendicular to the surface of the substrate, the bottom of the grooves exposes a portion of the surface of the substrate, and forming a supporting layer in the grooves; on the one hand, in the process of forming the grooves in the first gate, no additional mask is required, which saves costs; on the other hand, the supporting layer fills the grooves, and in the subsequent planarization process, the supporting effect of the supporting layer can avoid the problem of depression in the first region during the planarization process.
[0040] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.
[0041] Figures 5 to 12 It is a schematic structural diagram of each step of a method for forming a semiconductor structure in one embodiment of the present invention.
[0042] Please refer to Figure 5 , providing a substrate 200.
[0043] In this embodiment, the material of the substrate 200 is silicon; in other embodiments, the material of the substrate 200 may also be germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium; in other embodiments, the substrate may also be a silicon substrate on an insulator or a germanium substrate on an insulator.
[0044] In this embodiment, the substrate 200 includes a first region I and a second region II, the first region I is used to form a high voltage or medium voltage (HV / MV) device, and the second region II is used to form a core device.
[0045] In this embodiment, a shallow trench isolation structure 201 is formed in the substrate 200 , and the shallow trench isolation structure 201 is used to isolate the first region I from the second region II.
[0046] In this embodiment, the steps of forming the shallow trench isolation structure 201 include: etching away a portion of the thickness of the substrate 200, forming a shallow trench in the substrate 200, filling a dielectric layer in the shallow trench to form the shallow trench isolation structure 201, and the shallow trench isolation structure 201 isolates the first region I and the second region II.
[0047] In this embodiment, before filling the dielectric layer, an adhesion layer 202 is formed on the sidewall and bottom of the shallow trench and the surface of the substrate 200 . The adhesion layer 202 can serve as a gate oxide layer of the gate structure.
[0048] Please refer to Figure 6 An initial first gate dielectric layer 203 is formed on the surface of the substrate 200 , an initial second gate dielectric layer 204 is formed on the surface of the initial first gate dielectric layer 203 , and an initial gate layer 205 is formed on the surface of the initial second gate dielectric layer 204 .
[0049] The black dots in the figure represent doping ions.
[0050] In this embodiment, the initial gate layer 205 of the first region I is ion doped, wherein the doped ions include phosphorus or boron, and the concentration of the doped ions is 2·10 15 / cm 2 .
[0051] In this embodiment, the concentration of doped ions is selected within this range for the purpose of reducing the resistance of the initial gate layer 205 (polysilicon), and subsequently a silicide layer 211 will be formed to connect with the contact hole to reduce the contact resistance.
[0052] In this embodiment, the material of the initial first gate dielectric layer 203 includes hafnium dioxide.
[0053] In this embodiment, the material of the initial second gate dielectric layer 204 includes titanium nitride.
[0054] In this embodiment, the material of the initial gate layer 205 includes polysilicon.
[0055] In this embodiment, an initial first gate dielectric layer 203 is formed on the surfaces of the adhesion layer 202 and the shallow trench isolation structure 201 .
[0056] Please refer to Figure 7 A patterned layer 206 is formed on the surface of the initial gate layer 205, and the initial gate layer 205, the initial second gate dielectric layer 204 and the initial first gate dielectric layer 203 are etched in sequence using the patterned layer 206 as a mask, and a first gate dielectric layer 203a, a second gate dielectric layer 204a and a first gate 205a are formed in sequence on the first region I, and a groove 207 is formed in a direction perpendicular to the surface of the substrate 200 and penetrating the first gate 205a.
[0057] In this embodiment, the surface of the adhesion layer 202 is exposed at the bottom of the groove 207, replacing the traditional groove 207 where a partial thickness of the initial gate layer 205 is in contact with the initial second gate dielectric layer 204 at the bottom, thereby eliminating the problem of interface state traps generated at the bottom of the groove 207 and improving the performance and uniformity of the high voltage or medium voltage (HV / MV) device containing the groove 207.
[0058] In this embodiment, the number of the grooves 207 is three.
[0059] In other embodiments, the number of the grooves 207 may be four, five, two, or other different numbers, which can be set according to actual needs.
[0060] In this embodiment, three grooves 207 are distributed in parallel.
[0061] In this embodiment, the width of the trench 207 is in the range of 50 nm to 100 nm.
[0062] In this embodiment, during the process of patterning the initial gate layer 205, the initial second gate dielectric layer 204 and the initial first gate dielectric layer 203, a groove 207 is simultaneously formed through the first gate 205a in a direction perpendicular to the surface of the substrate 200. This omits the additional mask required for the traditional formation of the groove 207, thereby saving costs and shortening the production cycle.
[0063] Please continue to refer to Figure 7 At the same time, a first gate dielectric layer 203a, a second gate dielectric layer 204a and a first gate electrode 205a are sequentially formed on the second region II.
[0064] In this embodiment, the formation of the trench 207 and the formation of the first gate 205 a use the same photomask, which reduces the use of multiple layers of photomasks and simplifies the process flow.
[0065] Please refer to Figure 8 , a supporting layer 208 is formed in the groove 207 .
[0066] In this embodiment, a support layer 208 is formed in the groove 207, and the support layer 208 completely fills the groove 207. In the subsequent planarization process, the support effect of the support layer 208 can avoid the depression problem of the first region I during the planarization process.
[0067] In this embodiment, the material of the support layer 208 is silicon nitride.
[0068] In other embodiments, the material of the support layer 208 may also be silicon oxide, silicon carbide, silicon carbide nitride, etc.
[0069] In this embodiment, the support layer 208 fills the trench 207 and covers the sidewalls of the first gate 205 a , the second gate dielectric layer 204 a and the first gate dielectric layer 203 a , thereby protecting the first gate 205 a .
[0070] Please refer to Figures 9 to 11 A first source and drain 209 is formed in the substrate 200 on both sides of the first gate 205a in the first region I, and a second source and drain 210 is formed in the substrate 200 on both sides of the first gate 205a in the second region II.
[0071] Fig.10 and Fig.11 yes Fig. 9 A top view of the first zone I; Fig. 9 The viewing direction and Figure 8 The viewing direction is the same.
[0072] In this embodiment, please refer to Fig.10 , the extending direction of the trench 207 is parallel to the extending direction of the first source and drain 209, wherein Fig.10 In order to show the relationship between the trench 207 and the first gate 205 a , only a schematic diagram of the relationship between the trench 207 , the first gate 205 a and the first source and drain 209 is shown.
[0073] For other embodiments, please refer to Fig.11 , the extension direction of the trench 207 is perpendicular to the extension direction of the first source and drain 209 .
[0074] In this embodiment, please refer to Fig.10 The length of the first gate 205a in the extension direction parallel to the groove 207 is greater than the length of the groove 207 in the extension direction, and the width of the first gate 205a in the extension direction perpendicular to the groove 207 is greater than the width of the groove 207 in the extension direction, wherein the extension direction is the Y-axis direction, and the direction perpendicular to the extension direction is the X-axis direction.
[0075] Please continue to refer to Fig. 9 A second source and drain 210 is formed in the substrate 200 on both sides of the first gate 205 a in the second region II, and a silicide layer 211 is formed on the surface of the first source and drain 209 and the surface of the second source and drain 210 .
[0076] Please refer to Fig.12 , remove the first gate 205a on the second region II to form a gate opening, exposing the surface of the second gate dielectric layer 204a on the second region II at the bottom of the gate opening; form a second gate 212 in the gate opening, and the material of the second gate 212 is a metal material.
[0077] Accordingly, the present invention also provides a semiconductor structure, please refer to Fig.12 , including a substrate 200, the substrate 200 includes a first region I, a first gate 205a located on the first region I, the first gate 205a has a plurality of grooves 207 penetrating the first gate 205a in a direction perpendicular to the surface of the substrate 200, and a support layer 208 located in the grooves 207.
[0078] In this embodiment, the material of the support layer 208 is silicon nitride.
[0079] In other embodiments, the material of the support layer 208 may also be silicon oxide, silicon carbide, silicon carbide nitride, etc.
[0080] In this embodiment, a support layer 208 is formed in the groove 207, and the support layer 208 completely fills the groove 207. In the subsequent planarization process, the support effect of the support layer 208 can avoid the depression problem of the first region I during the planarization process.
[0081] In this embodiment, the surface of the adhesion layer 202 is exposed at the bottom of the groove 207, replacing the traditional groove 207 where a partial thickness of the initial gate layer 205 is in contact with the initial second gate dielectric layer 204, thereby eliminating the problem of electric traps generated at the interface at the bottom of the groove 207 and improving the performance and uniformity of the high voltage or medium voltage (HV / MV) device containing the groove 207.
[0082] In this embodiment, the substrate 200 further includes: a second region II adjacent to the first region I, and a second gate 212 located on the second region II.
[0083] In this embodiment, it also includes: a first gate dielectric layer 203a located on the surface of the first region I, a second gate dielectric layer 204a located on the surface of the first gate dielectric layer 203a, and a first gate 205a located on the surface of the second gate dielectric layer 204a; the material of the first gate dielectric layer 203a includes hafnium dioxide, and the material of the second gate dielectric layer 204a includes titanium nitride.
[0084] In this embodiment, the material of the first gate 205a is polysilicon, and the polysilicon contains doping ions. The types of doping ions include phosphorus or boron. The concentration of the doping ions is 2.10 15 / cm 2 .
[0085] In this embodiment, the second gate 212 is located on the surface of the second gate dielectric layer 204 a on the second region II, and the material of the second gate is metal.
[0086] In this embodiment, a shallow trench 207 isolation structure 201 is further included in the substrate 200 , and the shallow trench 207 isolation structure 201 isolates the first region I and the second region II.
[0087] In this embodiment, it further includes: a first source and a drain 209 located in the substrate 200 at two sides of the first gate 205 a .
[0088] In this embodiment, a second source and drain 210 is further included in the substrate 200 and is located at both sides of the second gate 212 .
[0089] In this embodiment, a silicide layer 211 is formed on the surface of the first source drain 209 and the surface of the second source drain 210 .
[0090] In this embodiment, please refer to Fig.10 , the extension direction of the trench 207 is parallel to the extension direction of the first source and drain 209 .
[0091] For other embodiments, please refer to Fig.11 , the extension direction of the trench 207 is perpendicular to the extension direction of the first source and drain 209 .
[0092] In this embodiment, please refer to Fig.10 The length of the first gate 205a in a direction parallel to the extension of the trench 207 is greater than the length of the trench 207 in the extension direction, and the width of the first gate 205a in a direction perpendicular to the extension of the trench 207 is greater than the width of the trench 207 in the extension direction.
[0093] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.
Claims
1. A semiconductor structure, characterized in that: include: a substrate comprising a first region; A first gate located on the first region, wherein the first gate has a plurality of grooves penetrating the first gate in a direction perpendicular to the surface of the substrate; A support layer is located within the groove.
2. The semiconductor structure according to claim 1, wherein: Also includes: A first source and a drain are respectively located in the substrate at two sides of the first gate.
3. The semiconductor structure according to claim 2, wherein: An extension direction of the trench is parallel to an extension direction of the first source and drain, or an extension direction of the trench is perpendicular to an extension direction of the first source and drain.
4. The semiconductor structure according to claim 1, wherein: The length of the first gate in a direction parallel to an extension of the trench is greater than the length of the trench in the extension direction, and the width of the first gate in a direction perpendicular to an extension of the trench is greater than the width of the trench in the extension direction.
5. The semiconductor structure according to claim 1, wherein: The substrate further includes: a second region adjacent to the first region, a second gate located on the second region, and second sources and drains located in the substrate at both sides of the second gate.
6. The semiconductor structure according to claim 5, characterized in that It also includes a shallow trench isolation structure located in the substrate, wherein the shallow trench isolation structure isolates the first region and the second region.
7. The semiconductor structure according to claim 6, wherein: Also includes: A first gate dielectric layer located on a surface of the first region, a second gate dielectric layer located on a surface of the first gate dielectric layer, and the first gate is located on a surface of the second gate dielectric layer; The material of the first gate dielectric layer includes hafnium dioxide, and the material of the second gate dielectric layer includes titanium nitride.
8. The semiconductor structure according to claim 7, wherein: The second gate is located on the surface of the second gate dielectric layer on the second region, and the material of the second gate is metal.
9. The semiconductor structure according to claim 1, wherein: The material of the first gate is polysilicon, the polysilicon contains doping ions, the type of the doping ions includes phosphorus or boron, and the concentration of the doping ions is 2·10 15 / cm 2 .
10. A method for forming a semiconductor structure, characterized in that: include: providing a substrate, the substrate comprising a first region; forming a first gate on the substrate in the first region; forming a plurality of grooves in the first gate and penetrating the first gate in a direction perpendicular to the surface of the substrate; A support layer is formed in the trench.
11. The method for forming a semiconductor structure according to claim 10, wherein: The method also includes forming a first source and a drain in the substrate on both sides of the first gate in the first region.
12. The method for forming a semiconductor structure according to claim 11, wherein: An extension direction of the trench is parallel to an extension direction of the first source and drain, or an extension direction of the trench is perpendicular to an extension direction of the first source and drain.
13. The method for forming a semiconductor structure according to claim 10, wherein: The length of the first gate in a direction parallel to an extension of the trench is greater than the length of the trench in the extension direction, and the width of the first gate in a direction perpendicular to an extension of the trench is greater than the width of the trench in the extension direction.
14. The method for forming a semiconductor structure according to claim 11, wherein: The substrate further includes a second region adjacent to the first region, the length of the first region is greater than the length of the second region, a second gate is formed on the second region, and a second source and drain are formed in the substrate on both sides of the second gate.
15. The method for forming a semiconductor structure according to claim 14, wherein: Before forming the first gate, the method further includes: forming an initial first gate dielectric layer on the surface of the substrate; forming an initial second gate dielectric layer on the surface of the initial first gate dielectric layer; An initial gate layer is formed on the surface of the initial second gate dielectric layer.
16. The method for forming a semiconductor structure according to claim 15, wherein: The step of forming the groove comprises: forming a patterned layer on a surface of the initial gate layer; Using the patterned layer as a mask, the initial gate layer, the initial second gate dielectric layer and the initial first gate dielectric layer are etched in sequence, and a first gate dielectric layer, a second gate dielectric layer and a first gate are formed in sequence on the first region, and the groove penetrating the first gate is formed in a direction perpendicular to the substrate surface; and a first gate dielectric layer, a second gate dielectric layer and a first gate are formed in sequence on the second region.
17. The method for forming a semiconductor structure according to claim 16, wherein: The method further includes forming a second source drain in the substrate at both sides of the first gate in the second region, and forming a silicide layer on a surface of the first source drain and a surface of the second source drain.
18. The method for forming a semiconductor structure according to claim 17, wherein: The method also includes removing the first gate on the second region to form a gate opening, exposing the surface of the second gate dielectric layer on the second region at the bottom of the gate opening; and forming a second gate in the gate opening, wherein the material of the second gate is a metal material.
19. The method for forming a semiconductor structure according to claim 10, wherein: The material of the support layer includes one or a combination of silicon nitride, silicon oxide, silicon carbide, and silicon carbide nitride.
20. The method for forming a semiconductor structure according to claim 10, wherein: The material of the first gate is polysilicon, and the polysilicon contains doping ions, and the types of the doping ions include phosphorus or boron, and the concentration of the doping ions is 2·10 15 / cm 2 .