Group III nitride transistor devices and methods of making group III nitride transistor devices

Abstract

There is provided a Group III nitride transistor device including: a Group III nitride substrate including a first main surface, a Group III nitride channel layer, and a Group III nitride barrier layer; a plurality of transistor cells; and a metallization structure including a first conductive layer and a second conductive layer. For each transistor cell, the first conductive layer includes source and drain fingers, and the second conductive layer includes a source bus line and a drain bus line. A source bus extends between and electrically connects the source fingers and extends over and electrically insulated from the drain fingers. A drain bus extends between and electrically connects the drain fingers and extends over and electrically insulated from the source fingers. In at least one transistor unit, the overlapping area between the source finger and the source bus line is larger than the overlapping area between the same source finger and the drain bus line and / or the overlapping area between the drain finger and the drain bus line is larger than the overlapping area between the same drain finger and the source bus line.

Description

Technical Field

[0001] The present invention relates to a III-nitride transistor device and a method of manufacturing a III-nitride transistor device. Background Art

[0002] To date, transistors used in power electronics applications have generally been fabricated using silicon (Si) semiconductor materials. Common transistor devices used in power applications include Si Si power MOSFETs and Si insulated gate bipolar transistors (IGBTs). More recently, silicon carbide (SiC) power devices have been considered. III-N semiconductor devices such as gallium nitride (GaN) devices are becoming attractive candidates to carry high currents, support high voltages, and provide very low on-resistance and fast switching times. Further improvements to III-nitride transistor devices are expected. Summary of the invention

[0003] According to the present invention, a III-nitride transistor device is provided, comprising: a III-nitride substrate, which comprises a first main surface, a III-nitride channel layer and a III-nitride barrier layer, wherein the III-nitride barrier layer is arranged on the III-nitride channel layer and a heterojunction is formed between the III-nitride barrier layer and the III-nitride channel layer; a plurality of transistor cells; and a metallization structure, which comprises a first conductive layer and a second conductive layer. For each transistor cell, the first conductive layer comprises a source finger and a drain finger arranged on the first main surface, and the second conductive layer comprises a source bus and a drain bus. The source bus extends between the source fingers of the plurality of transistor cells and electrically connects the source fingers of the plurality of transistor cells, and extends over the drain fingers and is electrically insulated from the drain fingers. The drain bus line extends between the drain fingers of the plurality of transistor cells and electrically connects the drain fingers of the plurality of transistor cells, and extends over the source fingers and is electrically insulated from the source fingers. In at least one transistor cell, the overlap area between the source finger and the source bus line is greater than the overlap area between the same source finger and the drain bus line, and / or in at least one transistor cell, the overlap area between the drain finger and the drain bus line is greater than the overlap area between the same drain finger and the source bus line.

[0004] The III-nitride transistor device is a lateral device, and a metallization structure is used to electrically couple a plurality of transistor cells in parallel. The III-nitride transistor device has reduced switching losses because the output capacitance CDS is reduced by a metallization structure having an overlap area between a drain finger and a source bus that is smaller than an overlap area between the drain finger and the drain bus, and / or having an overlap area between a source finger and a drain bus that is smaller than an overlap area between the source finger and the source bus.

[0005] The first and second conductive layers and thus the source and drain fingers of the first conductive layer and the source and drain busses of the second conductive layer are arranged in two horizontal or lateral planes spaced apart in a vertical direction. The source busses overlap, i.e. extend over and cover a portion of the source and drain fingers, and the drain busses overlap, i.e. extend over and cover a portion of the source and drain fingers.

[0006] The second conductive layer is arranged on the first main surface above the first conductive layer, so that the source bus is arranged above the source fingers and the drain fingers and extends thereon, whereby the source bus is electrically connected to the source fingers and is electrically insulated from the drain fingers, and the drain bus is arranged above the source fingers and extends thereon, whereby the drain bus is electrically connected to the drain fingers and is electrically insulated from the source fingers.

[0007] The metallization structure may further include at least one electrically insulating layer disposed between the first and second conductive layers. The source bus may be electrically connected to each source finger of the plurality of transistor cells through one or more conductive vias extending between each source finger and the source bus. The drain bus may be electrically connected to each drain finger of the plurality of transistor cells through one or more conductive vias extending between each drain finger and the drain bus.

[0008] The source bus line is electrically insulated from the drain fingers by an intervening electrical insulating layer, and the drain bus line is electrically insulated from the source fingers by an intervening electrical insulating layer.

[0009] The first and second electrically conductive layers and the electrically insulating layer may each comprise two or more sub-layers.

[0010] The III-nitride transistor device may also include a gate and is a lateral device having a source, a drain and a gate, which are arranged on the first main surface. In each transistor unit of the III-nitride transistor device, the gate is arranged laterally between the source and the drain. The source and / or the drain can be shared by two adjacent transistor units.

[0011] In some embodiments, the gate of each transistor cell comprises a gate finger arranged on the first main surface.The gate finger may be arranged laterally between a source contact and a drain contact arranged on the first main surface.

[0012] The source contact, the drain contact and the gate fingers may be elongated and have a stripe-like structure and extend substantially parallel to each other. The gate fingers may be formed of a different material than the source contact and the drain contact.

[0013] The III-nitride transistor device may include a core conductive layer including a source contact and a drain contact. The core conductive layer is arranged on a first main surface between a first conductive layer of a metallization structure and a first main surface of the III-nitride substrate. The gate finger may be separated from the core conductive layer and the first conductive layer. One or more passivation layers are arranged on the core conductive layer and the gate finger, and the first conductive layer of the metallization structure is arranged on the passivation layer (one or more).

[0014] The source contact extends parallel to and below the source fingers of the first conductive layer, and the drain contact extends parallel to and below the drain fingers of the first conductive layer. The source contact is electrically connected to the source fingers by an elongated conductive via extending through at least one passivation layer. The drain contact is electrically connected to the drain fingers by an elongated conductive via extending through at least one passivation layer.

[0015] The III-nitride transistor device may be a HEMT (High Electron Mobility Transistor) in which a two-dimensional charge gas, such as a two-dimensional electron gas or a two-dimensional hole gas, is formed at a heterojunction between a channel layer and a barrier layer. The III-nitride channel layer may be formed of GaN, and the III-nitride barrier layer may be formed of AlGaN.

[0016] In some embodiments, the area of ​​the portion of the source finger located under the drain bus is smaller than the area of ​​the source finger located under the source bus. The overlap area between a single source finger and the drain bus can be reduced in various ways. In some embodiments, the lateral shape of the source finger in the first conductive layer is modified.

[0017] In some embodiments, the area of ​​the portion of the drain finger located below the source bus is smaller than the area of ​​the drain finger located below the drain bus. The overlap area between a single drain finger and the source bus can also be reduced in various ways. In some embodiments, the lateral shape of the drain finger in the first conductive layer is modified.

[0018] In some embodiments, each source finger has a length and a width. The length is greater than the width, thereby forming a strip-like finger shape. The width of a first portion of a source finger located below the drain bus is less than the width of a second portion of the source finger located below the source bus. In some embodiments, each drain finger has a length and a width. The length is greater than the width, thereby forming a strip-like finger shape. The width of a first portion of a drain finger located below the source bus is less than the width of a second portion of the drain finger located below the drain bus.

[0019] In some embodiments, a first portion of the source finger below the drain bus has a tapered shape in a plan view, such as a triangle or a funnel shape in a plan view, and / or a first portion of the drain finger below the source bus has a tapered shape in a plan view, such as a triangle or a funnel shape in a plan view.

[0020] In some embodiments, the source finger includes an opening in the middle of its length and width, and the opening is located below the drain bus, and / or the drain finger includes an opening in the middle of its length and width, and the opening is located below the source bus. The opening may also be referred to as a hole or a hole, and extends through the thickness of the source finger or the drain finger.

[0021] The above-described structures and modified shapes for the source and drain fingers may be combined to reduce the overlap area with the drain bus line and the source bus line, respectively.

[0022] The source bus and the drain bus are laterally spaced apart from each other, for example, by a gap in the second conductive layer. In some embodiments, the source bus has a length and a width, the length extending substantially perpendicular to the length of the source fingers, and the width is substantially the same in a portion located above the source fingers and in a portion located above the drain fingers, and / or the drain bus has a length and a width, the length extending substantially perpendicular to the length of the source fingers, and the width is substantially the same in a portion located above the source fingers and in a portion located above the drain fingers. The source bus and the drain bus may be substantially rectangular in shape in a plan view, with a length greater than a corresponding width. The source bus and the drain bus may extend parallel to each other.

[0023] The above-described structures and modified shapes for the source and drain fingers may be combined with the above-described structures and modified shapes for the source and drain bus lines.

[0024] In some embodiments, each transistor cell further comprises a gate finger disposed on the first main surface, and the gate fingers each have a length and a width, wherein the width in the portion of the gate finger located under the source bus and the portion of the gate finger located under the drain bus is substantially the same. The length of the gate finger is greater than the width. The gate finger extends substantially parallel to the source finger and the drain finger. One gate finger is disposed between the source finger and the drain finger.

[0025] In some embodiments, the metallization structure further includes an electrically insulating layer arranged between the first and second conductive layers, wherein at least two source fingers of the plurality of transistor cells are each electrically connected to a source bus via a conductive via extending through the electrically insulating layer, and / or wherein at least two drain fingers of the plurality of transistor cells are each electrically connected to a drain bus via a conductive via.

[0026] In some embodiments, a width of a portion of the source finger located under the source bus line is greater than a width of a portion of the drain finger located under the drain bus line.

[0027] In some embodiments, the minimum width of the source fingers is equal to or greater than the minimum width of the drain fingers.

[0028] In some embodiments, the source bus is laterally spaced apart from the drain bus by a gap, wherein a width of a portion of the source fingers in the gap is substantially the same as a width of a portion of the source fingers under the source bus, and / or a width of a portion of the drain fingers in the gap is substantially the same as a width of a portion of the drain fingers under the drain bus.

[0029] In some embodiments, the overlapping area between each source finger and the drain bus line can be reduced by modifying the shape of the drain bus line in the second conductive layer. The overlapping area between each drain finger and the source bus line can be reduced by modifying the shape of the source bus line in the second conductive layer.

[0030] In some embodiments, the source bus and / or the drain bus include at least one hole. One or more holes may be positioned laterally adjacent to a conductive via extending between a source finger and the source bus and / or between a drain finger and the drain bus.

[0031] The III-nitride substrate may further include a III-nitride buffer structure disposed on the substrate, which has a composition different from that of the III-nitride. In some embodiments, the III-nitride channel layer is disposed directly on the buffer structure. In some embodiments, a back barrier layer forming a heterojunction with the III-nitride channel layer is disposed between the III-nitride channel layer and the buffer layer.

[0032] The substrate may include an upper surface or growth surface capable of supporting epitaxial growth of one or more Group III nitride based layers. In some embodiments, the substrate is a foreign substrate, i.e., formed of a material different from the Group III nitride material, and includes an upper surface or growth surface capable of supporting epitaxial growth of one or more Group III nitride based layers.

[0033] The common substrate may be formed of silicon, and may be formed of single crystal silicon or an epitaxial silicon layer (eg, sapphire).The buffer structure may include a transition layer on a growth surface of the substrate and a super lattice structure on the transition layer.

[0034] The first and second conductive layers may be formed of copper or a copper alloy.The electrically insulating layer may be formed of an oxide such as silicon oxide and / or a nitride such as silicon nitride.

[0035] According to the present invention, a method for manufacturing a III-nitride transistor is also provided. The method includes providing a III-nitride transistor having an initial design. The initial design includes: a III-nitride substrate including a first main surface, a III-nitride channel layer, and a III-nitride barrier layer, the III-nitride barrier layer being arranged on the III-nitride channel layer and forming a heterojunction between the III-nitride barrier layer and the III-nitride channel layer; a plurality of transistor cells; and a metallization structure including a first conductive layer and a second conductive layer. For each transistor cell, the first conductive layer includes a source finger and a drain finger on the first main surface. The second conductive layer includes a source bus and a drain bus. The source bus extends between and electrically connects the source fingers of the plurality of transistor cells, and extends on and electrically insulated from the drain fingers, so that for each transistor cell, a first initial overlap area between the drain finger and the source bus is formed. The drain bus extends between and electrically connects the drain fingers of the plurality of transistor cells and extends over and is electrically insulated from the source fingers, so that for each transistor cell, a second initial overlap area between the source fingers and the drain bus is formed. The method also includes measuring the capacitance between the source fingers and the drain bus in the initial design and / or measuring the capacitance between the drain fingers and the source bus in the initial design, measuring the on-state resistance of the III-nitride transistor device in the initial design, locally reducing the first and / or second initial overlap area, and forming a first and / or second modified overlap area, and generating a modified design with a reduced first and / or second overlap area.

[0036] In some embodiments, the method continues by outputting a data set including the modified design. The data set may be used to fabricate one or more photolithography masks or to structure these photolithography masks for forming source and drain fingers.

[0037] In some embodiments, the method further includes measuring new capacitance between the source fingers and the drain bus line in the modified design and / or measuring new capacitance between the drain fingers and the source bus line in the modified design.

[0038] In some embodiments, the method further includes forming source fingers and / or drain fingers according to the modified design.

[0039] In some embodiments, capacitance and on-state resistance between source fingers and drain bus of the III-nitride transistor device in an initial design are measured, and a first initial overlap area is reduced to form a first modified overlap area. In some embodiments, capacitance and on-state resistance between drain fingers and source bus of the III-nitride transistor device in an initial design are measured, and a second initial overlap area is reduced to form a second modified overlap area.

[0040] In some embodiments, the first and / or second initial overlap area is locally reduced by reducing the area of ​​one or both of the source fingers and the drain bus in the first initial overlap area and / or reducing the area of ​​one or both of the drain fingers and the source bus in the second initial overlap area.

[0041] In some embodiments, in an initial design, the source fingers have an initial width, an initial length, and an initial lateral shape. In some embodiments, the initial lateral shape is rectangular, and the area of ​​the source fingers is reduced by reducing the initial width of the source fingers in the first initial overlap area without reducing the initial length, and / or by introducing a hole in between the initial length and initial width of the source fingers in the first initial overlap area, and / or by forming a tapered shape from the rectangular initial lateral shape in the first initial overlap area.

[0042] In some embodiments, in the initial design, the drain finger has an initial width, an initial length, and an initial lateral shape. In some embodiments, the initial lateral shape is rectangular, and the area of ​​the drain finger is reduced by reducing the initial width of the drain finger in the second initial overlap area without reducing the initial length, and / or by introducing a hole in between the initial length and the initial width of the drain finger in the second initial overlap area, and / or by forming a tapered shape from the rectangular initial lateral shape in the second initial overlap area.

[0043] In some embodiments, the overlap area between a source finger and a source bus is greater than the overlap area between the same source finger and a drain bus, and / or the overlap area between a drain finger and a drain bus is greater than the overlap area between the same drain finger and a source bus.

[0044] In some embodiments, a first initial overlap area between a source finger and a drain bus is reduced compared to an overlap area between the same source finger and the source bus, and / or a second initial overlap area between a drain finger and a source bus is reduced compared to an overlap area between the same drain finger and the drain bus.

[0045] In some embodiments, in an initial design, the drain bus has an initial area, and the method further includes forming at least one hole in the drain bus and / or removing a peripheral portion of the drain bus. In some embodiments, in an initial design, the source bus has an initial area, and the method further includes forming at least one hole in the source bus and / or removing a peripheral portion of the source bus. The peripheral areas of the source bus and the drain bus may be laterally located outside the active switching area of ​​the transistor device, and the holes may be located above and within the lateral areas of the active switching area of ​​the transistor device.

[0046] Portions of the drain bus outside the active switching area of ​​the transistor device may be removed in a region laterally adjacent to the distal ends of the source and drain fingers and / or adjacent to the length of the source and drain fingers and / or in a peripheral region of the substrate. Portions of the source bus may be removed in a region laterally adjacent to the distal ends of the source and drain fingers and / or adjacent to the length of the source and drain fingers and / or in a peripheral region of the substrate.

[0047] In some embodiments, the relationship between the on-state resistance and the output capacitance is further optimized. In some embodiments, the method further includes measuring a new on-state resistance of the modified design. If the new capacitance is less than the initial capacitance and the on-state resistance is less than a predetermined threshold, the lateral size and shape of the source fingers are output to the final design data set. The source fingers and drain fingers are then formed according to the final design data set. If the new capacitance is less than the initial capacitance and the on-state resistance is equal to or greater than the predetermined threshold, the area of ​​the source fingers is increased and the method is repeated by returning to measuring the on-state resistance and new capacitance of the new modified design.

[0048] Those skilled in the art will recognize additional features and advantages upon reading the following detailed description and upon reviewing the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] The elements in the drawings are not necessarily drawn to scale relative to each other. The same reference numerals represent corresponding similar parts. The features of the various illustrated embodiments may be combined unless they exclude each other. Exemplary embodiments are described in the drawings and detailed in the following description.

[0050] Figure 1 A circuit diagram of a transistor device is shown.

[0051] Figure 2A shows a top view of a comparative transistor device, and Figure 2B A cross-sectional view thereof is shown, Figure 2C shows a top view of a III-nitride transistor device according to an embodiment, and Figure 2D A cross-sectional view thereof is shown, and Figure 2E Shows Figure 2D Enlarged cross-sectional view of .

[0052] Figure 3A shows a top view of a comparative III-nitride transistor device, and Figure 3B A top view of a III-nitride transistor device according to an embodiment is shown.

[0053] Figure 4 A top view of a portion of a metallization structure of a III-nitride device according to an embodiment is shown.

[0054] Figure 5A shows a top view of a metallization structure of a comparative III-nitride transistor device, and Figure 5B A top view of a metallization structure of a III-nitride transistor device according to an embodiment is shown.

[0055] Figure 6 A flow chart illustrating a method of fabricating a III-nitride transistor device is shown. DETAILED DESCRIPTION

[0056] In the detailed description below, reference is made to the accompanying drawings, which form a part of the detailed description, and in which specific embodiments in which the present invention may be implemented are shown by way of illustration. In this regard, directional terms such as "top", "bottom", "front", "back", "front", "rear", etc. are used with reference to the orientation of the (one or more) accompanying drawings described. Because the components of the embodiments can be positioned in many different orientations, the directional terms are used for illustrative purposes and are by no means restrictive. It should be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present invention. The following detailed description thereof is not intended to be limiting, and the scope of the present invention is defined by the appended claims.

[0057] A number of exemplary embodiments will be explained below. In this case, identical structural features are denoted in the figures by identical or similar reference symbols. In the context of this specification, "lateral" or "lateral direction" is to be understood as meaning a direction or extent extending approximately parallel to the lateral extent of the semiconductor material or semiconductor carrier. The lateral direction thus extends approximately parallel to these surfaces or sides. In contrast, the term "vertical" or "vertical direction" is to be understood as a direction extending generally perpendicular to these surfaces or sides and therefore perpendicular to the lateral direction. The vertical direction thus extends in the thickness direction of the semiconductor material or semiconductor carrier.

[0058] As used in this specification, when an element such as a layer, region, or substrate is referred to as being "on" or "extending onto" another element, it can be directly on or extending onto the other element, or intervening elements may also be present. In contrast, when an element is referred to as being "directly on" or "extending directly onto" another element, there are no intervening elements present.

[0059] As used in this specification, when an element is referred to as being "connected" or "coupled" to another element, it may be directly connected or coupled to the other element, or there may be intervening elements. Conversely, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements.

[0060] A depletion mode device, such as a high voltage depletion mode transistor, has a negative threshold voltage, which means it can conduct current at zero gate voltage. These devices are normally on. An enhancement mode device, such as a low voltage enhancement mode transistor, has a positive threshold voltage, which means it cannot conduct current at zero gate voltage and is normally off. Enhancement mode devices are not limited to low voltages and can also be high voltage devices.

[0061] As used herein, the phrase "Group III nitride" refers to a compound semiconductor comprising nitrogen (N) and at least one Group III element, such as aluminum (Al), gallium (Ga), indium (In), and boron (B), and including but not limited to any alloys thereof, such as aluminum gallium nitride (AlxGa ( 1-x ) N), Indium Gallium Nitride (InyGa ( 1-y ) N), aluminum indium gallium nitride (AlxInyGa ( 1-xy ) N), gallium arsenide phosphide nitride (GaAsaPbN(1-ab)) and aluminum indium gallium arsenide phosphide nitride (AlxInyGa(1-xy)AsaPbN(1-ab)). Aluminum gallium nitride and AlGaN refer to the compounds represented by the formula AlxGa( 1-x ) N describes the alloy, where 0 <x<1。

[0062] Figure 1 A circuit diagram of a Group III transistor device 10 including source (S), drain (D), and gate (G) terminals is shown. Figure 1 A capacitance CGD formed between the gate and the drain, a capacitance CGS formed between the gate and the source, and an output capacitance CDS formed between the drain and the source are also indicated.

[0063] The transistor device 10 includes a plurality of transistor cells formed in a semiconductor substrate and electrically coupled in parallel. The transistor device 10 also includes a metallization structure used to electrically connect the various transistor cells to each other and to provide a redistribution structure between the transistor cells and contact regions.

[0064] In order to reduce the switching losses, it is proposed to reduce the output capacitance CDS. In particular, it is proposed to reduce the output capacitance CDS by providing an improved metallization structure. The measures described herein can be used together with measures to reduce the on-state resistance (Ron) to reduce the overall losses of the III-nitride transistor device.

[0065] A lateral III-nitride transistor device, such as a HEMT, is provided, which is suitable for fast switching applications and has a metallization structure, the structure of which results in low Ron losses and lower switching losses. In order to reduce the switching losses, the effect of the metallization structure on the output capacitance CDS is taken into account by appropriate structuring of the metallization structure. The metallization structure can be designed as a compromise between Ron and output capacitance CDS.

[0066] In some embodiments, the metallization structure includes two metal layers arranged in a stack, wherein an interlayer dielectric is arranged between them in the stack. In some embodiments, the width of the first lower drain metal layer is reduced in an area with low current density and / or low Ron effect and / or the second source metal layer is located above. In some embodiments, the width of the first source metal layer is reduced in an area with low current density and / or low Ron effect and / or the second drain metal layer is located above. These measures can be used without changing the thickness of the interlayer dielectric arranged between the two metal layers, thereby avoiding process problems that may occur when forming conductive vias through thicker interlayer dielectrics.

[0067] Figure 2A A top view of a portion of a comparative III-nitride transistor device 20 is shown, and Figure 2B It shows that Figure 2A Cross-sectional view along line AA. Figure 2CA top view of a portion of a III-nitride transistor device 20 ′ according to an embodiment including a reduced output capacitance CDS is shown, and Figure 2D It shows that Figure 2C Cross-sectional view along line A'-A'. Figure 2E An enlarged cross-sectional view of a III-nitride transistor device 20 ′ is shown.

[0068] refer to Figure 2B , 2D 2E, the III-nitride transistor device 20, 20' includes a III-nitride substrate 21 having a first major surface 22, a III-nitride channel layer 23, and a III-nitride barrier layer 24 disposed on the III-nitride channel layer 23. The III-nitride barrier layer 24 and the channel layer 23 have different compositions and band gaps, so that a heterojunction is formed between the III-nitride barrier layer 24 and the III-nitride channel layer 23. For example, the III-nitride channel layer 23 can be formed of GaN, and the III-nitride barrier layer 24 can be formed of AlGaN. A two-dimensional charge gas such as a two-dimensional electron gas (2DEG) can be formed by spontaneous and piezoelectric polarization at the heterojunction 25, and is schematically indicated by a dotted line.

[0069] The III-nitride device 30 includes a plurality of transistor cells 26, each including a source contact 27, a drain contact 28, and a gate finger 29, which is laterally arranged between the source contact 27 and the drain contact 28 and formed on the first main surface 22. The source contact 27 and the drain contact 28 are part of a core conductive layer 33 arranged on the first main surface 22 and covered by a passivation layer 34. The source and drain contacts 27, 28 may be common to adjacent transistor cells 26, thereby forming a repeating pattern of source-gate-drain-gate-source-gate-drain on the first main surface 22. Each of the source contact 27, the drain contact 28, and the gate finger 29 may have an elongated strip-like structure having a length extending in the y direction and a width extending in the x direction using a Cartesian coordinate system, the length being longer than the width. The first main surface 22 is located in the xy plane, and the thickness of the III-nitride substrate 21 is in the z direction. Source contact 27, drain contact 28, and gate finger 29 extend substantially parallel to each other. Source contact 27 and drain contact 28 may form an ohmic contact with group III-nitride substrate 21.

[0070] from Figure 2EAs can be seen in the enlarged view of , the gate finger 29 can include a p-doped III-nitride layer 30 (e.g., p-doped gallium nitride) and a gate metal layer 31 disposed on the p-doped III-nitride layer 30. This structure of the gate finger 29 provides an enhancement mode device that is normally off. In other embodiments, the gate finger 29 may have a recessed gate structure, wherein the gate finger is formed in a recess formed in the first main surface 22, so that the thickness of the III-nitride barrier layer 24 below the recess is less than the thickness of the barrier layer laterally adjacent to the gate finger 29. The recessed gate structure can also be used to provide an enhancement mode device. The gate metal 31 can form an ohmic contact or a Schottky contact.

[0071] In some embodiments, the ohmic contact has a multilayer structure, such as Ti, Al, and a capping metal (e.g., Ti). The Schottky metal contact may be formed of one or more of TiN, Ti, W, WSix, Ta, TaN, Ni, Pd, Pt, and Ir. The III-nitride transistor device 20 may be a HEMT (high electron mobility transistor).

[0072] The III-nitride channel layer 23 is disposed on a buffer structure 32, which in turn is disposed on a substrate 21. The substrate 21 includes an upper surface or growth surface 34 capable of supporting epitaxial growth of one or more III-nitride-based layers. In some embodiments, the substrate 21 is a foreign substrate, i.e., formed of a material different from the III-nitride material, and includes an upper surface or growth surface 34 capable of supporting epitaxial growth of one or more III-nitride-based layers. The substrate 21 can be formed of silicon, such as single crystal silicon or an epitaxial silicon layer or sapphire.

[0073] In some embodiments not shown, the III-nitride-based semiconductor substrate 21 may further include a III-nitride back barrier layer disposed between the III-nitride channel layer 23 and the buffer structure 32. The channel layer 23 is formed on the back barrier layer and forms a heterojunction with the back barrier layer. The III-nitride barrier layer 24 is formed on one side of the III-nitride channel layer 23 opposite to the back barrier layer. The III-nitride back barrier layer has a different band gap from the III-nitride channel layer 23 and may include, for example, AlGaN. The composition of the AlGaN of the back barrier layer may be different from the composition of the AlGaN used for the barrier layer 24.

[0074] A typical transition or buffer structure 32 for a silicon substrate includes an AlN starting layer on the silicon substrate, which may have a thickness of several hundred nanometers, followed by an AlxGa ( 1-x )A sequence of N layers, each also a few hundred nanometers thick, is used, whereby the Al content of about 50-75% is reduced to 10-25% before growing the GaN layer or the AlGaN back barrier (if present). Alternatively, a superlattice buffer can be used. Again, an AlN starter layer on a silicon substrate is used. Depending on the superlattice chosen, AlN and AlxGaN are grown. ( 1-x ) A sequence of N pairs, where the AlN layer and the AlxGa ( 1-x ) The thickness of N is in the range of 2-25 nm. Depending on the desired breakdown voltage, the superlattice may include 20 to 100 pairs. Alternatively, AlxGa ( 1-x ) N-layer sequences can be used in conjunction with the above-described superlattices.

[0075] The III-nitride transistor device 20 also includes a metallization structure 40, which includes a first conductive layer 41 and a second conductive layer 42 arranged above the first conductive layer 41 in the z-direction. The first conductive layer 41 includes a source finger 43 and a drain finger 44 for each transistor cell 26. The source finger 43 and the drain finger 44 have an elongated strip-like structure with a length extending in the y-direction and a width extending in the x-direction, and extend substantially parallel to each other in the y-direction. The source finger 43 is vertically arranged above the source contact 27, wherein the lengths of the source contact 27 and the source finger 43 are aligned with each other, and the drain finger 44 is vertically arranged above the drain contact 28 and aligned therewith. Each source finger 43 is electrically connected to one of the underlying source contacts 27 through a conductive via 45, and each drain finger 44 is electrically connected to one of the underlying drain contacts 28 through a conductive via 45. The conductive via 45 can be elongated and extend over most of the length of the corresponding contact. A passivation layer 34 is formed between the die conductive layer 33 and the first conductive layer 41 , and a conductive via 45 extends through the passivation layer 34 .

[0076] The second conductive layer 42 includes a source bus line 46 and a drain bus line 47. The source bus line 46 extends substantially perpendicular to the length of the source fingers 43 and the drain fingers 44. The source bus line 46 may have an elongated strip-like structure, with a length extending in the x-direction and a width extending in the y-direction, the length being greater than the width. The source bus line 46 extends over the source fingers 43 of the plurality of transistor cells 26 and electrically connects them to each other, thereby also extending over the drain fingers 44 arranged in the middle between the source fingers 43. The source bus line 46 is electrically insulated from the drain fingers 44 by an electrically insulating layer 48, which forms an interlayer dielectric and is arranged between the first conductive layer 41 and the second conductive layer 42 of the metallization structure 40.

[0077] Similarly, drain bus 47 has an elongated strip-like structure, with a length extending in the x-direction and a width extending in the y-direction, the length being greater than the width, and extending substantially perpendicular to the lengths of source fingers 43 and drain fingers 44. Drain bus 47 extends over drain fingers 44 and electrically connects drain fingers 44 to each other, and also extends over and is electrically insulated from source fingers 43 in the middle of first conductive layer 41. Drain bus 47 is laterally spaced apart from source bus 46 in the y-direction and extends substantially parallel to source bus 46. In some embodiments, two or more source bus lines and two or more drain bus lines are provided.

[0078] Each source finger 43 is electrically connected to the source bus line 46 by a corresponding conductive via 49 extending through the dielectric layer 48 and between a first portion 51 of the source finger 43 disposed below the source bus line 46 and the overlying source bus line 46. The drain bus line 47 is electrically connected to each drain finger 44 by a corresponding conductive via 49 extending between a first portion 52 of the drain finger 44 vertically below the drain bus line 47 and the drain bus line 47. The conductive vias 49 are elongated and have a stripe-like shape having a length equal to or slightly less than the width of the corresponding bus lines 46, 47.

[0079] exist Figure 2A and 2B In the illustrated comparative III-nitride transistor device 20, the width of each source finger 43 is uniform along its length, so that each source finger 43 has a rectangular shape. Similarly, the width of each drain finger 44 is uniform along its length, so that each drain finger 44 has a rectangular shape. In some embodiments, the width of the source finger 43 is the same as the width of the drain finger 44.

[0080] As in Figure 2B As schematically indicated in the cross-sectional view of , capacitors 54 are formed between source fingers 43 and overlying drain bus 47 because the conductive source fingers 43 and the conductive drain bus 47 are separated by the electrically insulating layer 48. In the region of vertical overlap, the source fingers 43 and the drain bus 47 can each be considered to provide plates of a capacitor because there is a potential difference across the dielectric layer 48 between the source fingers 43 and the overlying drain bus 47. Similarly, capacitors 54 are also formed between drain fingers 44 and the overlying source bus 46. These capacitors 54 formed in the metallization structure 40 contribute to the overall value of the output capacitance CDS of the III-nitride transistor device 20.

[0081] Figure 2C shows a top view of a III-nitride transistor device 20 ′ according to an embodiment having reduced output capacitance, Figure 2D Shown along Figure 2C A cross-sectional view of the line A'-A' shown in FIG. Figure 2E An enlarged cross-sectional view is shown. In some embodiments, the reduction in the overlap area between source fingers 43 and the overlying drain bus 47 is achieved by reducing the lateral area of ​​source fingers 43 .

[0082] The III-transistor device 20′ differs from the comparative III-nitride transistor device 20 in that, in at least one transistor cell 26, the overlap area between the source finger 43 and the source bus line 46 is greater than the overlap area between the same source finger 43 and the drain bus line 47. The overlap area between each source finger 43 and the source bus line 46 may be greater than the overlap area between the source finger 43 and the drain bus line 47.

[0083] refer to Figure 2C 4. In a top view of the source finger 43, in some embodiments, the source finger 43 has a uniform width in a first portion 51 of its length, which is located below the source bus 46. The area of ​​the source finger 43 in the second portion 50 arranged below the drain bus 47 is reduced relative to the area of ​​the first portion 51 of the source finger 43 arranged below the source bus 46. In an embodiment, in the second portion 50 of the source finger 43 located below the drain bus 47, the source finger 43 has a tapered shape, that is, its width gradually decreases, for example, having a triangular or funnel shape. The width of the middle portion 55 of the source finger 43 arranged in the gap between the source bus 46 and the drain bus 47 and between the first and second portions 50, 51 is the same as its width in the first portion 51. The width of the source finger 43 decreases from the gap in the direction below the drain bus 37 to its distal end. The conductive via 49 extending between the source finger 43 and the source bus line 46 is located in the wider first portion 51 of the source finger 43 .

[0084] The drain finger 44 of at least one transistor cell 26 and in some embodiments all transistor cells 26 has an area of ​​overlap with the drain bus line 47 that is greater than the overlap area between the same drain finger 44 and the source bus line 46. The drain finger 44 has a uniform width in a first portion 52 that is arranged below the drain bus line 47 and overlaps the drain bus line 47. The width in a second portion 53 of the drain finger 44 that is located below and vertically overlaps the source bus line 46 is reduced relative to the area of ​​the first portion 52. The second portion 53 has a tapered shape in a plan view, such as a triangular or funnel shape. The middle portion 56 of the drain finger 44 that is arranged in a gap formed between the source bus line 46 and the drain bus line 47 and between the first and second portions 52, 53 has a width that is substantially the same as its width in the first portion 52.

[0085] Since the area of ​​the first portion 50 of the source finger 43 located below the drain bus 37 is smaller than that of the comparative transistor device 20, the capacitance CDS formed between the source finger 43 and the overlying drain bus 47 is reduced in the III-nitride transistor device 20'. Similarly, the capacitance CDS between the tapered second portion 53 of the drain finger 44 and the overlying source bus 46 is reduced compared to the arrangement of the comparative III-nitride transistor 20' because the overlap area between the drain finger 44 and the source bus 46 is reduced. The III-nitride transistor device 20' has a reduced output capacitance CDS and therefore has lower switching losses.

[0086] Figure 3A A top view of a portion of a comparative III-nitride transistor device 60 is shown, and Figure 3B A top view of a portion of a III-nitride transistor device 60 ′ is shown in accordance with an embodiment.

[0087] refer to Figure 3A , similar to the III-nitride transistor device 20, the width of each source finger 43 of the III-nitride transistor device 60 is uniform over its length, and thus is uniform in the first portion 51 disposed under the source bus line 46, in the middle portion 55, and in the second portion 50 disposed under the drain bus line 47. Similarly, the width of each drain finger 44 is uniform over its length, and thus is uniform in the second portion 53 disposed under the source bus line 46, in the middle portion 56, and in the first portion 52 disposed under the drain bus line 47. Figure 3A The comparative III-nitride transistor 60 shown in FIG. Figure 2A The comparative III-nitride transistor device 20 shown in is different in that the width of the source finger 43 over the entire length of the source finger 43 is greater than the width of the drain finger 44 over the entire length of the drain finger 44 .

[0088] refer to Figure 3B In the III-nitride transistor device 60' according to the embodiment, the second portion 50 of each source finger 43 has a tapered shape in the overlapping area between the second portion 50 of the source finger 43 and the overlying drain bus line 47. The width of the second portion 53 of the drain finger 44 vertically located below the source bus line 46 is smaller than its width in the first portion 52 of the drain finger 44 vertically located below the drain bus line 47. In some embodiments, the reduced width of the second portion 53 of the drain finger 44 located below the source bus line 46 may be substantially uniform in this portion 53, so that the second portion 53 has a rectangular shape, such as Figure 3BIn other embodiments, the second portion 53 may have a tapered shape. In addition, the width of the source finger 43 over the entire length of the source finger 43 is greater than the width of the drain finger 44 over the entire length of the drain finger 44.

[0089] The width of the middle portion 55 of the source finger 43 located in the gap between the source bus line 46 and the drain bus line 47 is substantially the same as the width of the middle portion 55 of the source finger 43 located in the gap between the source bus line 46 and the drain bus line 47 is substantially the same as the width of the first portion 51 of the drain finger 44 located vertically below the source bus line 46. Similarly, the width of the middle portion 56 of the drain finger 44 located in the gap between the source bus line 46 and the drain bus line 47 is substantially the same as the width of the first portion 52 of the drain finger 44 located vertically below the drain bus line 47.

[0090] For example, a first portion 51 of a source finger 43 under a source bus 46 may have a width of about 13 μm, and the source finger 43 may taper to a width of about 4 μm in a second portion 50 under a drain bus 47. A first portion 52 of a drain finger 44 under a drain bus 47 may have a width of about 5 μm, and a second portion 53 of the same drain finger 44 under a source bus 46 may have a width of about 4 μm.

[0091] Reducing the area of ​​source and drain fingers 43, 44 may result in a slight increase in on-state resistance Ron due to the reduction in conductive area. However, for a given reduction in the area of ​​source and drain fingers 43, 44, the resulting reduction in output capacitance is greater than the resulting increase in Ron. For the example given above, CDS may be reduced by 13% while Ron increases by less than 1%, thus providing a III-nitride transistor device having lower switching losses overall.

[0092] Therefore, in some embodiments, the reduction in area of ​​second portion 50 of source finger 43 under drain bus 47 and the reduction in area of ​​second portion 53 of drain finger 44 under source bus 46 are selected as a tradeoff between reducing CDS capacitance and increasing on-state resistance.

[0093] Figure 4 An arrangement for reducing the overlapping area between a portion of a source finger 43 arranged below a drain bus 47 and the drain bus is shown, and a top view of a portion of a lower first conductive layer 41 of a metallization structure 40, one source finger 43 and the underlying source contact 27 and a conductive contact via 45 is shown.

[0094] In this embodiment, the overlap area between the second portion 50 of the source finger 43 arranged under the drain bus 47 and the drain bus 47 is reduced by introducing one or more openings or holes 57 in the source finger 43 in the portion 51 of the source finger 43 arranged under the drain bus 47. The opening 57 may be in the shape of an elongated strip and located in the middle of the length and width of the source finger 43. In these embodiments, the conductive via 45 formed between the source contact 27 of the die conductive layer 33 and the overlying source finger 43 of the first conductive layer 41 of the metallization structure 40 is interrupted in the portion below the hole 57, so that the contact via 45 includes a plurality of portions spaced apart from each other along the length of the source contact 27. Similarly, one or more holes may also be located in the middle of the length and width of the drain finger 44 and located in the second portion 52 of the drain finger 44 arranged under the source bus 46. Conductive via 45 formed between drain contact 28 of die conductive layer 33 and overlying drain finger 44 of first conductive layer 41 of metallization structure 40 is interrupted in the portion below the hole such that contact via 45 includes multiple portions spaced apart from one another along the length of drain contact 28 .

[0095] The combination of one or more openings 57 introduced in the middle of the length and width of the source finger 43 and the drain finger 44 can be similar to that of, for example, Figure 2D and 3B The reduced widths of the source fingers 43 and drain fingers 44 described are used in combination.

[0096] In the above-described embodiments, the overlapping area between the source fingers 43 and the overlying drain bus 47 and / or between the drain fingers 44 and the overlying source bus 46 is reduced by reducing the area of ​​the source fingers 43 and the drain fingers in the lower first conductive layer 41 of the metallization structure 40. In other embodiments that may be used in addition to or in place of these embodiments, the overlapping area between the source fingers 43 and the overlying drain bus 47 and / or between the drain fingers 44 and the overlying source bus 46 is reduced by reducing the area of ​​the source bus 46 and the drain bus 47 in the upper second conductive layer 42 of the metallization structure 40.

[0097] Figure 5A A top view of a comparative III-nitride transistor device 20, 50 is shown, which may have Figure 2A Or the arrangement shown in 3A. Figure 5A An upper second conductive layer 42 of the metallization structure 40 is shown, including a drain bus 47 , a source bus 46 , and a gate pad 61 which is also part of the second conductive layer 42 .

[0098] The drain bus 47 has a rectangular form and includes one or more contact regions 62. The contact region 62 may be formed by an area of ​​the upper surface of the drain bus 47 that is exposed by an opening 63 in the passivation layer 64, which covers the surface of the source bus 46, the drain bus 47, the gate pad 61, and the upper surface of the III-nitride transistor device 20, 50. In some embodiments, the exposed contact region 62 includes one or more additional metal layers for promoting adhesion to the bonding wire or for improving the wettability and adhesion of the solder. The gate pad 61 may be arranged in a corner of the first main surface 22 of the transistor device 20, 50, or may be arranged in the middle of the length of one side of the first main surface 22 toward the periphery 65 of the first main surface 22. The source bus 43 has a substantially rectangular form and may extend around the gate pad 61 and be laterally spaced apart from the gate pad 61. The source bus 46 also includes one or more contact regions 62.

[0099] Figure 5B 1 shows a III-nitride transistor device 20 ′, 50 ′ according to an embodiment, wherein the overlap area between the source bus 46 and the lower portion of the drain finger 44 and between the drain bus 47 and the lower portion of the source finger 43 is reduced by reducing the area of ​​the source bus 46 and / or the drain bus 47 compared to the overlap area between the source bus 46 and the lower portion of the drain finger 44. Figure 5A The source fingers 43 and the drain fingers 44 of the first conductive layer 41 of the metallization structure 40 and the III-nitride substrate 21 with its core conductive layer 33 and passivation layer 34 may have the form described and shown with reference to FIG. 2 or FIG. 3 .

[0100] The area of ​​source bus line 46 and drain bus line 47 may be reduced by introducing one or more holes 66 and / or removing peripheral areas of source bus line 46 and drain bus line 47. At least a portion 67 of source bus line 46 extends over each underlying source finger 43 of transistor cell 26, thereby allowing conductive via 49 to be formed between the underlying second portion 50 of each source finger 43 and source bus line 46. Similarly, at least a portion 68 of drain bus line 47 extends over each drain finger 44, thereby allowing conductive via 49 to be formed between the underlying first portion 52 of each drain finger 44 and drain bus line 47.

[0101] The hole(s) 57 may be positioned, and the outer contours of the source bus 46 and the drain bus 47 positioned so that the position of the contact region 62 remains at a predetermined position, e.g. Figure 5A Position shown.

[0102] The output capacitance of metallization structure 40 may be reduced by reducing the overlap area between source fingers 43 and overlying drain bus 47 and drain fingers 44 and overlying source bus 46 without increasing the thickness of interlayer dielectric 48 disposed therebetween.

[0103] Figure 6 A method of manufacturing a III-nitride transistor device is shown in flowchart 100. The method may be used to manufacture any of the III-nitride transistor devices described herein, including the III-nitride transistor devices 20' and 50'.

[0104] In block 101, a lateral III-nitride transistor having an initial design is provided. The initial design includes a III-nitride substrate including a first main surface, a III-nitride channel layer forming a heterojunction therebetween and a III-nitride barrier layer on the III-nitride channel layer, a plurality of transistor cells, and a metallization structure on the first main surface, the metallization structure including a first conductive layer and a second conductive layer disposed on the first conductive layer. For each transistor cell, the first conductive layer includes source fingers and drain fingers on the first main surface, and the second conductive layer includes a source bus and a drain bus. The source bus extends between and electrically connects the source fingers of the plurality of transistor cells, and extends over and is electrically insulated from the drain fingers, such that for each transistor cell, a first initial overlap area between the drain fingers and the source bus of the transistor cell is formed. A drain bus extends between and electrically connects drain fingers of the plurality of transistor cells and extends over and is electrically insulated from source fingers such that for each transistor cell a second initial overlap area between the source fingers of the transistor cell and the drain bus is formed.

[0105] In block 102 , capacitance between initially designed source fingers and a drain bus line and / or capacitance between initially designed drain fingers and a source bus line is measured.

[0106] In block 103 , an on-state resistance of a III-nitride transistor device having an initial design is measured.

[0107] In block 104, the first initial overlap area and / or the second initial overlap area are locally reduced, and the first and / or second modified overlap areas and modified designs are formed. For example, the first initial overlap area may be locally reduced by reducing the area of ​​one or both of the source fingers and the drain bus in the first initial overlap area, and / or the second initial overlap area may be reduced by reducing the area of ​​one or both of the drain fingers and the source bus in the second initial overlap area. In another example, in the initial design, the source fingers have an initial width, an initial length, and an initial lateral shape, and the initial lateral shape is a rectangle. The area of ​​the source fingers is reduced by reducing the initial width of the source fingers in the first initial overlap area without reducing the initial length, and / or by introducing a hole between the initial length and the initial width of the source fingers in the first initial overlap area, and / or by forming a tapered shape from the rectangular initial lateral shape in the first initial overlap area. In another example, in the initial design, the drain fingers have an initial width, an initial length, and an initial lateral shape, and the initial lateral shape is a rectangle. The area of ​​the drain finger is reduced by reducing the initial width of the drain finger in the second initial overlap area without reducing the initial length, and / or by introducing a hole in the middle of the initial length and initial width of the drain finger in the second initial overlap area, and / or by reducing the initial width by forming a tapered shape from a rectangular initial lateral shape in the second initial overlap area.

[0108] In the modified design, the overlap area between a source finger and a source bus is larger than the overlap area between the same source finger and a drain bus, and / or the overlap area between a drain finger and a drain bus is larger than the overlap area between the same drain finger and a source bus.

[0109] In block 105 , new capacitances between source fingers and drain bus lines in the modified design and / or new capacitances between drain fingers and source bus lines in the modified design are measured.

[0110] In block 106, source fingers and / or drain fingers are formed according to the modified design. For example, one or more photolithography masks may be fabricated according to the modified design for fabricating source and / or drain fingers of a first conductive layer of a metallization structure of a III-nitride transistor device.

[0111] In an alternative method, after block 105, the method proceeds to block 107 instead of block 106, and the new on-state resistance of the modified design is measured. The method then proceeds to decision block 108. If the new capacitance is less than the initial capacitance and the on-state resistance is less than a predetermined threshold (yes), the method proceeds to block 109, and the lateral size and shape of the source finger and / or drain finger and / or source bus and / or drain bus are output in a final design data set. If in decision block 108, the new capacitance is less than the initial capacitance and the on-state resistance is equal to or greater than the predetermined threshold (no), the method proceeds to block 111, and the area of ​​the source finger and / or drain finger is increased, respectively, and the method returns to block 105, followed by block 107. After block 109, the method proceeds to block 110, and the source finger and drain finger are formed according to the final design data set. For example, the final design data set can be used to manufacture or structure a suitable photolithography mask for forming a metallization structure.

[0112] In an optional further method that may be performed as part of block 104 or block 111, the drain bus has an initial area and the source bus has an initial area, and the method further includes forming at least one hole in the drain bus and / or removing a peripheral portion of the drain bus and / or forming at least one hole in the source bus and / or removing a peripheral portion of the source bus. Portions of the drain bus may be removed in an area laterally adjacent to the distal ends of the source and drain fingers and / or adjacent to the length of the source and drain fingers and / or in a peripheral area of ​​the substrate. Portions of the source bus may be removed in an area laterally adjacent to the distal ends of the source and drain fingers and / or adjacent to the length of the source and drain fingers and / or in a peripheral area of ​​the substrate.

[0113] A lateral III-nitride transistor device suitable for fast switching applications, such as a HEMT, is provided. These lateral III-nitride transistor devices have a metallization structure that results in low Ron losses and lower switching losses. To reduce switching losses, the effect of the metallization structure on the output capacitance CDS is taken into account by appropriate structuring of the metallization structure. The metallization can be designed as a compromise between Ron and output capacitance CDS.

[0114] In some embodiments, the width of the first lower drain metal layer is reduced in areas with low current density and / or low Ron effect and / or where the second source metal layer is located above. In some embodiments, the width of the first source metal layer is reduced in areas with low current density and / or low Ron effect and / or where the second drain metal layer is located above. These measures can be used without changing the thickness of the interlayer dielectric disposed between the two metal layers, thereby avoiding process problems that may occur when forming conductive vias through thicker interlayer dielectrics.

[0115] For ease of description, spatially relative terms such as "below," "lower," "below," "above," "on," etc. are used to explain the positioning of one element relative to a second element. These terms are intended to include different orientations of the device in addition to those shown in the figures. In addition, terms such as "first," "second," etc. are also used to describe various elements, regions, parts, etc., and are not intended to be limiting. Throughout the description, the same terms refer to the same elements.

[0116] As used herein, the terms "having", "comprising", "including", "comprising", etc. are open terms that indicate the presence of the recited elements or features, but do not exclude additional elements or features. Unless the context clearly indicates otherwise, the articles "a", "an", and "the" are intended to include the plural as well as the singular. It should be understood that the features of the various embodiments described herein may be combined with each other unless otherwise specifically stated.

[0117] Although specific embodiments have been shown and described herein, it will be appreciated by those of ordinary skill in the art that various alternative and / or equivalent implementations may be substituted for the specific embodiments shown and described without departing from the scope of the present invention. This application is intended to cover any modifications or variations of the specific embodiments discussed herein. Therefore, the present invention is intended to be limited only by the claims and their equivalents.

Claims

1. A III-nitride transistor device, comprising: a group III nitride substrate comprising a first major surface, a group III nitride channel layer, and a group III nitride barrier layer, the group III nitride barrier layer being disposed on the group III nitride channel layer and forming a heterojunction between the group III nitride barrier layer and the group III nitride channel layer; a plurality of transistor cells; A metallization structure comprising a first conductive layer and a second conductive layer, wherein: For each transistor cell, the first conductive layer comprises a source finger and a drain finger on the first main surface, and The second conductive layer includes a source bus and a drain bus, wherein the source bus extends between the source fingers of the plurality of transistor cells and electrically connects the source fingers of the plurality of transistor cells, and extends over the drain fingers and is electrically insulated from the drain fingers, and the drain bus extends between the drain fingers of the plurality of transistor cells and electrically connects the drain fingers of the plurality of transistor cells, and extends over the source fingers and is electrically insulated from the source fingers, wherein in at least one transistor unit, an overlapping area between a source finger and a source bus is larger than an overlapping area between the same source finger and a drain bus, and / or In at least one transistor unit, an overlapping area between a drain finger and a drain bus is larger than an overlapping area between the same drain finger and a source bus.

2. The III-nitride transistor device according to claim 1, wherein: The source fingers each have a length and a width, and a portion of the source finger located below the drain bus has a width that is smaller than a width of another portion of the source finger located below the source bus, and / or The drain fingers each have a length and a width, and a portion of the drain finger located under the source bus line has a width that is smaller than a width of another portion of the drain finger located under the drain bus line.

3. The III-nitride transistor device according to claim 2, wherein: The portion of the source finger located below the drain bus line has a tapered shape, and / or The portion of the drain finger located below the source bus line has a tapered shape, and / or The source finger includes an opening midway between its length and width, and the opening is located below the drain bus, and / or The drain finger includes an opening midway between its length and width, and the opening is located below the source bus line.

4. The III-nitride transistor device according to any one of claims 1 to 3, The source bus line has a length and a width, the length extending substantially perpendicular to the length of the source fingers, and the width being substantially the same over the source fingers and over the drain fingers, and / or The drain bus line has a length and a width, the length extending substantially perpendicular to the length of the source fingers, and the width being substantially the same over the source fingers and over the drain fingers.

5. The III-nitride transistor device according to any one of claims 1 to 4, Each transistor unit further comprises a gate finger arranged on the first main surface, and each gate finger has a length and a width, wherein the widths of the gate fingers under the source bus and under the drain bus are substantially the same.

6. The III-nitride transistor device according to any one of claims 1 to 5, The metallization structure further comprises an electrically insulating layer arranged between the first and second conductive layers, wherein at least two source fingers of the plurality of transistor cells are each electrically connected to the source bus via a conductive via extending through the electrically insulating layer, and / or wherein at least two drain fingers of the plurality of transistor cells are each electrically connected to the drain bus via a conductive via.

7. The III-nitride transistor device according to any one of claims 2 to 6, wherein the width of the source finger under the source bus line is greater than the width of the drain finger under the drain bus line.

8. The III-nitride transistor device of any one of claims 2 to 7, wherein the source bus is spaced apart from the drain bus by a gap, wherein the width of the source finger in the gap is substantially the same as the width of the source finger below the source bus, and / or the width of the drain finger in the gap is substantially the same as the width of the drain finger below the drain bus.

9. The III-nitride transistor device of any one of claims 1 to 8, wherein the source bus and / or the drain bus comprises at least one hole.

10. A method for fabricating a Group III nitride transistor, the method comprising: A III-nitride transistor having an initial design is provided, the initial design comprising: a group III nitride substrate comprising a first major surface, a group III nitride channel layer and a group III nitride barrier layer forming a heterojunction therebetween, A plurality of transistor units, a metallization structure comprising a first conductive layer and a second conductive layer, wherein for each transistor cell, the first conductive layer comprises source and drain fingers on the first main surface, and the second conductive layer comprises a source bus and a drain bus, wherein the source bus extends between and electrically connects the source fingers of the plurality of transistor cells, and extends over and is electrically insulated from the drain fingers, so that for each transistor cell, a first initial overlap area between the drain fingers and the source bus is formed, and wherein the drain bus extends between and electrically connects the drain fingers of the plurality of transistor cells, and extends over and is electrically insulated from the source fingers, so that for each transistor cell, a second initial overlap area between the source fingers and the drain bus is formed; Measuring the capacitance between the source fingers and the drain bus line in the initial design, and / or measuring the capacitance between the drain fingers and the source bus line in the initial design; Measuring the on-state resistance of III-nitride transistor devices in an initial design; locally reducing the first and / or second initial overlap area and forming a first and / or second modified overlap area and a modified design; measuring new capacitance between source fingers and drain bus lines in the modified design, and / or measuring new capacitance between drain fingers and source bus lines in the modified design; According to the modified design, source fingers and / or drain fingers are formed.

11. The method of claim 10, wherein the first and / or second initial overlap area is locally reduced by reducing the area of ​​one or both of the source fingers and the drain bus line in the first initial overlap area and / or reducing the area of ​​one or both of the drain fingers and the source bus line in the second initial overlap area.

12. The method of claim 11 , wherein in an initial design, the source fingers have an initial width, an initial length, and an initial lateral shape, The initial lateral shape is rectangular, and the area of ​​the source fingers is reduced by reducing the initial width of the source fingers in the first initial overlapping area without reducing the initial length, and / or by introducing a hole between the initial length and the initial width of the source fingers in the first initial overlapping area, and / or by forming a tapered shape from a rectangular initial lateral shape in the first initial overlapping area.

13. The method according to any one of claims 10 to 12, wherein a first initial overlap area between a source finger and a drain bus is reduced compared to an overlap area between the same source finger and the source bus, and / or A second initial overlap area between a drain finger and a source bus line is reduced compared to an overlap area between the same drain finger and the drain bus line.

14. The method according to any one of claims 10 to 13, wherein the drain bus line has an initial area, and the method further comprises: forming at least one hole in the drain bus and / or removing a peripheral portion of the drain bus, wherein the portion of the drain bus is removed in an area laterally adjacent to the distal ends of the source and drain fingers and / or adjacent to the length of the source and drain fingers and / or in a peripheral area of ​​the substrate, and / or At least one hole is formed in the source bus and / or a peripheral portion of the source bus is removed, wherein portions of the drain bus are removed in areas laterally adjacent to distal ends of source and drain fingers and / or adjacent to the lengths of source and drain fingers and / or in peripheral areas of the substrate.

15. The method according to any one of claims 10 to 14, further comprising: Step A Measure the new on-state resistance of the modified design; outputting the lateral size and shape of the source finger in a final design data set when the new capacitance is less than the initial capacitance and the on-state resistance is less than a predetermined threshold; In the case where the new capacitance is less than the initial capacitance and the on-state resistance is equal to or greater than a predetermined threshold, increasing the area of ​​the source finger and returning to step A, According to the final design data set, source fingers and drain fingers are formed.

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