Device for improving performance of CMOS image sensor

Abstract

The invention provides a device for improving the performance of a CMOS (Complementary Metal Oxide Semiconductor) image sensor. According to the pixel unit, a photodiode and a floating diffusion node are both located on a (100) crystal face / lt; 110gt, 110gt; in the substrate of the crystal orientation, a transmission tube is fixed on the upper surface of the substrate and directly faces between the photodiode and the floating diffusion node, and the channel direction of the transmission tube is < 100 > crystal orientation so as to improve the electron transmission speed; the photodiode is connected with the floating diffusion node through the transmission tube; an ion implantation layer is added on a floating diffusion node close to a channel region so as to form a potential gradient, and the transmission efficiency of an electric signal is improved. According to the invention, the channel direction of the transmission tube in the pixel unit is changed into the crystal orientation of < 100 >, so that the electron transmission speed is increased; by adding the ion implantation layer, a potential gradient is formed, and the transmission efficiency of an electric signal is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a device for improving the performance of a CMOS image sensor. Background Art

[0002] In recent years, as high-speed CMOS image sensors have been widely used in machine vision, sports and scientific research fields, and as the size of pixels (pixel units) has become larger and larger, higher requirements have been placed on the transmission speed and Image Lag of photodiodes.

[0003] CIS (Contact Image Sensor) products use (100) crystal plane / <100> The substrate has a crystal orientation, and the transmission of electrical signals in the electric field mainly relies on concentration diffusion. As the pixel unit area continues to increase, the lateral electric field transmission speed slows down. During the switching process of the TX tube (transmission tube), the electrons in the PD (photodiode) area cannot be completely extracted, and the smear phenomenon becomes increasingly serious, thereby putting higher requirements on the transmission speed of the photodiode.

[0004] In order to solve the above problems, it is necessary to propose a new device for improving the performance of CMOS image sensors. Summary of the invention

[0005] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a device for improving the performance of a CMOS image sensor, so as to solve the problem that the transmission speed of the photodiode in the prior art has a higher requirement.

[0006] To achieve the above-mentioned object and other related objects, the present invention provides a device for improving the performance of a CMOS image sensor, comprising:

[0007] Pixel unit;

[0008] The pixel unit comprises:

[0009] The photodiode and floating diffusion nodes are both located on the (100) crystal plane. <110> In a substrate with a crystal orientation, a transmission tube is fixed on the upper surface of the substrate, facing between the photodiode and the floating diffusion node, and the channel direction of the transmission tube is a <100> crystal orientation to increase the electron transmission speed;

[0010] The photodiode is connected to the floating diffusion node through the transmission tube, and the other end of the floating diffusion node is connected to the source of the reset tube and the gate of the source follower;

[0011] The drains of the source follower and the reset tube are both connected to the bias voltage VDD, and the source of the source follower is connected to the drain of the row selection tube;

[0012] An ion implantation layer is added near the channel region of the floating diffusion node to form a potential gradient, thereby improving the transmission efficiency of the electrical signal.

[0013] Preferably, shallow trench isolation is formed on the substrate to define an active area, and the pixel unit is located on the active area.

[0014] Preferably, the shallow trench isolation forms a shallow trench isolation structure between adjacent sensor pixel units to prevent crosstalk between adjacent pixel units.

[0015] Preferably, the substrate is P-type doped.

[0016] Preferably, the floating diffusion node is an N-type heavily doped region.

[0017] Preferably, the doping ions of the ion implantation layer are at least one of P and As.

[0018] Preferably, the photodiode is composed of a surface P-type heavily doped region, an N-type buried layer as a charge collection region and the substrate from top to bottom.

[0019] Preferably, the P-type heavily doped region is longer than the N-type buried layer.

[0020] Preferably, the ion implantation layer is an N-type heavily doped region.

[0021] Preferably, the ion implantation layer is formed in the N-type buried layer close to one side of the transmission tube, and the upper surface of the ion implantation layer extends from the lower surface of the P-type heavily doped region to the N-type buried layer.

[0022] Preferably, the potential of the pixel unit increases sequentially from a side away from the floating diffusion node to a side of the floating diffusion node.

[0023] As described above, the device for improving the performance of a CMOS image sensor of the present invention has the following beneficial effects:

[0024] The present invention changes the direction of the transmission pipe channel in the pixel unit to a <100> crystal direction to increase the electron transmission speed; and forms a potential gradient by adding an ion implantation layer to increase the transmission efficiency of the electrical signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 Shown is a schematic diagram of the principle of a pixel unit in the prior art;

[0026] Figure 2 Shown is a schematic diagram of hole mobility on different crystal planes of the silicon substrate of the present invention;

[0027] Figure 3It shows a schematic diagram of the pixel unit structure and potential distribution of the present invention. DETAILED DESCRIPTION

[0028] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0029] See also Figure 3 The present invention provides a device for improving the performance of a CMOS image sensor, comprising:

[0030] Pixel unit;

[0031] The pixel unit includes:

[0032] The photodiode and the floating diffusion node 103 are both located on the (100) crystal plane. <110> In the substrate 101 with a crystal orientation, the transmission tube 104 is fixed on the upper surface of the substrate 101, facing between the photodiode and the floating diffusion node 103, and the channel direction of the transmission tube 104 is a <100> crystal orientation to increase the electron transmission speed; see Figure 2 Since the holes along different channel directions on the silicon substrate 101 with different crystal planes have different effective masses, the hole mobility along different channel directions on different crystal planes is different. The hole mobility along the channel direction <100> on the Si (100) crystal plane is about 40% higher than that along the channel direction <110>.

[0033] In the embodiment of the present invention, a shallow trench isolation 102 is formed on the substrate 101 to define an active region, and the pixel unit is located on the active region.

[0034] In the embodiment of the present invention, the shallow trench isolation 102 forms a shallow trench isolation 102 structure between adjacent sensor pixel units to prevent crosstalk between adjacent pixel units.

[0035] The photodiode is connected to the floating diffusion node 103 through the transmission tube 104, and the other end of the floating diffusion node 103 is connected to the source of the reset tube and the gate of the source follower;

[0036] The drains of the source follower and the reset tube are both connected to the bias voltage VDD, and the source of the source follower is connected to the drain of the row select tube;

[0037] An ion implantation layer 107 is added near the channel region of the floating diffusion node 103 to form a potential gradient, thereby improving the transmission efficiency of the electrical signal and increasing the full well capacity.

[0038] In an embodiment of the present invention, the substrate 101 is P-type doped.

[0039] In the embodiment of the present invention, the floating diffusion node 103 is an N-type heavily doped region.

[0040] In an embodiment of the present invention, the photodiode is composed of a top-down surface P-type heavily doped region 106, an N-type buried layer 105 as a charge collection region and a substrate 101, and the two ends of the P-type heavily doped region 106 are respectively located at the edge of the shallow trench isolation 102 and the edge of the channel below the transmission tube 104.

[0041] In the embodiment of the present invention, the P-type heavily doped region 106 is longer than the N-type buried layer 105 .

[0042] In the embodiment of the present invention, the ion implantation layer 107 is an N-type heavily doped region.

[0043] In an embodiment of the present invention, the doping ions of the ion implantation layer 107 are at least one of P and As.

[0044] In an embodiment of the present invention, the ion implantation layer 107 is formed in the N-type buried layer 105 near one side of the transmission tube 104 , and the upper surface of the ion implantation layer 107 extends from the lower surface of the P-type heavily doped region 106 to the N-type buried layer 105 .

[0045] In the embodiment of the present invention, the potential in the pixel unit increases from the side away from the floating diffusion node 103 to the side of the floating diffusion node 103, wherein a gradient increasing potential is formed in the photodiode due to the increase of the ion implantation layer 107.

[0046] It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner. Therefore, the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0047] In summary, the present invention changes the direction of the transmission pipe channel in the pixel unit to a <100> crystal direction to increase the electron transmission speed; by adding an ion implantation layer, an electric potential gradient is formed to increase the transmission efficiency of the electrical signal. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has a high industrial utilization value.

[0048] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A device for improving the performance of a CMOS image sensor, characterized in that: include: Pixel unit; The pixel unit comprises: The photodiode and the floating diffusion node are both located in the substrate, and the transmission tube is fixed on the upper surface of the substrate, facing between the photodiode and the floating diffusion node; The photodiode is connected to the floating diffusion node through the transmission tube; An ion implantation layer is added near the channel region of the floating diffusion node to form a potential gradient, thereby improving the transmission efficiency of the electrical signal.

2. The device for improving the performance of a CMOS image sensor according to claim 1, characterized in that: Shallow trench isolation is formed on the substrate to define an active area, and the pixel unit is located on the active area.

3. The device for improving the performance of a CMOS image sensor according to claim 2, characterized in that: The shallow trench isolation forms a shallow trench isolation structure between adjacent sensor pixel units, thereby preventing crosstalk between adjacent pixel units.

4. The device for improving the performance of a CMOS image sensor according to claim 1, characterized in that: The substrate is P-type doped.

5. The device for improving the performance of a CMOS image sensor according to claim 4, characterized in that: The floating diffusion node is an N-type heavily doped region.

6. The device for improving the performance of a CMOS image sensor according to claim 5, characterized in that: The photodiode is composed of a top-down surface P-type heavily doped region, an N-type buried layer as a charge collection region and the substrate.

7. The device for improving the performance of a CMOS image sensor according to claim 6, characterized in that: The P-type heavily doped region is longer than the N-type buried layer.

8. The device for improving the performance of a CMOS image sensor according to claim 7, characterized in that: The ion implantation layer is an N-type heavily doped region.

9. The device for improving the performance of a CMOS image sensor according to claim 8, characterized in that: The doping ions of the ion implantation layer are at least one of P and As.

10. The device for improving the performance of a CMOS image sensor according to claim 8, characterized in that: The ion implantation layer is formed in the N-type buried layer close to one side of the transmission tube, and the upper surface of the ion implantation layer extends from the lower surface of the P-type heavily doped region to the N-type buried layer.

11. The device for improving the performance of a CMOS image sensor according to claim 10, characterized in that: The potential of the pixel unit increases sequentially from the side away from the floating diffusion node to the side of the floating diffusion node.

12. The device for improving the performance of a CMOS image sensor according to claim 1, characterized in that: The pixel unit also includes: the other end of the floating diffusion node is connected to the source of the reset tube and the gate of the source follower, the drains of the source follower and the reset tube are both connected to the bias voltage VDD, and the source of the source follower is connected to the drain of the row selection tube.

13. The device for improving the performance of a CMOS image sensor according to claim 12, characterized in that: The transmission tube is controlled by a transmission signal, the reset tube is controlled by a reset signal, and the gate of the row selection tube is connected to the row selection signal and is controlled by the row selection signal.

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