Laminated TCO thin film, heterojunction battery and preparation method of heterojunction battery

Abstract

The invention relates to the technical field of solar cells, in particular to a laminated TCO thin film, a heterojunction cell and a preparation method of the heterojunction cell. The laminated TCO thin film sequentially comprises a BTCO layer, an MTCO layer and a TTCO layer, along the direction from the BTCO layer to the TTCO layer, the BTCO layer comprises a first ITO layer, a first doped metal oxide and ITO composite layer and a first doped metal oxide layer, the MTCO layer comprises a second doped metal oxide layer, a second doped metal oxide and ITO composite layer and a second ITO layer, and the TTCO layer is a third ITO layer. According to the laminated TCO thin film, through the synergistic effect of all the layers, the resistivity of the laminated TCO thin film can be reduced, good ohmic contact with other film layers of a battery can be formed, transmission of photo-generated current is facilitated, the light transmittance of the laminated TCO thin film can be improved, and improvement of the efficiency of the laminated TCO thin film and reduction of the target material cost are facilitated.

Description

Technical Field

[0001] The present invention relates to the technical field of solar cells, and in particular to a laminated TCO film, a heterojunction cell and a preparation method thereof. Background Art

[0002] Solar cells are well known for their clean, safe and pollution-free characteristics. Solar cells are semiconductor devices that can convert solar energy into electrical energy. Under light conditions, photocurrent is generated inside the solar cell and the current is output through the electrodes. As one of the most important applications of solar energy, photovoltaic technology can effectively change the energy consumption structure, reduce global warming and the growing trend of ecological environment deterioration. Therefore, vigorously developing photovoltaic technology has far-reaching and significant significance. As the global market pays more and more attention to the efficiency of solar cells, the conversion efficiency of P-type solar cells has reached a bottleneck, and the iteration of battery technology is imperative. At present, the mainstream solar cells mainly include TOPCon cells, heterojunction cells, BC cells, perovskite cells and their corresponding various types of stacked solar cells. Among them, transparent conductive films, as a key component of various types of solar cells, play a vital role in improving the performance of solar cells. Today, magnetron sputtering technology has developed into the main transparent conductive oxide (Transparent Conductive Oxides, TCO) film deposition technology. During the preparation process of TCO films, on the one hand, they will be affected by the magnetron sputtering equipment itself. On the other hand, when different doped metal oxide targets are used in the same magnetron sputtering equipment, the process environment parameters also have a great influence on the quality of their film deposition. In solar cells, transparent conductive films not only need to have high light transmittance to ensure that sunlight can penetrate to the maximum extent and reach the light absorption layer of the cell to achieve efficient light energy capture, but also must have good conductivity to quickly collect and transmit the charges generated by the solar cell to improve the photoelectric conversion efficiency of the cell. Therefore, in-depth research on the characteristics of transparent conductive films and their applications in various types of solar cells is of great significance for promoting the development of solar cell technology and realizing the widespread application of solar energy.

[0003] In solar cells, first of all, transparent conductive films are usually used as electrode materials. They can be used as the front electrode of solar cells to collect photogenerated carriers and transmit them to the external circuit; they can also be used as the back electrode to reflect unabsorbed sunlight and improve the light absorption efficiency of solar cells. At the same time, transparent conductive films can also play the role of anti-reflection and anti-reflection, further improving the performance of solar cells. Secondly, transparent conductive films can be used as the intermediate composite layer between two sub-cells in stacked solar cells. For example, in perovskite crystalline silicon stacked cells, on the one hand, it can help the holes generated by the perovskite layer and the electrons generated by the crystalline silicon layer to effectively separate and transmit at the interface, reduce the recombination loss of carriers, and improve the photoelectric conversion efficiency of the battery. On the other hand, the transparent conductive film of the intermediate composite layer can also passivate the interface between the perovskite layer and the crystalline silicon layer, reduce interface defects and surface states, and reduce the recombination probability of carriers. Good interface passivation can improve the open circuit voltage and fill factor of the battery, thereby improving the performance of the battery. Among them, the material selection and characteristic regulation of transparent conductive films are crucial, and they have a great impact on the performance of solar cells.

[0004] There are many types of typical doped monomer TCO films used in the current solar cell production process, such as indium tin oxide (ITO) film, aluminum zinc oxide (AZO) film, fluorine doped tin oxide (FTO) film, etc. Among them, ITO film is a commonly used TCO film. Due to the limited global reserves of indium, even at a smaller production capacity, the shortage of indium will limit the production of solar cells, so it is imperative to find more abundant and low-cost alternative materials. The AZO film mentioned above is another commonly used TCO film. Because the main components of this film are Zn and Al, the cost of AZO film is only about 1 / 10 of that of ITO film. In order to reduce the cost of TCO film preparation, there is a solution to replace ITO film with low-cost AZO film. In the presence of AZO film, the series resistance of the battery increases, mainly due to the large contact resistance between AZO and the silver electrode and the amorphous silicon film. Therefore, it cannot meet the requirements of ultra-thin, high light transmittance and high conductivity at the same time. Limited by the semiconductor conductive mechanism, the efficiency of heterojunction solar cells prepared by unilateral AZO film as TCO film is low. In order to take into account the advantages of high efficiency and low cost, some studies have superimposed multilayer ITO film or ITO film with other types of doped metal oxide films. However, the superposition of multilayer ITO film and ITO film with other types of doped metal oxide films leads to a trend of deterioration in the optical and electrical properties of TCO film, and the obtained TCO film has poor film uniformity and density. Due to the poor contact between the film layers of the multilayer film, the potential barrier overcome by electrons or holes is large, and effective transmission cannot be obtained. In addition, the superposition of other types of doped metal oxide films will inevitably lead to a decrease in transparency, resulting in changes in the work function between the film layers and reduced ohmic contact.

[0005] Therefore, how to prepare TCO films with better optical and electrical properties is an urgent problem to be solved in the process of solar cell preparation. Summary of the invention

[0006] The present invention provides a laminated TCO film, a heterojunction battery and a preparation method thereof, which are used to solve the problem of poor optical and electrical properties of the TCO film in the prior art.

[0007] The present invention provides a laminated TCO film, which comprises a BTCO layer, a MTCO layer and a TTCO layer in sequence. Along the BTCO layer toward the TTCO layer, the BTCO layer comprises a first ITO layer, a first doped metal oxide and ITO composite layer and a first doped metal oxide layer, the MTCO layer comprises a second doped metal oxide layer, a second doped metal oxide and ITO composite layer and a second ITO layer, and the TTCO layer is a third ITO layer.

[0008] The laminated TCO film of the present invention comprises a BTCO layer, an MTCO layer and a TTCO layer in sequence. When in use, the BTCO layer is in direct contact with the doped silicon film layer, the TTCO layer is in contact with the metal electrode, and the MTCO layer plays a transition role. The present invention further optimizes the structures of the BTCO layer, the MTCO layer and the TTCO layer. The BTCO layer comprises a first ITO layer, a first doped metal oxide and ITO composite layer and a first doped metal oxide layer. Such a design structure can not only improve the interface contact performance between the laminated TCO film and the doped silicon film layer, but also improve the contact barrier between the MTCO layer and the doped silicon film layer. The TTCO layer uses an ITO film and can form a good ohmic contact with the metal electrode. The MTCO layer comprises a second doped metal oxide layer, a second doped metal oxide and ITO composite layer and a second ITO layer. Such a design can better play a transition role, reduce the carrier concentration and improve the carrier mobility. The laminated TCO film of the present invention adopts doped metal oxide to replace part of the more expensive ITO, and the structure between the layers is finely designed, so that the layers can play a better synergistic role, which can reduce the damage of magnetron sputtering to crystalline silicon and doped metal oxide films, and can reduce the resistivity of the laminated TCO film, so that it can form a good ohmic contact with other film layers of the battery, which is beneficial to the transmission of photogenerated current, and improves the light transmittance of the entire laminated TCO film, ultimately ensuring the improvement of efficiency and the reduction of target material cost.

[0009] The stacked TCO film of the present invention can be applied to all solar cells, such as the middle composite layer of a perovskite crystalline silicon stacked cell or the transparent conductive film layer of a top electrode or a bottom cell.

[0010] Furthermore, the thickness of the BTCO layer is 15-20nm; the thickness of the MTCO layer is 20-45nm; and the thickness of the TTCO layer is 50-70nm. The thickness of each layer of the stacked TCO film has an important influence on its electrical, optical and stability properties. By precisely controlling the thickness of each layer, the comprehensive performance of the film can be optimized to meet the needs of different applications.

[0011] In some specific embodiments, the thickness of the BTCO layer is 18-20 nm; the thickness of the MTCO layer is 20-45 nm; and the thickness of the TTCO layer is 50-70 nm.

[0012] Preferably, the thickness of the BTCO layer, the MTCO layer and the TTCO layer satisfies: BTCO layer < MTCO layer < TTCO layer. By such thickness design, the electrical and optical losses of the battery can be further reduced, and the efficiency of the stacked TCO film can be improved.

[0013] In order to improve the electrical and optical properties of solar cells prepared by the stacked TCO film, more preferably, the thickness of the BTCO layer accounts for 15-20% of the total film thickness of the stacked TCO film; and / or the thickness of the MTCO layer accounts for 25-40% of the total film thickness of the stacked TCO film; and / or the thickness of the TTCO layer accounts for 45-60% of the total film thickness of the stacked TCO film.

[0014] Furthermore, the thickness of the first doped metal oxide and ITO composite layer is 0.5-3nm; further, the thickness of the second doped metal oxide and ITO composite layer is 0.5-3nm. The doped metal oxide and ITO composite layer plays a key bridge role between the doped metal oxide layer and the ITO layer, which can improve the charge transfer characteristics between the doped metal oxide layer and the ITO layer, reduce the scattering effect at the interface, thereby improving the conductivity of the overall film, and by optimizing the thickness of the doped metal oxide and ITO composite layer, the overall application performance of the laminated TCO film can be improved.

[0015] In the present invention, the doped metal oxide and ITO composite layer plays a key bridge role between the doped metal oxide layer and the ITO layer. The thickness of the doped metal oxide and ITO composite layer can regulate the charge transfer characteristics between the doped metal oxide layer and the ITO layer and the scattering effect at the interface, thereby affecting the conductivity of the entire film. In order to improve the overall application performance of the laminated TCO film, it is preferred that the thickness of the first doped metal oxide and ITO composite layer is 0.5-3nm; or, it is preferred that the thickness of the second doped metal oxide and ITO composite layer is 0.5-3nm; it is further preferred that the thickness of the first doped metal oxide and ITO composite layer is 0.5-3nm, and, the thickness of the second doped metal oxide and ITO composite layer is 0.5-3nm.

[0016] Furthermore, the sum of the thicknesses of the first doped metal oxide layer and the second doped metal oxide layer is 10%-25% of the total thickness of the laminated TCO film. By limiting the sum of the thicknesses of the first doped metal oxide layer and the second doped metal oxide layer to a reasonable range, the conversion efficiency of the heterojunction solar cell can be improved while reducing the production cost.

[0017] Further, the doped metal oxide in the first doped metal oxide and the doped metal oxide in the second doped metal oxide are each independently one or more of AZO, a tin-based compound having a tin oxide weight content greater than 97%, and ITO having an indium oxide weight content less than 70%. In some specific embodiments, the doped metal oxide in the first doped metal oxide and the doped metal oxide in the second doped metal oxide are each independently AZO.

[0018] According to a second aspect of the present invention, the present invention further provides a heterojunction battery, comprising: Silicon substrate; A first intrinsic amorphous silicon film, an N-type doped silicon film, a front transparent conductive oxide layer and a first metal electrode are sequentially arranged on the front surface of the silicon substrate; A second intrinsic amorphous silicon film, a P-type doped silicon film, a back transparent conductive oxide layer and a second metal electrode are sequentially arranged on the back side of the silicon substrate, and the front transparent conductive oxide layer and / or the back transparent conductive oxide layer are the above-mentioned laminated TCO film.

[0019] Applying the laminated TCO film of the present invention to a heterojunction battery can improve the electrical and optical properties of the heterojunction battery.

[0020] It should be noted that the laminated TCO film structure of the present invention is not limited to the back P-type doped silicon film, but can also be applied to the front N-type doped silicon film. In some specific embodiments, when the laminated TCO film is applied to the back P-type doped silicon film, the front transparent conductive oxide layer preferably uses a high indium ratio target material that is beneficial to optics.

[0021] According to a third aspect of the present invention, the present invention also provides a method for preparing the above-mentioned heterojunction battery, comprising the following steps: providing a silicon substrate; A first intrinsic amorphous silicon film and an N-type doped silicon film are sequentially deposited on the front side of the silicon substrate by a plasma chemical gas deposition method; a second intrinsic amorphous silicon film and a P-type doped silicon film are sequentially deposited on the back side of the silicon substrate by a plasma chemical gas deposition method; Depositing a front transparent conductive oxide layer on the N-type doped silicon film by magnetron sputtering; depositing a back transparent conductive oxide layer on the P-type doped silicon film by magnetron sputtering; A first metal electrode is prepared on the front transparent conductive oxide layer; and a second metal electrode is prepared on the back transparent conductive oxide layer.

[0022] The method for preparing the heterojunction battery of the present invention does not substantially change the structure of the original magnetron sputtering equipment when preparing the laminated TCO film, and the process is simple and easy to implement.

[0023] Furthermore, the deposition of a back transparent conductive oxide layer on the P-type doped silicon film includes: depositing a BTCO layer on the P-type doped silicon film; depositing an MTCO layer on the BTCO layer; and depositing a TTCO layer on the MTCO layer. The application of the laminated TCO film on the back of the heterojunction cell can significantly improve the photoelectric conversion efficiency, optical performance and stability of the cell.

[0024] Furthermore, the deposition of the front transparent conductive oxide layer on the N-type doped silicon film by magnetron sputtering is carried out in the first process chamber, the sputtering target is tin-doped indium oxide, the weight ratio of In2O3 and SnO2 in the tin-doped indium oxide is (90-97): (3-10), and the sputtering process gas is argon and oxygen, and the volume ratio of argon and oxygen is (50-200): 1. The composition of the sputtering target and the sputtering process gas have an important influence on the electrical, optical, structural morphology and stability properties of the front transparent conductive oxide layer. By optimizing the characteristics of the target and the sputtering gas, the overall performance of the front transparent conductive oxide layer can be significantly improved.

[0025] The BTCO layer is deposited on the P-type doped silicon film on the same cathode in the second process chamber, and tin-doped indium oxide and aluminum-doped zinc oxide are sputtered in sequence, the weight ratio of In2O3 and SnO2 in the tin-doped indium oxide is (90-97): (3-10), the weight ratio of ZnO and Al2O3 in the aluminum-doped zinc oxide is (95-99): (1-5), and the sputtering process gas is argon and oxygen, and the volume ratio of argon and oxygen is (50-200): 1. The composition of the sputtering target and the sputtering process gas have an important influence on the electrical, optical, structural morphology and stability properties of the BTCO layer. By optimizing the characteristics of the target and the sputtering gas, the overall performance of the BTCO layer can be significantly improved.

[0026] The MTCO layer is deposited on the BTCO layer on the same cathode in the third process chamber, and aluminum-doped zinc oxide and tin-doped indium oxide are sputtered in sequence, the weight ratio of ZnO and Al2O3 in the aluminum-doped zinc oxide is (95-99): (1-5), the weight ratio of In2O3 and SnO2 in the tin-doped indium oxide is (90-97): (3-10), and the sputtering process gas is argon and oxygen, and the volume ratio of argon and oxygen is (75-100): 1. The composition of the sputtering target and the sputtering process gas have an important influence on the electrical, optical, structural morphology and stability properties of the MTCO layer. By optimizing the characteristics of the target and the sputtering gas, the overall performance of the MTCO layer can be significantly improved.

[0027] The deposition of the TTCO layer on the MTCO layer is carried out in the fourth process chamber, the sputtering target is tin-doped indium oxide, the weight ratio of In2O3 and SnO2 in the tin-doped indium oxide is (90-97): (3-10), and the sputtering process gas is argon and oxygen, and the volume ratio of argon and oxygen is (50-200): 1. The composition of the sputtering target and the sputtering process gas have an important influence on the electrical, optical, structural morphology and stability properties of the TTCO layer. By optimizing the characteristics of the target and the sputtering gas, the overall performance of the TTCO layer can be significantly improved.

[0028] The sputtering power and other parameters of the PVD magnetron sputtering equipment can be precisely controlled. The two process steps of preparing the TCO transparent conductive film of the above heterojunction battery can be completed at one time through one PVD equipment.

[0029] The first process chamber, the second process chamber, the third process chamber and the fourth process chamber are connected in sequence.

[0030] Furthermore, a cathode is separately configured in each process chamber, and two sputtering targets can be placed on each cathode, and the distance between the two sputtering targets is 5 cm. The power supply in each process chamber adopts a DC pulse discharge mode or a DC discharge mode.

[0031] Furthermore, the first process chamber, the second process chamber, the third process chamber and the fourth process chamber independently satisfy at least one of parameters (1) to (3) during operation. Specifically, parameter (1) is a pressure of 5e -1 -8e -1 Pa; the parameter (2) is the temperature of 80-120°C; the parameter (3) is the water partial pressure 1e -4 Pa to 3e -4Pa. Pressure affects the density and stability of the plasma in the sputtering chamber. An appropriate pressure range helps maintain a stable plasma environment, thereby improving sputtering efficiency. Reasonable control of temperature helps improve the crystallinity of the film layer, thereby improving its electrical and optical properties. Too high a water partial pressure will introduce impurities into the film, affecting its purity and stability. Maintaining a low water partial pressure helps maintain the stability of the sputtering process and avoid process fluctuations caused by moisture. By controlling the pressure, temperature and water partial pressure in each process chamber within a reasonable range, the sputtering efficiency can be improved, thereby improving the performance of the film layer.

[0032] Furthermore, in the process of providing the silicon substrate, the silicon substrate needs to be pre-treated, and the pre-treatment specifically includes the following steps: first, use ammonia water to clean the dirt on the surface of the silicon substrate, and then use potassium hydroxide to alkaline polish it to remove the damaged layer, and then use texturing additives and potassium hydroxide to texturize, so that a pyramid structure is formed on the surface of the silicon substrate, and the texturing size is 2-3μm, and finally, it is post-cleaned with acid and alkali to achieve a texturing structure with a higher degree of cleanliness.

[0033] Furthermore, a first intrinsic amorphous silicon film and an N-type doped silicon film are sequentially deposited on the front side of the silicon substrate by plasma chemical gas deposition method, specifically: the first intrinsic amorphous silicon film is deposited to a thickness of 5-10nm, using gases SiH4 and H2; the N-type doped amorphous silicon or microcrystalline silicon layer is deposited to a thickness of 8-15nm, using gases SiH4, H2, PH3, and the PH3 doping ratio is 1-5%.

[0034] Furthermore, a second intrinsic amorphous silicon film and a P-type doped silicon film are sequentially deposited on the back side of the silicon substrate by plasma chemical gas deposition, specifically: the second intrinsic amorphous silicon film is deposited to a thickness of 10-15nm, using gases SiH4 and H2; a P-type doped amorphous silicon or microcrystalline silicon layer is deposited to a thickness of 10-20nm, using gases SiH4, H2, and B2H6, and the B2H6 doping ratio is 3-5%.

[0035] A stacked TCO film provided according to the present invention comprises a BTCO layer, an MTCO layer and a TTCO layer in sequence. Through the synergistic effect between the layers, the damage of magnetron sputtering to crystalline silicon and doped metal oxide films can be reduced, and the resistivity of the stacked TCO film can be reduced, so that it forms a good ohmic contact with other film layers of the battery, which is beneficial to the transmission of photogenerated current, improves the light transmittance of the entire stacked TCO film, and ultimately ensures the improvement of efficiency and the reduction of target material cost.

[0036] The preparation method of the heterojunction battery of the present invention does not substantially change the structure of the original magnetron sputtering equipment when preparing the laminated TCO film, and the process method is simple and easy to implement. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] In order to more clearly illustrate the technical solutions in the present invention or the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0038] Figure 1 It is a schematic diagram of the structure of a heterojunction battery provided in Example 1 of the present invention.

[0039] Figure 2 It is a schematic diagram of the structure of a stacked TCO film in a heterojunction battery provided in Example 1 of the present invention.

[0040] Figure 3 It is a schematic diagram of the structure of the magnetron sputtering equipment used in Example 1 of the present invention.

[0041] Figure 4 It is a schematic structural diagram of a heterojunction battery provided in Comparative Example 1 of the present invention.

[0042] Reference numerals: 1: BTCO layer; 11: first ITO layer; 12: first AZO and ITO composite layer; 13: first AZO layer; 2: MTCO layer; 21: second AZO layer; 22: second AZO and ITO composite layer; 23: second ITO layer; 3: TTCO layer. DETAILED DESCRIPTION

[0043] In order to make the purpose, technical solution and advantages of the present invention clearer, the technical solution of the present invention will be clearly and completely described below in conjunction with the drawings of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0044] Example 1 This embodiment provides a heterojunction battery, such as Figure 1 As shown, including: Silicon substrate (Nc-Si), thickness 130 μm; A first intrinsic amorphous silicon film a-Si:H(i) (7 nm thick), an N-type doped silicon film a-Si:H(n) (10 nm thick), a front transparent conductive oxide layer (TCO layer) and an Ag electrode are sequentially arranged on the front surface of the silicon substrate; A second intrinsic amorphous silicon film a-Si:H(i) (12 nm thick), a P-type doped silicon film a-Si:H(p) (15 nm thick), a back transparent conductive oxide layer and an Ag electrode are sequentially arranged on the back side of the silicon substrate.

[0045] The front transparent conductive oxide layer is a single TCO layer (thickness is 110nm), and the back transparent conductive oxide layer is a laminated TCO film, such as Figure 2 As shown, the stacked TCO film includes a BTCO layer 1, an MTCO layer 2 and a TTCO layer 3, the thicknesses of the BTCO layer 1, the MTCO layer 2 and the TTCO layer 3 are 20 nm, 30 nm and 70 nm respectively, along the direction from the BTCO layer 1 to the TTCO layer 3, the BTCO layer 1 includes a first ITO layer 11, a first AZO and ITO composite layer 12 and a first AZO layer 13, the thicknesses of the first ITO layer 11, the first AZO and ITO composite layer 12 and the first AZO layer 13 are 8 nm, 2 nm and 10 nm respectively, the MTCO layer 2 includes a second AZO layer 21, a second AZO and ITO composite layer 22 and a second ITO layer 23, the thicknesses of the second AZO layer 21, the second AZO and ITO composite layer 22 and the second ITO layer 23 are 15 nm, 2 nm and 13 nm respectively, the TTCO layer 3 is a third ITO layer, and the thickness of the third ITO layer is 70 nm.

[0046] The preparation method thereof comprises the following steps: Step 1: The silicon wafer used in the battery is an N-type single crystal silicon wafer, the resistivity of the silicon wafer is 0.3-2.1Ω·cm, the thickness of the silicon wafer is 130μm, and the size of the silicon wafer is 166*166mm. First, use ammonia water to clean the surface dirt of the silicon wafer, then use potassium hydroxide to alkaline polish it to remove the damaged layer, and then use texturing additives and potassium hydroxide to texturing, so that the surface of the silicon wafer forms a pyramid structure, the size of the velvet is about 2.5μm, and finally after acid and alkali post-cleaning, a velvet structure with a high degree of cleanliness is achieved.

[0047] Step 2: Use a plate-type PECVD (plasma chemical vapor deposition) device to deposit the first intrinsic amorphous silicon layer and N-type doped amorphous silicon or microcrystalline silicon layer on the front side of the silicon wafer prepared in step 1. The thickness of the first intrinsic amorphous silicon is 7nm, and the gases SiH4 and H2 are used; the thickness of the N-type doped amorphous silicon or microcrystalline silicon layer is 10nm, and the gases SiH4, H2, and PH3 are used, and the PH3 doping ratio is 3%. Sequentially deposit the second intrinsic amorphous silicon layer and P-type doped amorphous silicon or microcrystalline silicon layer on the back side of the silicon wafer; the thickness of the second intrinsic amorphous silicon layer is 12nm, and the gases SiH4 and H2 are used; the thickness of the P-type doped amorphous silicon or microcrystalline silicon layer is 15nm, and the gases SiH4, H2, and B2H6 are used, and the B2H6 doping ratio is 4%.

[0048] Step 3: After step 2, the silicon wafer is subjected to magnetron sputtering by PVD equipment to deposit a transparent conductive film (TCO) on the front and back of the silicon wafer. The process chamber and target position of the magnetron sputtering equipment used are as follows: Figure 3As shown, a cathode is separately configured in each process chamber, and two sputtering targets can be placed on each cathode, and the distance between the two sputtering targets is 5cm. The power supply in each process chamber adopts a DC pulse discharge mode. The deposition of TCO on the front n-type doped amorphous silicon or microcrystalline silicon layer is completed in the first process chamber (first cathode) of the PVD equipment. The targets 1.1 and 1.2 used in magnetron sputtering are both tin-doped indium oxide, and the ratio of In2O3:SnO2 in tin-doped indium oxide is 97%:3%; the sputtering process gases are high-purity argon and oxygen, and the ratio of these two gases entering the first process chamber is controlled to be 150:1; the final sputtering deposition film thickness is 110nm (the current step completes the front TCO deposition of the battery). A BTCO layer, an MTCO layer, and a TTCO layer are sequentially deposited on the back P-type doped amorphous silicon or microcrystalline silicon layer by magnetron sputtering using a PVD device to prepare a laminated TCO film; this step is sequentially completed in the second process chamber, the third process chamber, and the fourth process chamber of the PVD, and the target material 2.1 of the second cathode in the second process chamber is arranged as tin-doped indium oxide (ITO), and the ratio of In2O3:SnO2 in the tin-doped indium oxide (ITO) is 90%:10%, and the target material 2.2 of the second cathode is arranged as aluminum-doped zinc oxide (AZO), and the ratio of ZnO:Al2O3 in the doped zinc oxide (AZO) is 98%:2%. The target material 3.1 of the third cathode in the third process chamber is set as aluminum-doped zinc oxide (AZO), and in the aluminum-doped zinc oxide (AZO), ZnO:Al2O3 is 98%:2%, and the target material 3.2 of the third cathode is set as tin-doped indium oxide (ITO), and in the tin-doped indium oxide (ITO), In2O3:SnO2 is 90%:10%. The targets 4.1 and 4.2 of the fourth cathode in the fourth process chamber are both set as tin-doped indium oxide, and in the tin-doped indium oxide, In2O3:SnO2 is 90%:10%. The sputtering process gases are both high-purity argon and oxygen, and the ratio of these two gases introduced into the second process chamber is controlled to be 150:1; the total film thickness of the final sputtered deposited BTCO layer is 20nm, of which the ITO single layer film thickness is 8nm, the composite layer film thickness of ITO and AZO is 2nm, and the AZO thin film layer is 10nm. The ratio of the two gases entering the third process chamber is controlled to be 100:1; the thickness of the final sputtering deposited MTCO layer is 30nm, of which the AZO thin film layer is 15nm, the AZO and ITO composite layer is 2nm, and the ITO thin film layer is 13nm. The ratio of the two gases entering the fourth process chamber is controlled to be 150:1; the thickness of the final sputtering deposited TTCO layer is 70nm, and this layer is all ITO thin film (the current step completes the TCO deposition on the back of the battery). The pressure in the first process chamber, the second process chamber, the third process chamber, and the fourth process chamber is controlled at 6e - 1Pa, the temperature is controlled at 80-120℃, and the water partial pressure is controlled at 1e -4 Pa to 3e -4 Pa.

[0049] Step 4: Screen-print the silicon wafer after step 3 to form a silver electrode, and then anneal and perform light injection treatment to obtain a finished battery cell.

[0050] Example 2 This embodiment provides a heterojunction battery, whose structure is different from that of Embodiment 1 in that the thickness of the MTCO layer is 45 nm, the thicknesses of the second AZO layer, the second AZO and ITO composite layer and the second ITO layer are 30 nm, 3 nm and 12 nm respectively, and the thickness of the third ITO layer is 55 nm.

[0051] The preparation method thereof comprises the following steps: Step 1: The silicon wafer used in the battery is an N-type single crystal silicon wafer, the resistivity of the silicon wafer is 0.3-2.1Ω·cm, the thickness of the silicon wafer is 130μm, and the size of the silicon wafer is 166*166mm. First, use ammonia water to clean the surface dirt of the silicon wafer, then use potassium hydroxide to alkaline polish it to remove the damaged layer, and then use texturing additives and potassium hydroxide to texturing, so that the surface of the silicon wafer forms a pyramid structure, the size of the velvet is about 2.5μm, and finally after acid and alkali post-cleaning, a velvet structure with a high degree of cleanliness is achieved.

[0052] Step 2: Use a plate-type PECVD (plasma chemical vapor deposition) device to deposit the first intrinsic amorphous silicon layer and N-type doped amorphous silicon or microcrystalline silicon layer on the front side of the silicon wafer prepared in step 1. The thickness of the first intrinsic amorphous silicon layer is 7nm, and the gases SiH4 and H2 are used; the N-type doped amorphous silicon or microcrystalline silicon layer is deposited to a thickness of 10nm, and the gases SiH4, H2, and PH3 are used, and the PH3 doping ratio is 3%. The second intrinsic amorphous silicon layer and P-type doped amorphous silicon or microcrystalline silicon layer are deposited on the back side of the silicon wafer in sequence; the second intrinsic amorphous silicon layer is deposited to a thickness of 12nm, and the gases SiH4 and H2 are used; the P-type doped amorphous silicon or microcrystalline silicon layer is deposited to a thickness of 15nm, and the gases SiH4, H2, and B2H6 are used, and the B2H6 doping ratio is 4%.

[0053] Step 3: After step 2, the silicon wafer is magnetron sputtered by PVD equipment to deposit a transparent conductive film (TCO) on the front and back of the silicon wafer. The deposition of ITO on the front n-type doped amorphous silicon or microcrystalline silicon layer is completed in the first process chamber (first cathode) of the PVD equipment. The target material used for magnetron sputtering is tin-doped indium oxide, and the ratio of In2O3:SnO2 in tin-doped indium oxide is 97%:3%. The sputtering process gases are high-purity argon and oxygen. The ratio of these two gases introduced into the first process chamber is controlled to be 150:1. The final sputtering deposition film thickness is 110nm (the current step completes the TCO deposition on the front side of the battery). A BTCO layer, an MTCO layer, and a TTCO layer are sequentially deposited on the back P-type doped amorphous silicon or microcrystalline silicon layer by a PVD device magnetron sputtering method to prepare a laminated TCO film; this step is completed in the PVD second process chamber, the third process chamber, and the fourth process chamber in sequence. The present invention arranges the target material 2.1 of the second cathode in the second process chamber as tin-doped indium oxide (ITO), and the In2O3:SnO2 in the tin-doped indium oxide (ITO) is 90%:10%, and the target material 2.2 of the second cathode is arranged as aluminum-doped zinc oxide (AZO), and the ZnO:Al2O3 in the aluminum-doped zinc oxide (AZO) is 98%:2%. The target material 3.1 of the third cathode in the third process chamber is set as aluminum-doped zinc oxide (AZO), and the ratio of ZnO:Al2O3 in the aluminum-doped zinc oxide (AZO) is 98%:2%. The target material 3.2 of the third cathode is set as tin-doped indium oxide (ITO), and the ratio of In2O3:SnO2 in the tin-doped indium oxide (ITO) is 90%:10%. The targets 4.1 and 4.2 of the fourth cathode in the fourth process chamber are both set as tin-doped indium oxide, and the ratio of In2O3:SnO2 in the tin-doped indium oxide is 90%:10%. The sputtering process gases are both high-purity argon and oxygen, and the ratio of these two gases introduced into the second process chamber is controlled to be 150:1; the total film thickness of the final sputtered deposited BTCO layer is 20nm, of which the thickness of the ITO single layer is 8nm, the thickness of the ITO and AZO composite layer is 2nm, and the AZO thin film layer is 10nm. The ratio of the two gases introduced into the third process chamber is controlled to be 100:1; the thickness of the final sputtering deposited MTCO layer is 45nm, of which the AZO thin film layer is 30nm, the AZO and ITO composite layer is 3nm, and the ITO thin film layer is 12nm. The ratio of the two gases introduced into the fourth process chamber is controlled to be 150:1; the thickness of the final sputtering deposited TTCO layer is 55nm, and this layer is all ITO thin film (the current step completes the TCO deposition on the back of the battery).

[0054] Step 4: Screen-print the silicon wafer after step 3 to form a silver electrode, and then anneal and perform light injection treatment to obtain a finished battery cell.

[0055] Example 3 This embodiment provides a heterojunction battery, the structure of which is different from that of Embodiment 1 in that the thickness of the MTCO layer is 45 nm, the thicknesses of the second AZO layer, the second AZO and ITO composite layer and the second ITO layer are 8 nm, 1 nm and 36 nm respectively, and the thickness of the third ITO layer is 55 nm.

[0056] The preparation method thereof comprises the following steps: Step 1: The silicon wafer used in the battery is an N-type single crystal silicon wafer, the resistivity of the silicon wafer is 0.3-2.1Ω·cm, the thickness of the silicon wafer is 130μm, and the size of the silicon wafer is 166*166mm. First, use ammonia water to clean the surface dirt of the silicon wafer, then use potassium hydroxide to alkaline polish it to remove the damaged layer, and then use texturing additives and potassium hydroxide to texturing, so that the surface of the silicon wafer forms a pyramid structure, the size of the velvet is about 2.5μm, and finally after acid and alkali post-cleaning, a velvet structure with a high degree of cleanliness is achieved.

[0057] Step 2: Use a plate-type PECVD (plasma chemical vapor deposition) device to deposit the first intrinsic amorphous silicon layer and N-type doped amorphous silicon or microcrystalline silicon layer on the front side of the silicon wafer prepared in step 1. The thickness of the first intrinsic amorphous silicon layer is 7nm, and the gases SiH4 and H2 are used; the N-type doped amorphous silicon or microcrystalline silicon layer is deposited to a thickness of 10nm, and the gases SiH4, H2, and PH3 are used, and the PH3 doping ratio is 3%. The second intrinsic amorphous silicon layer and P-type doped amorphous silicon or microcrystalline silicon layer are deposited on the back side of the silicon wafer in sequence; the second intrinsic amorphous silicon layer is deposited to a thickness of 12nm, and the gases SiH4 and H2 are used; the P-type doped amorphous silicon or microcrystalline silicon layer is deposited to a thickness of 15nm, and the gases SiH4, H2, and B2H6 are used, and the B2H6 doping ratio is 4%.

[0058] Step 3: After step 2, the silicon wafer is magnetron sputtered by PVD equipment to deposit a transparent conductive film (TCO) on the front and back of the silicon wafer. The deposition of ITO on the front n-type doped amorphous silicon or microcrystalline silicon layer is completed in the first process chamber (first cathode) of the PVD equipment. The target material used for magnetron sputtering is tin-doped indium oxide, and the ratio of In2O3:SnO2 in tin-doped indium oxide is 97%:3%. The sputtering process gases are high-purity argon and oxygen. The ratio of these two gases introduced into the first process chamber is controlled to be 150:1. The final sputtering deposition film thickness is 110nm (the current step completes the TCO deposition on the front side of the battery). A BTCO layer, an MTCO layer, and a TTCO layer are sequentially deposited on the back P-type doped amorphous silicon or microcrystalline silicon layer by a PVD device magnetron sputtering method to prepare a laminated TCO film; this step is sequentially completed in the PVD second process chamber, the third process chamber, and the fourth process chamber. The present invention arranges the target material 2.1 of the second cathode in the second process chamber as tin-doped indium oxide (ITO), and the ratio of In2O3:SnO2 in the tin-doped indium oxide (ITO) is 90%:10%, and the target material 2.2 of the second cathode is arranged as aluminum-doped zinc oxide (AZO), and the ratio of ZnO:Al2O3 in the aluminum-doped zinc oxide (AZO) is 98%:2%. The target material 3.1 of the third cathode in the third process chamber is set as aluminum-doped zinc oxide (AZO), and in the aluminum-doped zinc oxide (AZO), ZnO:Al2O3 is 98%:2%, and the target material 3.2 of the third cathode is set as tin-doped indium oxide (ITO), and In2O3:SnO2 in the tin-doped indium oxide (ITO) is 90%:10%. The targets 4.1 and 4.2 of the fourth cathode in the fourth process chamber are both set as tin-doped indium oxide, and In2O3:SnO2 in the tin-doped indium oxide is 90%:10%. The sputtering process gases are both high-purity argon and oxygen, and the ratio of these two gases introduced into the second process chamber is controlled to be 150:1; the total film thickness of the final sputtered deposited BTCO layer is 20nm, of which the ITO single layer film thickness is 8nm, the ITO and AZO composite layer film thickness is 2nm, and the AZO thin film layer is 10nm. The ratio of the two gases introduced into the third process chamber is controlled to be 100:1; the thickness of the final sputtering deposited MTCO layer is 45nm, of which the AZO thin film layer is 8nm, the AZO and ITO composite layer is 1nm, and the ITO thin film layer is 36nm. The ratio of the two gases introduced into the fourth process chamber is controlled to be 150:1; the thickness of the final sputtering deposited TTCO layer is 55nm, and this layer is all ITO thin film (the current step completes the TCO deposition on the back of the battery).

[0059] Step 4: Screen-print the silicon wafer after step 3 to form a silver electrode, and then anneal and perform light injection treatment to obtain a finished battery cell.

[0060] Comparative Example 1 This comparative example provides a conventional heterojunction battery, the structure of which is as follows Figure 4 As shown, the difference from Example 1 is that the back transparent conductive oxide layer is a single TCO layer (with a thickness of 120 nm).

[0061] The preparation method thereof comprises the following steps: Step 1: The silicon wafer used in the battery is an N-type single crystal silicon wafer, the resistivity of the silicon wafer is 0.3-2.1Ω·cm, the thickness of the silicon wafer is 130μm, and the size of the silicon wafer is 166*166mm. First, use ammonia water to clean the surface dirt of the silicon wafer, then use potassium hydroxide to alkaline polish it to remove the damaged layer, and then use texturing additives and potassium hydroxide to texturing, so that the surface of the silicon wafer forms a pyramid structure, the size of the velvet is about 2.5μm, and finally after acid and alkali post-cleaning, a velvet structure with a high degree of cleanliness is achieved.

[0062] Step 2: Use a plate-type PECVD (plasma chemical vapor deposition) device to deposit the first intrinsic amorphous silicon layer and N-type doped amorphous silicon or microcrystalline silicon layer on the front side of the silicon wafer prepared in step 1. The thickness of the first intrinsic amorphous silicon layer is 7nm, and the gases SiH4 and H2 are used; the N-type doped amorphous silicon or microcrystalline silicon layer is deposited to a thickness of 10nm, and the gases SiH4, H2, and PH3 are used, and the PH3 doping ratio is 3%. The second intrinsic amorphous silicon layer and P-type doped amorphous silicon or microcrystalline silicon layer are deposited on the back side of the silicon wafer in sequence; the second intrinsic amorphous silicon layer is deposited to a thickness of 12nm, and the gases SiH4 and H2 are used; the P-type doped amorphous silicon or microcrystalline silicon layer is deposited to a thickness of 15nm, and the gases SiH4, H2, and B2H6 are used, and the B2H6 doping ratio is 4%.

[0063] Step 3: After step 2, the silicon wafer is magnetron sputtered by PVD equipment to deposit a transparent conductive film (TCO) on the front and back of the silicon wafer. The deposition of ITO on the front n-type doped amorphous silicon or microcrystalline silicon layer is completed in the first process chamber (first cathode) of the PVD equipment. The target material used for magnetron sputtering is tin-doped indium oxide, and the ratio of In2O3:SnO2 in tin-doped indium oxide is 97%:3%. The sputtering process gases are high-purity argon and oxygen. The ratio of these two gases introduced into the first process chamber is controlled to be 150:1. The final sputtering deposition film thickness is 110nm (the current step completes the TCO deposition on the front side of the battery). The deposition of ITO on the back P-type doped amorphous silicon or microcrystalline silicon layer is completed in the fourth cathode in the fourth process chamber of PVD. The target material used for magnetron sputtering is tin-doped indium oxide, and the In2O3:SnO2 in tin-doped indium oxide is 90%:10%. The sputtering process gas is high-purity argon and oxygen. The ratio of these two gases introduced into the fourth process chamber is controlled to be 150:1. The final sputtering deposited film thickness is 120nm (the current step completes the TCO deposition on the back of the battery).

[0064] Step 4: Screen-print the silicon wafer after step 3 to form a silver electrode, and then anneal and perform light injection treatment to obtain a finished battery cell.

[0065] Comparative Example 2 This comparative example provides a conventional heterojunction battery, which is different from Example 1 in that the transparent conductive oxide layer on the back side is a laminated TCO film, which includes an MTCO layer (50 nm thick) and a TTCO layer (70 nm thick), and does not contain a BTCO layer.

[0066] The preparation method thereof comprises the following steps: Step 1: The silicon wafer used in this battery is an N-type single crystal silicon wafer, the resistivity of the silicon wafer is 0.3-2.1Ω·cm, the thickness of the silicon wafer is 130μm, and the size of the silicon wafer is 166*166mm. First, use ammonia water to clean the surface dirt of the silicon wafer, then use potassium hydroxide to alkaline polish it to remove the damaged layer, and then use texturing additives and potassium hydroxide to texturize it, so that the surface of the silicon wafer forms a pyramid structure, and the size of the velvet is about 2.5μm. Finally, after acid and alkali post-cleaning, a velvet structure with a high degree of cleanliness is achieved. Step 2: Use a plate-type PECVD (plasma chemical vapor deposition) device to deposit the first intrinsic amorphous silicon layer and N-type doped amorphous silicon or microcrystalline silicon layer on the front side of the silicon wafer prepared in step 1. The thickness of the first intrinsic amorphous silicon layer is 7nm, and the gases SiH4 and H2 are used; the N-type doped amorphous silicon or microcrystalline silicon layer is deposited to a thickness of 10nm, and the gases SiH4, H2, and PH3 are used, and the PH3 doping ratio is 3%. The second intrinsic amorphous silicon layer and P-type doped amorphous silicon or microcrystalline silicon layer are sequentially deposited on the back side of the silicon wafer; the second intrinsic amorphous silicon layer is deposited to a thickness of 12nm, and the gases SiH4 and H2 are used; the P-type doped amorphous silicon or microcrystalline silicon layer is deposited to a thickness of 15nm, and the gases SiH4, H2, and B2H6 are used, and the B2H6 doping ratio is 4%.

[0067] Step 3: After step 2, the silicon wafer is magnetron sputtered by PVD equipment to deposit a transparent conductive film (TCO) on the front and back of the silicon wafer. The deposition of ITO on the front n-type doped amorphous silicon or microcrystalline silicon layer is completed in the first process chamber (first cathode) of the PVD equipment. The target material used for magnetron sputtering is tin-doped indium oxide, and the ratio of In2O3:SnO2 in tin-doped indium oxide is 97%:3%. The sputtering process gases are high-purity argon and oxygen. The ratio of these two gases introduced into the first process chamber is controlled to be 150:1. The final sputtering deposition film thickness is 110nm (the current step completes the TCO deposition on the front side of the battery). On the back P-type doped amorphous silicon or microcrystalline silicon layer, a MTCO layer and a TTCO layer are sequentially deposited by magnetron sputtering of a PVD device to prepare a laminated TCO film; this step is completed in the third process chamber and the fourth process chamber of the PVD in turn, and the target material 3.1 and the target material 3.2 of the third cathode in the third process chamber are placed as aluminum-doped zinc oxide (AZO), and the ratio of ZnO:Al2O3 in the aluminum-doped zinc oxide (AZO) is 98%:2%, and the target material 4.1 and the target material 4.2 of the fourth cathode in the fourth process chamber are both placed as tin-doped indium oxide, and the ratio of In2O3:SnO2 in the tin-doped indium oxide is 90%:10%, and the sputtering process gases are both high-purity argon and oxygen. The ratio of the two gases introduced into the third process chamber is controlled to be 100:1; the final sputtering deposited film thickness is 50nm, and this layer is all AZO film. The ratio of the two gases introduced into the fourth process chamber is controlled to be 150:1; the final sputtering deposited film thickness is 70nm, and this layer is all ITO thin film (the current step completes the TCO deposition on the back side of the battery).

[0068] The silicon wafer after step 3 is screen-printed to form a silver electrode, and then annealed and light-injected to obtain a finished battery cell.

[0069] The performance data of the heterojunction cells of the embodiments and comparative examples are shown in Table 1 below.

[0070] Table 1

[0071] It can be seen from the data results of the above embodiments and comparative examples that the cell efficiency of the heterojunction battery prepared by the laminated TCO film of the present invention is above 25%, and the heterojunction battery of the present invention does not basically change the structure of the original magnetron sputtering equipment when preparing the laminated TCO film. The process method is simple and easy to implement, which can not only optimize the interface contact between the TCO film and the doped amorphous silicon, but also avoid the problems of increased square resistance of the entire TCO film layer and reduced transmittance of the TCO film caused by the conventional TCO laminated structure, so that the transmittance of the laminated TCO film is increased by more than 2% compared with Comparative Example 1. Importantly, the introduction of aluminum-doped zinc oxide (AZO) film can reduce the usage of ITO target by about 10-30%, thereby reducing the production cost of the target while ensuring that the conversion efficiency of the heterojunction solar cell is increased by 0.05%. When the battery efficiency of Examples 1 and 3 is higher than that of Comparative Example 1, AZO can also replace more than 15% of ITO, which can effectively reduce the preparation cost of the heterojunction battery. When the battery efficiency of Example 2 is only 0.1% lower than that of Comparative Example 1, AZO can replace more than 30% of ITO.

[0072] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A laminated TCO film, characterized in that: The invention comprises a BTCO layer, an MTCO layer and a TTCO layer in sequence. Along the BTCO layer toward the TTCO layer, the BTCO layer comprises a first ITO layer, a first doped metal oxide and ITO composite layer and a first doped metal oxide layer. The MTCO layer comprises a second doped metal oxide layer, a second doped metal oxide and ITO composite layer and a second ITO layer. The TTCO layer is a third ITO layer.

2. The laminated TCO film according to claim 1, characterized in that: The thickness of the BTCO layer is 15-20 nm; the thickness of the MTCO layer is 20-45 nm; the thickness of the TTCO layer is 50-70 nm; Preferably, the thicknesses of the BTCO layer, the MTCO layer and the TTCO layer satisfy: BTCO layer<MTCO layer<TTCO layer; More preferably, the thickness of the BTCO layer accounts for 15-20% of the total thickness of the stacked TCO film; And / or, the thickness of the MTCO layer accounts for 25-40% of the total thickness of the stacked TCO film; and / or, the thickness of the TTCO layer accounts for 45-60% of the total thickness of the stacked TCO film.

3. The laminated TCO film according to claim 1 or 2, characterized in that: The thickness of the first doped metal oxide and ITO composite layer is 0.5-3 nm; and / or the thickness of the second doped metal oxide and ITO composite layer is 0.5-3 nm.

4. The laminated TCO film according to any one of claims 1 to 3, characterized in that: The sum of the thickness of the first doped metal oxide layer and the second doped metal oxide layer is 10%-25% of the total film thickness of the stacked TCO thin film.

5. The laminated TCO film according to any one of claims 1 to 4, characterized in that: The doped metal oxide in the first doped metal oxide and the doped metal oxide in the second doped metal oxide are each independently one or more of AZO, a tin-based compound having a tin oxide weight content greater than 97%, and ITO having an indium oxide weight content less than 70%.

6. A heterojunction battery, characterized in that: include: Silicon substrate; A first intrinsic amorphous silicon film, an N-type doped silicon film, a front transparent conductive oxide layer and a first metal electrode are sequentially arranged on the front surface of the silicon substrate; A second intrinsic amorphous silicon film, a P-type doped silicon film, a back transparent conductive oxide layer and a second metal electrode are sequentially arranged on the back side of the silicon substrate, and the front transparent conductive oxide layer and / or the back transparent conductive oxide layer are the stacked TCO films described in any one of claims 1 to 5.

7. The method for preparing a heterojunction battery according to claim 6, characterized in that: The steps include: providing a silicon substrate; A first intrinsic amorphous silicon film and an N-type doped silicon film are sequentially deposited on the front side of the silicon substrate by a plasma chemical gas deposition method; a second intrinsic amorphous silicon film and a P-type doped silicon film are sequentially deposited on the back side of the silicon substrate by a plasma chemical gas deposition method; Depositing a front transparent conductive oxide layer on the N-type doped silicon film by magnetron sputtering; Depositing a back transparent conductive oxide layer on the P-type doped silicon film by magnetron sputtering; A first metal electrode is prepared on the front transparent conductive oxide layer; and a second metal electrode is prepared on the back transparent conductive oxide layer.

8. The preparation method according to claim 7, characterized in that: The step of depositing a back transparent conductive oxide layer on the P-type doped silicon film comprises: depositing a BTCO layer on the P-type doped silicon film; depositing an MTCO layer on the BTCO layer; and depositing a TTCO layer on the MTCO layer.

9. The preparation method according to claim 8, characterized in that: Depositing a front transparent conductive oxide layer on the N-type doped silicon film by magnetron sputtering is carried out in a first process chamber, the sputtering target is tin-doped indium oxide, the weight ratio of In2O3 and SnO2 in the tin-doped indium oxide is (90-97): (3-10), the sputtering process gas is argon and oxygen, and the volume ratio of argon and oxygen is (50-200): 1; And / or, the BTCO layer is deposited on the P-type doped silicon film on the same cathode in the second process chamber, and tin-doped indium oxide and aluminum-doped zinc oxide are sputtered in sequence, the weight ratio of In2O3 and SnO2 in the tin-doped indium oxide is (90-97): (3-10), the weight ratio of ZnO and Al2O3 in the aluminum-doped zinc oxide is (95-99): (1-5), and the sputtering process gas is argon and oxygen, and the volume ratio of argon and oxygen is (50-200): 1; And / or, the MTCO layer is deposited on the BTCO layer on the same cathode in the third process chamber, aluminum-doped zinc oxide and tin-doped indium oxide are sputtered in sequence, the weight ratio of ZnO and Al2O3 in the aluminum-doped zinc oxide is (95-99): (1-5), the weight ratio of In2O3 and SnO2 in the tin-doped indium oxide is (90-97): (3-10), and the sputtering process gas is argon and oxygen, and the volume ratio of argon and oxygen is (75-100): 1; and / or, depositing the TTCO layer on the MTCO layer is performed in a fourth process chamber, the sputtering target is tin-doped indium oxide, the weight ratio of In2O3 and SnO2 in the tin-doped indium oxide is (90-97): (3-10), the sputtering process gas is argon and oxygen, and the volume ratio of argon and oxygen is (50-200): 1; Preferably, the first process chamber, the second process chamber, the third process chamber and the fourth process chamber are connected in sequence.

10. The preparation method according to claim 9, characterized in that: The first process chamber, the second process chamber, the third process chamber, and the fourth process chamber independently satisfy at least one of parameters (1) to (3) during operation: The parameter (1) is that the pressure is controlled at 5e -1 -8e -1 Pa; The parameter (2) is that the temperature is controlled at 80-120°C; The parameter (3) is to control the water partial pressure at 1e -4 Pa to 3e -4 Pa.

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