Silicon optical chip structure and manufacturing method

Abstract

The invention discloses a silicon optical chip structure and a manufacturing method. The silicon optical chip structure comprises a dielectric isolation structure arranged below the surface of a substrate; the dielectric layer is arranged on the surface of the substrate; the first device layer and the second device layer are arranged in the dielectric layer, are sequentially arranged far away from the surface of the substrate and are separated from each other; the first device layer is provided with a first passive device, and the second device layer is provided with a second passive device and an active device; the end face coupling deep groove is arranged below the surface of the dielectric layer, the bottom of the end face coupling deep groove extends into the substrate, and the end face coupling deep groove is connected with the dielectric isolation structure. According to the invention, the stability and reliability of the chip structure can be improved, light can be effectively prevented from leaking into the substrate, and integration of a silicon light process and improvement of the performance of the silicon light chip are facilitated.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor integrated circuit process technology, and in particular to a silicon photonic chip structure and a manufacturing method. Background Art

[0002] In the era of big data, people have higher and higher requirements for the computing power and speed of electronic computer processing systems. Electronic chips developed based on Moore's Law have encountered great challenges in computing speed and power consumption. Photonic chips use photons as information carriers and have the advantages of high-speed parallelism and low power consumption. Therefore, they are considered to be a very promising solution for future applications in high-speed, large-volume, and artificial intelligence computing and processing.

[0003] Silicon photonics is an integrated circuit manufacturing technology based on silicon substrate materials that integrates various optical waveguides, optical modulators and photodetectors onto the same chip. It can make full use of existing semiconductor logic circuit manufacturing technology to achieve high-performance optoelectronic device integration.

[0004] In silicon photonic chips, end couplers are generally used as input / output devices of silicon photonic chips. However, since the optical mode spot size of ordinary optical fibers is much larger than that of the optical mode spot size in silicon photonic chips, such as end couplers, this will cause large insertion losses. Therefore, how to reduce the insertion loss of end couplers is an important research topic in silicon photonic chip manufacturing.

[0005] On the one hand, since the light spot size in the silicon nitride waveguide is larger than that in the silicon waveguide, the spot mismatch loss can be reduced by using a silicon nitride end coupler. However, silicon nitride materials are difficult to integrate with other silicon optical devices. On the other hand, in order to reduce the leakage loss of light into the substrate, it is usually necessary to use a substrate hollowing (Undercut) structure, but this will also bring mechanical stability and reliability problems. These will have an impact on the integrated application of silicon nitride materials in silicon optical chips. Summary of the invention

[0006] The purpose of the present invention is to overcome the above-mentioned defects in the prior art and provide a silicon photonic chip structure and a manufacturing method.

[0007] To achieve the above object, the technical solution of the present invention is as follows:

[0008] The present invention provides a silicon photonic chip structure, comprising:

[0009] substrate;

[0010] a dielectric isolation structure disposed below the surface of the substrate;

[0011] a dielectric layer disposed on the surface of the substrate;

[0012] A first device layer and a second device layer are arranged in the dielectric layer, the first device layer and the second device layer are arranged in sequence and spaced apart from the substrate surface; the first device layer is provided with a first passive device, and the second device layer is provided with a second passive device and an active device;

[0013] An end surface coupling deep groove is arranged below the surface of the dielectric layer and has a bottom extending into the substrate, and the end surface coupling deep groove is connected to the dielectric isolation structure.

[0014] Further, one of the first passive components is aligned with the dielectric isolation structure; or, one of the second passive components or one of the active components is aligned with the dielectric isolation structure; or, one of the second passive components and one of the active components are aligned with the dielectric isolation structure at different positions respectively; or, one of the second passive components is aligned with one of the first passive components and is aligned with the dielectric isolation structure at the same time.

[0015] Furthermore, the end face coupling deep groove is located on the outer side of the first device layer and the second device layer, and is arranged close to the same side of one of the first passive devices aligned with the dielectric isolation structure; and / or, the dielectric isolation structure includes a deep groove dielectric isolation structure.

[0016] Further, the first device layer material includes an annealed dielectric, and / or the second device layer material includes a semiconductor.

[0017] Further, the dielectric layer includes a first dielectric layer, a second dielectric layer and a third dielectric layer sequentially arranged on the surface of the substrate, the first device layer is located on the first dielectric layer and in the second dielectric layer, and the second device layer is located on the second dielectric layer and in the third dielectric layer; and / or, the third dielectric layer is also provided with connected conductive vias and metal interconnection layers, and the active device is led out through the conductive vias and the metal interconnection layers.

[0018] The present invention also provides a method for manufacturing a silicon photonic chip structure, comprising the following steps:

[0019] providing a substrate;

[0020] forming a dielectric isolation structure below the surface of the substrate;

[0021] forming a dielectric layer on the surface of the substrate;

[0022] Forming a first device layer and a second device layer in the dielectric layer, which are sequentially arranged away from the substrate surface and spaced apart from each other, and forming a first passive device in the first device layer, and forming a second passive device and an active device in the second device layer;

[0023] An end surface coupling deep groove with a bottom extending into the substrate is formed below the surface of the dielectric layer, and the end surface coupling deep groove is connected to the dielectric isolation structure.

[0024] Furthermore, a deep groove located in the substrate is formed on the surface of the substrate by using photolithography and etching processes, and the deep groove is filled by using a dielectric deposition process, and a deep groove dielectric isolation structure serving as the dielectric isolation structure is formed below the surface of the substrate by using a planarization process.

[0025] Further, forming a first device layer and a second device layer in the dielectric layer that are sequentially arranged away from the substrate surface and separated from each other, and forming a first passive device in the first device layer, and forming a second passive device and an active device in the second device layer, specifically includes:

[0026] forming a first dielectric layer and a first device layer in sequence on the surface of the substrate to cover the dielectric isolation structure;

[0027] Using a patterning process, forming a first passive device on the first device layer, and aligning the position of one of the first passive devices with the dielectric isolation structure;

[0028] forming a second dielectric layer on the surface of the first dielectric layer to cover the first passive device;

[0029] forming a second device layer on the surface of the second dielectric layer and covering the first passive device;

[0030] A second passive device and an active device are formed on the second device layer by a patterning process, and one of the second passive devices is located above one of the first passive devices aligned with the dielectric isolation structure and relatively aligned; or, one of the second passive devices is located above one of the first passive devices aligned with the dielectric isolation structure and relatively aligned, and one of the active devices is aligned with the dielectric isolation structure at a different position;

[0031] The step of forming an end face coupling deep groove with a bottom extending into the substrate below the surface of the dielectric layer, and connecting the end face coupling deep groove to the dielectric isolation structure specifically includes:

[0032] forming a third dielectric layer on the surface of the second dielectric layer to cover the second passive device and the active device;

[0033] Using a patterning process, forming a conductive via connected to the active device and a metal interconnection layer connected to the conductive via in the third dielectric layer;

[0034] Forming a fourth dielectric layer on the surface of the third dielectric layer, and using a patterning process to form a lead pad on the surface of the fourth dielectric layer that is connected to the metal interconnection layer at the bottom;

[0035] forming a dielectric passivation layer on the surface of the fourth dielectric layer, and using a patterning process to form a window on the surface of the dielectric passivation layer to expose the top of the pad; the first dielectric layer to the fourth dielectric layer and the dielectric passivation layer constitute the dielectric layer;

[0036] A step-by-step patterning process is adopted to first form a first deep trench whose bottom is located on the surface of the substrate below the surface of the passivation layer, and then a second deep trench whose bottom extends into the substrate is formed on the bottom of the first deep trench, thereby forming an end-face coupled deep trench composed of the first deep trench and the second deep trench, and the first deep trench is located on the outer side of the first device layer and the second device layer, and is arranged on the same side of a first passive device and a second passive device aligned with the dielectric isolation structure, so that the side wall of the second deep trench is connected to the side of the dielectric isolation structure aligned with the first passive device.

[0037] Furthermore, before forming the first passive component, the method further includes:

[0038] The first device layer is annealed to drive out hydrogen in the material of the first device layer and reduce the absorption of C-band light by the material of the first device layer.

[0039] Further, forming a second device layer on the surface of the second dielectric layer specifically includes:

[0040] Providing an SOI substrate, wherein the SOI substrate comprises a bottom silicon layer, a buried oxide layer and a top silicon layer arranged in sequence;

[0041] forming a fifth dielectric layer on the surface of the top silicon layer;

[0042] Aligning the SOI substrate with the substrate, and bonding the surface of the fifth dielectric layer with the surface of the second dielectric layer through the surface of the fifth dielectric layer;

[0043] removing the bottom silicon layer and the buried oxide layer, and sequentially forming the fifth dielectric layer and the top silicon layer as the second device layer on the surface of the second dielectric layer;

[0044] The first dielectric layer to the fifth dielectric layer and the dielectric passivation layer constitute the dielectric layer.

[0045] It can be seen from the above technical scheme that the present invention forms a dielectric isolation structure in the substrate, and uses the dielectric isolation structure to cooperate with the dielectric layer on the substrate to form an optical isolation layer with a certain depth, which can effectively prevent the light transmitted to the first passive device, the second passive device, and the active device aligned with the dielectric isolation structure from leaking into the substrate, and can reduce thermal crosstalk, improve the characteristics of silicon photonic chip devices, and no longer need to form a traditional substrate hollowing structure, thereby completely avoiding the process risks of collapse, peeling, etc., and improving mechanical stability, reliability and yield. In addition, by using annealed dielectric as the material for forming the first passive device, a high-performance optical passive device that is superior to ordinary semiconductor materials can be formed, and the influence of high-temperature processes on the formation of active devices can be avoided; by using the top silicon layer of the SOI substrate to form the second device layer, a high degree of integration of high-performance optoelectronic devices including active devices and passive devices is achieved on a single chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] Figure 1 This is a schematic diagram of a silicon photonic chip structure according to a preferred embodiment of the present invention.

[0047] Figure 2 The present invention is a flowchart of a method for manufacturing a silicon photonic chip structure according to a preferred embodiment of the present invention.

[0048] Figure 3-Figure 11 A preferred embodiment of the present invention is based on Figure 2 Schematic diagram of the process steps for forming a silicon photonic chip structure using the method. DETAILED DESCRIPTION

[0049] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention. Unless otherwise defined, the technical terms or scientific terms used herein should be understood by people with general skills in the field to which the present invention belongs. "Including" and similar words used in this article mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects.

[0050] The specific implementation modes of the present invention are further described in detail below in conjunction with the accompanying drawings.

[0051] refer to Figure 1A silicon photonic chip structure of the present invention comprises a dielectric isolation structure 202 disposed below the upper surface of a substrate 201, a dielectric layer 211 disposed on the upper surface of the substrate 201, a first device layer 204 and a second device layer 206 disposed in the dielectric layer 211, and an end face coupling deep groove 210 disposed below the surface of the dielectric layer 211 and extending to the bottom of the substrate 201.

[0052] The first device layer 204 and the second device layer 206 are sequentially arranged above the upper surface of the substrate 201, and the first device layer 204 and the second device layer 206 are separated by the dielectric layer 211 and are separated from the substrate 201. The first device layer 204 is provided with a first passive device; the second device layer 206 is provided with a second passive device and an active device.

[0053] The lower portion of the end surface coupling deep trench 210 is connected to the dielectric isolation structure 202 .

[0054] refer to Figure 1 In some embodiments, a first passive component (first end face coupler 2041 ) is disposed in the first component layer 204 and aligned with the dielectric isolation structure 202 in a vertical position.

[0055] In some embodiments, a second passive device (second end face coupler 2061 ) or an active device (thermal phase shifter 2063 ) in the second device layer 206 is aligned with the dielectric isolation structure 202 in the upper and lower positions.

[0056] In some embodiments, the second device layer 206 includes a second passive device (second end face coupler 2061 ) and an active device (thermal phase shifter 2063 ) which are aligned with the dielectric isolation structure 202 at different positions.

[0057] In some embodiments, a second passive component (second end face coupler 2061) in the second component layer 206 is aligned with a first passive component (first end face coupler 2041) in the first component layer 204 in an upper and lower position, and is also aligned with the dielectric isolation structure 202 at a lower position.

[0058] In some embodiments, the end coupling deep trench 210 is located at the outer side of the first device layer 204 and the second device layer 206 (eg Figure 1 As shown, the end surface coupling deep groove 210 is located on the left side of the periphery of the first device layer 204 and the second device layer 206 , and is arranged on the same side (ie, the left side) of a first passive device (first end surface coupler 2041 ) aligned with the dielectric isolation structure 202 .

[0059] In some embodiments, the dielectric isolation structure 202 includes a deep trench dielectric isolation structure 202 , that is, a deep trench isolation structure filled with dielectric. The depth of the deep trench isolation structure in the substrate 201 is greater than the depth of a conventional shallow trench isolation (STI) structure in the substrate 201 .

[0060] refer to Figure 1 In some embodiments, the dielectric layer 211 includes a first dielectric layer 203, a second dielectric layer 205, and a third dielectric layer 207 sequentially disposed on the upper surface of the substrate 201. The first device layer 204 is located on the first dielectric layer 203 and in the second dielectric layer 205; the second device layer 206 is located on the second dielectric layer 205 and in the third dielectric layer 207.

[0061] In some embodiments, the third dielectric layer 207 is further provided with connected conductive vias 208 and metal interconnection layers 209. The active devices (modulator 2062, thermal phase shifter 2063, photodetector 2065) of the second device layer 206 are led out through the conductive vias 208 and metal interconnection layers 209.

[0062] In some embodiments, the substrate 201 may be a semiconductor substrate 201 , for example, the substrate 201 may be a silicon substrate 201 .

[0063] The filling medium in the deep trench of the dielectric isolation structure 202 may be, for example, silicon dioxide, but is not limited thereto.

[0064] The material of the first device layer 204 includes an annealed dielectric, such as annealed silicon nitride, silicon oxynitride, aluminum nitride or silicon carbide.

[0065] The material of the second device layer 206 includes a semiconductor, such as a silicon semiconductor.

[0066] In some embodiments, the first passive device includes a first end face coupler 2041 and other first passive devices 2042 (such as waveguides, etc.) The first end face coupler 2041 is aligned with the dielectric isolation structure 202 located below to prevent light from leaking to the substrate 201 .

[0067] In some embodiments, the second passive device includes a second end face coupler 2061 and other second passive devices 2064 (such as waveguides, etc.). The active device includes a modulator 2062, a thermal phase shifter 2063, and a photodetector 2065. The second end face coupler 2061 is aligned with the first end face coupler 2041 and the dielectric isolation structure 202 located at the lower position, which can prevent light from leaking to the substrate 201. The thermal phase shifter 2063 is aligned with the dielectric isolation structure 202 located at the lower position at different positions, which can prevent light from leaking to the substrate 201 and reduce thermal crosstalk, thereby improving device characteristics.

[0068] The conductive via 208 may be, for example, a conductive tungsten via.

[0069] The metal interconnection layer 209 can be made of, for example, copper metal interconnection lines in one or more layers.

[0070] In some embodiments, the second device layer 206 is formed using another SOI substrate. The SOI substrate includes a bottom silicon layer, a buried oxide layer, and a top silicon layer arranged in sequence. A fifth dielectric layer is formed on the surface of the top silicon layer; by aligning the SOI substrate with the substrate 201, and bonding the surface of the fifth dielectric layer to the surface of the second dielectric layer 205 on the substrate 201, and removing the bottom silicon layer and the buried oxide layer after bonding, a fifth dielectric layer (not shown) and a top silicon layer are sequentially formed on the upper surface of the second dielectric layer 205 after removing the bottom silicon layer and the buried oxide layer, and the top silicon layer is used as the second device layer 206. The second device layer 206 can also be formed using another silicon substrate.

[0071] In some embodiments, a fourth dielectric layer (not shown) is further formed on the upper surface of the third dielectric layer 207, and a lead pad of the bottom connection metal interconnection layer 209 is formed on the upper surface of the fourth dielectric layer. The pad may be, for example, an aluminum pad.

[0072] A dielectric passivation layer is formed on the upper surface of the fourth dielectric layer, and a window is formed on the surface of the dielectric passivation layer, and the top of the pad is exposed from the window. The dielectric passivation layer can be a multi-layer stack, for example, the dielectric passivation layer can be a stack of silicon dioxide and silicon nitride.

[0073] The first dielectric layer 203 to the fifth dielectric layer and the dielectric passivation layer together constitute a dielectric layer 211 located on the upper surface of the substrate 201. The end face coupling deep groove 210 also passes through the dielectric passivation layer, the fourth dielectric layer, the third dielectric layer 207, the fifth dielectric layer, the second dielectric layer 205 and the first dielectric layer 203 from the upper surface of the dielectric passivation layer downward, and extends to the bottom in the substrate 201.

[0074] In some embodiments, the end face coupling deep trench 210 includes a first deep trench 2101 and a second deep trench 2102 connected from top to bottom. The first deep trench 2101 is formed in the dielectric layer 211 from the surface of the dielectric layer 211 downward, and the bottom of the first deep trench 2101 is located on the upper surface of the substrate 201; the second deep trench 2102 is formed in the substrate 201 from the upper surface of the substrate 201 downward. The opening top of the second deep trench 2102 is connected to the bottom of the first deep trench 2101, and the first deep trench 2101 is located on the left side of the periphery of the first device layer 204 and the second device layer 206, and is arranged close to the left side of a first end face coupler 2041 and a second end face coupler 2061 aligned with the dielectric isolation structure 202; at the same time, the sidewall of the second deep trench 2102 is connected to the side of the dielectric isolation structure 202 aligned with the first end face coupler 2041.

[0075] The materials of the first dielectric layer 203, the second dielectric layer 205, the fourth dielectric layer and the fifth dielectric layer can be, for example, silicon dioxide. The third dielectric layer 207 serves as an interlayer dielectric layer (ILD). It should be noted that the various materials listed above are only used to illustrate the embodiments of the present invention, and are not used to limit the types of materials used in the structure of the present invention.

[0076] The following is a further detailed description of a method for manufacturing a silicon photonic chip structure of the present invention through specific implementation methods and in combination with the accompanying drawings.

[0077] refer to Figure 2 Combined with reference Figure 3-Figure 11 The present invention provides a method for manufacturing a silicon photonic chip structure, which can be used to manufacture the above-mentioned Figure 1 A silicon photonic chip structure of the present invention may include the following steps:

[0078] Step S1: providing a substrate 201 .

[0079] like Figure 3 As shown, a silicon wafer substrate 201 can be used to manufacture the above-mentioned Figure 1 A silicon photonic chip structure of the present invention.

[0080] Step S2 : forming a dielectric isolation structure 202 below the surface of the substrate 201 .

[0081] like Figure 3As shown, a deep groove located in the substrate 201 is formed on the upper surface of the substrate 201 by using a photolithography and etching process. Then, a dielectric deposition process is used to fill the deep groove. The filling medium can be, for example, silicon dioxide. Afterwards, a planarization process is used to remove the excess silicon dioxide dielectric filling material on the upper surface of the substrate 201, thereby forming a deep groove dielectric isolation structure 202 (deep trench isolation structure) as a dielectric isolation structure 202 below the upper surface of the substrate 201. The depth of the formed deep groove (dielectric isolation structure 202) is 10,000 to 50,000 angstroms. In this embodiment, a deep groove with a depth of 20,000 angstroms is formed on the upper surface of the silicon substrate 201 by using a photolithography and etching process. Then, a CVD process, such as a PECVD process or a HDPCVD process, is used to deposit 30,000 angstroms of silicon dioxide dielectric on the upper surface of the silicon substrate 201. Next, a chemical mechanical polishing process is used to remove excess silicon dioxide on the upper surface of the silicon substrate 201 to form a deep trench isolation structure (deep trench dielectric isolation structure 202) with a depth of 20,000 angstroms.

[0082] Step S3: forming a dielectric layer 211 on the surface of the substrate 201, forming a first device layer 204 and a second device layer 206 in the dielectric layer 211 which are arranged in sequence away from the surface of the substrate 201 and are separated from each other, forming a first passive device in the first device layer 204, and forming a second passive device and an active device in the second device layer 206.

[0083] like Figure 4 As shown, a first dielectric layer 203 is formed on the upper surface of the silicon substrate 201 to cover the dielectric isolation structure 202. The thickness of the first dielectric layer 203 is 15000 to 35000 angstroms. In this embodiment, a 20000 angstrom silicon dioxide first dielectric layer 203 is deposited by LPCVD process as a dielectric isolation layer between the first device layer 204 and the substrate 201.

[0084] like Figure 5 As shown, a first device layer 204 is formed on the upper surface of the first dielectric layer 203 to cover the dielectric isolation structure 202 below. The first device layer 204 has a thickness of 500 to 10,000 angstroms and is used to form a first passive device such as a high-performance waveguide. In this embodiment, 4,000 angstroms of high-performance waveguide material silicon nitride is deposited by LPCVD process to form the first device layer 204.

[0085] Then, the first device layer 204 formed of the high-performance waveguide material is subjected to high-temperature annealing at a temperature of 700-1300° C. to drive out hydrogen in the material of the first device layer 204 and reduce the absorption of C-band light by the material of the first device layer 204. In this embodiment, the silicon substrate 201 having the first device layer 204 of the high-performance waveguide material silicon nitride is placed in a nitrogen atmosphere and annealed at 1200° C. for about 1 hour, so that the NH bonds and Si-H bonds in the high-performance waveguide material silicon nitride are broken, and H is driven out of the silicon nitride film, thereby achieving the effect of reducing the absorption of C-band light.

[0086] like Figure 6 As shown, then, a first passive device is formed on the first device layer 204 by a patterning process, and a first passive device is aligned with the dielectric isolation structure 202. In this embodiment, a high-performance silicon nitride waveguide material is patterned by a photolithography and etching process to form a silicon nitride first end face coupler 2041 and other first silicon nitride passive devices 2042 (such as silicon nitride waveguides) as the first passive device. The formed silicon nitride first end face coupler 2041 is located directly above the dielectric isolation structure 202, which can prevent light from leaking to the silicon substrate 201 and improve device characteristics.

[0087] like Figure 7 As shown, a second dielectric layer 205 is formed on the surface of the first dielectric layer 203 to cover the first passive device. In this embodiment, a 6000 angstrom silicon dioxide second dielectric layer 205 is deposited by LPCVD process or PECVD process to cover the silicon nitride first passive device, and together with the first dielectric layer 203, it serves as a dielectric isolation layer between the second device layer 206 and the substrate 201, and a chemical mechanical polishing process is used to flatten the upper surface of the second dielectric layer 205.

[0088] like Figure 8 As shown, a silicon second device layer 206 is formed on the surface of the second dielectric layer 205 and covers the first passive device. The thickness of the silicon second device layer 206 is 1000 to 30000 angstroms. The silicon second device layer 206 located on the second dielectric layer 205 can be formed by transferring the top silicon layer of the SOI substrate (or other silicon substrate) onto the upper surface of the planarized second dielectric layer 205.

[0089] In this embodiment, an SOI substrate is used, and the SOI substrate includes a bottom silicon layer, a buried oxide layer, and a top silicon layer arranged in sequence. The thickness of the top silicon layer is 2200 angstroms. And the LPCVD process is used to deposit 1000 angstroms of silicon dioxide on the surface of the top silicon layer of the SOI substrate as the fifth dielectric layer (not shown). Then, the SOI substrate is aligned with the silicon substrate 201, and the silicon dioxide-silicon dioxide fusion bonding process is used to bond the SOI substrate face to face with the silicon substrate 201 formed with the second dielectric layer 205 of silicon dioxide through the surface of the fifth dielectric layer. Afterwards, the bottom silicon layer and the buried oxide layer of the SOI substrate are removed to form a fifth dielectric layer and a silicon second device layer 206 (top silicon layer) located in sequence on the second dielectric layer 205.

[0090] like Fig. 9 As shown, a second passive device and an active device are formed on the second device layer 206 by using a patterning process, and a second passive device is located above a first passive device aligned with the dielectric isolation structure 202 and aligned with each other. Furthermore, an active device is also aligned with the dielectric isolation structure 202 at a different position.

[0091] In this embodiment, photolithography, etching and other processes are used to complete silicon patterning of different depths on the second device layer 206. Then, various silicon-based devices and germanium-based devices of the silicon photonic chip are formed by injection, germanium epitaxial process and patterning process for different devices. Among them, the silicon-based device includes a second end face coupler 2061 as a second passive device, other second passive devices 2064 (such as waveguides), and a modulator 2062 and a thermal phase shifter 2063 as active devices. The germanium-based device includes a germanium photodetector 2065 as an active device. The formed second end face coupler 2061 is located directly above the dielectric isolation structure 202, which can prevent light from leaking to the silicon substrate 201. The thermal phase shifter 2063 is located directly above the dielectric isolation structure 202 at different positions, which can prevent light from leaking to the silicon substrate 201 and reduce thermal crosstalk, thereby improving device characteristics.

[0092] Step S4 : forming an end surface coupling deep trench 210 with a bottom extending into the substrate 201 below the surface of the dielectric layer 211 , and connecting the end surface coupling deep trench 210 to the dielectric isolation structure 202 .

[0093] like Fig.10As shown, a third dielectric layer 207 is formed on the surface of the second dielectric layer 205 to cover the second passive device and the active device. In this embodiment, a conventional CMOS process is used to first deposit a first interlayer dielectric layer as a component of the third dielectric layer 207. Then, tungsten conductive vias 208 are formed in the first interlayer dielectric layer by using processes such as photolithography, etching, tungsten deposition and CMP, and the tungsten conductive vias 208 are respectively connected to the modulator 2062, the thermal phase shifter 2063 and the germanium photodetector 2065 below. Then, a second interlayer dielectric layer as a component of the third dielectric layer 207 is continuously deposited, and a copper metal interconnection layer 209 connected to the tungsten conductive via 208 is formed by using a Damascene process. The copper metal interconnection layer 209 can be a single copper metal interconnection line layer, or a multi-layer copper metal interconnection line layer formed by using multiple Damascene processes.

[0094] Then, further, it also includes forming a fourth dielectric layer on the surface of the third dielectric layer 207, and using a patterning process to form a lead-out pad for the bottom connected metal interconnection layer 209 on the surface of the fourth dielectric layer; forming a dielectric passivation layer on the surface of the fourth dielectric layer, and using a patterning process to form a window on the surface of the dielectric passivation layer to expose the top of the pad (not shown above). In this embodiment, a fourth dielectric layer of silicon dioxide is first deposited on the surface of the third dielectric layer 207; then, a pad through hole is formed on the upper surface of the fourth dielectric layer using a photolithography and etching process; then, aluminum is deposited and patterned to form an aluminum pad for lead-out; then, silicon dioxide and silicon nitride are deposited on the upper surface of the fourth dielectric layer as a dielectric passivation layer, and a window is formed on the upper surface of the dielectric passivation layer using a photolithography and etching process to expose the top of the aluminum pad. The first dielectric layer 203 to the fifth dielectric layer and the dielectric passivation layer together constitute, for example Figure 1 The dielectric layer 211 in the.

[0095] Finally Fig.11As shown, a step-by-step patterning process is used to first form a first deep trench 2101 with a bottom located on the surface of the substrate 201 below the surface of the dielectric passivation layer, and then a second deep trench 2102 with a bottom extending into the substrate 201 is formed on the bottom of the first deep trench 2101, thereby forming an end face coupling deep trench 210 consisting of the first deep trench 2101 and the second deep trench 2102. In this embodiment, a dielectric etching process is first used to etch each dielectric layer 211 (a dielectric passivation layer, a fourth dielectric layer, a third dielectric layer 207, a fifth dielectric layer, a second dielectric layer 205, and a first dielectric layer 203) above the silicon substrate 201 to form a first deep trench 2101 with a bottom located on the surface of the silicon substrate 201. Then, a deep silicon etching process, such as a Bosch process, is used to continue etching the silicon substrate 201 to form a second deep trench 2102 with a depth of, for example, about 100 μm in the silicon substrate 201 to form a complete end face coupling deep trench 210. The first deep trench 2101 can be located on the left side of the periphery of the first device layer 204 and the second device layer 206, and can be arranged close to the left side of a first end face coupler 2041 and a second end face coupler 2061 aligned with the dielectric isolation structure 202; at the same time, the side wall of the second deep trench 2102 is connected to the side of the dielectric isolation structure 202 aligned with the first end face coupler 2041. After etching, cleaning can be performed to complete the silicon photonic process.

[0096] In summary, the present invention forms a dielectric isolation structure 202 in the substrate 201, and utilizes the dielectric isolation structure 202 to cooperate with the dielectric layer 211 (the first dielectric layer 203, the second dielectric layer 205) on the substrate 201 to form an optical isolation layer with sufficient depth between the first device layer 204 and the second device layer 206 and the substrate 201. This can effectively prevent the light transmitted to the first passive device (first end face coupler 2041), the second passive device (second end face coupler 2061), and the active device (thermal phase shifter 2063) aligned with the dielectric isolation structure 202 from leaking into the substrate 201, and can reduce the thermal crosstalk of the active device thermal phase shifter 2063, thereby improving the device characteristics of the silicon photonic chip, and there is no need to form a traditional substrate hollowing structure, thereby completely avoiding the process risks of collapse, peeling, etc., and improving the mechanical stability, reliability and yield. Furthermore, by using an annealed dielectric (e.g., a high-performance waveguide material such as silicon nitride annealed at high temperature) as the material for forming the first passive device, a high-performance optical passive device superior to ordinary semiconductor materials can be formed, and the influence of high-temperature processes on the formation of active devices can be avoided. By also using the top silicon layer of the SOI substrate to form the second device layer 206, a high degree of integration of high-performance optoelectronic devices including active devices and passive devices is achieved on a single chip.

[0097] Although the embodiments of the present invention are described in detail above, it is obvious to those skilled in the art that various modifications and variations can be made to these embodiments. However, it should be understood that such modifications and variations are within the scope and spirit of the present invention as described in the claims. Moreover, the present invention described herein may have other embodiments and may be implemented or realized in a variety of ways.

Claims

1. A silicon photonic chip structure, characterized in that: include: substrate; a dielectric isolation structure disposed below the surface of the substrate; a dielectric layer disposed on the surface of the substrate; A first device layer and a second device layer are arranged in the dielectric layer, the first device layer and the second device layer are arranged in sequence and spaced apart from the substrate surface; the first device layer is provided with a first passive device, and the second device layer is provided with a second passive device and an active device; An end surface coupling deep groove is arranged below the surface of the dielectric layer and has a bottom extending into the substrate, and the end surface coupling deep groove is connected to the dielectric isolation structure.

2. The silicon photonic chip structure according to claim 1, characterized in that: One of the first passive components is aligned with the dielectric isolation structure; or one of the second passive components or one of the active components is aligned with the dielectric isolation structure; or one of the second passive components and one of the active components are aligned with the dielectric isolation structure at different positions; Alternatively, one of the second passive components is aligned with one of the first passive components and is aligned with the dielectric isolation structure at the same time.

3. The silicon photonic chip structure according to claim 2, characterized in that: The end face coupling deep trench is located at the outer side of the first device layer and the second device layer, and is arranged close to the same side of one of the first passive devices aligned with the dielectric isolation structure; and / or the dielectric isolation structure includes a deep trench dielectric isolation structure.

4. The silicon photonic chip structure according to claim 1, characterized in that: The first device layer material comprises an annealed dielectric, and / or the second device layer material comprises a semiconductor.

5. The silicon photonic chip structure according to claim 1, characterized in that: The dielectric layer comprises a first dielectric layer, a second dielectric layer and a third dielectric layer which are sequentially arranged on the surface of the substrate, the first device layer is located on the first dielectric layer and in the second dielectric layer, and the second device layer is located on the second dielectric layer and in the third dielectric layer; and / or, the third dielectric layer is further provided with connected conductive vias and a metal interconnection layer, and the active device is led out through the conductive vias and the metal interconnection layer.

6. A method for manufacturing a silicon photonic chip structure, characterized in that: The following steps are involved: providing a substrate; forming a dielectric isolation structure below the surface of the substrate; forming a dielectric layer on the surface of the substrate; Forming a first device layer and a second device layer in the dielectric layer, which are sequentially arranged away from the substrate surface and spaced apart from each other, and forming a first passive device in the first device layer, and forming a second passive device and an active device in the second device layer; An end surface coupling deep groove with a bottom extending into the substrate is formed below the surface of the dielectric layer, and the end surface coupling deep groove is connected to the dielectric isolation structure.

7. The method for manufacturing a silicon photonic chip structure according to claim 6, characterized in that: A deep trench located in the substrate is formed on the surface of the substrate by using photolithography and etching processes, and the deep trench is filled by using a dielectric deposition process, and a deep trench dielectric isolation structure serving as the dielectric isolation structure is formed below the surface of the substrate by using a planarization process.

8. The method for manufacturing a silicon photonic chip structure according to claim 6, characterized in that: The step of forming a first device layer and a second device layer in the dielectric layer that are sequentially arranged away from the substrate surface and separated from each other, and forming a first passive device in the first device layer, and forming a second passive device and an active device in the second device layer specifically includes: forming a first dielectric layer and a first device layer in sequence on the surface of the substrate to cover the dielectric isolation structure; Using a patterning process, forming a first passive device on the first device layer, and aligning the position of one of the first passive devices with the dielectric isolation structure; forming a second dielectric layer on the surface of the first dielectric layer to cover the first passive device; forming a second device layer on the surface of the second dielectric layer and covering the first passive device; A second passive device and an active device are formed on the second device layer by a patterning process, and one of the second passive devices is located above one of the first passive devices aligned with the dielectric isolation structure and relatively aligned; or, one of the second passive devices is located above one of the first passive devices aligned with the dielectric isolation structure and relatively aligned, and one of the active devices is aligned with the dielectric isolation structure at a different position; The step of forming an end face coupling deep groove with a bottom extending into the substrate below the surface of the dielectric layer, and connecting the end face coupling deep groove to the dielectric isolation structure specifically includes: forming a third dielectric layer on the surface of the second dielectric layer to cover the second passive device and the active device; Using a patterning process, forming a conductive via connected to the active device and a metal interconnection layer connected to the conductive via in the third dielectric layer; Forming a fourth dielectric layer on the surface of the third dielectric layer, and using a patterning process to form a lead pad on the surface of the fourth dielectric layer that is connected to the metal interconnection layer at the bottom; forming a dielectric passivation layer on the surface of the fourth dielectric layer, and using a patterning process to form a window on the surface of the dielectric passivation layer to expose the top of the pad; the first dielectric layer to the fourth dielectric layer and the dielectric passivation layer constitute the dielectric layer; A step-by-step patterning process is adopted to first form a first deep trench whose bottom is located on the surface of the substrate below the surface of the passivation layer, and then a second deep trench whose bottom extends into the substrate is formed on the bottom of the first deep trench, thereby forming an end-face coupled deep trench composed of the first deep trench and the second deep trench, and the first deep trench is located on the outer side of the first device layer and the second device layer, and is arranged on the same side of a first passive device and a second passive device aligned with the dielectric isolation structure, so that the side wall of the second deep trench is connected to the side of the dielectric isolation structure aligned with the first passive device.

9. The method for manufacturing a silicon photonic chip structure according to claim 8, characterized in that: Before forming the first passive component, the method further includes: The first device layer is annealed to drive out hydrogen in the material of the first device layer and reduce the absorption of C-band light by the material of the first device layer.

10. The method for manufacturing a silicon photonic chip structure according to claim 8, characterized in that: The forming of the second device layer on the surface of the second dielectric layer specifically includes: Providing an SOI substrate, wherein the SOI substrate comprises a bottom silicon layer, a buried oxide layer and a top silicon layer arranged in sequence; forming a fifth dielectric layer on the surface of the top silicon layer; Aligning the SOI substrate with the substrate, and bonding the surface of the fifth dielectric layer with the surface of the second dielectric layer through the surface of the fifth dielectric layer; removing the bottom silicon layer and the buried oxide layer, and sequentially forming the fifth dielectric layer and the top silicon layer as the second device layer on the surface of the second dielectric layer; The first dielectric layer to the fifth dielectric layer and the dielectric passivation layer constitute the dielectric layer.

Images