Display chip and manufacturing method

Abstract

The invention discloses a display chip and a manufacturing method, and belongs to the technical field of semiconductors. The display chip comprises a chip structure which comprises a first semiconductor layer, a quantum well light-emitting layer and a second semiconductor layer which are arranged in sequence; one of the first semiconductor layer and the second semiconductor layer is an n-type semiconductor layer, and the other one of the first semiconductor layer and the second semiconductor layer is a p-type semiconductor layer; wherein the first semiconductor layer, the quantum well light-emitting layer and the second semiconductor layer are nitrogen polar film layers. The light-emitting efficiency of the display chip can be improved.

Description

Technical Field

[0001] The present application belongs to the field of semiconductor technology, and in particular, relates to a display chip and a manufacturing method thereof. Background Art

[0002] At present, the film material in display devices such as micro light-emitting diodes (Micro-LEDs) is gallium-polar material. The growth temperature of the gallium-polar film layer is low, resulting in a high threading dislocation density, accompanied by the quantum confined Stark effect caused by the strong polarization electric field in the quantum well, resulting in low luminescence efficiency of the display device. Summary of the invention

[0003] The present application aims to solve at least one of the technical problems existing in the prior art. To this end, the present application proposes a display chip and a manufacturing method, which can improve the luminous efficiency of the display chip.

[0004] In a first aspect, the present application provides a display chip, including:

[0005] A chip structure comprises a first semiconductor layer, a quantum well light-emitting layer and a second semiconductor layer arranged in sequence; one of the first semiconductor layer and the second semiconductor layer is an n-type semiconductor layer, and the other is a p-type semiconductor layer;

[0006] Wherein, the first semiconductor layer, the quantum well light-emitting layer and the second semiconductor layer are all nitrogen-polar film layers.

[0007] According to the display chip of the present application, the first semiconductor layer, the quantum well light-emitting layer and the second semiconductor layer are all nitrogen-polar film layers. The nitrogen-polar film layers can be grown at high temperatures, thereby improving the crystal quality of the potential well layer material in the quantum well, improving the chip carrier injection efficiency, and effectively suppressing the overflow of carriers, thereby alleviating the Droop effect of the chip under large current injection, and improving the luminescence efficiency of the display chip.

[0008] According to one embodiment of the present application, the chip structure further includes a fourth undoped semiconductor layer, a first barrier layer, a first superlattice layer, and a second superlattice layer, which are sequentially arranged between the first semiconductor layer and the quantum well light-emitting layer;

[0009] The fourth undoped semiconductor layer, the first barrier layer, the first superlattice layer and the second superlattice layer are all nitrogen-polar film layers.

[0010] According to one embodiment of the present application, the fourth undoped semiconductor layer includes a u-GaN layer, the first barrier layer includes a GaN layer, and the first superlattice layer includes a u-In a Ga 1-a N / u-GaN superlattice layer, 0.01≤a≤0.05; the second superlattice layer includes u-In bGa 1-b N / n-GaN superlattice layer, 0.05≤b≤0.1.

[0011] According to one embodiment of the present application, the first semiconductor layer includes a heavily doped semiconductor layer and a lightly doped semiconductor layer located between the heavily doped semiconductor layer and the quantum well light emitting layer;

[0012] The heavily doped semiconductor layer and the lightly doped semiconductor layer are both nitrogen polar film layers.

[0013] According to one embodiment of the present application, the heavily doped semiconductor layer includes an n-GaN heavily doped layer or an n-Al c Ga 1- c N / n-GaN superlattice layer, 0.02≤c≤0.15; the lightly doped semiconductor layer includes an n-GaN lightly doped layer or an n-Al g Ga 1- g N / n-GaN superlattice layer, 0.02≤g≤0.08.

[0014] According to one embodiment of the present application, the quantum well light-emitting layer includes a fifth undoped semiconductor layer, a first potential well layer, a first cap layer, a second potential barrier layer, a sixth undoped semiconductor layer, a second potential well layer, a second cap layer and a third potential barrier layer, which are sequentially arranged between the first semiconductor layer and the second semiconductor layer;

[0015] The fifth undoped semiconductor layer, the first potential well layer, the first cap layer, the second potential barrier layer, the sixth undoped semiconductor layer, the second potential well layer, the second cap layer and the third potential barrier layer are all nitrogen polar film layers.

[0016] According to one embodiment of the present application, the fifth undoped semiconductor layer and the sixth undoped semiconductor layer both include u-GaN layers, the first cap layer and the second cap layer both include GaN layers; the first potential well layer includes u-In x Ga 1-x N layer, 0.1≤x≤0.15; the second barrier layer includes a GaN layer or a u-In y Ga 1-y N layer, 0.01≤y≤0.03; the second potential well layer includes u-In z Ga 1-z N layer, 0.35≤z≤0.4; the third barrier layer includes u-Al d Ga 1-d N layers, 0.3≤d≤0.35.

[0017] According to one embodiment of the present application, the second semiconductor layer includes an electron blocking layer, a hole injection layer and an ohmic contact layer which are sequentially arranged on a side of the quantum well light-emitting layer away from the first semiconductor layer;

[0018] The electron blocking layer, the hole injection layer and the ohmic contact layer are all nitrogen polar film layers.

[0019] According to one embodiment of the present application, the electron blocking layer includes a p-AlGaN polarization inducing layer or a p-Al e Ga 1- e N / p-GaN superlattice layer, 0.15≤e≤0.25; the hole injection layer includes a p-GaN layer; the ohmic contact layer includes a p-In f Ga 1-f N / p-GaN superlattice layer, 0.1≤f≤0.2.

[0020] According to an embodiment of the present application, the chip structure further includes a first transparent conductive layer, a first reflective layer, and a bonding layer, which are sequentially located on a side of the second semiconductor layer away from the quantum well light-emitting layer.

[0021] According to one embodiment of the present application, the chip structure further includes a protective layer located between the quantum well light-emitting layer and the second semiconductor layer.

[0022] According to one embodiment of the present application, the quantum well light-emitting layer includes a red light quantum well light-emitting layer.

[0023] According to an embodiment of the present application, the display chip further includes a substrate; the substrate is bonded to a side of the chip structure facing away from the first semiconductor layer.

[0024] According to one embodiment of the present application, the display chip further includes a passivation layer and a second reflective layer;

[0025] The passivation layer is located on a side of the chip structure away from the substrate and covers a side wall of the chip structure, and the second reflective layer covers the passivation layer.

[0026] According to an embodiment of the present application, the display chip further includes a second transparent conductive layer located on a side of the second reflective layer away from the substrate, and the second transparent conductive layer penetrates the second reflective layer and the passivation layer and is connected to the first semiconductor layer.

[0027] According to an embodiment of the present application, the display chip further includes a third reflective layer located on a peripheral side of the chip structure, and a microlens located on a side of the second transparent conductive layer away from the chip structure.

[0028] In a second aspect, the present application provides a method for manufacturing a display chip, comprising:

[0029] forming a base;

[0030] A chip structure is formed on one side of the substrate; the chip structure comprises a first semiconductor layer, a quantum well light-emitting layer, and a second semiconductor layer sequentially arranged on one side of the substrate; one of the first semiconductor layer and the second semiconductor layer is an n-type semiconductor layer, and the other is a p-type semiconductor layer; wherein the first semiconductor layer, the quantum well light-emitting layer, and the second semiconductor layer are all nitrogen-polar film layers;

[0031] The substrate is removed.

[0032] According to one embodiment of the present application, the base includes a substrate, a buffer layer, and a non-doped semiconductor composite layer;

[0033] The forming of the substrate comprises:

[0034] providing a substrate;

[0035] forming a buffer layer on one side of the substrate;

[0036] A non-doped semiconductor composite layer is formed on a side of the buffer layer away from the substrate; the chip structure is located on a side of the non-doped semiconductor composite layer away from the buffer layer;

[0037] Wherein, the buffer layer and the non-doped semiconductor composite layer are both nitrogen-polar film layers.

[0038] According to one embodiment of the present application, the non-doped semiconductor composite layer includes a plurality of non-doped semiconductor layers and at least one insertion layer stacked in layers, and there is one insertion layer between any two adjacent non-doped semiconductor layers;

[0039] The non-doped semiconductor layer and the insertion layer are both nitrogen-polar film layers.

[0040] According to one embodiment of the present application, the plurality of undoped semiconductor layers include a first undoped semiconductor layer, a second undoped semiconductor layer and a third undoped semiconductor layer, and the at least one insertion layer includes a first insertion layer and a second insertion layer; the first undoped semiconductor layer, the first insertion layer, the second undoped semiconductor layer, the second insertion layer and the third undoped semiconductor layer are sequentially arranged between the buffer layer and the first semiconductor layer;

[0041] The first non-doped semiconductor layer, the second non-doped semiconductor layer and the third non-doped semiconductor layer all include u-GaN layers, and the first insertion layer includes porous SiN x layer, and the second insertion layer includes an AlN layer.

[0042] According to one embodiment of the present application, removing the substrate includes:

[0043] removing the substrate;

[0044] The buffer layer and the undoped semiconductor composite layer are removed.

[0045] According to one embodiment of the present application, before removing the substrate, the method further includes:

[0046] The side of the chip structure facing away from the base is bonded to a substrate.

[0047] According to one embodiment of the present application, after removing the substrate, the method further includes:

[0048] forming a passivation layer on a side of the chip structure facing away from the substrate, wherein the passivation layer covers a side wall of the chip structure;

[0049] A second reflective layer is formed on the surface of the passivation layer.

[0050] According to one embodiment of the present application, the method further includes:

[0051] forming a second transparent conductive layer on a side of the second reflective layer away from the substrate, wherein the second transparent conductive layer penetrates the second reflective layer and the passivation layer and is connected to the first semiconductor layer;

[0052] A microlens is formed on a side of the second transparent conductive layer facing away from the substrate.

[0053] The above one or more technical solutions in the embodiments of the present application have at least one of the following technical effects:

[0054] The first semiconductor layer, the quantum well light-emitting layer and the second semiconductor layer are all nitrogen-polar film layers. The nitrogen-polar film layers can be grown at high temperatures, thereby improving the crystal quality of the potential well layer material in the quantum well, improving the chip carrier injection efficiency, and effectively inhibiting the overflow of carriers, thereby alleviating the Droop effect of the chip under large current injection, and improving the luminescence efficiency of the display chip.

[0055] Furthermore, an insertion layer is provided in the non-doped semiconductor composite layer to reduce the threading dislocation density in the non-doped semiconductor layer, improve the internal quantum efficiency of the chip, and further improve the luminous efficiency of the display chip.

[0056] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become apparent from the description below, or will be learned through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0057] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which:

[0058] Figure 1 It is a flowchart of a method for manufacturing a display chip provided in an embodiment of the present application;

[0059] Figure 2 This is one of the structural schematic diagrams of the manufacturing process of the display chip provided in the embodiment of the present application;

[0060] Figure 3 This is the second structural schematic diagram of the manufacturing process of the display chip provided in the embodiment of the present application;

[0061] Figure 4 This is the third structural schematic diagram of the manufacturing process of the display chip provided in the embodiment of the present application;

[0062] Figure 5 This is the fourth structural diagram of the manufacturing process of the display chip provided in the embodiment of the present application;

[0063] Figure 6 This is the fifth structural diagram of the manufacturing process of the display chip provided in the embodiment of the present application;

[0064] Figure 7 This is the sixth structural diagram of the manufacturing process of the display chip provided in the embodiment of the present application;

[0065] Figure 8 This is the seventh structural diagram of the manufacturing process of the display chip provided in the embodiment of the present application;

[0066] Fig. 9 This is the eighth structural diagram of the manufacturing process of the display chip provided in the embodiment of the present application;

[0067] Fig.10 This is the ninth structural diagram of the manufacturing process of the display chip provided in the embodiment of the present application;

[0068] Fig.11 This is the tenth structural diagram of the manufacturing process of the display chip provided in the embodiment of the present application;

[0069] Fig.12 This is the eleventh structural diagram of the manufacturing process of the display chip provided in the embodiment of the present application;

[0070] Fig.13 This is the twelfth structural diagram of the manufacturing process of the display chip provided in the embodiment of the present application;

[0071] Fig.14 It is a schematic diagram of the structure of the display chip provided in the embodiment of the present application. DETAILED DESCRIPTION

[0072] The embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and cannot be understood as limiting the present application.

[0073] The display chip and manufacturing method provided by the embodiments of the present application are described below with reference to the accompanying drawings.

[0074] Figure 1 A schematic diagram of a process flow of a method for manufacturing a display chip provided in an embodiment of the present application, wherein the display chip may be a Micro-LED display chip.

[0075] like Figure 1 As shown, the method for manufacturing a display chip provided in the embodiment of the present application includes step 110, step 120 and step 130.

[0076] Step 110: forming a substrate.

[0077] In some embodiments, Figure 2 As shown, the substrate 10 may include a substrate 1, a buffer layer 2, and a non-doped semiconductor composite layer 3. The formation of the substrate in step 110 includes: providing a substrate 1; forming a buffer layer 2 on one side of the substrate 1; and forming a non-doped semiconductor composite layer 3 on a side of the buffer layer 2 facing away from the substrate 1. The buffer layer 2 and the non-doped semiconductor composite layer 3 are both nitrogen polar film layers.

[0078] The substrate 1 may include a sapphire substrate with a certain bevel angle, etc. The buffer layer 2 may include an undoped GaN (u-GaN) layer, and the thickness of the buffer layer 2 may be 15 nm to 35 nm. The undoped semiconductor composite layer 3 may be a film layer with a low dislocation density.

[0079] For example, using a MOCVD (metal organic chemical vapor deposition) system, a hydrogen atmosphere is first provided to the substrate 1 at a temperature of 1080°C to 1100°C for 300s to 400s. The hydrogen atmosphere is maintained, the temperature of the reaction chamber is lowered to 1020°C to 1060°C, and then ammonia is introduced to perform nitridation treatment on the surface of the substrate 1.

[0080] Then, a low-temperature buffer layer 2 is grown on one side of the substrate 1, that is, the hydrogen atmosphere is switched to a nitrogen atmosphere, ammonia is continuously introduced, and the temperature of the reaction chamber is reduced to 550° C. to 580° C. The nitrogen atmosphere is maintained, the temperature of the reaction chamber is increased to 1060° C. to 1080° C., and the buffer layer 2 is annealed for 500s to 600s.

[0081] It should be noted that the buffer layer 2 may also be formed by using other processes, which are not specifically limited here.

[0082] A non-doped semiconductor composite layer 3 is formed on the side of the buffer layer 2 facing away from the substrate 1. In some embodiments, the non-doped semiconductor composite layer 3 includes a plurality of non-doped semiconductor layers and at least one insertion layer stacked in layers, and an insertion layer is provided between any two adjacent non-doped semiconductor layers. The non-doped semiconductor layer and the insertion layer are both nitrogen-polar film layers. The insertion layer can reduce the threading dislocation density in the non-doped semiconductor layer and improve the internal quantum efficiency of the chip.

[0083] In some embodiments, Figure 2 As shown, the plurality of non-doped semiconductor layers include a first non-doped semiconductor layer 31, a second non-doped semiconductor layer 33 and a third non-doped semiconductor layer 35, and the at least one insertion layer includes a first insertion layer 32 and a second insertion layer 34. The first non-doped semiconductor layer 31, the first insertion layer 32, the second non-doped semiconductor layer 33, the second insertion layer 34 and the third non-doped semiconductor layer 35 are sequentially arranged on the side of the buffer layer 2 away from the substrate 1.

[0084] The first non-doped semiconductor layer 31 may include a u-GaN layer, and the thickness of the first non-doped semiconductor layer 31 may be 300 nm to 500 nm. The first insertion layer 32 may include a porous SiNx layer. The main functions of the first insertion layer 32 are: on the one hand, to reduce the defect density and impurity ion concentration of the u-GaN layer; on the other hand, to reduce the background electron concentration of the nitrogen-polar u-GaN layer, improve mobility, and improve luminescence performance.

[0085] The second non-doped semiconductor layer 33 may include a u-GaN layer, and the thickness of the second non-doped semiconductor layer 33 is 1 μm to 1.2 μm. The second insertion layer 34 may include an AlN layer, and the thickness of the second insertion layer 34 may be 5 nm to 30 nm. The third non-doped semiconductor layer 35 may include a u-GaN layer, and the thickness of the third non-doped semiconductor layer 35 may be 1.5 μm to 2.5 μm. The overall thickness of the non-doped semiconductor composite layer 3 may be 3 μm to 4 μm.

[0086] For example, after growing the buffer layer 2, the atmosphere is switched from nitrogen to hydrogen, the temperature of the reaction chamber is raised to 1080°C to 1100°C, and the first non-doped semiconductor layer 31 is grown on the side of the buffer layer 2 facing away from the substrate 1. Only ammonia (NH3) and silane (SiH4) are introduced, and the first insertion layer 32 is grown on the side of the first non-doped semiconductor layer 31 facing away from the buffer layer 2.

[0087] Then, in a hydrogen atmosphere, when the reaction chamber temperature is 1080°C to 1100°C, a second non-doped semiconductor layer 33 is grown on the side of the first insertion layer 32 away from the first non-doped semiconductor layer 31. Then, the reaction chamber temperature is lowered to 900°C to 1000°C, and a low-temperature second insertion layer 34 is grown on the side of the second non-doped semiconductor layer 33 away from the first insertion layer 32. Then, in a hydrogen atmosphere, when the reaction chamber temperature is 1080°C to 1100°C, a third non-doped semiconductor layer 35 is grown on the side of the second insertion layer 34 away from the second non-doped semiconductor layer 33.

[0088] It should be noted that the non-doped semiconductor composite layer 3 may also be formed by using other processes, which are not specifically limited here.

[0089] Step 120, forming a chip structure on one side of the substrate; the chip structure includes a first semiconductor layer, a quantum well light-emitting layer and a second semiconductor layer sequentially arranged on one side of the substrate; one of the first semiconductor layer and the second semiconductor layer is an n-type semiconductor layer, and the other is a p-type semiconductor layer; wherein the first semiconductor layer, the quantum well light-emitting layer and the second semiconductor layer are all nitrogen-polar film layers.

[0090] Combination Figures 3 to 7 As shown, the chip structure 20 includes a first semiconductor layer 4, a quantum well light emitting layer 5 and a second semiconductor layer 6. The step 120 of forming the chip structure on one side of the substrate includes: forming the first semiconductor layer 4 on one side of the substrate 10; forming the quantum well light emitting layer 5 on the side of the first semiconductor layer 4 away from the substrate 10; and forming the second semiconductor layer 6 on the side of the quantum well light emitting layer 5 away from the first semiconductor layer 4.

[0091] The first semiconductor layer 4 is an n-type semiconductor layer, and the second semiconductor layer 6 is a p-type semiconductor layer. Alternatively, the first semiconductor layer 4 is a p-type semiconductor layer, and the second semiconductor layer 6 is an n-type semiconductor layer. In some embodiments, the chip structure 20 is a nitrogen-polarity InGaN-based chip structure, the first semiconductor layer 4 is an n-type semiconductor layer, and the second semiconductor layer 6 is a p-type semiconductor layer.

[0092] In some embodiments, Figure 3 As shown, the first semiconductor layer 4 includes a heavily doped semiconductor layer 41 and a lightly doped semiconductor layer 42. The heavily doped semiconductor layer 41 is located on one side of the substrate 10, such as the heavily doped semiconductor layer 41 is located on the side of the non-doped semiconductor composite layer 3 away from the substrate 1, and the lightly doped semiconductor layer 42 is located on the side of the heavily doped semiconductor layer 41 away from the substrate 10. Among them, the heavily doped semiconductor layer 41 and the lightly doped semiconductor layer 42 are both nitrogen polar film layers.

[0093] The heavily doped semiconductor layer 41 may include an n-GaN heavily doped layer. The electron concentration of the heavily doped semiconductor layer 41 is 1×1018 cm -3 ~2×10 19 cm -3 The heavily doped semiconductor layer 41 has a thickness of 0.5 μm to 1.5 μm.

[0094] For example, the temperature of the reaction chamber is 1080°C to 1100°C, silane is introduced, and a delta doping method is used to separate the process of introducing silane from the growth process of the heavily doped semiconductor layer 41, so as to periodically grow a non-doped semiconductor layer. The n-type doping of the non-doped semiconductor layer is achieved by the diffusion of Si atoms during the growth process to obtain the heavily doped semiconductor layer 41. The non-doped semiconductor layer may include a GaN layer, and the heavily doped semiconductor layer 41 may include an n-GaN layer. The periodic thickness of the non-doped semiconductor layer may be 10nm to 30nm, and the flow rate of silane may be 2nmol / min to 80nmol / min, so that the electron concentration of the heavily doped semiconductor layer 41 may be 1×10 18 cm -3 ~2×10 19 cm -3 The heavily doped semiconductor layer 41 has a thickness of 0.5 μm to 1.5 μm.

[0095] It should be noted that silane is usually selected as the n-type dopant of the GaN layer, but uniform silane doping leads to a decrease in the mobility of Ga atoms and easily forms V-type defects. Therefore, this embodiment adopts a δ doping method to avoid V-type defects.

[0096] The heavily doped semiconductor layer 41 may also include n-Al c Ga 1-c N / n-GaN superlattice layer, 0.02≤c≤0.15, electron concentration is 1×10 18 cm -3 ~2×10 19 cm -3 Among them, n-Al c Ga 1-c The Al content in N is about 2% to 15%, and the thickness can be 2nm to 3nm. The thickness of n-GaN can be 2.5nm to 15nm. c Ga 1-c N / n-GaN superlattice layers can alleviate dislocation extension and stress regulation.

[0097] The lightly doped semiconductor layer 42 may include an n-GaN lightly doped layer. The electron concentration of the lightly doped semiconductor layer 42 is 1×10 17 cm -3 ~5×10 17 cm -3The thickness of the lightly doped semiconductor layer 42 is 0.2 μm to 0.5 μm.

[0098] For example, the temperature of the reaction chamber is 1080°C to 1100°C, silane is introduced, a delta doping method is used, a non-doped semiconductor layer is periodically grown, and n-type ions are doped in the non-doped semiconductor layer to obtain a lightly doped semiconductor layer 42. The non-doped semiconductor layer includes a GaN layer, and the lightly doped semiconductor layer 42 includes an n-GaN layer. The periodic thickness of the non-doped semiconductor layer is 10nm to 30nm, and the flow rate of silane is 0.1nmol / min to 1.5nmol / min, which can achieve an electron concentration of 1×10 17 cm -3 ~5×10 17 cm -3 , the thickness of the lightly doped semiconductor layer 42 is 0.2 μm to 0.5 μm.

[0099] The lightly doped semiconductor layer 42 may also include n-Al g Ga 1-g N / n-GaN superlattice layer, 0.02≤g≤0.08, electron concentration is 1×10 17 cm -3 ~5×10 17 cm -3 Among them, n-Al g Ga 1-g The Al component in N is about 2% to 8%, the thickness is 2nm to 3nm, and the thickness of n-GaN is 2.5nm to 15nm.

[0100] In some embodiments, Figure 4 As shown, the formation of the chip structure in step 120 also includes: forming a fourth non-doped semiconductor layer 71, a first barrier layer 72, a first superlattice layer 73 and a second superlattice layer 74 in sequence on the side of the first semiconductor layer 4 away from the substrate 10, and the quantum well light-emitting layer 5 is located on the side of the second superlattice layer 74 away from the first superlattice layer 73. The fourth non-doped semiconductor layer 71, the first barrier layer 72, the first superlattice layer 73 and the second superlattice layer 74 are all nitrogen polar film layers.

[0101] The fourth non-doped semiconductor layer 71 may include a u-GaN layer, and the thickness of the fourth non-doped semiconductor layer 71 may be 10 nm to 30 nm. The first barrier layer 72 may include a GaN layer, and the thickness of the first barrier layer 72 may be 10 nm to 30 nm. The first superlattice layer 73 may include at least one period (e.g., 1 to 3 periods) of u-In a Ga 1-a N / u-GaN superlattice layer, 0.01≤a≤0.05. Among them, u-In a Ga1-a The thickness of N can be 2nm to 3nm, the In component is 1% to 5%, and the thickness of u-GaN can be 2.5nm to 15nm. The second superlattice layer 74 can include at least one period (such as 1 to 3 periods) of u-In b Ga 1-b N / n-GaN superlattice layer, 0.05≤b≤0.1. The electron concentration of n-GaN can be 1×10 17 cm -3 ~5×10 17 cm -3 ,u-In b Ga 1-b The thickness of N can be 2nm to 3nm, the In component can be 5% to 10%, and the thickness of n-GaN can be 2.5nm to 15nm.

[0102] For example, after the lightly doped semiconductor layer 42 is grown, the temperature of the reaction chamber is lowered to 900° C. to 1000° C., and a fourth non-doped semiconductor layer 71 is grown on the side of the lightly doped semiconductor layer 42 away from the heavily doped semiconductor layer 41. The fourth non-doped semiconductor layer 71 is used to repair damage from hydrogen etching during the cooling process.

[0103] Then, the nitrogen atmosphere is switched, the temperature of the reaction chamber is lowered to 800° C. to 900° C., and the first barrier layer 72 is grown on the side of the fourth non-doped semiconductor layer 71 away from the lightly doped semiconductor layer 42. Then, the first superlattice layer 73 is grown on the side of the first barrier layer 72 away from the fourth non-doped semiconductor layer 71. The second superlattice layer 74 is grown on the side of the first superlattice layer 73 away from the first barrier layer 72.

[0104] Then, if Figure 5 As shown, a quantum well light emitting layer 5 is formed on a side of the second superlattice layer 74 facing away from the first superlattice layer 73 .

[0105] In some embodiments, the quantum well light emitting layer 5 includes a red light quantum well light emitting layer. This embodiment uses a nitrogen polar film layer, which can alleviate the Droop effect of the chip under large current injection and improve the red light effect.

[0106] In some embodiments, the quantum well light-emitting layer 5 includes at least one periodic structure (such as 2 to 3 periodic structures), each periodic structure includes a fifth non-doped semiconductor layer, a first potential well layer, a first cap layer, a second potential barrier layer, a sixth non-doped semiconductor layer, a second potential well layer, a second cap layer and a third potential barrier layer sequentially arranged between the first semiconductor layer 4 and the second semiconductor layer 6. Among them, the fifth non-doped semiconductor layer, the first potential well layer, the first cap layer, the second potential barrier layer, the sixth non-doped semiconductor layer, the second potential well layer, the second cap layer and the third potential barrier layer are all nitrogen polar film layers.

[0107] The fifth non-doped semiconductor layer may include a low-temperature u-GaN layer, and the thickness of the fifth non-doped semiconductor layer may be 2nm to 3nm. The first potential well layer may include u-In x Ga 1-x N layer, 0.1≤x≤0.15, the thickness of the first potential well layer can be 2.5nm-3.5nm. The first cap layer can include a GaN layer, and the thickness of the first cap layer can be 2nm-3nm. The second barrier layer can include a GaN layer or a u-In y Ga 1-y N layer, 0.01≤y≤0.03, the thickness of the second barrier layer may be 10nm-15nm. The sixth non-doped semiconductor layer may include a low-temperature u-GaN layer, and the thickness of the sixth non-doped semiconductor layer may be 2nm-3nm. The second potential well layer may include u-In z Ga 1-z N layer, 0.35≤z≤0.4, the thickness of the second potential well layer can be 2.5nm-3.5nm. The second cap layer can include a GaN layer, and the thickness of the second cap layer can be 2nm-3nm. The third barrier layer can include u-Al d Ga 1-d N layer, 0.3≤d≤0.35, the thickness of the third barrier layer can be 10nm~15nm.

[0108] In some embodiments, Figure 6 As shown, the chip structure formed in step 120 further includes: forming a protective layer 75 on the side of the quantum well light-emitting layer 5 away from the first semiconductor layer 4. The protective layer 75 is a nitrogen-polar film layer. The protective layer 75 may include a u-GaN layer, and the thickness of the protective layer 75 may be 20nm to 50nm.

[0109] For example, in a nitrogen atmosphere, the protection layer 75 is grown on the side of the quantum well light emitting layer 5 facing away from the first semiconductor layer 4 .

[0110] Then, if Figure 6 As shown, the second semiconductor layer 6 is formed on the side of the protection layer 75 facing away from the quantum well light-emitting layer 5 .

[0111] In some embodiments, the second semiconductor layer 6 includes an electron blocking layer 61, a hole injection layer 62 and an ohmic contact layer 63 formed in sequence on the side of the quantum well light emitting layer 5 away from the first semiconductor layer 4. The electron blocking layer 61, the hole injection layer 62 and the ohmic contact layer 63 are all nitrogen polar film layers.

[0112] The electron blocking layer 61 may include a p-AlGaN polarization induction layer. The thickness of the p-AlGaN polarization induction layer may be 50 nm to 60 nm. The Al component may increase linearly from 0% to 20% or 30%. The theoretical hole concentration of the film layer is 2×10 18 cm -3 ~2.5×10 18 cm -3 The electron blocking layer 61 may also include p-Al e Ga 1-e N / p-GaN superlattice layer, 0.15≤e≤0.25, the hole concentration can be 1.5×10 18 cm -3 ~2.5×10 18 cm -3 , p-Al e Ga 1-e The Al content in N is about 15% to 25%, and p-Al e Ga 1-e The thickness of N can be 2nm to 3nm, and the thickness of p-GaN can be 5nm to 15nm.

[0113] The hole injection layer 62 may include a p-GaN layer, and the thickness of the hole injection layer 62 may be 100 nm to 140 nm. The ohmic contact layer 63 may include at least one period (eg, 2 to 4 periods) of p-In f Ga 1-f N / p-GaN superlattice layer, 0.1≤f≤0.2. Among them, p-In f Ga 1-f The In component in N is about 10% to 20%, and p-In f Ga 1-f The thickness of N can be 2nm to 3nm, and the thickness of p-GaN can be 5nm to 15nm.

[0114] For example, the hydrogen atmosphere is switched to grow the electron blocking layer 61 on the side of the protective layer 75 away from the quantum well light emitting layer 5. Then, the hole injection layer 62 is deposited on the side of the electron blocking layer 61 away from the protective layer 75. The ohmic contact layer 63 is deposited on the side of the hole injection layer 62 away from the electron blocking layer 61.

[0115] It should be noted that the second semiconductor layer 6 may also be formed by using other processes, which are not specifically limited here.

[0116] In some embodiments, Figure 7As shown, the chip structure formed in step 120 further includes: forming a first transparent conductive layer 76, a first reflective layer 77 and a bonding layer 78 in sequence on the side of the second semiconductor layer 6 away from the quantum well light emitting layer 5. The first reflective layer 77 is used to enhance the light extraction efficiency of the display chip.

[0117] The first transparent conductive layer 76 may include an ITO (indium tin oxide) layer. The first reflective layer 77 may include a metal reflective layer, such as at least one of Ag and Al. The bonding layer 78 may include a metal layer, such as at least one of Cr, Pt, Ni, Ti, Ni and Ag.

[0118] For example, the first transparent conductive layer 76 is deposited on the side of the ohmic contact layer 63 away from the hole injection layer 62 by electron beam evaporation or PVD (Physical Vapor Deposition) process, and an annealing process is combined to improve the transmittance of the first transparent conductive layer 76 and reduce the material resistance.

[0119] Then, the first reflective layer 77 is deposited on the side of the first transparent conductive layer 76 away from the ohmic contact layer 63 by electron beam evaporation or PVD process. Then, the bonding layer 78 is deposited on the side of the first reflective layer 77 away from the first transparent conductive layer 76 by electron beam evaporation or PVD process.

[0120] It should be noted that the first transparent conductive layer 76 and the first reflective layer 77 may also be formed by using other processes, which are not specifically limited here.

[0121] Along the c-axis growth direction, GaN materials have two polarities, namely gallium polarity and nitrogen polarity. Compared with gallium polarity, the incorporation efficiency of In in nitrogen polarity InGaN materials is higher. The main reason includes that the In atoms in nitrogen polarity InGaN materials can form stronger In-N bonds with surface N atoms. Moreover, there are 4 In-N bonds around each In atom on the surface of nitrogen polarity InGaN materials, which makes the desorption efficiency of In in nitrogen polarity InGaN materials lower, which is conducive to the incorporation of In. Therefore, under the same In component, nitrogen polarity InGaN materials can have a higher growth temperature, which is conducive to improving the crystal quality of the potential well layer material in the quantum well and improving the internal quantum efficiency of the chip structure.

[0122] Moreover, nitrogen-polar materials have the opposite polarization direction to gallium-polar materials, which can reduce the barrier of carrier injection into the quantum well in the chip, and at the same time increase the barrier of carrier overflow into the quantum well. Therefore, nitrogen-polar InGaN-based chips have higher carrier injection efficiency, and can also suppress the overflow of carriers, which can alleviate the Droop effect of the chip under high current (high current density) to a certain extent and improve the luminous efficiency of the display chip.

[0123] In some embodiments, the method for manufacturing the display chip further includes:

[0124] The substrate is bonded to the side of the chip structure facing away from the base.

[0125] like Figure 8 As shown, the chip structure 20 is bonded to the substrate 30 via a bonding layer 78. The substrate 30 may include a silicon substrate or a silicon-based complementary metal oxide semiconductor (CMOS) pixel driving backplane.

[0126] Step 130: remove the substrate.

[0127] The substrate 10 may include a substrate 1, a buffer layer 2 and a non-doped semiconductor composite layer 3. The removal of the substrate in the display chip in step 130 includes: removing the substrate 1; removing the buffer layer 2 and the non-doped semiconductor composite layer 3.

[0128] For example Fig. 9 As shown, the laser lift-off technique is used to remove the substrate 1. The selected pulse laser wavelengths may be 355 nm, 266 nm and 248 nm.

[0129] Then, if Fig.10 As shown, the buffer layer 2 and the non-doped semiconductor layer composite layer 3 are etched by ICP-RIE (inductively coupled plasma-reactive ion etching) process until the heavily doped semiconductor layer 41 is exposed. Then, the surface of the heavily doped semiconductor layer 41 is mechanically polished. Fig.11 As shown, the chip structure 20 is etched by photolithography and ICP-RIE process to meet different pixel size requirements.

[0130] In some embodiments, Fig.11 As shown, the manufacturing method of the display chip further includes: forming a passivation layer 81 on the side of the chip structure 20 away from the substrate 30, and the passivation layer 81 covers the side wall of the chip structure 20; forming a second reflective layer 82 on the surface of the passivation layer 81. The passivation layer 81 is located on the side of the heavily doped semiconductor layer 41 away from the substrate 30 and the side wall of the chip structure 20, and the second reflective layer 82 is located on the surface of the passivation layer 81. The second reflective layer 82 can further enhance the light extraction efficiency of the chip.

[0131] The passivation layer 81 may include SiO2, SiN x and Al2O3, the thickness of the passivation layer 81 can be 10nm-40nm, the second reflective layer 82 can include a DBR (Distributed Bragg Reflection) layer, and the DBR layer can include TiO2 / SiO2 or Ta2O5 / SiO2, etc.

[0132] For example, wet etching (such as 25% TMAH solution) is used to repair the sidewall of the chip structure 20, and then an ALD device is used to deposit the passivation layer 81. Then, a second reflective layer 82 is deposited using PVD, electron beam evaporation or ALD equipment.

[0133] For another example, a PE-ALD device plasma is used to process the sidewall of the chip structure 20, and the gas may include O2, Ar, H2, NH3, N2, etc., to deposit the passivation layer 81. Then, a PVD, electron beam evaporation or ALD device is used to deposit the second reflective layer 82.

[0134] For another example, a protective layer is deposited on the chip structure 20 by a PECVD process through a photolithography process. The thickness of the protective layer is 10 nm to 40 nm. The sidewalls of the chip structure 20 are plasma processed by a PE-ALD device, and the gas may include O2, Ar, H2, NH3, N2, etc., to deposit a passivation layer 81. Then, a second reflective layer 82 is deposited by a PVD, electron beam evaporation or ALD device.

[0135] In some embodiments, Fig.12 As shown, the manufacturing method of the display chip further includes: forming a first isolation layer 83 on the peripheral side of the chip structure 20. The first isolation layer 83 may include SiO2 and SiN x At least one of .

[0136] For example, an ICP-RIE process is used to etch an isolation groove around the chip structure 20. Then, a photolithography process and PECVD equipment are used to form a first isolation layer 83 in the groove, and the photoresist is removed with an acetone solution, ultrasonically cleaned with ethanol and deionized water, and dried with nitrogen.

[0137] It should be noted that the first isolation layer 83 may also be formed by using other processes, which are not specifically limited here.

[0138] In some embodiments, Fig.13 As shown, the manufacturing method of the display chip further includes: forming a second transparent conductive layer 84 on the side of the second reflective layer 82 away from the substrate 30, and the second transparent conductive layer 84 penetrates the second reflective layer 82 and the passivation layer 81 and is connected to the first semiconductor layer 4. Fig.13 As shown, the second transparent conductive layer 84 is located on the side of the second reflective layer 82 away from the substrate 30 and on the side of the first isolation layer 83 away from the substrate 30, and the second transparent conductive layer 84 penetrates the second reflective layer 82 and the passivation layer 81 and is connected to the heavily doped semiconductor layer 41 in the first semiconductor layer 4.

[0139] The second transparent conductive layer 84 may include an ITO layer, and the thickness of the second transparent conductive layer 84 may be 100 nm to 400 nm.

[0140] For example, a photolithography process and an ICP-RIE etching process are used to etch the second reflective layer 82 and the passivation layer 81 on the side of the heavily doped semiconductor layer 41 away from the substrate 30 to expose the heavily doped semiconductor layer 41. The second transparent semiconductor layer 84 is deposited by an electron beam evaporation or PVD process, and an annealing process is combined to improve the transmittance of the second transparent semiconductor layer 84 and reduce the material resistance.

[0141] In some embodiments, Fig.14 As shown, the manufacturing method of the display chip further includes: forming an n-type ohmic contact electrode and a third reflective layer 85 on the peripheral side of the chip structure 20, and the n-type ohmic contact electrode and the third reflective layer 85 are located on the side of the second transparent semiconductor layer 84 away from the substrate 30. The third reflective layer 85 can reduce the light crosstalk and light divergence angle between pixels, and improve the light extraction efficiency.

[0142] The n-type ohmic contact electrode includes a metal layer, such as Ti / Al / Ti / Au, etc. The third reflective layer may include a metal layer, such as at least one of Ag and Al, etc.

[0143] For example, the n-type ohmic contact electrode is prepared by photolithography and electron beam evaporation. The third reflective layer is deposited by electron beam evaporation or PVD. It should be noted that the n-type ohmic contact electrode and the third reflective layer 85 can also be formed by other processes, which are not specifically limited here.

[0144] In some embodiments, Fig.14 As shown, the manufacturing method of the display chip also includes: forming a second isolation layer 86 on the peripheral side of the chip structure 20; forming a micro-lens 85 (micro-lens) on the side of the second transparent conductive layer 84 away from the substrate 30. The second isolation layer 86 covers the second transparent semiconductor layer 84, the n-type ohmic contact electrode and the third reflective layer 85, and the surface of the second isolation layer 86 away from the substrate 30 can be flush with the surface of the second transparent conductive layer 84 away from the substrate 30. The first isolation layer 83 and the second isolation layer 86 are used to achieve electrical insulation between pixel mesas. The second isolation layer 86 may include SiO2 and SiN x At least one of the above. The microlens 85 corresponds to the position of the chip structure 20, and is used to increase the light collection of the chip. The microlens 85 may include SiO2 or the like.

[0145] For example, a photolithography process and a PECVD device are used to deposit the second isolation layer 86. A PECVD device is used to deposit the microlens 87.

[0146] According to the manufacturing method of the display chip provided in the embodiment of the present application, the first semiconductor layer, the quantum well light-emitting layer and the second semiconductor layer are all nitrogen-polar film layers. The nitrogen-polar film layers can be grown at high temperatures, thereby improving the crystal quality of the potential well layer material in the quantum well, improving the chip carrier injection efficiency, and effectively suppressing the overflow of carriers, alleviating the Droop effect of the chip under large current injection, improving the luminous efficiency of the display chip, and thereby improving the display effect of the display chip.

[0147] Accordingly, the embodiment of the present application further provides a display chip, which can be manufactured using the above-mentioned method for manufacturing a display chip, wherein the display chip can be a Micro-LED display chip.

[0148] like Fig.14 As shown, the display chip includes a chip structure 20, which includes a first semiconductor layer 4, a quantum well light-emitting layer 5 and a second semiconductor layer 6. The quantum well light-emitting layer 5 is located on one side of the first semiconductor layer 4, and the second semiconductor layer 6 is located on the side of the quantum well light-emitting layer 5 away from the first semiconductor layer 4.

[0149] One of the first semiconductor layer 4 and the second semiconductor layer 6 is an n-type semiconductor layer, and the other is a p-type semiconductor layer, that is, the first semiconductor layer 4 is an n-type semiconductor layer, and the second semiconductor layer 6 is a p-type semiconductor layer; or, the first semiconductor layer 4 is a p-type semiconductor layer, and the second semiconductor layer 6 is an n-type semiconductor layer.

[0150] The first semiconductor layer 4 , the quantum well light-emitting layer 5 and the second semiconductor layer 6 are all nitrogen-polar film layers.

[0151] In this embodiment, the first semiconductor layer 4, the quantum well light-emitting layer 5 and the second semiconductor layer 6 are all nitrogen-polar film layers. The nitrogen-polar film layers can be grown at high temperatures, thereby improving the crystal quality of the potential well layer material in the quantum well, improving the chip carrier injection efficiency, and effectively inhibiting the overflow of carriers, thereby alleviating the Droop effect of the chip under large current injection, and improving the luminescence efficiency of the display chip.

[0152] In some embodiments, the chip structure 20 is a nitrogen-polarity InGaN-based chip structure, the first semiconductor layer 4 is an n-type semiconductor layer, and the second semiconductor layer 6 is a p-type semiconductor layer.

[0153] In some embodiments, Fig.14 As shown, the first semiconductor layer includes a heavily doped semiconductor layer 41 and a lightly doped semiconductor layer 42. The lightly doped semiconductor layer 42 is located between the heavily doped semiconductor layer 41 and the quantum well light emitting layer 5. The heavily doped semiconductor layer 41 and the lightly doped semiconductor layer 42 are both nitrogen polar film layers.

[0154] The heavily doped semiconductor layer 41 may include an n-GaN heavily doped layer. The electron concentration of the heavily doped semiconductor layer 41 is 1×10 18 cm -3 ~2×10 19 cm -3 The heavily doped semiconductor layer 41 has a thickness of 0.5 μm to 1.5 μm. The heavily doped semiconductor layer 41 may also include n-Al c Ga 1-c N / n-GaN superlattice layer, 0.02≤c≤0.15, electron concentration is 1×10 18 cm -3 ~2×10 19 cm -3 Among them, n-Al c Ga 1-c The Al content in N is about 2% to 15%, and the thickness can be 2nm to 3nm. The thickness of n-GaN can be 2.5nm to 15nm. c Ga 1-c N / n-GaN superlattice layers can alleviate dislocation extension and stress regulation.

[0155] The lightly doped semiconductor layer 42 may include an n-GaN lightly doped layer. The electron concentration of the lightly doped semiconductor layer 42 is 1×10 17 cm -3 ~5×10 17 cm -3 The thickness of the lightly doped semiconductor layer 42 is 0.2 μm to 0.5 μm. The lightly doped semiconductor layer 42 may also include n-Al g Ga 1-g N / n-GaN superlattice layer, 0.02≤g≤0.08, electron concentration is 1×10 17 cm -3 ~5×10 17 cm -3 Among them, n-Al g Ga 1-g The Al component in N is about 2% to 8%, the thickness is 2nm to 3nm, and the thickness of n-GaN is 2.5nm to 15nm.

[0156] In some embodiments, Fig.14As shown, the chip structure 20 further includes a fourth non-doped semiconductor layer 71, a first barrier layer 72, a first superlattice layer 73, and a second superlattice layer 74, which are sequentially arranged between the first semiconductor layer 4 and the quantum well light-emitting layer 5, that is, the fourth non-doped semiconductor layer 71 is located between the lightly doped semiconductor layer 42 and the quantum well light-emitting layer 5, the first barrier layer 72 is located between the fourth non-doped semiconductor layer 71 and the quantum well light-emitting layer 5, the first superlattice layer 73 is located between the first barrier layer 72 and the quantum well light-emitting layer 5, and the second superlattice layer 74 is located between the first superlattice layer 73 and the quantum well light-emitting layer 5. The fourth non-doped semiconductor layer 71, the first barrier layer 72, the first superlattice layer 73, and the second superlattice layer 74 are all nitrogen-polar film layers.

[0157] The fourth non-doped semiconductor layer 71 may include a u-GaN layer, and the thickness of the fourth non-doped semiconductor layer 71 may be 10 nm to 30 nm. The first barrier layer 72 may include a GaN layer, and the thickness of the first barrier layer 72 may be 10 nm to 30 nm. The first superlattice layer 73 may include at least one period (e.g., 1 to 3 periods) of u-In a Ga 1-a N / u-GaN superlattice layer, 0.01≤a≤0.05. Among them, u-In a Ga 1-a The thickness of N can be 2nm to 3nm, the In component can be 1% to 5%, and the thickness of u-GaN can be 2.5nm to 15nm. The second superlattice layer 74 can include at least one period (such as 1 to 3 periods) of u-In b Ga 1-b N / n-GaN superlattice layer, 0.05≤b≤0.1. The electron concentration of n-GaN can be 1×10 17 cm -3 ~5×10 17 cm -3 ,u-In b Ga 1-b The thickness of N can be 2nm to 3nm, the In component can be 5% to 10%, and the thickness of n-GaN can be 2.5nm to 15nm.

[0158] In some embodiments, the quantum well light emitting layer 5 includes a red light quantum well light emitting layer.

[0159] In some embodiments, the quantum well light-emitting layer 5 includes at least one periodic structure (such as 2 to 3 periodic structures), each periodic structure includes a fifth non-doped semiconductor layer, a first potential well layer, a first cap layer, a second potential barrier layer, a sixth non-doped semiconductor layer, a second potential well layer, a second cap layer and a third potential barrier layer sequentially arranged between the first semiconductor layer 4 and the second semiconductor layer 6. Among them, the fifth non-doped semiconductor layer, the first potential well layer, the first cap layer, the second potential barrier layer, the sixth non-doped semiconductor layer, the second potential well layer, the second cap layer and the third potential barrier layer are all nitrogen polar film layers.

[0160] The fifth non-doped semiconductor layer may include a low-temperature u-GaN layer, and the thickness of the fifth non-doped semiconductor layer may be 2nm to 3nm. The first potential well layer may include u-In x Ga 1-x N layer, 0.1≤x≤0.15, the thickness of the first potential well layer can be 2.5nm-3.5nm. The first cap layer can include a GaN layer, and the thickness of the first cap layer can be 2nm-3nm. The second barrier layer can include a GaN layer or a u-In y Ga 1-y N layer, 0.01≤y≤0.03, the thickness of the second barrier layer may be 10nm-15nm. The sixth non-doped semiconductor layer may include a low-temperature u-GaN layer, and the thickness of the sixth non-doped semiconductor layer may be 2nm-3nm. The second potential well layer may include u-In z Ga 1-z N layer, 0.35≤z≤0.4, the thickness of the second potential well layer can be 2.5nm-3.5nm. The second cap layer can include a GaN layer, and the thickness of the second cap layer can be 2nm-3nm. The third barrier layer can include u-Al d Ga 1-d N layer, 0.3≤d≤0.35, the thickness of the third barrier layer can be 10nm~15nm.

[0161] This embodiment uses a nitrogen-polar film layer, so that the quantum well light-emitting layer can be grown at a high temperature, thereby improving the crystal quality of the barrier layer material in the quantum well light-emitting layer, and can reduce the barrier for carrier injection into the quantum well light-emitting layer in the chip, while also increasing the barrier for carrier overflow from the quantum well light-emitting layer, that is, improving the carrier injection efficiency, while suppressing the overflow of carriers and alleviating the Droop effect of the chip under large current injection.

[0162] In some embodiments, Fig.14 As shown, the chip structure 20 may further include a protective layer 75, which is located between the quantum well light-emitting layer 5 and the second semiconductor layer 6. The protective layer 75 is a nitrogen-polar film layer, wherein the protective layer 75 includes a u-GaN layer, and the thickness of the protective layer 75 is 20 nm to 50 nm.

[0163] In some embodiments, Fig.14 As shown, the second semiconductor layer 6 includes an electron blocking layer 61, a hole injection layer 62 and an ohmic contact layer 63 which are sequentially arranged on the side of the quantum well light emitting layer 5 away from the first semiconductor layer 4. The electron blocking layer 61, the hole injection layer 62 and the ohmic contact layer 63 are all nitrogen polar film layers.

[0164] The electron blocking layer 61 may include a p-AlGaN polarization induction layer. The thickness of the p-AlGaN polarization induction layer may be 50 nm to 60 nm. The Al component may increase linearly from 0% to 20% or 30%. The theoretical hole concentration of the film layer is 2×10 18 cm -3 ~2.5×10 18 cm -3 The electron blocking layer 61 may also include p-Al e Ga 1-e N / p-GaN superlattice layer, 0.15≤e≤0.25, the hole concentration can be 1.5×10 18 cm -3 ~2.5×10 18 cm -3 , p-Al e Ga 1-e The Al content in N is about 15% to 25%, and p-Al e Ga 1-e The thickness of N can be 2nm to 3nm, and the thickness of p-GaN can be 5nm to 15nm.

[0165] The hole injection layer 62 may include a p-GaN layer, and the thickness of the hole injection layer 62 may be 100 nm to 140 nm. The ohmic contact layer 63 may include at least one period (eg, 2 to 4 periods) of p-In f Ga 1-f N / p-GaN superlattice layer, 0.1≤f≤0.2. p-In f Ga 1-f The In component in N is about 10% to 20%, and p-In f Ga 1-f The thickness of N can be 2nm to 3nm, and the thickness of p-GaN can be 5nm to 15nm.

[0166] In some embodiments, the chip structure 20 further includes a first transparent conductive layer 76, a first reflective layer 77, and a bonding layer 78, which are sequentially located on the side of the second semiconductor layer 6 away from the quantum well light-emitting layer 5, that is, the first transparent conductive layer 76 is located on the side of the ohmic contact layer 63 away from the hole injection layer 62, the first reflective layer 77 is located on the side of the first transparent conductive layer 76 away from the ohmic contact layer 63, and the bonding layer 78 is located on the side of the first reflective layer 77 away from the first transparent conductive layer 76. The first reflective layer 77 is used to enhance the light extraction efficiency of the display chip, and the bonding layer 78 is used to bond the display chip to other substrates.

[0167] The first transparent conductive layer 76 may include an ITO (indium tin oxide) layer. The first reflective layer 77 may include a metal reflective layer, such as Ag and Al. The bonding layer 78 may include a metal layer, such as Cr, Pt, Ni, Ti, Ni and Ag.

[0168] Along the c-axis growth direction, GaN materials have two polarities, namely gallium polarity and nitrogen polarity. Compared with gallium polarity, the incorporation efficiency of In in nitrogen polarity InGaN materials is higher. The main reason includes that the In atoms in nitrogen polarity InGaN materials can form stronger In-N bonds with surface N atoms. Moreover, there are 4 In-N bonds around each In atom on the surface of nitrogen polarity InGaN materials, which makes the desorption efficiency of In in nitrogen polarity InGaN materials lower, which is conducive to the incorporation of In. Therefore, under the same In component, nitrogen polarity InGaN materials can have a higher growth temperature, which is conducive to improving the crystal quality of the potential well layer material in the quantum well and improving the internal quantum efficiency of the chip structure.

[0169] Moreover, nitrogen-polar materials have the opposite polarization direction to gallium-polar materials, which can reduce the barrier of carrier injection into the quantum well in the chip, and at the same time increase the barrier of carrier overflow into the quantum well. Therefore, the nitrogen-polar InGaN-based chip structure has a higher carrier injection efficiency, and can also suppress the overflow of carriers, which can alleviate the Droop effect of the chip under high current (high current density) to a certain extent and improve the luminous efficiency of the display chip.

[0170] In some embodiments, Fig.14 As shown, the display chip further includes a substrate 30. The substrate 30 is bonded to a side of the chip structure 20 that is away from the first semiconductor layer 4.

[0171] In some embodiments, the substrate 30 is located on a side of the bonding layer 78 facing away from the first semiconductor layer 4 , and the substrate 30 is bonded to the chip structure 20 via the bonding layer 78 .

[0172] The substrate 30 may include a silicon substrate or a silicon-based complementary metal oxide semiconductor (CMOS) pixel driving backplane.

[0173] In some embodiments, Fig.14 As shown, the display chip further includes a passivation layer 81 and a second reflective layer 82. The passivation layer 81 is located on the side of the chip structure 20 away from the substrate 30 and covers the sidewall of the chip structure 20, that is, the passivation layer 81 is located on the side of the heavily doped semiconductor layer 41 away from the substrate 30 and the sidewall of the chip structure 20. The second reflective layer 82 covers the passivation layer 81, that is, the second reflective layer 82 is located on the surface of the passivation layer 81.

[0174] The passivation layer 81 may include SiO2, SiN x and Al2O3, the thickness of the passivation layer 81 may be 10nm-40nm, the second reflective layer 82 may include a DBR layer, and the DBR layer may include TiO2 / SiO2 or Ta2O5 / SiO2, etc.

[0175] In some embodiments, the display chip further includes a first isolation layer 83, and the first isolation layer 83 is located on the peripheral side of the chip structure 20. The first isolation layer 83 may include SiO2 and SiN x At least one of .

[0176] In some embodiments, the display chip also includes a second transparent conductive layer 84, which is located on the side of the second reflective layer 82 away from the substrate 30 and on the side of the first isolation layer 83 away from the substrate 30, and the second transparent conductive layer 84 penetrates the second reflective layer 82 and the passivation layer 81 and is connected to the heavily doped semiconductor layer 41 in the first semiconductor layer 4.

[0177] The second transparent conductive layer 84 may include an ITO layer, and the thickness of the second transparent conductive layer 84 may be 100 nm to 400 nm.

[0178] In some embodiments, the display chip further includes an n-type ohmic contact electrode, which is located on the peripheral side of the chip structure 20 and on the side of the second transparent conductive layer 84 away from the substrate 30. The n-type ohmic contact electrode includes a metal layer, such as Ti / Al / Ti / Au, etc.

[0179] In some embodiments, Fig.14 As shown, the display chip further includes a third reflective layer 85, which is located on the peripheral side of the chip structure 20, and the third reflective layer 85 is located on the side of the second transparent conductive layer 84 away from the substrate 30. The third reflective layer 85 can reduce the light crosstalk and light divergence angle between pixels, and improve the light extraction efficiency of the chip. The third reflective layer 85 may include a metal layer, such as at least one of Ag and Al.

[0180] In some embodiments, the display chip further includes a second isolation layer 86, which is located on the peripheral side of the chip structure 20 and covers the second transparent conductive layer 84 and the third reflective layer 85. The surface of the second isolation layer 86 facing away from the substrate 30 may be flush with the surface of the second transparent conductive layer 84 facing away from the substrate 30. The second isolation layer 86 may include SiO2 and SiN x At least one of the above. The first isolation layer 83 and the second isolation layer 86 are used to achieve electrical insulation between pixel mesas.

[0181] In some embodiments, the display chip further includes a microlens 85, which is located on the side of the second transparent conductive layer 84 away from the chip structure 20, and the microlens 85 corresponds to the position of the chip structure 20. The microlens 85 is used to increase the light collection of the chip. The microlens 85 includes SiO2 and the like.

[0182] According to the display chip provided in the embodiment of the present application, the first semiconductor layer 4, the quantum well light-emitting layer 5 and the second semiconductor layer 6 are all nitrogen-polar film layers. The nitrogen-polar film layers can be grown at high temperatures, thereby improving the crystal quality of the potential well layer material in the quantum well, improving the chip carrier injection efficiency, and effectively inhibiting the overflow of carriers, alleviating the Droop effect of the chip under large current injection, and improving the luminous efficiency of the display chip, thereby improving the display effect of the display chip.

[0183] The terms "first", "second", etc. in the specification and claims of this application are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the terms used in this way can be interchangeable under appropriate circumstances, so that the embodiments of the present application can be implemented in an order other than those illustrated or described herein, and the objects distinguished by "first", "second", etc. are generally of the same type, and the number of objects is not limited. For example, the first object can be one or more.

[0184] In the description of the present application, “plurality” means two or more.

[0185] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "illustrative embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0186] Although the embodiments of the present application have been shown and described, those skilled in the art will appreciate that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present application, and that the scope of the present application is defined by the claims and their equivalents.

Claims

1. A display chip, characterized in that: include: The chip structure comprises a first semiconductor layer, a quantum well light-emitting layer and a second semiconductor layer arranged in sequence; One of the first semiconductor layer and the second semiconductor layer is an n-type semiconductor layer, and the other is a p-type semiconductor layer; Wherein, the first semiconductor layer, the quantum well light-emitting layer and the second semiconductor layer are all nitrogen-polar film layers.

2. The display chip according to claim 1, characterized in that: The chip structure further includes a fourth non-doped semiconductor layer, a first barrier layer, a first superlattice layer and a second superlattice layer which are sequentially arranged between the first semiconductor layer and the quantum well light-emitting layer; The fourth undoped semiconductor layer, the first barrier layer, the first superlattice layer and the second superlattice layer are all nitrogen-polar film layers.

3. The display chip according to claim 1, characterized in that: The first semiconductor layer includes a heavily doped semiconductor layer and a lightly doped semiconductor layer located between the heavily doped semiconductor layer and the quantum well light emitting layer; The heavily doped semiconductor layer and the lightly doped semiconductor layer are both nitrogen polar film layers.

4. The display chip according to claim 1, characterized in that: The quantum well light-emitting layer comprises a fifth undoped semiconductor layer, a first potential well layer, a first cap layer, a second potential barrier layer, a sixth undoped semiconductor layer, a second potential well layer, a second cap layer and a third barrier layer, which are sequentially arranged between the first semiconductor layer and the second semiconductor layer; The fifth undoped semiconductor layer, the first potential well layer, the first cap layer, the second potential barrier layer, the sixth undoped semiconductor layer, the second potential well layer, the second cap layer and the third potential barrier layer are all nitrogen polar film layers.

5. The display chip according to claim 1, characterized in that: The second semiconductor layer comprises an electron blocking layer, a hole injection layer and an ohmic contact layer which are sequentially arranged on a side of the quantum well light emitting layer away from the first semiconductor layer; The electron blocking layer, the hole injection layer and the ohmic contact layer are all nitrogen polar film layers.

6. The display chip according to claim 1, characterized in that: The chip structure further includes a first transparent conductive layer, a first reflective layer and a bonding layer which are sequentially located on a side of the second semiconductor layer away from the quantum well light-emitting layer.

7. The display chip according to claim 1, characterized in that: The chip structure further includes a protection layer located between the quantum well light-emitting layer and the second semiconductor layer.

8. The display chip according to claim 1, characterized in that: The display chip further includes a substrate; The substrate is bonded to a side of the chip structure facing away from the first semiconductor layer.

9. The display chip according to claim 8, characterized in that: The display chip further includes a passivation layer and a second reflective layer; The passivation layer is located on a side of the chip structure away from the substrate and covers a side wall of the chip structure, and the second reflective layer covers the passivation layer.

10. The display chip according to claim 9, characterized in that: The display chip further includes a second transparent conductive layer located on a side of the second reflective layer away from the substrate, and the second transparent conductive layer penetrates the second reflective layer and the passivation layer and is connected to the first semiconductor layer.

11. The display chip according to claim 10, characterized in that: The display chip further comprises a third reflective layer located on the peripheral side of the chip structure, and a microlens located on a side of the second transparent conductive layer away from the chip structure.

12. The display chip according to any one of claims 1 to 11, characterized in that: The quantum well light-emitting layer comprises a red light quantum well light-emitting layer.

13. A method for manufacturing a display chip, characterized in that: include: forming a base; A chip structure is formed on one side of the substrate; the chip structure comprises a first semiconductor layer, a quantum well light-emitting layer, and a second semiconductor layer sequentially arranged on one side of the substrate; one of the first semiconductor layer and the second semiconductor layer is an n-type semiconductor layer, and the other is a p-type semiconductor layer; wherein the first semiconductor layer, the quantum well light-emitting layer, and the second semiconductor layer are all nitrogen-polar film layers; The substrate is removed.

14. The method for manufacturing a display chip according to claim 13, characterized in that: The base comprises a substrate, a buffer layer and a non-doped semiconductor composite layer; The forming of the substrate comprises: providing a substrate; forming a buffer layer on one side of the substrate; A non-doped semiconductor composite layer is formed on a side of the buffer layer away from the substrate; the chip structure is located on a side of the non-doped semiconductor composite layer away from the buffer layer; Wherein, the buffer layer and the non-doped semiconductor composite layer are both nitrogen-polar film layers.

15. The method for manufacturing a display chip according to claim 14, characterized in that: The non-doped semiconductor composite layer comprises a plurality of non-doped semiconductor layers and at least one insertion layer which are stacked, and there is one insertion layer between any two adjacent non-doped semiconductor layers; The non-doped semiconductor layer and the insertion layer are both nitrogen-polar film layers.

16. The method for manufacturing a display chip according to claim 15, characterized in that: The plurality of non-doped semiconductor layers include a first non-doped semiconductor layer, a second non-doped semiconductor layer and a third non-doped semiconductor layer, the at least one insertion layer includes a first insertion layer and a second insertion layer; the first non-doped semiconductor layer, the first insertion layer, the second non-doped semiconductor layer, the second insertion layer and the third non-doped semiconductor layer are sequentially arranged between the buffer layer and the first semiconductor layer; The first non-doped semiconductor layer, the second non-doped semiconductor layer and the third non-doped semiconductor layer all include u-GaN layers, and the first insertion layer includes porous SiN x layer, and the second insertion layer includes an AlN layer.

17. The method for manufacturing a display chip according to any one of claims 14 to 16, characterized in that: The removing of the substrate comprises: removing the substrate; The buffer layer and the undoped semiconductor composite layer are removed.

18. The method for manufacturing a display chip according to claim 13, characterized in that: Before removing the substrate, the method further comprises: The side of the chip structure facing away from the base is bonded to a substrate.

19. The method for manufacturing a display chip according to claim 18, characterized in that: After removing the substrate, the method further comprises: forming a passivation layer on a side of the chip structure facing away from the substrate, wherein the passivation layer covers a side wall of the chip structure; A second reflective layer is formed on the surface of the passivation layer.

20. The method for manufacturing a display chip according to claim 19, characterized in that: The method further comprises: forming a second transparent conductive layer on a side of the second reflective layer away from the substrate, wherein the second transparent conductive layer penetrates the second reflective layer and the passivation layer and is connected to the first semiconductor layer; A microlens is formed on a side of the second transparent conductive layer facing away from the substrate.

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