Light-emitting element

Abstract

A light emitting device includes a semiconductor stack including a first semiconductor layer, a second semiconductor layer, and an active layer between the first semiconductor layer and the second semiconductor layer; a first electrode pad adjacent to the first side of the light emitting element; the second electrode pad is adjacent to a second side of the light-emitting element, and the first side and the second side are located on different sides of the light-emitting element from the top view of the light-emitting element; and the insulating layer comprises one or more first openings adjacent to the first side and one or more second openings adjacent to the second side, the one or more first openings and the one or more second openings are exposed out of the first semiconductor layer, one of the one or more first openings comprises a first maximum length, and the other one of the one or more second openings comprises a second maximum length. And one of the one or more second openings has a second maximum length greater than the first maximum length.

Description

[0001] This application is a divisional application of the Chinese invention patent application (application number: 2019107060985, application date: August 1, 2019, invention name: light-emitting element). Technical Field

[0002] The present invention relates to a light emitting element, and in particular to a flip-chip light emitting element, which comprises a semiconductor stack, a first electrode and a second electrode located on the same side of the semiconductor stack. Background Art

[0003] Light-Emitting Diode (LED) is a solid-state semiconductor light-emitting element with the advantages of low power consumption, low heat generation, long service life, shock resistance, small size, fast response speed and good photoelectric properties, such as stable light emission wavelength. Therefore, light-emitting diodes are widely used in household appliances, equipment indicator lights, and optoelectronic products. Summary of the invention

[0004] An object of the present invention is to provide a light emitting element and a method for manufacturing the same to improve the light extraction efficiency of the light emitting element.

[0005] Another object of the present invention is to provide a light-emitting element and a method for manufacturing the same which improves light extraction efficiency by means of patterns on the side surfaces of a semiconductor stack.

[0006] Another object of the present invention is to provide a light emitting element and a manufacturing method thereof that provide a recognition pattern and a recognition method that facilitate cutting to improve production yield.

[0007] Another object of the present invention is to provide a light emitting element and a method for manufacturing the same which can improve the reliability of a packaging device.

[0008] To achieve at least one of the above-mentioned purposes, according to one embodiment of the present invention, a light-emitting element is disclosed, comprising a semiconductor stack, comprising a first semiconductor layer, a second semiconductor layer and an active layer located between the first semiconductor layer and the second semiconductor layer; a first electrode pad adjacent to a first side of the light-emitting element; a second electrode pad adjacent to a second side of the light-emitting element, wherein from a top view of the light-emitting element, the first side and the second side are located on different sides of the light-emitting element; and an insulating layer comprising one or more first openings adjacent to the first side and one or more second openings adjacent to the second side, and the one or more first openings and the one or more second openings expose the first semiconductor layer, one of the one or more first openings comprises a first maximum length, and one of the one or more second openings comprises a second maximum length greater than the first maximum length.

[0009] To achieve at least one of the above-mentioned purposes, according to one embodiment of the present invention, a light-emitting element is disclosed, comprising a substrate having multiple corners and multiple edges; a semiconductor stack located on the substrate; and multiple semiconductor structures respectively located on the multiple corners or multiple edges of the substrate, wherein the multiple semiconductor structures are separated from the semiconductor stack by a distance and the multiple semiconductor structures are separated from each other. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 A top view of a light emitting element 1 according to an embodiment of the present invention;

[0011] Figure 2 A manufacturing flow chart of a light emitting element 1 disclosed in one embodiment of the present invention;

[0012] Figure 3 For along Figure 1 A cross-sectional view of the tangent line a-a';

[0013] Figure 3A For along Figure 1 A cross-sectional view of the tangent line A-A';

[0014] Figure 4 For along Figure 1 A cross-sectional view of the tangent line B-B';

[0015] Figure 5 For along Figure 1 A cross-sectional view of the tangent line C-C';

[0016] Fig. 6A for Figure 1 A partially enlarged top view of a portion of X1;

[0017] Figure 6B For along Fig. 6A A cross-sectional view of the tangent line X1'-X1";

[0018] Figure 6C for Figure 1 A partially enlarged top view of a portion of X2;

[0019] Fig.6D For along Figure 6C A cross-sectional view of the tangent line X2'-X2";

[0020] Figure 7 A top view of a light emitting element 2 disclosed in an embodiment of the present invention;

[0021] Figure 8 A manufacturing flow chart of a light emitting element 2 disclosed in one embodiment of the present invention;

[0022] Fig. 9 For along Figure 7 A cross-sectional view of the tangent line D-D';

[0023] Fig.9A For along Figure 7 A cross-sectional view of the tangent line H-H';

[0024] Fig.10 For along Figure 7 A cross-sectional view of the tangent line E-E';

[0025] Fig.11 For along Figure 7 A cross-sectional view of the tangent line F-F';

[0026] Fig.12 For along Figure 7 A cross-sectional view of the tangent line G-G';

[0027] Fig.13A A schematic diagram of a method for manufacturing a light emitting element 1A according to an embodiment of the present invention;

[0028] Fig. 13B A schematic diagram of a method for manufacturing a light emitting element 1A according to an embodiment of the present invention;

[0029] Fig. 13C A top view of a light emitting element 1A according to an embodiment of the present invention;

[0030] Fig.14 is a schematic diagram of a light emitting device 3 according to an embodiment of the present invention;

[0031] Fig.15 is a schematic diagram of a light emitting device 4 according to an embodiment of the present invention;

[0032] Fig.16 A top view of a light emitting element 5 disclosed in an embodiment of the present invention;

[0033] Fig.17 For along Fig.16 A cross-sectional view of the tangent line I-I';

[0034] Fig.18 For along Fig.16 Sectional view of the tangent line J-J'.

[0035] Explanation of symbols

[0036] 1, 2, 1A, 5 light emitting elements

[0037] 2a First light emitting unit

[0038] 2b Second light-emitting unit

[0039] 3,4 Light-emitting device

[0040] 10 substrate

[0041] 100 Upper surface

[0042] 101 first side surface

[0043] 102 second side surface

[0044] 103 Third side surface

[0045] 1031 First end of the third side surface

[0046] 1032 second end of the third side surface

[0047] 104 fourth side surface

[0048] 1041 First end of the fourth side surface

[0049] 1042 second end of the fourth side surface

[0050] 11 Groove

[0051] 20 Semiconductor stack

[0052] 200 Hole

[0053] 200s inner surface

[0054] 201 First semiconductor layer

[0055] 202 Second semiconductor layer

[0056] 203 Active layer

[0057] 204 concavity

[0058] 204a first recess

[0059] 204b second recess

[0060] 204s outer surface

[0061] 204as outer surface

[0062] 204bs outer surface

[0063] 205 Semiconductor Platform

[0064] 205a First Semiconductor Platform

[0065] 205b Second Semiconductor Platform

[0066] 205c Corner of the semiconductor platform

[0067] 205e The outer edge of the semiconductor platform

[0068] 2050 concave platform

[0069] 2051 convex platform

[0070] 2051c First Corner

[0071] 2051e First Edge

[0072] 2052c Second Corner

[0073] 2052e, 2052e' Second outer edge

[0074] 20520 Second multiple concave platform

[0075] 20521 Second Multiple Protrusion Platform

[0076] 2053e The Third Outer Edge

[0077] 2054e The Fourth Outer Edge

[0078] 2011 First Sidewall

[0079] 2012 Second Sidewall

[0080] 2013 Third Sidewall

[0081] 2014 The Fourth Sidewall

[0082] 206 Semiconductor Structure

[0083] 2061 First Semiconductor Structure

[0084] 2062 Second Semiconductor Structure

[0085] 2063 The Third Semiconductor Structure

[0086] 2064 The fourth semiconductor structure

[0087] 221 First recognition structure

[0088] 222 Second identification structure

[0089] 223 Third identification structure

[0090] 30 First insulation layer

[0091] 300 First insulation layer opening

[0092] 301 first insulating layer first opening

[0093] 301w Maximum length

[0094] 302 first insulating layer second opening

[0095] 302w Maximum length

[0096] 303 first insulating layer third opening

[0097] 303a, 303b first insulating layer third opening

[0098] 40 Contact electrode

[0099] 40a First contact electrode

[0100] 40b Second contact electrode

[0101] 50 Reflection layer

[0102] 50a First reflection layer

[0103] 50b Second reflection layer

[0104] 60 Second insulation layer

[0105] 600 Second insulation layer opening

[0106] 600a Second insulating layer first unit opening

[0107] 600b Second insulating layer second unit opening

[0108] 601 second insulating layer first opening

[0109] 601w Maximum length

[0110] 602 second insulating layer second opening

[0111] 602w Maximum length

[0112] 603 The third opening of the second insulating layer

[0113] 603a The third opening of the second insulating layer

[0114] 603b The fourth opening of the second insulating layer

[0115] 70 Connecting electrodes

[0116] 701 First connection end

[0117] 702 Second connection terminal

[0118] 703 Third connection terminal

[0119] 71 Lower electrode

[0120] 71a First lower electrode

[0121] 71b Second lower electrode

[0122] 71s top

[0123] 72 Upper electrode

[0124] 72b Second upper electrode

[0125] 72s top

[0126] 80 Third insulation layer

[0127] 801 third insulating layer first opening

[0128] 802 third insulating layer second opening

[0129] 91 First electrode pad

[0130] 92 Second electrode pad

[0131] 1000, 1001 position

[0132] 2000, 2001 Location

[0133] 3000, 3001 position

[0134] θ1 First angle

[0135] θ2 Second angle

[0136] θ3 The third angle

[0137] θ4 Fourth angle

[0138] C1 First Corner

[0139] C2 Second Corner

[0140] C3 Third Corner

[0141] C4 Fourth Corner

[0142] D Spacing

[0143] D1 first spacing

[0144] D2 Second spacing

[0145] d1, d2 distance

[0146] w1, w2 width

[0147] E1 First side

[0148] E2 Second side

[0149] E3 Third side

[0150] E4 Fourth side

[0151] L1 First shortest distance

[0152] L2 Second shortest distance

[0153] L3 Third shortest distance

[0154] L4 Fourth shortest distance

[0155] 101A First Side

[0156] 102A Second Side

[0157] 103A The Third Side

[0158] 104A The Fourth Side

[0159] S1 First slope

[0160] S2 Second slope

[0161] Z1, Z2 cutting path

[0162] t1 upper surface

[0163] b1 Lower surface 51 Package substrate

[0164] 511 First Gasket

[0165] 512 Second gasket

[0166] 53 Insulation

[0167] 54 Reflection Structure

[0168] 602 Lampshade

[0169] 604 Reflector

[0170] 606 bearing part

[0171] 608 Luminous Body

[0172] 610 Light emitting module

[0173] 612 Lamp Holder

[0174] 614 Heat sink

[0175] 616 Connection

[0176] 618 Electrical connection components DETAILED DESCRIPTION

[0177] In order to make the description of the present invention more detailed and complete, please refer to the description of the following embodiments and the relevant illustrations. However, the embodiments shown below are used to illustrate the light-emitting elements of the present invention, and the present invention is not limited to the following embodiments. In addition, the dimensions, materials, shapes, relative configurations, etc. of the components recorded in the embodiments of this specification are not limited to this, but are simply illustrated. The size or positional relationship of the components shown in each figure may be exaggerated for the purpose of clear description. Moreover, in the following description, in order to appropriately omit detailed description, the same or similar components are displayed with the same name or symbol.

[0178] Figure 1 It is a top view of a light emitting element 1 disclosed in an embodiment of the present invention. Figure 2 FIG. 1 is a flowchart of manufacturing a light emitting element 1 according to an embodiment of the present invention. Figure 3 For along Figure 1 Cross-sectional view of the tangent line a-a'. Figure 3A For along Figure 1 Cross-sectional view of the tangent line A-A'. Figure 4 For along Figure 1 Cross-sectional view of the tangent line BB'. Figure 5 For along Figure 1 The structure of the light emitting element 1 can improve the light extraction efficiency.

[0179] like Figure 1 , Figure 3 and Figure 3A As shown, a light emitting element 1 comprises a substrate 10 comprising an upper surface 100, a first side surface 101, a second side surface 102, a third side surface 103 and a fourth side surface 104. The first side surface 101 and the second side surface 102 of the substrate 10 are located at two opposite sides of the upper surface 100 of the substrate 10, and the third side surface 103 and the fourth side surface 104 of the substrate 10 are located at the other two opposite sides of the upper surface 100 of the substrate 10. The first side surface 101, the second side surface 102, the third side surface 103 and the fourth side surface 104 constitute an outer periphery of the substrate 10.

[0180] The light emitting element 1 comprises a semiconductor stack 20 located on the upper surface 100 of the substrate 10 . The semiconductor stack 20 comprises a first semiconductor layer 201 , a second semiconductor layer 202 , and an active layer 203 located between the first semiconductor layer 201 and the second semiconductor layer 202 .

[0181] In another embodiment, the light emitting element 1 may have a polygonal shape, such as a triangle, hexagon, rectangle or square. From the top view, the size of the light emitting element 1 may be, for example, a square shape of 1000 μm×1000 μm or 700 μm×700 μm or a rectangular shape of similar size, but is not particularly limited thereto.

[0182] The substrate 10 may be a growth substrate, including a gallium arsenide (GaAs) wafer for epitaxially growing aluminum gallium indium phosphide (AlGaInP), or a sapphire (Al2O3) wafer, a gallium nitride (GaN) wafer, a silicon carbide (SiC) wafer, or an aluminum nitride (AlN) wafer for growing gallium nitride (GaN), indium gallium nitride (InGaN), or aluminum gallium nitride (AlGaN). In another embodiment, the substrate 10 may be a support substrate, and the growth substrate originally used for epitaxially growing the semiconductor stack 20 may be selectively removed according to the needs of the application, and then the semiconductor stack 20 may be transferred to the aforementioned support substrate.

[0183] The support substrate includes a conductive material, such as silicon (Si), aluminum (Al), copper (Cu), tungsten (W), molybdenum (Mo), gold (Au), silver (Ag), silicon carbide (SiC) or an alloy of the above materials, or a thermal conductive material, such as diamond, graphite, or aluminum nitride. In addition, although not shown in the figure, the side of the substrate 10 that is connected to the semiconductor stack 20 may have a surface with increased roughening, and the roughened surface may be a surface with an irregular shape or a surface with a regular shape, such as a surface with a plurality of hemispherical shapes protruding or recessed from the upper surface 100, a surface with a plurality of conical shapes protruding or recessed from the upper surface 100, or a surface with a plurality of polygonal cone shapes protruding or recessed from the upper surface 100.

[0184] In one embodiment of the present invention, a semiconductor stack 20 having optoelectronic properties, such as a light-emitting stack, is formed on a substrate 10 by metal organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), hydride vapor phase deposition (HVPE), physical vapor deposition (PVD) or ion plating, wherein the physical vapor deposition method includes sputtering or evaporation.

[0185] In one embodiment of the present invention, the semiconductor stack 20 may further include a buffer layer (not shown) located between the first semiconductor layer 201 and the substrate 10 to release the stress generated by the material lattice mismatch between the substrate 10 and the semiconductor stack 20, so as to reduce dislocation and lattice defects, thereby improving the epitaxial quality. The buffer layer may be a single layer or a structure including multiple layers. In one embodiment, PVD aluminum nitride (AlN) may be selected as a buffer layer, formed between the semiconductor stack 20 and the substrate 10, to improve the epitaxial quality of the semiconductor stack 20. In one embodiment, the target material for forming PVD aluminum nitride (AlN) is composed of aluminum nitride. In another embodiment, a target material composed of aluminum is used to reactively form aluminum nitride with an aluminum target material in a nitrogen source environment. In one embodiment, the buffer layer includes a plurality of sublayers (not shown). The sublayers include the same material or different materials. In one embodiment, the buffer layer includes two sublayers, wherein the growth method of the first sublayer is sputtering, and the growth method of the second sublayer is MOCVD. In one embodiment, the buffer layer further comprises a third sublayer. The third sublayer is grown by MOCVD, and the growth temperature of the second sublayer is higher or lower than the growth temperature of the third sublayer. In one embodiment, the first, second and third sublayers comprise the same material, such as aluminum nitride.

[0186] The wavelength of light emitted by the light emitting element 1 can be adjusted by changing the physical and chemical composition of one or more layers in the semiconductor stack 20. The material of the semiconductor stack 20 includes III-V semiconductor materials, such as Al x In y Ga (1-x-y) N or Al x In y Ga (1-x-y) P, where 0≤x, y≤1; (x+y)≤1. When the material of the semiconductor stack 20 is AlInGaP series material, red light with a wavelength between 610 nm and 650 nm, or green light with a wavelength between 530 nm and 570 nm can be emitted. When the material of the semiconductor stack 20 is InGaN series material, blue light with a wavelength between 400 nm and 490 nm can be emitted. When the material of the semiconductor stack 20 is AlGaN series or AlInGaN series material, ultraviolet light with a wavelength between 400 nm and 250 nm can be emitted.

[0187] The first semiconductor layer 201 and the second semiconductor layer 202 may be cladding layers, and the two have different conductivity types, electrical properties, polarities, or provide electrons or holes according to doped elements. For example, the first semiconductor layer 201 is an n-type electrical semiconductor, and the second semiconductor layer 202 is a p-type electrical semiconductor. The active layer 203 is formed between the first semiconductor layer 201 and the second semiconductor layer 202. Electrons and holes recombine in the active layer 203 under a current drive, converting electrical energy into light energy to emit a light. The active layer 203 may be a single heterostructure (SH), a double heterostructure (DH), a double-side double heterostructure (DDH), or a multi-quantum well (MQW). The material of the active layer 203 may be a neutral, p-type, or n-type electrical semiconductor. The first semiconductor layer 201 , the second semiconductor layer 202 , or the active layer 203 may be a single layer or a structure including multiple layers.

[0188] like Figure 2 and Figure 3 As shown, selective etching is performed on the semiconductor stack 20 to form the hole 200, the recess 204 and the semiconductor platform 205 on the semiconductor stack 20. For example, a photoresist is applied, and then a portion of the photoresist is removed through a conventional patterning process to form a photoresist pattern of the hole 200, the recess 204 and the semiconductor platform 205. Then, the photoresist pattern is used as an etching mask to perform an etching process to form the hole 200, the recess 204 and the semiconductor platform 205. Specifically, the semiconductor platform 205 is formed by removing a portion of the second semiconductor layer 202 and the active layer 203 to form a structure including the first semiconductor layer 201, the second semiconductor layer 202 and the active layer 203. The hole 200 and the recess 204 are formed by removing a portion of the second semiconductor layer 202 and the active layer 203 to expose the first semiconductor layer 201 respectively. After the etching process, the remaining photoresist pattern is removed.

[0189] like Figure 3As shown, the semiconductor platform 205 includes an upper surface t1 and a lower surface b1, and the active layer 203 includes a first upper surface 203t and a second lower surface 203b, wherein the first upper surface 203t of the active layer 203 is closer to the upper surface t1 of the semiconductor platform 205 than the second lower surface 203b, and a first thickness is included between the upper surface t1 of the semiconductor platform 205 and the first upper surface 203t of the active layer 203, and a second thickness is included between the lower surface b1 of the semiconductor platform 205 and the second lower surface 203b of the active layer 203, and the second thickness is greater than the first thickness.

[0190] In another embodiment (not shown), when the semiconductor stack 20 is transferred from the growth substrate to the supporting substrate, each semiconductor platform 205 includes an upper surface t1 and a lower surface b1, and the active layer 203 includes a first upper surface 203t and a second lower surface 203b, wherein the upper surface t1 of the semiconductor platform 205 and the first upper surface 203t of the active layer 203 are respectively closer to the supporting substrate than the lower surface b1 of the semiconductor platform and the second lower surface 203b of the active layer 203, a first thickness is included between the upper surface t1 of the semiconductor platform 205 and the first upper surface 203t of the active layer 203, and a second thickness is included between the lower surface b1 of the semiconductor platform 205 and the second lower surface 203b of the active layer 203, and the second thickness is greater than the first thickness.

[0191] like Figure 1 As shown, from a top view of the light-emitting element 1, the substrate 10 of the light-emitting element 1 includes a plurality of corners and a plurality of sides, wherein any corner is formed by two adjacent sides. The plurality of corners includes a first corner C1, a second corner C2, a third corner C3, and a fourth corner C4. The plurality of sides includes a first side E1, a second side E2, a third side E3, and a fourth side E4.

[0192] like Figure 1 and Figure 2 As shown, an outer edge 205e of the semiconductor platform 205 includes a first outer edge 2051e adjacent to the first side E1 and a second outer edge 2052e adjacent to the second side E2. In order to increase the light-emitting area and light extraction efficiency of the light-emitting element 1, compared with the second outer edge 2052e adjacent to the second side E2, the first outer edge 2051e adjacent to the first side E1 includes a plurality of concave platforms 2050 and a plurality of convex platforms 2051. The plurality of concave platforms 2050 and the plurality of convex platforms 2051 are arranged alternately with each other.

[0193] like Figure 1 As shown, a first distance D1 between one side of the convex platform 2051 of the first outer edge 2051e and the first side E1 is smaller than a second distance D2 between the second outer edge 2052e and the second side E2.

[0194] The contours of the plurality of concave platforms 2050 and the plurality of convex platforms 2051 form a first outer edge 2051e. In the top view of the light emitting element 1, the first outer edge 2051e can be wavy, sawtooth or square. The positions of the subsequent insulating layer openings, contact layers, or electrode layers can be determined according to the configuration positions of the plurality of concave platforms 2050 and the plurality of convex platforms 2051. The light extraction efficiency of the light emitting element can be improved by designing the pattern of the side surface of the semiconductor stack 20.

[0195] like Figure 1 and Figure 2 As shown, the corners 205 c of the semiconductor platform 205 may be rounded to prevent the current from being locally concentrated at the corners of the light emitting element 1 .

[0196] like Figure 2 As shown, the recess 204 is located at the outermost side of the semiconductor stack 20 , wherein the recess 204 continuously or discontinuously surrounds the second semiconductor layer 202 and the active layer 203 of the semiconductor platform 205 by continuously or discontinuously exposing the surface of the outermost first semiconductor layer 201 of the semiconductor stack 20 .

[0197] In another embodiment (not shown), the recess 204 discontinuously surrounds the second semiconductor layer 202 and the active layer 203 of the semiconductor platform 205 by discontinuously exposing the surface of the outermost first semiconductor layer 201 of the semiconductor stack 20 .

[0198] like Figure 1 and Figure 2 As shown, the hole 200 is located inside the semiconductor stack 20 and is surrounded by the recess 204. In other words, the hole 200 is surrounded by the second semiconductor layer 202 and the active layer 203. From a top view of the self-luminous element 1, the shape of the hole 200 includes an ellipse, a circle, a rectangle or any other shape.

[0199] The light emitting element 1 includes a plurality of holes 200, and the number and arrangement positions of the plurality of holes 200 are not limited, and can be arranged regularly at certain intervals so that the current can be evenly dispersed in the horizontal direction. The plurality of holes 200 can be arranged in a plurality of columns to form an array, and the holes 200 on any two adjacent columns or each two adjacent columns can be aligned or staggered with each other. The positions of the subsequent contact layer and the electrode layer can be determined according to the arrangement positions of the plurality of holes 200.

[0200] like Figure 3As shown, the hole portion 200 includes a first inclined surface S1, which has an inclined angle within a range, such as an angle of 10 to 80 degrees, relative to the inner surface 200s of the first semiconductor layer 201. The recess 204 includes a second inclined surface S2, which has an inclined angle within a range, such as an angle of 10 to 80 degrees, relative to the outer surface 204s of the first semiconductor layer 201. If the angle is less than 10 degrees, the too low slope will reduce the area of ​​the active layer 203, and the reduction in the area of ​​the active layer 203 will cause the brightness of the light-emitting element to decrease. If the angle is greater than 80 degrees, the subsequent insulating layer and metal layer may not be able to completely cover the side walls of the first semiconductor layer 201, the second semiconductor layer 202, and / or the active layer 203, thereby causing the film layer to break.

[0201] In one embodiment of the present invention, the second slope S2 has an angle of 20 to 75 degrees, preferably 30 to 65 degrees, and more preferably 40 to 55 degrees relative to the outer surface 204s of the first semiconductor layer 201 .

[0202] Figure 3 For along Figure 1 The cross-sectional view of the tangent line a-a'. Figure 3 As shown, the first semiconductor layer 201 near the fourth side E4 includes a first sidewall 2011 connected to the upper surface 100 of the substrate 10 or directly connected to the fourth side surface 104 of the substrate 10. The first semiconductor layer 201 near the second side E2 includes a second sidewall 2012 inclined to the upper surface 100 of the substrate 10 and separated from the second side surface 102 of the substrate 10 by a distance D to expose the upper surface 100 of the substrate 10.

[0203] Figure 3A For along Figure 1 The sectional view of the tangent line A-A'. Figure 3A As shown, the first semiconductor layer 201 near the first edge E1 includes a first sidewall 2011 connected to the upper surface 100 of the substrate 10, and is separated from the first side surface 101 of the substrate 10 by a first spacing D' to expose the upper surface 100 of the substrate 10. The first semiconductor layer 201 near the second edge E2 includes a second sidewall 2012 inclined to the upper surface 100 of the substrate 10 and separated from the second side surface 102 of the substrate 10 by a spacing D to expose the upper surface 100 of the substrate 10, wherein the second spacing D' is smaller than the spacing D.

[0204] In one embodiment of the invention, Figure 1As shown, the first semiconductor layer 201 includes a plurality of first side walls 2011 and a plurality of second side walls 2012 to form a periphery of the first semiconductor layer 201. The plurality of first side walls 2011 are respectively adjacent to the first side E1, the third side E3 and the fourth side E4, and the plurality of second side walls 2012 are respectively adjacent to the second side E2, the third side E3 and the fourth side E4. From a top view of the self-light emitting element 1, one of the plurality of first side walls 2011 adjacent to the third side E3 and the fourth side E4 and one of the plurality of second side walls 2012 can be connected to each other through a side wall 201s. The side wall 201s can be a plane or a curved surface. The side wall 201s is connected to the first side wall 2011 and the second side wall 2012 at an oblique angle to increase the light extraction efficiency of the light emitting element 1.

[0205] In one embodiment of the invention, the first side wall 2011 adjacent to the first side E1 is spaced apart from the first side surface 101 of the substrate 10 by a primary spacing D' to expose the upper surface 100 of the substrate 10. The second side wall 2012 adjacent to the second side E2 is spaced apart from the second side surface 102 of the substrate 10 by a spacing D to expose the upper surface 100 of the substrate 10. The secondary spacing D' is smaller than the spacing D. The first side wall 2011 adjacent to the third side E3 and the fourth side E4 is directly connected to the third side surface 103 and the fourth side surface 104 of the substrate 10, respectively. The second side wall 2012 adjacent to the third side E3 and the fourth side E4 is inclined to the upper surface 100 of the substrate 10, and is spaced apart from the second side surface 102 of the substrate 10 by a spacing D to expose the upper surface 100 of the substrate 10.

[0206] In one embodiment of the invention (not shown), the first sidewalls 2011 adjacent to the first side E1, the third side E3 and the fourth side E4 are directly connected to the first side surface 101, the third side surface 103 and the fourth side surface 104 of the substrate 10. The second sidewalls 2012 adjacent to the second side E2, the third side E3 and the fourth side E4 are inclined to the upper surface 100 of the substrate 10 and are separated from the second side surface 102, the third side surface 103 and the fourth side surface 104 of the substrate 10 by a distance D to expose the upper surface 100 of the substrate 10.

[0207] In one embodiment of the invention (not shown), the first sidewalls 2011 are adjacent to the first edge E1 and the third edge E3, and the second sidewalls 2012 are adjacent to the second edge E2 and the fourth edge E4. The sidewalls 201s are located at the third corner C3 and the fourth corner C4 at an oblique angle and are connected to the first sidewalls 2011 and the second sidewalls 2012, respectively.

[0208] In one embodiment of the invention, Figure 1As shown, the plurality of first side walls 2011 and the plurality of second side walls 2012 can be adjusted according to the shape of the light emitting element 1, such as a circular, triangular, hexagonal, rectangular or square shape. In one embodiment of the invention, the positions surrounded by the plurality of first side walls 2011 and the plurality of second side walls 2012 can be adjusted according to the user's design, and are not limited by the above, provided that the subsequent manufacturing process can be operated, for example, the area surrounded by the plurality of first side walls 2011 and the plurality of second side walls 2012 can accommodate the subsequent electrode pad arrangement.

[0209] In one embodiment of the invention, Figure 3 As shown, the spacing D is preferably greater than 5 μm and less than 50 μm, and more preferably less than 30 μm. The upper surface 100 of the substrate 10 exposed by the spacing D is a rough surface. The rough surface can be a surface with an irregular shape or a surface with a regular shape, such as a surface with a plurality of hemispherical shapes protruding or recessed on the upper surface 100, a surface with a plurality of conical shapes protruding or recessed on the upper surface 100, or a surface with a plurality of polygonal cone shapes protruding or recessed on the upper surface 100.

[0210] like Figure 3 As shown, a first angle θ1 is formed between the first sidewall 2011 of the first semiconductor layer 201 and the upper surface 100 of the substrate 10 , and a second angle θ2 is formed between the second sidewall 2012 of the first semiconductor layer 201 and the upper surface 100 of the substrate 10 , and the second angle θ2 is different from the first angle θ1 .

[0211] In one embodiment of the invention, the first angle θ1 is greater than the second angle θ2.

[0212] In one embodiment of the invention, the first angle θ1 is between 70° and 90°, and the second angle θ2 is between 20° and 70°.

[0213] In one embodiment of the invention, the angle difference between the first angle θ1 and the second angle θ2 is greater than 20°.

[0214] Fig.16 It is a top view of a light emitting element 5 disclosed in an embodiment of the present invention. Fig.17 For along Fig.16 Cross-sectional view along the tangent line I-I'. Fig.18 For along Fig.16 The light emitting element 5 has substantially the same structure as the light emitting element 1, so for Figure 16~Figure 18 The light emitting element 5 and Figure 1~Figure 6D The light-emitting elements 1 have the same names and numbers, represent the same structure, have the same materials, or have the same functions, and the description thereof will be appropriately omitted or not repeated.

[0215] A light emitting element 5 includes a substrate 10 including a top surface 100, a first side surface 101, a second side surface 102, a third side surface 103 and a fourth side surface 104. The first side surface 101 and the second side surface 102 of the substrate 10 are located at two opposite sides of the top surface 100 of the substrate 10, and the third side surface 103 and the fourth side surface 104 of the substrate 10 are located at the other two opposite sides of the top surface 100 of the substrate 10. The first side surface 101, the second side surface 102, the third side surface 103 and the fourth side surface 104 constitute an outer periphery of the substrate 10.

[0216] like Fig.16 As shown, from a top view of the light-emitting element 5, the substrate 10 of the light-emitting element 5 includes a plurality of corners and a plurality of sides, wherein any corner is formed by two adjacent sides. The plurality of corners includes a first corner C1, a second corner C2, a third corner C3, and a fourth corner C4. The plurality of sides includes a first side E1, a second side E2, a third side E3, and a fourth side E4.

[0217] An outer edge 205e of the semiconductor platform 205 includes a first outer edge 2051e adjacent to the first side E1; a second outer edge 2052e′ adjacent to the second side E2; a third outer edge 2053e adjacent to the third side E3; and a fourth outer edge 2054e adjacent to the fourth side E4.

[0218] In order to increase the light emitting area and light extraction efficiency of the light emitting element 5, the first outer edge 2051e adjacent to the first side E1 includes a plurality of concave platforms 2050 and a plurality of convex platforms 2051. The plurality of concave platforms 2050 and the plurality of convex platforms 2051 are arranged alternately with each other. The second outer edge 2052e' adjacent to the second side E2 includes a second plurality of concave platforms 20520 and a second plurality of convex platforms 20521. The second plurality of concave platforms 20520 and the second plurality of convex platforms 20521 are arranged alternately with each other. In the top view of the light emitting element 5, the first outer edge 2051e and the second outer edge 2052e' can be wavy, sawtooth or square wave-shaped.

[0219] From the top view of the self-luminous element 5 , the number of the plurality of concave platforms 2050 is greater than the number of the second plurality of concave platforms 20520 . The number of the plurality of convex platforms 2051 is greater than the number of the second plurality of convex platforms 20521 .

[0220] The third outer edge 2053e of the third side E3 near the first side E1 includes a plurality of concave platforms 2050 and a plurality of convex platforms 2051, wherein the plurality of concave platforms 2050 and the plurality of convex platforms 2051 are continuously and alternately arranged. In one embodiment, the contours of the plurality of concave platforms 2050 and the plurality of convex platforms 2051 of the third outer edge 2053e are the same as or different from the contours of the plurality of concave platforms 2050 and the plurality of convex platforms 2051 of the first outer edge 2051e.

[0221] The third outer edge 2053e of the third side E3 near the second side E2 includes a second plurality of concave platforms 20520 and a second plurality of convex platforms 20521, wherein the second plurality of concave platforms 20520 and the second plurality of convex platforms 20521 are continuously and alternately arranged. In one embodiment, the contours of the second plurality of concave platforms 20520 and the second plurality of convex platforms 20521 of the third outer edge 2053e are the same as or different from the contours of the second plurality of concave platforms 20520 and the second plurality of convex platforms 20521 of the second outer edge 2052e'. The plurality of concave platforms 2050 and the plurality of convex platforms 2051 continuously and alternately arranged and the second plurality of concave platforms 20520 and the second plurality of convex platforms 20521 continuously and alternately arranged constitute the contour of the third outer edge 2053e. In the top view of the light emitting element 5, the contour of the third outer edge 2053e may be wavy, sawtooth or square wave.

[0222] The fourth outer edge 2054e of the fourth side E4 near the first side E1 includes a plurality of concave platforms 2050 and a plurality of convex platforms 2051, wherein the plurality of concave platforms 2050 and the plurality of convex platforms 2051 are continuously and alternately arranged. In one embodiment, the contours of the plurality of concave platforms 2050 and the plurality of convex platforms 2051 of the fourth outer edge 2054e are the same as or different from the contours of the plurality of concave platforms 2050 and the plurality of convex platforms 2051 of the first outer edge 2051e.

[0223] The fourth outer edge 2054e of the fourth side E4 near the second side E2 includes a second plurality of concave platforms 20520 and a second plurality of convex platforms 20521, wherein the second plurality of concave platforms 20520 and the second plurality of convex platforms 20521 are continuously and alternately arranged. In one embodiment, the contours of the second plurality of concave platforms 20520 and the second plurality of convex platforms 20521 of the fourth outer edge 2054e are the same as or different from the contours of the second plurality of concave platforms 20520 and the second plurality of convex platforms 20521 of the second outer edge 2052e'. The plurality of concave platforms 2050 and the plurality of convex platforms 2051 continuously and alternately arranged and the second plurality of concave platforms 20520 and the second plurality of convex platforms 20521 continuously and alternately arranged constitute the contour of the fourth outer edge 2054e. In the top view of the light emitting element 5, the contour of the fourth outer edge 2054e may be wavy, sawtooth or square wave.

[0224] like Fig.16 As shown, a first distance D1 between one side of the convex platform 2051 of the first outer edge 2051e and the first side E1 is smaller than a second distance D2' between one side of the convex platform 20521 of the second outer edge 2052e and the second side E2.

[0225] From the top view of the self-luminous element 5, a spacing D0 is included between one side of the convex platform 2051 of the first outer edge 2051e and one side of the concave platform 2050. A spacing D0' is included between the second plurality of concave platforms 20520 and the second plurality of convex platforms 20521 of the second outer edge 2052e. In one embodiment of the present invention, the spacing D0 and the spacing D0' include the same distance. In another embodiment of the present invention, the spacing D0 and the spacing D0' include different distances.

[0226] The positions of the subsequent insulating layer openings, contact layers, or electrode layers can be determined by the configuration positions of the plurality of concave platforms 2050, the plurality of convex platforms 2051, the second plurality of concave platforms 20520, and the second plurality of convex platforms 20521. The light extraction efficiency of the light emitting element 5 can be improved by pattern design of the side surface of the semiconductor stack 20.

[0227] The recess 204 is located at the outermost side of the semiconductor stack 20 , wherein the recess 204 continuously or discontinuously surrounds the second semiconductor layer 202 and the active layer 203 of the semiconductor platform 205 by continuously or discontinuously exposing the surface of the outermost first semiconductor layer 201 of the semiconductor stack 20 .

[0228] The hole 200 is located inside the semiconductor stack 20 and is surrounded by the recess 204. In other words, the hole 200 is surrounded by the second semiconductor layer 202 and the active layer 203. From a top view of the self-luminous element 5, the shape of the hole 200 includes an ellipse, a circle, a rectangle or any other shape.

[0229] like Fig.17 As shown, the first semiconductor layer 201 near the first edge E1 includes a first sidewall 2011 connected to the upper surface 100 of the substrate 10, and is separated from the first side surface 101 of the substrate 10 by a primary spacing D' to expose the upper surface 100 of the substrate 10. The first semiconductor layer 201 near the second edge E2 includes a second sidewall 2012 inclined to the upper surface 100 of the substrate 10 and separated from the second side surface 102 of the substrate 10 by a spacing D to expose the upper surface 100 of the substrate 10. The secondary spacing D' is smaller than the spacing D.

[0230] like Fig.18 As shown, the first semiconductor layer 201 near the fourth side E4 includes a first sidewall 2011 connected to the upper surface 100 of the substrate 10 or directly connected to the fourth side surface 104 of the substrate 10. The first semiconductor layer 201 near the second side E2 includes a second sidewall 2012 inclined to the upper surface 100 of the substrate 10 and separated from the second side surface 102 of the substrate 10 by a distance D to expose the upper surface 100 of the substrate 10.

[0231] The spacing D is preferably greater than 5 μm and less than 50 μm, more preferably less than 30 μm. The upper surface 100 of the substrate 10 exposed by the spacing D is a rough surface. The rough surface can be a surface with an irregular shape or a surface with a regular shape, such as a hemispherical surface with multiple protrusions or depressions on the upper surface 100, a conical surface with multiple protrusions or depressions on the upper surface 100, or a polygonal cone surface with multiple protrusions or depressions on the upper surface 100.

[0232] The third side E3 and the fourth side E4 of the light emitting element 5 and the light emitting element 1 include substantially the same structure. The side surface structure of the first semiconductor layer 201 of the light emitting element 5 adjacent to the third side E3 includes a first side wall 2011 and a second side wall 2012, wherein the first side wall 2011 is directly connected to the third side surface 103 of the substrate 10, the second side wall 2012 is inclined to the upper surface 100 of the substrate 10 and is separated from the third side surface 103 of the substrate 10 by a distance D to expose the upper surface 100 of the substrate 10, and compared with the first side wall 2011, the second side wall 2012 is closer to the second side E2. The side surface structure of the first semiconductor layer 201 of the light-emitting element 5 adjacent to the fourth side E4 includes a first side wall 2011 and a second side wall 2012, wherein the first side wall 2011 is directly connected to the fourth side surface 104 of the substrate 10, and the second side wall 2012 is respectively inclined to the upper surface 100 of the substrate 10 and is separated from the fourth side surface 104 of the substrate 10 by a distance D to expose the upper surface 100 of the substrate 10, and compared with the first side wall 2011, the second side wall 2012 is closer to the second side E2.

[0233] like Figure 1 , Figure 2 , Figure 3 , Fig.17 and Fig.18 As shown, a first insulating layer 30 is formed on the semiconductor stack 20. A first insulating layer opening 300 is formed in the hole portion 200 by a selective etching method to expose the first semiconductor layer 201 in the hole portion 200, one or more first insulating layer first openings 301 are formed on the concave portion 204 adjacent to the first side E1 to expose the first semiconductor layer 201, one or more first insulating layer second openings 302 are formed on the concave portion 204 adjacent to the second side E2 to expose the first semiconductor layer 201 in the concave portion 204, and a first insulating layer third opening 303 is formed on the second semiconductor layer 202. The first insulating layer 30 near the first insulating layer opening 300 covers a portion of the second semiconductor layer 202 outside the hole portion 200 and the first inclined surface S1 in the hole portion 200. The first insulating layer 30 near the concave portion 204 covers a portion of the second semiconductor layer 202 outside the concave portion 204 and the second inclined surface S2 of the concave portion 204.

[0234] like Figure 1 and Figure 2 As shown, in order to expose the same area of ​​the first semiconductor layer 201 through the first insulating layer first opening 301 and the first insulating layer second opening 302 , the first insulating layer second opening 302 adjacent to the second side E2 includes a maximum length 302w greater than the maximum length 301w of the first insulating layer first opening 301 adjacent to the first side E1 .

[0235] The first insulating layer 30 may be formed of an insulating material having light transmittance. For example, the first insulating layer 30 includes SiOx.

[0236] In one embodiment, the thickness of the first insulating layer 30 may be 1000 angstroms to 20000 angstroms.

[0237] In one embodiment, the material of the first insulating layer 30 is SiO2, TiO2, SiNx, etc. If the thickness of the first insulating layer 30 is less than 1000 angstroms, the thinner thickness may weaken the insulating property of the first insulating layer 30. Figure 2 , Figure 3 , Figure 4 , Fig.17 and Fig.18 As shown, the first insulating layer 30 is formed on the etched first inclined surface S1 and the second inclined surface S2. The first insulating layer 30 formed in accordance with the inclined surface coverage also has a specific slope. If the thickness of the first insulating layer 30 is less than 1000 angstroms, the film may be cracked.

[0238] In one embodiment, the material of the first insulating layer 30 is selected from SiO2, TiO2, SiNx and the like. If the thickness of the first insulating layer 30 exceeds 20,000 angstroms, it will increase the difficulty of selective etching on the first insulating layer 30. However, the above embodiment does not exclude other materials with good coverage extension or materials with high selective etching to avoid the problem of the first insulating layer 30 being too thin or too thick.

[0239] like Figure 3 , Figure 3A , Figure 4 , Figure 5 , Fig.17 and Fig.18 As shown, the first insulating layer 30 has a side surface, which is a slope relative to the horizontal extension plane of the inner surface 200s or the outer surface 204s of the first semiconductor layer 201 exposed by selective etching, and the slope has an angle between 10 degrees and 70 degrees relative to the horizontal extension plane of the inner surface 200s or the surface 204s of the first semiconductor layer 201 exposed by selective etching.

[0240] If the bevel angle of the side surface of the first insulating layer 30 is less than 10 degrees, the substantial thickness of the first insulating layer 30 will be reduced. Therefore, there may be a problem that it is difficult to ensure the insulating property.

[0241] If the oblique angle of the side surface of the first insulating layer 30 is greater than 70 degrees, the subsequent insulating layer and the metal layer may not be fully covered, thereby causing the film layer to be broken.

[0242] In one embodiment of the present invention, the oblique angle of the side surface of the first insulating layer 30 is between 20 degrees and 75 degrees, preferably between 30 degrees and 65 degrees, and more preferably between 40 degrees and 55 degrees.

[0243] like Figure 3 , Figure 3A , Figure 4 , Figure 5 , Fig.17 and Fig.18 As shown, a contact electrode 40 is formed on the second semiconductor layer 202. In other words, the contact electrode 40 is formed in the third opening 303 of the first insulating layer. The contact electrode 40 includes a transparent electrode. The material of the transparent electrode includes a light-transmitting conductive oxide or a light-transmitting metal. The light-transmitting conductive oxide includes indium tin oxide (ITO), zinc oxide (ZnO), zinc indium tin oxide (ZITO), zinc indium oxide (ZIO), zinc tin oxide (ZTO), gallium indium tin oxide (GITO), gallium indium oxide (GIO), or gallium zinc oxide (GZO). The light-transmitting conductive oxide may include various dopants, such as aluminum doped zinc oxide (AZO) or fluorine doped tin oxide (FTO). The light-transmitting metal includes nickel (Ni) or gold (Au).

[0244] The thickness of the contact electrode 40 is not limited, but may have a thickness of about 0.1 nm to 1000 nm. In one embodiment, the material of the contact electrode 40 is a light-transmitting conductive oxide. If the thickness of the contact electrode 40 is less than 0.1 nm, it cannot effectively form an ohmic contact with the second semiconductor layer 202 due to the thickness being too thin. In addition, if the thickness of the contact electrode 40 is greater than 200 nm, the light emitted by the active layer 203 is partially absorbed due to the thickness being too thick, thereby causing the problem of reduced brightness of the light-emitting element 1. Since the contact electrode 40 has a thickness within the above range, the current can be smoothly dispersed in the horizontal direction to improve the electrical performance of the light-emitting element 1. However, the above embodiments do not exclude other materials with lateral current diffusion.

[0245] like Figure 2 , Figure 3 , Figure 3A , Fig.17 and Fig.18As shown, the contact electrode 40 is formed on substantially the entire surface of the second semiconductor layer 202 and forms a low resistance contact, such as an ohmic contact, with the second semiconductor layer 202, so that the current can be uniformly diffused through the second semiconductor layer 202 through the contact electrode 40. In one embodiment, from the cross-sectional view of the self-luminous element 1, the contact electrode 40 includes an outermost side, which is spaced from the second inclined surface S2 of the recess 204 by a horizontal distance of less than 20 μm, preferably less than 10 μm, and more preferably less than 5 μm.

[0246] like Figure 2 , Figure 3 , Figure 3A , Fig.17 and Fig.18 As shown, a reflective layer 50 is formed on the contact electrode 40. The material of the reflective layer 50 includes metals such as aluminum (Al), silver (Ag), rhodium (Rh) or platinum (Pt) or alloys of the above materials. The reflective layer 50 is used to reflect light and make the reflected light emitted toward the substrate 10, wherein the reflected light is generated by the active layer 203.

[0247] In another embodiment, the step of forming the contact electrode 40 may be omitted. A reflective layer 50 is formed in the third opening 303 of the first insulating layer. The reflective layer 50 may form an ohmic contact with the second semiconductor layer 202 .

[0248] In one embodiment, the cross-sectional view of the self-luminous element is as follows: Figure 3 , Figure 3A , Figure 4 , Figure 5 , Fig.17 and Fig.18 As shown, the reflective layer 50 includes an outermost side, which is spaced apart from the second inclined surface S2 of the concave portion 204 by a horizontal distance less than 20 μm, preferably less than 10 μm, and more preferably less than 5 μm.

[0249] In one embodiment, the reflective layer 50 may be a one-layer or multi-layer structure, such as a Bragg reflection structure.

[0250] In one embodiment, the side surface of the reflective layer 50 is a slope relative to the upper surface of the second semiconductor layer 202, and the slope may have a slope angle of 10 to 60 degrees relative to the surface of the second semiconductor layer 202. The material of the reflective layer 50 is silver (Ag). If the slope angle of the reflective layer 50 is less than 10 degrees, the very gentle slope will reduce the reflection efficiency of the bottom light. In addition, it is difficult to ensure thickness uniformity at a slope angle less than 10 degrees. If the slope angle of the reflective layer 50 is greater than 60 degrees, the slope angle greater than 60 degrees may cause subsequent film layers to break. However, the above embodiments do not exclude other materials with high reflectivity.

[0251] The tilt angle of the reflective layer 50 can be adjusted by changing the configuration of the substrate and the advancing direction of the metal atoms in the thermal deposition process, for example, by adjusting the position of the substrate so that the surface of the substrate is an inclined surface relative to the deposition direction of evaporation or sputtering.

[0252] In one embodiment, a barrier layer (not shown) is formed on the reflective layer 50 to cover the upper surface and the side surface of the reflective layer 50 to prevent the surface of the reflective layer 50 from being oxidized, thereby deteriorating the reflectivity of the reflective layer 50. The material of the barrier layer includes a metal material, such as titanium (Ti), tungsten (W), aluminum (Al), indium (In), tin (Sn), nickel (Ni), chromium (Cr), platinum (Pt) and other metals or alloys of the above materials. The barrier layer can be a one or more multi-layer structure, and the multi-layer structure is, for example, titanium (Ti) / aluminum (Al), and / or nickel-titanium alloy (NiTi) / titanium-tungsten alloy (TiW). In one embodiment of the present invention, the barrier layer includes a stacked structure of titanium (Ti) / aluminum (Al) and a stacked structure of nickel-titanium alloy (NiTi) / titanium-tungsten alloy (TiW), wherein the stacked structure of titanium (Ti) / aluminum (Al) is located on a side away from the reflective layer 50, and the stacked structure of nickel-titanium alloy (NiTi) / titanium-tungsten alloy (TiW) is located on a side close to the reflective layer 50. In one embodiment of the present invention, the materials of the reflective layer 50 and the barrier layer preferably include metal materials other than gold (Au) or copper (Cu).

[0253] The stacked structure of the barrier layer is selected from nickel-titanium alloy (NiTi) / titanium-tungsten alloy (TiW) / platinum (Pt) / titanium (Ti) / aluminum (Al) / titanium (Ti) / aluminum (Al) / chromium (Cr) / platinum (Pt), and the barrier layer may have an oblique angle of 10 to 60 degrees relative to the surface of the second semiconductor layer 202. In one embodiment, if the oblique angle of the barrier layer is less than 10 degrees, the very gentle slope cannot completely cover the reflective layer 50. In addition, it is difficult to ensure thickness uniformity with an oblique angle less than 10 degrees. If the oblique angle of the barrier layer is greater than 60 degrees, the oblique angle greater than 60 degrees may cause subsequent film layers to crack.

[0254] In one embodiment, the thickness of the reflective layer 50 or the barrier layer is preferably 100 nm to 1 μm. If the thickness of the reflective layer 50 or the barrier layer is less than 100 nm, it cannot effectively reflect the light emitted by the active layer 203. Moreover, if the thickness of the reflective layer 50 or the barrier layer is greater than 1 μm, excessive production time will result in manufacturing losses.

[0255] In order to cover the upper surface and the side surface of the reflective layer 50 , the barrier layer includes a bottom surface to contact the second semiconductor layer 202 and / or the contact electrode 40 .

[0256] like Figure 2 , Figure 3 , Figure 3A, Figure 4 , Fig.17 and Fig.18 As shown, a second insulating layer 60 is formed on the semiconductor stack 20, and a second insulating layer opening 600 is formed in the hole 200 by a selective etching method to expose the first semiconductor layer 201 in the hole 200, a plurality of second insulating layer first openings 601 are formed on the concave portion 204 adjacent to the first side E1 to expose the first semiconductor layer 201, a plurality of second insulating layer second openings 602 are formed on the concave portion 204 adjacent to the second side E2 to expose a portion of the substrate 10 and the first semiconductor layer 201 in the concave portion 204, and a second insulating layer third opening 603 is formed on the second semiconductor layer 202 to expose a portion of the second semiconductor layer 202, the reflective layer 50 and / or the barrier layer. The remaining area is shielded by the second insulating layer 60.

[0257] like Figure 1 and Figure 2 As shown, in order to expose the same area of ​​the first semiconductor layer 201 in the second insulating layer first opening 601 and the second insulating layer second opening 602 , the second insulating layer second opening 602 adjacent to the second side E2 includes a maximum length 602w greater than the maximum length 601w of the second insulating layer first opening 601 adjacent to the first side E1 .

[0258] The second insulating layer 60 may be formed of an insulating material having light transmittance. For example, the second insulating layer 60 includes SiOx.

[0259] In one embodiment, the thickness of the second insulating layer 60 may be 1000 angstroms to 60000 angstroms.

[0260] In one embodiment, the material of the second insulating layer 60 is selected from SiO2, TiO2, SiNx and the like. If the thickness of the second insulating layer 60 is less than 1000 angstroms, the thinner thickness may weaken the insulating property of the second insulating layer 60. Specifically, the second insulating layer 60 is formed on the etched first inclined surface S1 and the second inclined surface S2. The second insulating layer 60 formed in accordance with the inclined surface coverage also has a specific slope. If the thickness of the second insulating layer 60 is less than 1000 angstroms, the film may be cracked.

[0261] In one embodiment, the material of the second insulating layer 60 is selected from SiO2, TiO2, SiNx and the like. If the thickness of the second insulating layer 60 exceeds 60,000 angstroms, it will increase the difficulty of selective etching on the second insulating layer 60. However, the above embodiment does not exclude other materials with good coverage extension or materials with high selective etching to avoid the problem of the second insulating layer 60 being too thin or too thick.

[0262] like Figure 3 , Figure 3A, Figure 4 , Figure 5 , Fig.17 and Fig.18 As shown, the second insulating layer 60 has a side surface, which is a slope relative to the horizontal extension plane of the inner surface 200s or the outer surface 204s of the first semiconductor layer 201 exposed by selective etching, and the slope has an angle between 10 degrees and 70 degrees relative to the horizontal extension plane of the inner surface 200s or the surface 204s of the first semiconductor layer 201 exposed by selective etching.

[0263] If the bevel angle of the side surface of the second insulating layer 60 is less than 10 degrees, the substantial thickness of the second insulating layer 60 will be reduced. Therefore, there may be a problem that it is difficult to ensure the insulating property.

[0264] If the oblique angle of the side surface of the second insulating layer 60 is greater than 70 degrees, the subsequent insulating layer and metal layer may not be fully covered, thereby causing film cracks.

[0265] In one embodiment of the present invention, the oblique angle of the side surface of the second insulating layer 60 is between 20 degrees and 75 degrees, preferably between 30 degrees and 65 degrees, and more preferably between 40 degrees and 55 degrees.

[0266] The formation positions of the second insulation layer opening 600, the second insulation layer first opening 601, the second insulation layer second opening 602 and the second insulation layer third opening 603 of the second insulation layer 60 correspond to the first insulation layer opening 300, the first insulation layer first opening 301, the first insulation layer second opening 302 and the first insulation layer third opening 303 of the first insulation layer 30 respectively.

[0267] like Figure 2 , Figure 3 , Figure 3A , Figure 4 , Fig.17 and Fig.18 As shown, the lower electrode 71 is formed on the second insulating layer 60 and extends into one or more second insulating layer openings 600, directly contacts the first semiconductor layer 201 in the hole 200, and forms an electrical connection with the first semiconductor layer 201 of the light emitting element 1. The lower electrode 71 extends from the semiconductor platform 205 along the first inclined surface S1 to cover the first semiconductor layer 201 in the hole 200. Figure 4 and Figure 5 As shown, the lower electrode 71 extends from the semiconductor platform 205, covers the first opening 601 of the second insulating layer adjacent to the first edge E1 and the second opening 602 of the second insulating layer adjacent to the second edge E2, and directly contacts the first semiconductor layer 201 located in the recess 204, so that the current can be evenly diffused at the outer edge of the light-emitting element 1.

[0268] like Figure 1 , Figure 2 , Figure 4 and Fig.16 As shown, a plurality of concave platforms 2050 and a plurality of convex platforms 2051 are arranged alternately, and a concave platform 2050 between two discontinuous convex platforms 2051 exposes the first semiconductor layer 201. The lower electrode 71 covers the plurality of convex platforms 2051 and covers the outer surface 204s of the first semiconductor layer 201 exposed in the concave portion 204 along the second inclined surface S2.

[0269] In order to make the current spread evenly at the outer edge of the light emitting element 1, Figure 1 , Figure 2 and Figure 4 As shown, a plurality of second insulating layer first openings 601 are arranged at fixed intervals. The distance d1 between two adjacent second insulating layer first openings 601 may be greater than n times the width w1 of the second insulating layer first opening 601, d1=(1+n)w1, where n may be an integer or a non-integer. For example, greater than 0.5 times, preferably greater than one times, and more preferably greater than two times.

[0270] like Figure 5 As shown, the plurality of second insulating layer second openings 602 discontinuously expose the outer surface 204s of the first semiconductor layer 201. The lower electrode 71 covers the first insulating layer 30 and the second insulating layer 60, and is electrically connected to the first semiconductor layer 201 through the plurality of first insulating layer second openings 302 and the plurality of second insulating layer second openings 602.

[0271] In order to make the current spread evenly at the outer edge of the light emitting element 1, Figure 4 As shown, a plurality of second insulating layer second openings 602 are arranged at fixed intervals. The distance d2 between two adjacent second insulating layer second openings 602 may be greater than n times the width w2 of the second insulating layer second opening 602, d2=(1+n)w2, where n may be an integer or a non-integer. For example, greater than 0.5 times, preferably greater than one times, and more preferably greater than two times.

[0272] like Figure 1 As shown, in order to allow the current to spread evenly at the outer edge of the light-emitting element 1, in one embodiment of the present invention, the distance d1 between two adjacent second insulating layer first openings 601 adjacent to the first side E1 is substantially the same as the distance d2 between two adjacent second insulating layer second openings 602 adjacent to the second side E2.

[0273] like Figure 1As shown, in order to allow the current to spread evenly at the outer edge of the light-emitting element 1, in one embodiment of the present invention, the width w1 of the first opening 601 of the second insulating layer adjacent to the first side E1 is substantially the same as the width w2 of the second opening 602 of the second insulating layer adjacent to the second side E2.

[0274] like Figure 3 , Figure 3A As shown, the upper electrode 72 is formed in the third opening 603 of the second insulating layer. The upper electrode 72 contacts and is electrically connected to the second semiconductor layer 202, the reflective layer 50 and / or the barrier layer. The second insulating layer 60 is located between the lower electrode 71 and the upper electrode 72 to prevent the lower electrode 71 and the upper electrode 72 from contacting and forming a short circuit.

[0275] like Figure 1 and Figure 2 As shown, from the top view of the light-emitting element 1 , the upper electrode 72 includes an area smaller than the lower electrode 71 , and is surrounded by the lower electrode 71 .

[0276] The lower electrode 71 and the upper electrode 72 include metal materials, such as chromium (Cr), titanium (Ti), tungsten (W), gold (Au), aluminum (Al), indium (In), tin (Sn), nickel (Ni) or platinum (Pt) or alloys thereof. The lower electrode 71 and the upper electrode 72 may be composed of a single layer or multiple layers. For example, the lower electrode 71 or the upper electrode 72 may include a Ti / Au layer, a Ti / Pt / Au layer, a Cr / Au layer, a Cr / Pt / Au layer, a Ni / Au layer, a Ni / Pt / Au layer or a Cr / Al / Cr / Ni / Au layer.

[0277] In one embodiment, the thickness of the lower electrode 71 or the upper electrode 72 is preferably 0.5 μm to 2.5 μm.

[0278] In one embodiment, if Figure 3 , Figure 3A , Fig.17 and Fig.18 As shown, the upper electrode 72 includes a top surface 72s lower than a top surface 71s of the lower electrode 71. In other words, there is a step difference between the top surface 72s of the upper electrode 72 and the top surface 71s of the lower electrode 71, wherein the step difference is between 2000 angstroms and 60000 angstroms.

[0279] In one embodiment, the step difference between the top surface 72 s of the upper electrode 72 and the top surface 71 s of the lower electrode 71 is substantially the same as the thickness of the second insulating layer 60 .

[0280] In one embodiment, the step difference between the top surface 72 s of the upper electrode 72 and the top surface 71 s of the lower electrode 71 and the thickness of the second insulating layer 60 have a deviation of ±30%.

[0281] In one embodiment, if Figure 3 , Figure 3A , Fig.17 and Fig.18 As shown, the step difference between the top surface 71s of the lower electrode 71 and the top surface 72s of the upper electrode 72 is less than 2000 angstroms, preferably less than 1000 angstroms, and more preferably less than 500 angstroms.

[0282] In one embodiment (not shown), a metal pad is provided under the lower electrode, and the thickness of the metal pad has a deviation of ±30% from the thickness of the second insulating layer 60, so that the top surface 71s of the lower electrode 71 and the top surface 72s of the upper electrode 72 are substantially flush.

[0283] like Figure 2 , Figure 3 , Figure 3A , Fig.17 and Fig.18 As shown, a third insulating layer 80 is formed on the semiconductor stack 20. A third insulating layer first opening 801 is formed on the lower electrode 71 by a selective etching method to expose the top surface 71s of the lower electrode 71. In addition, a third insulating layer second opening 802 is formed on the upper electrode 72 to expose the top surface 72s of the upper electrode 72.

[0284] The third insulating layer 80 may be formed of an insulating material having light transmittance. For example, the third insulating layer 80 includes SiOx.

[0285] In one embodiment, the material of the third insulating layer 80 is selected from materials such as SiO2, TiO2, SiNx, etc., and the thickness of the third insulating layer 80 may be 10,000 angstroms to 60,000 angstroms. If the thickness of the third insulating layer 80 is less than 10,000 angstroms, the thinner thickness may weaken the insulation properties and moisture resistance of the third insulating layer 80. In another embodiment, the material of the third insulating layer 80 is selected from materials such as SiO2, TiO2, SiNx, etc., and if the thickness of the third insulating layer 80 exceeds 60,000 angstroms, it will increase the difficulty of selective etching on the third insulating layer 80. However, the above embodiment does not exclude that other materials with good coverage extension or materials with high selective etching can avoid the problem of the third insulating layer 80 being too thin or too thick.

[0286] The first insulating layer 30, the second insulating layer 60 or the third insulating layer 80 can be formed by alternately stacking two or more materials with different refractive indices to form a Bragg reflector (DBR) structure. The first insulating layer 30, the second insulating layer 60 or the third insulating layer 80 can be stacked with layers such as SiO2 / TiO2 or SiO2 / Nb2O5 to selectively reflect light of a specific wavelength, thereby increasing the light extraction efficiency of the light emitting element 1. When the peak emission wavelength of the light emitting element 1 is λ, the optical thickness of the first insulating layer 30, the second insulating layer 60 or the third insulating layer 80 can be set to an integer multiple of λ / 4. The peak wavelength refers to the wavelength with the strongest intensity in the emission spectrum of the light emitting element 1. Based on the integer multiple of the optical thickness λ / 4, the thickness of the first insulating layer 30, the second insulating layer 60 or the third insulating layer 80 can have a deviation of ±30%.

[0287] The first insulating layer 30, the second insulating layer 60 or the third insulating layer 80 is formed of a non-conductive material, including an organic material, such as Su8, benzocyclobutene (BCB), perfluorocyclobutane (PFCB), epoxy resin, acrylic resin, cycloolefin polymer (COC), polymethyl methacrylate (PMMA), polyethylene terephthalate (PET), polycarbonate (PC), polyetherimide or fluorocarbon polymer, or an inorganic material, such as silicone or glass, or a dielectric material, such as aluminum oxide (Al2O3), silicon nitride (SiNx), silicon oxide (SiOx), titanium oxide (TiOx), or magnesium fluoride (MgFx).

[0288] like Figure 1 , Figure 3 , Figure 3A , Fig.17 and Fig.18 As shown, the light emitting element 1 includes a first electrode pad 91 to cover the first opening 801 of the third insulating layer and contact the lower electrode 71. The first electrode pad 91 is electrically connected to the first semiconductor layer 201 through the lower electrode 71. The light emitting element 1 includes a second electrode pad 92 to cover the second opening 802 of the third insulating layer and contact the upper electrode 72 to be electrically connected to the reflective layer 50, the contact electrode 40 and the second semiconductor layer 202.

[0289] In one embodiment, if Figure 3As shown, the first sidewall 2011 of the first semiconductor layer 201 near the fourth side E4 is not covered by the third insulating layer 80 , so that the first sidewall 2011 near the fourth side E4 is exposed. The second sidewall 2012 of the first semiconductor layer 201 near the second side E2 is covered by the third insulating layer 80 .

[0290] In one embodiment, if Figure 3A As shown, the first side wall 2011 of the first semiconductor layer 201 close to the first edge E1 is covered by the third insulating layer 80 , and the second side wall 2012 of the first semiconductor layer 201 close to the second edge E2 is covered by the third insulating layer 80 .

[0291] In one embodiment, if Figure 3A As shown, the third insulating layer 80 includes a first side surface of the third insulating layer and a second side surface of the third insulating layer. The first side surface of the third insulating layer is directly connected to the first side surface 101 of the substrate 10.

[0292] In one embodiment (not shown), the first side surface of the third insulating layer 80 is directly connected to the first side surface 101 of the substrate 10. From the cross-sectional view of the self-luminous element 1, the second side surface of the third insulating layer is located between the second side surface 102 of the substrate 10 and the second side wall 2012 of the first semiconductor layer 201, and is separated from the second side surface 102 of the substrate 10 by a distance to expose the upper surface 100 of the substrate 10.

[0293] From the top view of the self-luminous element 1, Figure 1 As shown, the first electrode pad 91 includes an upper surface area smaller than an upper surface area of ​​the lower electrode 71 . The second electrode pad 92 includes an upper surface area smaller than an upper surface area of ​​the upper electrode 72 .

[0294] The first electrode pad 91 and the second electrode pad 92 include metal materials, such as chromium (Cr), titanium (Ti), tungsten (W), gold (Au), aluminum (Al), indium (In), tin (Sn), nickel (Ni), platinum (Pt), etc., or alloys of the above materials. The first electrode pad 91 and the second electrode pad 92 may be composed of a single layer or multiple layers. For example, the first electrode pad 91 and the second electrode pad 92 may include a Ti / Au layer, a Ti / Pt / Au layer, a Cr / Au layer, a Cr / Pt / Au layer, a Ni / Au layer, a Ni / Pt / Au layer, or a Cr / Al / Cr / Ni / Au layer.

[0295] In one embodiment of the present invention, the first electrode pad 91 includes a size that is the same as or different from a size of the second electrode pad 92. The size may be a width or an area. For example, the top view area of ​​the first electrode pad 91 or the second electrode pad 92 may be greater than 0.8 times and less than 1 times the value obtained by adding the top view areas of the first electrode pad 91 and the second electrode pad 92.

[0296] The first electrode pad 91 or the second electrode pad 92 includes an inclined side surface, so the cross-sectional area of ​​the first electrode pad 91 or the second electrode pad 92 in the side view can change along the thickness direction. For example, the cross-sectional area of ​​the first electrode pad 91 or the second electrode pad 92 in the side view can gradually decrease as it moves away from the upper surface of the semiconductor stack 20.

[0297] The first electrode pad 91 or the second electrode pad 92 has a thickness between 1 and 100 μm, preferably between 1.5 and 6 μm.

[0298] There is a gap between the first electrode pad 91 and the second electrode pad 92, and the gap includes a shortest distance of about 10 μm or more and a longest distance of about 250 μm or less. Within the above range, by reducing the gap between the first electrode pad 91 and the second electrode pad 92, the upper viewing area of ​​the first electrode pad 91 and the second electrode pad 92 can be increased, thereby improving the heat dissipation efficiency of the light-emitting element 1 and avoiding a short circuit between the first electrode pad 91 and the second electrode pad 92.

[0299] Fig. 6A for Figure 1 A partially enlarged upper view of a portion of X1. Figure 6B For along Fig. 6A Sectional view of the tangent line X1'-X1". Figure 6C for Figure 1 A partially enlarged upper view of a portion of X2. Fig.6D For along Figure 6C Sectional view of the tangent line X2'-X2".

[0300] In one embodiment of the present invention, Figure 1 As shown, from the top view of the light emitting element 1, the light emitting element 1 includes a plurality of corners, wherein the plurality of corners include a first corner C1, a second corner C2, a third corner C3, and a fourth corner C4. The light emitting element 1 includes a plurality of semiconductor structures 206, wherein the plurality of semiconductor structures 206 include a first semiconductor structure 2061, a second semiconductor structure 2062, a third semiconductor structure 2063, and a fourth semiconductor structure 2064. The first semiconductor structure 2061, the second semiconductor structure 2062, the third semiconductor structure 2063, and the fourth semiconductor structure 2064 are located at the first corner C1, the second corner C2, the third corner C3, and the fourth corner C4, respectively.

[0301] In another embodiment of the present invention (not shown), the light emitting element 1 includes a plurality of edges, wherein the plurality of edges include a first edge E1, a second edge E2, a third edge E3 and a fourth edge E4. A plurality of semiconductor structures 206 may be respectively located on the plurality of edges.

[0302] like Figure 1 and Figure 6A to Figure 6D As shown, the plurality of semiconductor structures 206 are respectively separated from the semiconductor platform 205 by a distance, and the plurality of semiconductor structures 206 are separated from each other.

[0303] like Figure 1 and Figure 6A~Figure 6B As shown, the first semiconductor structure 2061 adjacent to the first side E1 is separated from the semiconductor platform 205 by a first shortest distance L1, and the fourth semiconductor structure 2064 adjacent to the first side E1 is separated from the semiconductor platform 205 by a fourth shortest distance L4 (not shown). Figure 1 and Figure 6C~Figure 6D As shown, the second semiconductor structure 2062 adjacent to the second side E2 is separated from the semiconductor platform 205 by a second shortest distance L2, and the third semiconductor structure 2063 adjacent to the second side E2 is separated from the semiconductor platform 205 by a third shortest distance L3 (not shown).

[0304] In one embodiment of the present invention, the second shortest distance L2 and the third shortest distance L3 are respectively greater than the first shortest distance L1.

[0305] In one embodiment of the present invention, the second shortest distance L2 and the third shortest distance L3 are substantially the same.

[0306] In one embodiment of the present invention, the second shortest distance L2 and the third shortest distance L3 have a deviation of ±30%.

[0307] In one embodiment of the present invention, as an identification point of the light emitting element 1, the first shortest distance L1 and the fourth shortest distance L4 are different. The fourth shortest distance L4 is respectively greater than the first shortest distance L1, the second shortest distance L2 and / or the third shortest distance L3.

[0308] like Figure 6B As shown, near the first corner C1, the first semiconductor layer 201 is located between the first semiconductor structure 2061 and the semiconductor platform 205, and connects the first semiconductor structure 2061 and the semiconductor platform 205. Near the fourth corner C4, the first semiconductor layer 201 is located between the fourth semiconductor structure 2064 and the semiconductor platform 205, and connects the first semiconductor structure 2061 and the semiconductor platform 205 (not shown). Fig.6D As shown, adjacent to the second corner C2, the first semiconductor layer 201 between the second semiconductor structure 2062 and the semiconductor platform 205 is removed to expose the substrate 10, and the second semiconductor structure 2062 and the semiconductor platform 205 are separated from each other. Adjacent to the third corner C3, the first semiconductor layer 201 between the third semiconductor structure 2063 and the semiconductor platform 205 is removed to expose the substrate 10, and the third semiconductor structure 2063 and the semiconductor platform 205 are separated from each other (not shown).

[0309] In one embodiment of the present invention, from the top view of the light-emitting device 1 , the first semiconductor structure 2061 , the second semiconductor structure 2062 , the third semiconductor structure 2063 and the fourth semiconductor structure 2064 include a shape, such as a rectangle, a triangle or a fan.

[0310] The light emitting element 2 has substantially the same structure as the light emitting element 1, so Figure 7 to Figure 12 The light emitting element 2 and Figure 1~Figure 6D The light-emitting elements 1 have the same names and numbers, represent the same structure, have the same materials, or have the same functions, and the description thereof will be appropriately omitted or not repeated.

[0311] Figure 7 It is a top view of a light emitting element 2 disclosed in an embodiment of the present invention. Figure 8 FIG. 1 is a flowchart of manufacturing a light emitting element 2 according to an embodiment of the present invention. Fig. 9 For along Figure 7 Sectional view of the tangent line D-D'. Fig.9A For along Figure 7 Cross-sectional view of the tangent line H-H'. Fig.10 For along Figure 7 Sectional view of the tangent line E-E'. Fig.11 For along Figure 7 Sectional view of the tangent line F-F'. Fig.12 For along Figure 7 Sectional view of the tangent line G-G'.

[0312] like Figure 7 , Figure 8 , Fig. 9 , Fig.9A and Fig.10 As shown, a light emitting element 2 includes a substrate 10 ; and a first light emitting unit 2a and a second light emitting unit 2b are located on the substrate 10 , wherein the first light emitting unit 2a and the second light emitting unit 2b are separated by a groove 11 , and the groove 11 exposes the upper surface 100 of the substrate 10 .

[0313] like Figure 7 , Figure 8 , Fig. 9 , Fig.9A and Fig.10 As shown, the substrate 10 includes a first side surface 101 and a second side surface 102, wherein the first side surface 101 and the second side surface 102 of the substrate 10 are respectively connected to two opposite sides of the upper surface 100 of the substrate 10. Figure 7As shown, the substrate 10 further includes a third side surface 103 and a fourth side surface 104, wherein the third side surface 103 and the fourth side surface 104 of the substrate 10 are respectively connected to the other two opposite sides of the upper surface 100 of the substrate 10. The first side surface 101, the second side surface 102, the third side surface 103 and the fourth side surface 104 constitute an outer periphery of the substrate 10.

[0314] like Figure 7 As shown, the third side surface 103 of the substrate 10 includes a first end 1031 of the third side surface and a second end 1032 of the third side surface. The fourth side surface 104 of the substrate 10 includes a first end 1041 of the fourth side surface and a second end 1042 of the fourth side surface. The first end 1031 of the third side surface and the first end 1041 of the fourth side surface are located on both sides of the first light-emitting unit 2a. The second end 1032 of the third side surface and the second end 1042 of the fourth side surface are located on both sides of the second light-emitting unit 2b.

[0315] The first light emitting unit 2a and the second light emitting unit 2b are located on the upper surface 100 of the substrate 10 and each includes a semiconductor stack 20. The semiconductor stack 20 includes a first semiconductor layer 201, a second semiconductor layer 202, and an active layer 203 located between the first semiconductor layer 201 and the second semiconductor layer 202.

[0316] like Figure 8 , Fig. 9 , Fig.9A and Fig.10 As shown, selective etching is performed on the semiconductor stack 20 of the first light-emitting unit 2a to form a first recess 204a and a first semiconductor platform 205a. Selective etching is performed on the semiconductor stack 20 of the second light-emitting unit 2b to form a second recess 204b and a second semiconductor platform 205b. For example, a photoresist is applied and then a portion of the photoresist is removed through an existing patterning process to form a photoresist pattern of the recess and the semiconductor platform. The photoresist pattern is then used as an etching mask to perform an etching process to form the recess and the semiconductor platform. Specifically, the semiconductor platform is formed by removing a portion of the second semiconductor layer 202 and the active layer 203 to form a structure including the first semiconductor layer 201, the second semiconductor layer 202 and the active layer 203. The first recess 204a and the second recess 204b are formed by removing a portion of the second semiconductor layer 202 and the active layer 203 to expose the outer surface 204as and the outer surface 204bs of the first semiconductor layer 201. The remaining photoresist pattern is removed after the etching process.

[0317] like Fig. 9 and Fig.9AAs shown, the first concave portion 204a and the second concave portion 204b respectively include a second inclined surface S2, which has an inclined angle within a range, for example, an angle of 10 to 80 degrees relative to the outer surface 204as, 204bs of the first semiconductor layer 201. If the angle is less than 10 degrees, the too low slope will reduce the area of ​​the active layer 203, and the reduction in the area of ​​the active layer 203 will cause the brightness of the light-emitting element 2 to decrease. If the angle is greater than 80 degrees, the subsequent insulating layer and metal layer may not be able to completely cover the sidewalls of the first semiconductor layer 201, the second semiconductor layer 202, and / or the active layer 203, thereby causing the film layer to break.

[0318] like Figure 7 As shown, from a top view of the light-emitting element 2, the light-emitting element 2 includes a first side E1, a second side E2, a third side E3 and a fourth side E4. The first semiconductor platform 205a adjacent to the first side E1 includes a first outer edge 2051e, and the second semiconductor platform 205b adjacent to the second side E2 includes a second outer edge 2052e. In order to increase the light-emitting area of ​​the light-emitting element 2, compared with the second outer edge 2052e of the second semiconductor platform 205b adjacent to the second side E2, the first outer edge 2051e of the first semiconductor platform 205a adjacent to the first side E1 includes a plurality of concave platforms 2050 and a plurality of convex platforms 2051 arranged alternately with each other. A first spacing D1 between one side of the convex platform 2051 and the first side E1 is smaller than a second spacing D2 between the second outer edge 2052e and the second side E2. The contours of the plurality of concave platforms 2050 and the plurality of convex platforms 2051 constitute the first outer edge 2051e. In the top view of the light emitting element 2, the first outer edge 2051e can be wavy, sawtooth or square. The positions of the subsequent insulating layer openings, contact layers or electrode layers can be determined according to the configuration positions of the multiple concave platforms 2050 and the multiple convex platforms 2051.

[0319] In one embodiment, the first outer edge 2051e of the first semiconductor platform 205a adjacent to the first end 1031 of the third side surface and the first outer edge 2051e of the first semiconductor platform 205a adjacent to the first end 1041 of the fourth side surface include a plurality of concave platforms 2050 and a plurality of convex platforms 2051, wherein the plurality of concave platforms 2050 and the plurality of convex platforms 2051 are continuously and alternately arranged. In one embodiment, the contours of the plurality of concave platforms 2050 and the plurality of convex platforms 2051 of the first outer edge 2051e of the first semiconductor platform 205a adjacent to each side surface are the same or different.

[0320] In another embodiment of the present invention (not shown), the second outer edge 2052e of the second semiconductor platform 205b adjacent to the second side E2 may be wavy, sawtooth or square-shaped.

[0321] like Figure 7 As shown, the first corner 2051C of the first semiconductor platform 205a and the second corner 2052C of the second semiconductor platform 205b may be rounded to prevent the current from being locally concentrated at the corners of the light emitting element 2 .

[0322] like Figure 8 As shown, the first recess 204a is located at the outermost side of the semiconductor stack 20 of the first light-emitting unit 2a, and the second recess 204b is located at the outermost side of the semiconductor stack 20 of the second light-emitting unit 2b. The first recess 204a and the second recess 204b continuously or discontinuously surround the second semiconductor layer 202 and the active layer 203 of the semiconductor platform 205 by continuously or discontinuously exposing the surface of the outermost first semiconductor layer 201 of the semiconductor stack 20, wherein the substrate 10 of the second light-emitting unit 2b is exposed to surround the outermost first semiconductor layer 201 of the second light-emitting unit 2b.

[0323] In one embodiment, the first light-emitting unit 2a includes only one first recess 204a to continuously surround the first semiconductor platform 205a, and the second light-emitting unit 2b includes only one second recess 204b to continuously surround the second semiconductor platform 205b. The shapes of the first recess 204a and the second recess 204b include rectangular rings and are located at the outermost sides of the first light-emitting unit 2a and the second light-emitting unit 2b, respectively, wherein the corners of the rectangles can be rounded to avoid the current being locally concentrated at the corners of each light-emitting unit.

[0324] like Figure 7 and Fig. 9 As shown, the first semiconductor layer 201 of the first light emitting unit 2a at the first end 1031 close to the third side surface of the substrate 10 includes a first side wall 2011 connected to the upper surface 100 of the substrate 10 or directly connected to the third side surface 103 of the substrate 10. The first semiconductor layer 201 of the second light emitting unit 2b at the second end 1032 close to the third side surface of the substrate 10 includes a second side wall 2012 inclined to the upper surface 100 of the substrate 10 and spaced apart from the third side surface 103 of the substrate 10 by a distance D so as to expose the upper surface 100 of the substrate 10.

[0325] Fig.9A For along Figure 7 The cross-sectional view of the tangent line H-H'. Fig.9AAs shown, the first semiconductor layer 201 of the first light-emitting unit 2a near the first side E1 includes a first side wall 2011 connected to the upper surface 100 of the substrate 10, and is separated from the first side surface 101 of the substrate 10 by a primary spacing D' to expose the upper surface 100 of the substrate 10. The first semiconductor layer 201 of the second light-emitting unit 2b near the second end 1042 of the fourth side E4 includes a second side wall 2012 inclined to the upper surface 100 of the substrate 10 and separated from the fourth side surface 104 of the substrate 10 by a spacing D to expose the upper surface 100 of the substrate 10, wherein the secondary spacing D' is smaller than the spacing D.

[0326] In one embodiment of the invention, the first semiconductor layer 201 of the first light-emitting unit 2a includes a plurality of first sidewalls 2011 and a third sidewall 2013 to form a first periphery of the first light-emitting unit 2a, wherein the distances between the plurality of first sidewalls 2011 and the side surface of the substrate 10 are different. Specifically, the first sidewall 2011 close to the first edge E1 is connected to the upper surface 100 of the substrate 10, and is separated from the first side surface 101 of the substrate 10 by a distance D' to expose the upper surface 100 of the substrate 10. The first sidewall 2011 close to the third edge E3 and the fourth edge E4 is directly connected to the third side surface 103 and the fourth side surface 104 of the substrate 10, respectively. The third sidewall 2013 of the first semiconductor layer 201 of the first light-emitting unit 2a forms one side of the groove 11, and the third sidewall 2013 is inclined to the upper surface 100 of the substrate 10.

[0327] In another embodiment of the invention (not shown), the first semiconductor layer 201 of the first light emitting unit 2a includes a plurality of first side walls 2011 and a third side wall 2013 to form a first periphery of the first light emitting unit 2a. The plurality of first side walls 2011 are directly connected to the first side surface 101, a first end 1031 of the third side surface, and a first end 1041 of the fourth side surface of the substrate 10, respectively. The third side wall 2013 of the first semiconductor layer 201 of the first light emitting unit 2a forms one side of the groove 11, and the third side wall 2013 is inclined to the upper surface 100 of the substrate 10.

[0328] In one embodiment of the invention, Figure 7 , Figure 8 , Fig. 9 , Fig.9A and Fig.10As shown, the first semiconductor layer 201 of the second light emitting unit 2b includes a plurality of second sidewalls 2012 and a fourth sidewall 2014 to form a second periphery of the second light emitting unit 2b. The plurality of second sidewalls 2012 are respectively inclined to the upper surface 100 of the substrate 10, and are respectively spaced apart from the second side surface 102, a second end 1032 of the third side surface, and a second end 1042 of the fourth side surface of the substrate 10 by a distance D to expose the upper surface 100 of the substrate 10. The fourth sidewall 2014 of the first semiconductor layer 201 of the second light emitting unit 2b forms the other side of the groove 11, and the fourth sidewall 2014 is inclined to the upper surface 100 of the substrate 10.

[0329] In one embodiment of the invention, the distances D between the second sidewalls 2012 and the second side surface 102 , a second end 1032 of the third side surface, and a second end 1042 of the fourth side surface of the substrate 10 may be the same or different.

[0330] In one embodiment of the invention, Fig. 9 , Fig.9A and Fig.10 As shown, the spacing D is preferably greater than 5 μm and less than 50 μm, and more preferably less than 30 μm. The upper surface 100 of the substrate 10 exposed by the spacing D is a rough surface. The rough surface can be a surface with an irregular shape or a surface with a regular shape, such as a surface with a plurality of hemispherical shapes protruding or recessed on the upper surface 100, a surface with a plurality of conical shapes protruding or recessed on the upper surface 100, or a surface with a plurality of polygonal cone shapes protruding or recessed on the upper surface 100.

[0331] like Fig. 9 , Fig.9A As shown, a first angle θ1 is included between the first side wall 2011 of the first semiconductor layer 201 of the first light-emitting unit 2a and the upper surface 100 of the substrate 10, and a second angle θ2 is included between the second side wall 2012 of the first semiconductor layer 201 of the second light-emitting unit 2b and the upper surface 100 of the substrate 10, and the second angle θ2 is different from the first angle θ1.

[0332] In one embodiment of the invention, the first angle θ1 is greater than the second angle θ2.

[0333] In one embodiment of the invention, the first angle θ1 is between 70° and 90°, and the second angle θ2 is between 20° and 70°.

[0334] In one embodiment of the invention, the angle difference between the first angle θ1 and the second angle θ2 is greater than 20°.

[0335] In one embodiment of the invention, the third sidewall 2013 of the first light emitting unit 2a is inclined at a third angle θ3 to the upper surface 100 of the substrate 10, and the fourth sidewall 2014 of the second light emitting unit 2b is inclined at a fourth angle θ4 to the upper surface 100 of the substrate 10.

[0336] In one embodiment of the invention, the third angle θ3 is different from the fourth angle θ4. The third angle θ3 and the fourth angle θ4 are respectively between 20° and 70°.

[0337] In one embodiment of the invention, the angle difference between the third angle θ3 and the fourth angle θ4 is less than 20°.

[0338] In one embodiment of the invention, the third angle θ3 is greater than the fourth angle θ4. The third angle and the fourth angle are respectively between 20° and 70°.

[0339] In one embodiment of the invention, the third angle θ3 is smaller than the fourth angle θ4. The third angle and the fourth angle are respectively between 20° and 70°.

[0340] In one embodiment of the invention, the second angle θ2 is different from the third angle θ3. The second angle and the third angle are respectively between 20° and 70°.

[0341] In one embodiment of the invention, the second angle θ2 is greater than the third angle θ3. The second angle θ2 and the third angle θ3 are respectively between 20° and 70°.

[0342] In one embodiment of the invention, the second angle θ2 is smaller than the third angle θ3. The second angle and the third angle θ3 are respectively between 20° and 70°.

[0343] like Figure 7 and Figure 8 As shown, a first insulating layer 30 is formed on the semiconductor stack 20 of the first light-emitting unit 2a and the second light-emitting unit 2b. One or more first insulating layer first openings 301 are formed on the first concave portion 204a adjacent to the first side E1 by a selective etching method to expose the first semiconductor layer 201 of the first concave portion 204a of the first light-emitting unit 2a, and one or more first insulating layer second openings 302 are formed on the second concave portion 204b adjacent to the second side E2 to expose the first semiconductor layer 201 of the second concave portion 204b of the second light-emitting unit 2b. In addition, first insulating layer third openings 303a and 303b are formed on the first light-emitting unit 2a and the second light-emitting unit 2b, respectively, to expose the second semiconductor layer 202.

[0344] In one embodiment of the invention, Figure 7 and Figure 8As shown, the opening position of the first insulating layer 30 can determine the position of the subsequent contact layer and the electrode layer. In order to allow the current to spread evenly at the outer edge of the light-emitting element 2, the multiple first insulating layer second openings 302 adjacent to the second side E2 include a number that is the same as the number of the multiple first insulating layer first openings 301 adjacent to the first side E1.

[0345] like Figure 7 and Figure 8 As shown, in order to expose the same area of ​​the first semiconductor layer 201 through the first insulating layer first opening 301 and the first insulating layer second opening 302 , the first insulating layer second opening 302 adjacent to the second side E2 includes a maximum length 302w greater than the maximum length 301w of the first insulating layer first opening 301 adjacent to the first side E1 .

[0346] like Figure 8 , Fig. 9 and Fig.9A As shown, a first contact electrode 40a is formed in the third opening 303a of the first insulating layer of the first light-emitting unit 2a to form an ohmic contact with the second semiconductor layer 202 of the first light-emitting unit 2a. A second contact electrode 40b is formed in the third opening 303b of the first insulating layer of the second light-emitting unit 2b to form an ohmic contact with the second semiconductor layer 202 of the second light-emitting unit 2b. The first contact electrode 40a and the second contact electrode 40b include transparent electrodes. The material of the transparent electrode includes a light-transmitting conductive oxide or a light-transmitting metal. The light-transmitting conductive oxide includes indium tin oxide (ITO), zinc oxide (ZnO), zinc indium tin oxide (ZITO), zinc indium oxide (ZIO), zinc tin oxide (ZTO), gallium indium tin oxide (GITO), gallium indium oxide (GIO), or gallium zinc oxide (GZO). The light-transmitting conductive oxide may include various dopants, such as aluminum doped zinc oxide (AZO) or fluorine doped tin oxide (FTO). The light-transmitting metal includes nickel (Ni) or gold (Au).

[0347] The thickness of the first contact electrode 40a and the second contact electrode 40b is not limited, but can have a thickness of about 0.1 nm to 200 nm respectively. In one embodiment, the material of the first contact electrode 40a and the second contact electrode 40b is selected from a light-transmitting conductive oxide. If the thickness of the first contact electrode 40a or the second contact electrode 40b is less than 0.1 nm, it cannot effectively form an ohmic contact with the second semiconductor layer 202 due to the thickness being too thin. In addition, if the thickness of the first contact electrode 40a or the second contact electrode 40b is greater than 200 nm, it partially absorbs the light emitted by the active layer 203 due to the thickness being too thick, thereby causing the problem of reduced brightness of the light-emitting element 2. Since the first contact electrode 40a or the second contact electrode 40b has a thickness within the above range, the current can be smoothly dispersed in the horizontal direction to improve the electrical performance of the light-emitting element 2. However, the above embodiment does not exclude other materials with lateral current diffusion.

[0348] The first contact electrode 40a and the second contact electrode 40b are formed on substantially the entire surface of the second semiconductor layer 202, and form a low resistance contact, such as an ohmic contact, with the second semiconductor layer 202, so that the current can pass through the first contact electrode 40a and the second contact electrode 40b to uniformly diffuse through the second semiconductor layer 202. In one embodiment, from the cross-sectional view of the self-luminous element 2, the first contact electrode 40a and the second contact electrode 40b each include an outermost side, and are separated from the first concave portion 204a and the second concave portion 204b by a horizontal distance of less than 20 μm, preferably less than 10 μm, and more preferably less than 5 μm.

[0349] like Figure 8 , Fig. 9 and Fig.9A As shown, a first reflective layer 50a is formed on the first contact electrode 40a, and a second reflective layer 50b is formed on the second contact electrode 40b. The materials of the first reflective layer 50a and the second reflective layer 50b include metals such as aluminum (Al), silver (Ag), rhodium (Rh) or platinum (Pt) or alloys of the above materials. The first reflective layer 50a and the second reflective layer 50b are used to reflect light, and the reflected light is emitted toward the substrate 10, wherein the reflected light is generated by the active layer 203.

[0350] In another embodiment, the step of forming the first contact electrode 40a and the second contact electrode 40b can be omitted. The first reflective layer 50a and the second reflective layer 50b are formed in the third openings 303a and 303b of the first insulating layer, respectively. The first reflective layer 50a and the second reflective layer 50b can be in ohmic contact with the second semiconductor layer 202 of the first light emitting unit 2a and the second light emitting unit 2b, respectively.

[0351] In one embodiment, from the cross-sectional view of the light-emitting element 5, Fig. 9 and Fig.10 As shown, the first reflective layer 50a and the second reflective layer 50b each include an outermost layer, and are respectively separated from the first concave portion 204a and the second concave portion 204b by a horizontal distance less than 20 μm, preferably less than 10 μm, and more preferably less than 5 μm.

[0352] In another embodiment, a barrier layer (not shown) is formed on the first reflective layer 50a and the second reflective layer 50b to cover the upper surface and the side surface of the first reflective layer 50a and the second reflective layer 50b respectively to prevent the surface of the first reflective layer 50a and the second reflective layer 50b from being oxidized, thereby deteriorating the reflectivity of the first reflective layer 50a and the second reflective layer 50b. The material of the barrier layer includes a metal material, such as titanium (Ti), tungsten (W), aluminum (Al), indium (In), tin (Sn), nickel (Ni), chromium (Cr), platinum (Pt) and other metals or alloys of the above materials. The barrier layer can be a one or more multi-layer structure, and the multi-layer structure is, for example, titanium (Ti) / aluminum (Al), and / or nickel-titanium alloy (NiTi) / titanium-tungsten alloy (TiW). In one embodiment of the present invention, the barrier layer includes a stacked structure of titanium (Ti) / aluminum (Al) and a stacked structure of nickel-titanium alloy (NiTi) / titanium-tungsten alloy (TiW), wherein the stacked structure of titanium (Ti) / aluminum (Al) is located on a side away from the reflective layer, and the stacked structure of nickel-titanium alloy (NiTi) / titanium-tungsten alloy (TiW) is located on a side close to the reflective layer. In one embodiment of the present invention, the material of the reflective layer and the barrier layer preferably includes a metal material other than gold (Au) or copper (Cu).

[0353] like Fig. 9 , Fig.9A and Fig.10 As shown, the light emitting element 2 includes a second insulating layer 60 formed on the semiconductor stack 20 of the first light emitting unit 2a and the second light emitting unit 2b. One or more second insulating layer first openings 601 are formed on the first concave portion 204a by a selective etching method to expose the first semiconductor layer 201 of the first light emitting unit 2a located in the first concave portion 204a. One or more second insulating layer second openings 602 are formed on the second concave portion 204b to expose the first semiconductor layer 201 of the second light emitting unit 2b located in the second concave portion 204b. In addition, one or more second insulating layer third openings 603a are formed on the first light emitting unit 2a to expose the second semiconductor layer 202, the reflective layer 50a and / or the barrier layer of the first light emitting unit 2a, and a second insulating layer fourth opening 603b is formed on the second light emitting unit 2b to expose the second semiconductor layer 202, the second reflective layer 50b and / or the barrier layer of the second light emitting unit 2b.

[0354] The second insulating layer first opening 601, the second insulating layer second opening 602, and the second insulating layer fourth opening 603b of the second insulating layer 60 are formed at positions corresponding to the first insulating layer first opening 301, the first insulating layer second opening 302, and the first insulating layer third opening 303b of the first insulating layer 30. The second insulating layer third opening 603a is formed at a position overlapping with the first insulating layer third opening 303a.

[0355] like Figure 7 and Figure 8 As shown, in order to make the second insulating layer first opening 601 and the second insulating layer second opening 602 expose the same area of ​​the first semiconductor layer 201, the multiple second insulating layer second openings 602 located in the second light-emitting unit 2b respectively include a maximum length 602w that is greater than the maximum length 601w of one of the multiple second insulating layer first openings 601 located in the first light-emitting unit 2a.

[0356] The opening position of the second insulating layer 60 can determine the position of the subsequent electrode layer. Figure 7 , Figure 8 and Fig.10 As shown, in order to make the current spread evenly at the outer edge of the light-emitting element 2, the second insulating layer 60 further includes one or more second insulating layer openings 600 formed between the first light-emitting unit 2a and the second light-emitting unit 2b. The second insulating layer openings 600 include one or more second insulating layer first unit openings 600a exposing the first semiconductor layer 201 of the first light-emitting unit 2a located in the first concave portion 204a; and one or more second insulating layer second unit openings 600b exposing the first semiconductor layer 201 of the second light-emitting unit 2b located in the second concave portion 204b.

[0357] In one embodiment (not shown), the plurality of second insulating layer first unit openings 600a and the plurality of second insulating layer third openings 603a are located on the same side of the first light-emitting unit 2a, and the plurality of second insulating layer first unit openings 600a and the plurality of second insulating layer third openings 603a are arranged alternately with each other. In order to increase the injection of current and reduce the loss of the light-emitting area, the plurality of second insulating layer third openings 603a include a number greater than the plurality of second insulating layer first unit openings 600a. The number of the second insulating layer first unit openings 600a is the same as the number of the second insulating layer second unit openings 600b. The second insulating layer first unit openings 600a and the second insulating layer second unit openings 600b are connected at the bottom of the top view of the light-emitting element 2.

[0358] The second insulating layer 60 may be formed of an insulating material having light transmittance. For example, the second insulating layer 60 includes SiOx.

[0359] In one embodiment, the thickness of the second insulating layer 60 may be 1000 angstroms to 60000 angstroms.

[0360] In one embodiment, the material of the second insulating layer 60 is selected from SiO2, TiO2, SiNx and the like. If the thickness of the second insulating layer 60 is less than 1000 angstroms, the thinner thickness may weaken the insulating property of the second insulating layer 60. Specifically, the second insulating layer 60 is formed on the etched inclined surface, and the second insulating layer 60 formed in accordance with the inclined surface coverage also has a specific slope. If the thickness of the second insulating layer 60 is less than 1000 angstroms, the film layer may be cracked.

[0361] In one embodiment, the material of the second insulating layer 60 is selected from SiO2, TiO2, SiNx and the like. If the thickness of the second insulating layer 60 exceeds 60,000 angstroms, it will increase the difficulty of selective etching on the second insulating layer 60. However, the above embodiment does not exclude other materials with good coverage extension or materials with high selective etching to avoid the problem of the second insulating layer 60 being too thin or too thick.

[0362] like Fig. 9 , Fig.9A and Fig.10 As shown, the second insulating layer 60 has a side surface, which has an oblique angle between 10 degrees and 70 degrees relative to a horizontally extending plane of the outer surface 204 s of the first semiconductor layer 201 exposed by the selective etching.

[0363] If the bevel angle of the side surface of the second insulating layer 60 is less than 10 degrees, the substantial thickness of the second insulating layer 60 will be reduced. Therefore, there may be a problem that it is difficult to ensure the insulating property.

[0364] If the oblique angle of the side surface of the second insulating layer 60 is greater than 70 degrees, the subsequent insulating layer and metal layer may not be fully covered, thereby causing film cracks.

[0365] In one embodiment of the present invention, the oblique angle of the side surface of the second insulating layer 60 is between 20 degrees and 75 degrees, preferably between 30 degrees and 65 degrees, and more preferably between 40 degrees and 55 degrees.

[0366] like Figure 7 , Fig. 9 and Fig.9AAs shown, the light emitting element 2 includes one or more connecting electrodes 70 formed between the first light emitting unit 2a and the second light emitting unit 2b. The one or more connecting electrodes 70 each include a first connecting end 701 located on the first concave portion 204a of the first light emitting unit 2a, extending to cover and electrically connected to the second semiconductor layer 202 of the first light emitting unit 2a; a second connecting end 702 located on the second concave portion 204b of the second light emitting unit 2b, and electrically connected to the first semiconductor layer 201 of the second light emitting unit 2b; and a third connecting end 703 located in the groove 11, sandwiched between the first concave portion 204a and the second concave portion 204b, and located between the first connecting end 701 and the second connecting end 702.

[0367] like Fig. 9 and Fig.9A As shown, the first insulating layer 30 and / or the second insulating layer 60 are located between the first connection terminal 701 and the first semiconductor layer 201. The first insulating layer 30 and / or the second insulating layer 60 are located between the second connection terminal 702 and the first semiconductor layer 201.

[0368] In one embodiment of the present invention, from a top view of the light-emitting element 2 , the connecting electrode 70 has a width of at least 15 μm, preferably 30 μm, and more preferably 50 μm.

[0369] like Figure 7 , Fig. 9 and Fig.9A As shown, the light emitting element 2 includes a first lower electrode 71a located on the first light emitting unit 2a; a second lower electrode 71b located on the second light emitting unit 2b; and a second upper electrode 72b located on the second light emitting unit 2b. External current is injected into the light emitting element 2 through the first lower electrode 71a and the second upper electrode 72b, and the first light emitting unit 2a and the second light emitting unit 2b are electrically connected in series through the second connection end 702 of the connection electrode 70 extending from the second lower electrode 71b, the third connection end 703 located in the groove 11, and the first connection end 701.

[0370] like Figure 7 , Fig. 9 and Fig.9A As shown, the second insulating layer 60 is located between the second connection end 702 and the first semiconductor layer 201 of the second light emitting unit 2b, so as to prevent the second connection end 702 from directly contacting the first semiconductor layer 201 of the second light emitting unit 2b. Figure 7 and Fig.10As shown, the second unit opening 600b of the second insulating layer exposes the first semiconductor layer 201 of the second light emitting unit 2b located in the second recess 204b, so that the second lower electrode 71b directly contacts the first semiconductor layer 201 of the second light emitting unit 2b through the second unit opening 600b of the second insulating layer. The current flowing to the second connection terminal 702 passes through the second lower electrode 71b of the second light emitting unit 2b to be conducted to the first semiconductor layer 201 of the second light emitting unit 2b.

[0371] The connecting electrode 70, the first lower electrode 71a, the second lower electrode 71b and / or the second upper electrode 72b include a metal material, such as chromium (Cr), titanium (Ti), tungsten (W), gold (Au), aluminum (Al), indium (In), tin (Sn), nickel (Ni) or platinum (Pt) or an alloy of the above materials. The connecting electrode 70, the first lower electrode 71a, the second lower electrode 71b and / or the second upper electrode 72b may be composed of a single layer or a plurality of layers. For example, the connecting electrode 70, the first lower electrode 71a, the second lower electrode 71b and / or the second upper electrode 72b may include a Ti / Au layer, a Ti / Pt / Au layer, a Cr / Au layer, a Cr / Pt / Au layer, a Ni / Au layer, a Ni / Pt / Au layer or a Cr / Al / Cr / Ni / Au layer.

[0372] The thickness of the connecting electrode 70 , the first lower electrode 71 a , the second lower electrode 71 b and / or the second upper electrode 72 b is preferably 0.5 μm to 2.5 μm.

[0373] like Fig. 9 , Fig.9A and Fig.10 As shown, the light emitting element 2 includes a third insulating layer 80 formed on the first light emitting unit 2a and the second light emitting unit 2b. A first opening 801 of the third insulating layer is formed on the first lower electrode 71a by a selective etching method to expose a top surface of the first lower electrode 71a. In addition, a second opening 802 of the third insulating layer is formed on the second upper electrode 72b to expose a top surface of the second upper electrode 72b.

[0374] The third insulating layer 80 may be formed of an insulating material having light transmittance. For example, the third insulating layer 80 includes SiOx.

[0375] In one embodiment, the material of the third insulating layer 80 is selected from materials such as SiO2, TiO2, SiNx, etc., and the thickness of the third insulating layer 80 may be 10,000 angstroms to 60,000 angstroms. If the thickness of the third insulating layer 80 is less than 10,000 angstroms, the thinner thickness may weaken the insulation properties and moisture resistance of the third insulating layer 80. In another embodiment, the material of the third insulating layer 80 is selected from materials such as SiO2, TiO2, SiNx, etc., and if the thickness of the third insulating layer 80 exceeds 60,000 angstroms, it will increase the difficulty of selective etching on the third insulating layer 80. However, the above embodiment does not exclude that other materials with good coverage extension or materials with high selective etching can avoid the problem of the third insulating layer 80 being too thin or too thick.

[0376] The first insulating layer 30, the second insulating layer 60 or the third insulating layer 80 may be formed by alternately stacking two or more materials having different refractive indices to form a Bragg reflector (DBR) structure. For example, the first insulating layer 30, the second insulating layer 60 or the third insulating layer 80 may include stacked layers such as SiO2 / TiO2 or SiO2 / Nb2O5 to selectively reflect light of a specific wavelength, thereby increasing the light extraction efficiency of the light emitting element 2. When the peak emission wavelength of the light emitting element 2 is λ, the optical thickness of the first insulating layer 30, the second insulating layer 60 or the third insulating layer 80 may be set to an integer multiple of λ / 4. The peak wavelength refers to the wavelength with the strongest intensity in the emission spectrum of the light emitting element 2. Based on the integer multiple of the optical thickness λ / 4, the thickness of the first insulating layer 30, the second insulating layer 60 or the third insulating layer 80 may have a deviation of ±30%.

[0377] The first insulating layer 30, the second insulating layer 60 or the third insulating layer 80 is formed of a non-conductive material, including an organic material, such as Su8, benzocyclobutene (BCB), perfluorocyclobutane (PFCB), epoxy resin, acrylic resin, cycloolefin polymer (COC), polymethyl methacrylate (PMMA), polyethylene terephthalate (PET), polycarbonate (PC), polyetherimide or fluorocarbon polymer, or an inorganic material, such as silicone or glass, or a dielectric material, such as aluminum oxide (Al2O3), silicon nitride (SiNx), silicon oxide (SiOx), titanium oxide (TiOx), or magnesium fluoride (MgFx).

[0378] like Figure 7 , Fig. 9 , Fig.9A and Fig.10As shown, the light emitting element 2 includes a first electrode pad 91 to cover the first opening 801 of the third insulating layer and contact the first lower electrode 71a. The first electrode pad 91 is electrically connected to the first semiconductor layer 201 of the first light emitting unit 2a through the first lower electrode 71a. The light emitting element 2 includes a second electrode pad 92 to cover the second opening 802 of the third insulating layer and contact the second upper electrode 72b.

[0379] In one embodiment, if Fig. 9 As shown, the first sidewall 2011 of the first semiconductor layer 201 near the first end 1031 of the third side surface 103 is not covered by the third insulating layer 80 . The second sidewall 2012 of the first semiconductor layer 201 near the second end 1032 of the third side surface 103 is covered by the third insulating layer 80 .

[0380] In one embodiment, if Fig.9A As shown, the first sidewall 2011 of the first semiconductor layer 201 close to the first side surface 101 of the substrate 10 is covered by the third insulating layer 80. The second sidewall 2012 of the first semiconductor layer 201 close to the second end 1042 of the fourth side surface 104 is covered by the third insulating layer.

[0381] In one embodiment, if Fig.10 As shown, the first sidewall 2011 of the first semiconductor layer 201 near the first end 1041 of the fourth side surface 104 is not covered by the third insulating layer 80 . The second sidewall 2012 of the first semiconductor layer 201 near the second end 1042 of the fourth side surface 104 is covered by the third insulating layer 80 .

[0382] The first electrode pad 91 and the second electrode pad 92 include metal materials, such as chromium (Cr), titanium (Ti), tungsten (W), gold (Au), aluminum (Al), indium (In), tin (Sn), nickel (Ni), platinum (Pt), etc., or alloys of the above materials. The first electrode pad 91 and the second electrode pad 92 may be composed of a single layer or multiple layers. For example, the first electrode pad 91 and the second electrode pad 92 may include a Ti / Au layer, a Ti / Pt / Au layer, a Cr / Au layer, a Cr / Pt / Au layer, a Ni / Au layer, a Ni / Pt / Au layer, or a Cr / Al / Cr / Ni / Au layer.

[0383] In one embodiment of the present invention, the first electrode pad 91 includes a size that is the same as or different from a size of the second electrode pad 92. The size may be a width or an area. For example, the top view area of ​​the first electrode pad 91 or the second electrode pad 92 may be greater than 0.8 times and less than 1 times the value obtained by adding the top view areas of the first electrode pad 91 and the second electrode pad 92.

[0384] The first electrode pad 91 or the second electrode pad 92 includes an inclined side surface, so the cross-sectional area of ​​the first electrode pad 91 or the second electrode pad 92 in the side view can change along the thickness direction. For example, the cross-sectional area of ​​the first electrode pad 91 or the second electrode pad 92 in the side view can gradually decrease as it moves away from the upper surface of the semiconductor stack.

[0385] The first electrode pad 91 or the second electrode pad 92 has a thickness between 1 and 100 μm, preferably between 1.5 and 6 μm.

[0386] There is a gap between the first electrode pad 91 and the second electrode pad 92, and the gap includes a shortest distance of about 10 μm or more and a longest distance of about 250 μm or less. Within the above range, by reducing the gap between the first electrode pad 91 and the second electrode pad 92, the upper viewing area of ​​the first electrode pad 91 and the second electrode pad 92 can be increased, thereby improving the heat dissipation efficiency of the light-emitting element 2 and avoiding a short circuit between the first electrode pad 91 and the second electrode pad 92.

[0387] Fig.11 For along Figure 7 Sectional view of the tangent line F-F'. Fig.12 For along Figure 7 Sectional view of the tangent line G-G'.

[0388] In one embodiment of the present invention, Figure 7 As shown, from the top view of the light emitting element 2, the light emitting element 2 includes a plurality of corners, wherein the plurality of corners include a first corner C1, a second corner C2, a third corner C3, and a fourth corner C4. The light emitting element 2 includes a plurality of semiconductor structures 206, wherein the plurality of semiconductor structures 206 include a first semiconductor structure 2061, a second semiconductor structure 2062, a third semiconductor structure 2063, and a fourth semiconductor structure 2064. The first semiconductor structure 2061, the second semiconductor structure 2062, the third semiconductor structure 2063, and the fourth semiconductor structure 2064 are located at the first corner C1, the second corner C2, the third corner C3, and the fourth corner C4, respectively.

[0389] In another embodiment of the present invention (not shown), the light emitting element 2 includes a plurality of edges, wherein the plurality of edges include a first edge E1, a second edge E2, a third edge E3 and a fourth edge E4. A plurality of semiconductor structures 206 may be respectively located on the plurality of edges.

[0390] like Figure 7 , Fig.11 and Fig.12As shown, the first semiconductor structure 2061 and the fourth semiconductor structure 2064 are respectively separated from the first semiconductor platform 205a by a distance, and the first semiconductor structure 2061 and the fourth semiconductor structure 2064 are separated from each other. The second semiconductor structure 2062 and the third semiconductor structure 2063 are respectively separated from the second semiconductor platform 205b by a distance, and the second semiconductor structure 2062 and the third semiconductor structure 2063 are separated from each other.

[0391] like Fig.11 As shown, the first semiconductor structure 2061 adjacent to the first side E1 is separated from the first semiconductor platform 205a by a first shortest distance L1, and the fourth semiconductor structure 2064 adjacent to the first side E1 is separated from the first semiconductor platform 205a by a fourth shortest distance L4 (not shown). Fig.12 As shown, the second semiconductor structure 2062 adjacent to the second side E2 is separated from the second semiconductor platform 205b by a second shortest distance L2, and the third semiconductor structure 2063 adjacent to the second side E2 is separated from the second semiconductor platform 205b by a third shortest distance L3 (not shown).

[0392] In one embodiment of the present invention, the second shortest distance L2 and the third shortest distance L3 are respectively greater than the first shortest distance L1.

[0393] like Figure 7 and Fig.11 As shown, in one embodiment of the present invention, near the first corner C1, the first semiconductor layer 201 is located between the first semiconductor structure 2061 and the first semiconductor platform 205a, and connects the first semiconductor structure 2061 and the first semiconductor platform 205a. Near the fourth corner C4, the first semiconductor layer 201 is located between the fourth semiconductor structure 2064 and the first semiconductor platform 205a, and connects the fourth semiconductor structure 2064 and the first semiconductor platform 205a (not shown). Figure 7 and Fig.12 As shown, in one embodiment of the present invention, adjacent to the second corner C2, the first semiconductor layer 201 between the second semiconductor structure 2062 and the second semiconductor platform 205b is removed to expose the substrate 10, and the second semiconductor structure 2062 and the second semiconductor platform 205b are separated from each other. Adjacent to the third corner C3, the first semiconductor layer 201 between the third semiconductor structure 2063 and the second semiconductor platform 205b is removed to expose the substrate 10, and the third semiconductor structure 2063 and the second semiconductor platform 205b are separated from each other (not shown).

[0394] In one embodiment of the present invention, from the top view of the light-emitting element 2 , the first semiconductor structure 2061 , the second semiconductor structure 2062 , the third semiconductor structure 2063 and the fourth semiconductor structure 2064 include a shape, such as a rectangle, a triangle or a fan.

[0395] Fig.13A A partial top view of a wafer showing a method for manufacturing a light emitting device 1A according to an embodiment of the present invention. Fig. 13B A method for manufacturing a light emitting element 1A according to an embodiment of the present invention is disclosed. Fig. 13C It is a top view of a light emitting element 1A disclosed in one embodiment of the present invention.

[0396] Fig.13A It is a partial top view of a wafer used to illustrate the manufacturing process of producing the light-emitting element 1A from the wafer.

[0397] As mentioned above, the wafer can use raw materials such as gallium arsenide (GaAs) wafer, sapphire (Al2O3) wafer, gallium nitride (GaN) wafer or silicon carbide (SiC) wafer as a growth substrate. On the growth substrate, a semiconductor stack, such as a light-emitting structure consisting of a first semiconductor layer, a second semiconductor layer and an active layer, is grown by metal organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), hydride vapor deposition (HVPE), physical vapor deposition (PVD) or ion plating. Then, an electrode structure and an insulating layer structure are formed by photolithography and etching processes.

[0398] After forming a wafer containing semiconductor light-emitting elements, it is necessary to separate the wafer into individual semiconductor light-emitting elements by dicing. Since the size of light-emitting elements tends to decrease gradually according to different applications, for example, the area of ​​a single light-emitting element is less than 100,000 μm 2 If the cutting accuracy is insufficient, the production yield of the light-emitting element will be affected. Therefore, in the actual cutting process, it is necessary to provide a reference point for the cutting device (not shown) so that the cutting device can be accurately aligned with the cutting path. The present invention provides a recognition method and structure that helps cutting to improve the production yield of the light-emitting element.

[0399] refer to Fig.13A and Fig. 13B . Fig. 13B for Fig.13AThe enlarged view of the part of the position 1001, 2001 and 3001 of the wafer. Cutting lanes Z1 and Z2 are formed on the wafer of the light emitting element 1A to define a plurality of light emitting elements 1A. A second identification structure 222 is set on the edge of the light emitting element 1A adjacent to the cutting lane Z1, and / or a first identification structure 221 and a third identification structure 223 are respectively set on the two corners connected to the aforementioned edge. These identification structures 221, 222 and 223 serve as marks for the cutting device to identify the position of the cutting lane Z1.

[0400] In one embodiment of the present invention, a plurality of light emitting elements 1A are arranged in an array on a wafer. In order to accurately cut the plurality of light emitting elements 1A, a second identification structure 222 is disposed on each side of the light emitting element 1A, or a first identification structure 221 or a third identification structure 223 is disposed on each corner of the light emitting element 1A. The first identification structure 221, the second identification structure 222 and / or the third identification structure 223 include semiconductor structures.

[0401] In one embodiment, the semiconductor structure of the second identification structure 222 , the first identification structure 221 and / or the third identification structure 223 includes a semiconductor stack.

[0402] In one embodiment of the present invention, Fig. 13C As shown, the light-emitting element 1A includes a semiconductor stack, and has a first identification structure 221, a second identification structure 222, and a third identification structure 223 composed of semiconductor structures at a corner position 1000, an edge position 2000, and a corner position 3000. The light-emitting element 1A has multiple corners and multiple edges, wherein the corner is composed of two adjacent edges. The multiple edges include a first edge 101A, a second edge 102A, a third edge 103A, and a fourth edge 104A. Multiple semiconductor structures are respectively located at multiple corners or multiple edges. The multiple semiconductor structures located at multiple corners, such as the first identification structure 221 or the third identification structure 223, are separated from the semiconductor stack by a spacing. In one embodiment, the first identification structure 221 and the semiconductor stack are separated by a distance at the aforementioned spacing, and there is no semiconductor layer connected between the first identification structure 221 and the semiconductor stack; the third identification structure 223 and the semiconductor stack are connected by a semiconductor layer. The aforementioned spacing can expose the surface of the aforementioned semiconductor layer or substrate. A plurality of semiconductor structures, such as the first identification structure 221 or the third identification structure 223, are separated from each other. A plurality of semiconductor structures located on a plurality of sides, such as the second identification structure 222, are directly connected to the semiconductor stack.

[0403] Fig.14Schematic diagram of a light emitting device 3 according to an embodiment of the present invention. The light emitting element 1, 1A, 2 or 5 in the above-mentioned embodiment is mounted on the first pad 511 and the second pad 512 of the packaging substrate 51 in the form of a flip chip. The first pad 511 and the second pad 512 are electrically insulated by an insulating portion 53 containing an insulating material. The flip chip mounting is to set the side of the growth substrate opposite to the electrode pad forming surface as the main light extraction surface. In order to increase the light extraction efficiency of the light emitting device 3, a reflective structure 54 can be set around the light emitting element 1, 1A, 2 or 5.

[0404] Another object of the present invention is to provide a light-emitting element and a manufacturing method thereof that can improve the reliability of a packaging device. Taking the light-emitting element 1 as an example, when the light-emitting element 1 is mounted on the first pad 511 and the second pad 512 of the packaging substrate 51 in the form of a flip chip, the first electrode pad 91 is bonded to the first pad 511 through solder paste, and the second electrode pad 92 is bonded to the second pad 512 through solder paste. Since the first electrode pad 91 is electrically connected to the first semiconductor layer 201, even if the solder paste overflows from the first electrode pad 91 to the first semiconductor layer 201, the light-emitting element 1 will not fail due to leakage. However, the second electrode pad 92 is electrically connected to the second semiconductor layer 202. If the solder paste overflows from the second electrode pad 92 to the first semiconductor layer 201, the light-emitting element 1 will fail due to leakage. Therefore, the present invention improves the reliability of the light-emitting element by forming a third insulating layer 80 to cover the outer surface 204s and the second side wall 2012 of the first semiconductor layer 201 near the second electrode pad 92. In addition, since the first semiconductor layer 201 near the first electrode pad 91 does not need to be additionally coated, the area of ​​the semiconductor stack to be removed can be reduced, thereby improving the brightness of the light-emitting element.

[0405] Fig.15 Schematic diagram of a light emitting device 4 according to an embodiment of the present invention. The light emitting device 3 is a bulb lamp including a lampshade 6021, a reflector 604, a light emitting module 610, a lamp holder 612, a heat sink 614, a connecting portion 616 and an electrical connecting element 618. The light emitting module 610 includes a carrier 606, and a plurality of light emitting units 608 located on the carrier 606, wherein the plurality of light emitting units 608 may be the light emitting elements 1, 1A, 2, 5 or the light emitting device 3 in the aforementioned embodiments.

[0406] The embodiments listed in the present invention are only used to illustrate the present invention, and are not used to limit the scope of the present invention. Any obvious modification or change made by anyone to the present invention does not deviate from the spirit and scope of the present invention.

Claims

1. A light emitting element, characterized in that: Include: A semiconductor stack, comprising a first semiconductor layer, a second semiconductor layer and an active layer located between the first semiconductor layer and the second semiconductor layer; A first electrode pad adjacent to a first side of the light emitting element; a second electrode pad adjacent to a second side of the light emitting element, wherein the first side and the second side are located on different sides of the light emitting element when viewed from a top view of the light emitting element; and The insulating layer includes one or more first openings adjacent to the first edge and one or more second openings adjacent to the second edge, and the one or more first openings and the one or more second openings expose the first semiconductor layer, one of the one or more first openings includes a first maximum length, and one of the one or more second openings includes a second maximum length greater than the first maximum length. 2 . The light-emitting element as claimed in claim 1 , wherein the first side and the second side are located at opposite sides of the light-emitting element. 3 . The light emitting element as claimed in claim 1 , wherein the first insulating layer further comprises a third opening, and the insulating layer opening is located between the third opening and the second opening. 4 . The light emitting element as claimed in claim 3 , wherein an area of ​​the third opening is larger than areas of the first opening, the second opening and the insulating layer opening. 5 . The light emitting element as claimed in claim 3 , wherein the third opening has a first long side, and the insulating layer opening has a second long side parallel to the first long side.

6. The light-emitting element as described in claim 1, wherein the light-emitting element further includes a third side located between the first side and the second side, and the insulating layer includes one or more fourth openings adjacent to the third side, wherein one of the one or more fourth openings includes a third maximum length greater than the first maximum length. 7 . The light emitting device as claimed in claim 6 , wherein the insulating layer further comprises one or more fifth openings in the insulating layer adjacent to the third side, wherein one of the one or more fifth openings comprises a fourth maximum length different from the third maximum length. 8 . The light emitting element as claimed in claim 1 , wherein the number of the one or more second openings is greater than the number of the one or more first openings.

9. A light emitting element, characterized in that: Include: A semiconductor stack, comprising a first semiconductor layer, a second semiconductor layer and an active layer located between the first semiconductor layer and the second semiconductor layer; A first electrode pad adjacent to a first side of the light emitting element; A second electrode pad adjacent to a second side of the light emitting element; as well as The first insulating layer includes one or more first openings adjacent to the first edge and one or more second openings adjacent to the first edge, and the one or more first openings and the one or more second openings expose the first semiconductor layer, one of the one or more first openings includes a first maximum length, and one of the one or more second openings includes a second maximum length greater than the first maximum length.

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