Display device and method of manufacturing same

Abstract

The invention provides a display device and a manufacturing method thereof. The display device includes: an insulating layer disposed on a substrate; a bank pattern disposed on the insulating layer; a first electrode including a plurality of metal layers disposed on the bank pattern; a first metal layer disposed on the first electrode; a solder pattern disposed on the first metal layer; a light emitting element disposed on the solder pattern; and a second electrode disposed on the light emitting element, in which the first metal layer is disposed only in a region overlapping the light emitting element.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 2023-0158177, filed on November 15, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Embodiments relate to a display device using an inorganic light emitting diode as a light source and a method of manufacturing the display device. Background Art

[0004] The electroluminescent display device includes an organic light emitting display device in which an organic light emitting diode (OLED) is provided and an inorganic light emitting display device (hereinafter referred to as "LED display device") in which an inorganic light emitting diode (hereinafter referred to as "LED") is provided.

[0005] The electroluminescent display device displays images using self-luminous elements and thus does not require a separate light source such as a backlight unit, and can be implemented in various thin forms.

[0006] In an organic light emitting display device, since oxidation may occur between an organic light emitting layer and an electrode due to the penetration of moisture and oxygen, a design for preventing the penetration of oxygen and moisture is required.

[0007] Recently, as an example of inorganic light-emitting display devices, micro-LED display devices in which micro-LEDs are arranged in pixels have attracted attention as next-generation display devices. Micro-LEDs can be inorganic LEDs with a size of 100 μm or less. Micro-LEDs are manufactured through a separate semiconductor process and transferred to the pixel position on the display panel substrate of the display device. They can be arranged in each sub-pixel for each color. Summary of the Invention

[0008] The present disclosure provides a display device in which a metal layer having low bonding strength with a first optical layer and a second optical layer is prevented from contacting the first optical layer and the second optical layer in areas other than an area overlapping with a light-emitting element, thereby increasing the bonding strength between the first optical layer and the second optical layer and an insulating layer and reducing the contact resistance between a circuit component and a signal line of a pad portion in a pad portion.

[0009] The technical problems to be solved by the present disclosure are not limited to the above-mentioned technical problems, and other technical problems not mentioned will be clearly understood by ordinary technicians in this field from the following description.

[0010] This technical problem is solved by a display device, which includes: an insulating layer arranged on a substrate; a dam pattern arranged on the insulating layer; a first electrode arranged on the dam pattern, the first electrode including multiple metal layers; a first metal layer arranged on the first electrode; a solder pattern arranged on the first metal layer; a light-emitting element arranged on the solder pattern; and a second electrode arranged on the light-emitting element, wherein the first metal layer is only arranged in an area overlapping with the light-emitting element.

[0011] According to the present disclosure, the first metal layer is formed only in the area overlapping with the light-emitting element. Therefore, when the first metal layer includes indium tin oxide (ITO), the bonding strength with the first optical layer and / or the second optical layer is reduced, thereby preventing the first optical layer and / or the second optical layer from lifting on the first metal layer. In addition, in the pad portion, when the circuit component is attached to a portion of the signal line via an adhesive containing conductive balls (e.g., an anisotropic conductive film (ACF)), the problem of increased contact resistance with the first metal layer can be prevented.

[0012] Furthermore, when wet etching is performed to form an opening in the first metal layer including indium tin oxide (ITO) disposed on the bank pattern, a problem in which crystallized indium tin oxide (ITO) is not etched can be prevented.

[0013] Various beneficial advantages and effects of the present disclosure are not limited to the above-mentioned contents, and other effects not mentioned will be clearly understood by those of ordinary skill in the art from the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] The above and other objects, features and advantages of the present invention will become more apparent to those skilled in the art by describing in detail exemplary embodiments thereof with reference to the accompanying drawings, in which:

[0015] Figure 1 is a view showing a display device according to one embodiment of the present disclosure;

[0016] Figure 2 It shows Figure 1 An enlarged view of area A in FIG;

[0017] Figure 3 is a diagram showing a partial area of ​​a pixel;

[0018] Figure 4 It is along Figure 3 A sectional view taken along line II' in FIG.

[0019] Figure 5 It is along Figure 3 A sectional view taken along line II-II';

[0020] Figure 6 It is along Figure 3 A sectional view taken along line III-III';

[0021] Figure 7 is a cross-sectional view showing an example in which a main light emitting element and a sub-light emitting element are electrically connected to a pixel driving circuit;

[0022] Figure 8 is a view showing a display device according to another embodiment of the present disclosure;

[0023] Figure 9 It is along Figure 8 A sectional view taken along line IV-IV';

[0024] Figure 10A is a view showing a display device according to yet another embodiment of the present disclosure;

[0025] Figure 10B yes Figure 10A An enlarged view of region B in FIG;

[0026] Figure 11 It is along Figure 10B A sectional view taken along line AA';

[0027] Figures 12A to 12G 1 is a diagram illustrating a manufacturing process of a display device according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0028] The advantages and features of the present disclosure and their implementation methods will become apparent with reference to the embodiments described in detail below in conjunction with the accompanying drawings. The present disclosure is not limited to the embodiments to be described below and can be implemented in various forms. The embodiments are provided only to fully disclose the present disclosure and fully convey the scope of the present disclosure to those skilled in the art, and the present disclosure is limited only by the scope of the claims.

[0029] Since the shapes, sizes, proportions, angles, quantities, etc. disclosed in the drawings used to describe the embodiments of the present disclosure are merely exemplary, the present disclosure is not limited to the items shown in the drawings. Throughout the specification, the same reference numerals refer to substantially the same components. In addition, when describing the present disclosure, if it is determined that a detailed description of a related known technology may unnecessarily obscure the gist of the present disclosure, its detailed description will be omitted.

[0030] When the terms "provide," "have," "include," "comprise," and "compose" are used in the present disclosure, other parts may be added unless "only" is used. Components expressed in the singular may also be interpreted as plural unless explicitly stated otherwise.

[0031] When explaining the components, it should be understood that an error range is included even when there is no separate explicit description.

[0032] When describing the positional relationship and interconnection relationship between two components, such as "on", "upper", "lower", "adjacent", "connected or combined", "crossing or intersecting", etc., unless it is mentioned that "immediately next to" or "directly", one or more other components may be inserted between the two components.

[0033] When a temporal relationship is described as, for example, "after," "subsequently," "then," "before," etc., the temporal relationship may not be continuous on the time axis unless "immediately" or "directly" is used.

[0034] First, second, etc. can be used before the component name to distinguish the components, but the function or structure is not limited by these ordinal numbers or component names. For ease of description, the ordinal numbers before the same component name can be different between embodiments.

[0035] The following embodiments may be partially or completely combined with each other, and various types of interconnections and drives may be technically implemented. The embodiments may be implemented independently of each other or may be implemented together in an interrelated relationship.

[0036] Hereinafter, various embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0037] A display device according to one embodiment of the present disclosure includes: a display area for displaying an image, or a display panel having a screen disposed thereon; and a pixel driver circuit for driving pixels of the display panel. The display area includes a pixel region in which pixels are disposed. The pixel region includes multiple light-emitting regions. A light-emitting element is disposed in each light-emitting region. The pixel driver circuit may be built into the display panel.

[0038] Figure 1 is a view illustrating a display device according to one embodiment of the present disclosure. Figure 2 yes Figure 1 Magnified view of area A in FIG. Figure 3 is a diagram showing a partial area of ​​a pixel.

[0039] Reference Figure 1 and Figure 2According to one embodiment of the present disclosure, a display device 100 includes a display panel that visually reproduces an input image. The display panel may include a display area AA for displaying an image and a non-display area NA for not displaying an image. Various circuits and driver circuits may be mounted in the non-display area NA, and pad portions PAD for connection to integrated circuits, printed circuits, and the like may be provided. The display panel may be a rectangular panel having a width in the X-axis direction, a length in the Y-axis direction, and a thickness in the Z-axis direction. In this case, the width and length of the display panel may be set to various design values ​​depending on the application of the display device. The X-axis direction may refer to a width direction, a row direction, or a horizontal direction; the Y-axis direction may refer to a length direction, a column direction, or a longitudinal direction; and the Z-axis direction may refer to a vertical direction or a thickness direction. Furthermore, the X-axis direction, the Y-axis direction, and the Z-axis direction may be perpendicular to each other, but may also represent different directions that are not perpendicular to each other. Therefore, each of the X-axis direction, the Y-axis direction, and the Z-axis direction may be described as one of a first direction, a second direction, and a third direction. Furthermore, a plane extending in the X-axis direction and the Y-axis direction may represent a horizontal plane.

[0040] The plurality of light emitting elements 10 disposed in the display area AA and forming the pixels PXL may be micro-sized inorganic light emitting elements that can be grown on a silicon wafer and then attached to the display panel through a transfer process.

[0041] The transfer process of the light emitting element 10 can be performed for each previously divided area. Figure 1 In the embodiment described above, the display area AA is divided into nine transfer areas ST. However, the size or number of the divided transfer areas is not limited thereto. The transfer process can be performed sequentially or simultaneously on the first to ninth transfer areas ST. The blue light-emitting element 10, the green light-emitting element 10, and the red light-emitting element 10 can be sequentially transferred to each transfer area ST.

[0042] In the non-display area NA, a data driving circuit or a gate driving circuit may be provided, and lines for supplying control signals for controlling these driving circuits may be provided. Here, the control signals may include various timing signals including a clock signal, an input data enable signal, and a synchronization signal, and may be received through the pad portion PAD.

[0043] The pixel PXL can be driven by a pixel driving circuit. The pixel driving circuit can receive a driving voltage, an image signal (digital signal), a synchronization signal synchronized with the image signal, etc., and output an anode voltage and a cathode voltage of the light-emitting element 10 to drive multiple pixels. The driving voltage can be a high potential voltage EVDD. The cathode voltage can be a low potential voltage EVSS commonly applied to the pixel. The anode voltage can be a voltage corresponding to the pixel data value of the image signal. The pixel driving circuit can be arranged in the non-display area NA or below the display area AA.

[0044] Each pixel PXL may include multiple sub-pixels having different colors. For example, each of the multiple pixels may include a red sub-pixel having a light-emitting element 10 emitting red wavelength light, a green sub-pixel having a light-emitting element 10 emitting green wavelength light, and a blue sub-pixel having a light-emitting element 10 emitting blue wavelength light. The multiple pixels may also include a white pixel.

[0045] Reference Figure 2 and Figure 3 , multiple pixels PXL can be continuously arranged in the first direction (X-axis direction) and the second direction (Y-axis direction). Multiple sub-pixels of the same color can be arranged in the pixels of the display area AA. For example, each of the multiple pixels may include a first red sub-pixel in which a 1-1 light-emitting element 11a emitting red wavelength light is arranged, a second red sub-pixel in which a 1-2 light-emitting element 11b emitting red wavelength light is arranged, a first green sub-pixel in which a 2-1 light-emitting element 12a emitting green wavelength light is arranged, a second green sub-pixel in which a 2-2 light-emitting element 12b emitting green wavelength light is arranged, a first blue sub-pixel in which a 3-1 light-emitting element 13a emitting blue wavelength light is arranged, and a second blue sub-pixel in which a 3-2 light-emitting element 13b emitting blue wavelength light is arranged. 1-1 light-emitting element 11a, 2-1 light-emitting element 12a, and 3-1 light-emitting element 13a can be understood as main light-emitting elements. 1-2 light-emitting element 11b, 2-2 light-emitting element 12b, and 3-2 light-emitting element 13b can be understood as secondary light-emitting elements.

[0046] A sub-pixel may include at least one or more light-emitting elements, so when one light-emitting element becomes defective, the brightness of the sub-pixel may be adjusted by increasing the brightness of other light-emitting elements. However, the present disclosure is not necessarily limited thereto, and a sub-pixel may include only one light-emitting element.

[0047] A plurality of first electrodes 161 may be disposed below the light-emitting element 10 and may be selectively connected to a plurality of signal lines TL1 to TL6 via a connection portion 161 a. A high potential voltage may be applied to the pixel driving circuit via the signal lines TL1 to TL6. During the electrode patterning process, the signal lines TL1 to TL6 and the first electrodes 161 may be formed into an integrated electrode pattern.

[0048] For example, the first signal line TL1 can be connected to the anode of the first red sub-pixel, and the second signal line TL2 can be connected to the anode of the second red sub-pixel. The third signal line TL3 can be connected to the anode of the first green sub-pixel, and the fourth signal line TL4 can be connected to the anode of the second green sub-pixel. The fifth signal line TL5 can be connected to the anode of the first blue sub-pixel, and the sixth signal line TL6 can be connected to the anode of the second blue sub-pixel. When a sub-pixel includes only one light-emitting element, the number of signal lines TL can be reduced by half.

[0049] The second electrode 170 may be a cathode that is arranged in each row and applies a cathode voltage to the light-emitting elements 10 that are continuously arranged in the first direction (X-axis direction). A plurality of second electrodes 170 may be arranged to be spaced apart from each other in the second direction (Y-axis direction). A plurality of second electrodes 170 may be connected to the cathode voltage through the contact electrode 163. Each of the plurality of second electrodes 170 may be electrically connected to the contact electrode 163. However, the present disclosure is not necessarily limited thereto, and the second electrode 170 may not be divided into a plurality of second electrodes 170 and may be configured as one electrode layer and used as a common electrode.

[0050] Figure 4 It is along Figure 3 A cross-sectional view taken along line II' in FIG. Figure 5 It is along Figure 3 A cross-sectional view taken along line II-II'. Figure 6 It is along Figure 3 A cross-sectional view taken along line III-III'. Figure 7 is a cross-sectional view showing an example in which two light emitting elements are connected to a pixel driving circuit.

[0051] Reference Figures 3 to 5 According to the embodiment, the display device includes a plurality of first electrodes 161 and a contact electrode 163 provided on a substrate 110, a plurality of light emitting elements 10 provided on the plurality of first electrodes 161, a first optical layer 141 provided between the plurality of light emitting elements 10, and a second electrode 170 provided on the plurality of light emitting elements 10.

[0052] The substrate 110 may include a flexible plastic. For example, the substrate 110 may be manufactured as a single-layer or multi-layer substrate including a material selected from the group consisting of polyimide, polyethylene terephthalate, polyethylene naphthalate, polycarbonate, polyethersulfone, polyarylate, polysulfone, and cyclic olefin copolymer, but is not limited thereto. For example, the substrate 110 may be a ceramic substrate or a glass substrate.

[0053] The pixel driving circuit 20 may be provided in the display area AA on the substrate 110. The pixel driving circuit 20 may include a plurality of thin film transistors using an amorphous silicon semiconductor, a polysilicon semiconductor, or an oxide semiconductor.

[0054] The pixel driving circuit 20 may include at least one driving thin film transistor, at least one switching thin film transistor, and at least one storage capacitor. When the pixel driving circuit 20 includes multiple thin film transistors, it may be formed on the substrate 110 using a thin film transistor (TFT) manufacturing process. In an embodiment, the pixel driving circuit 20 may be a concept that collectively refers to multiple thin film transistors electrically connected to the light emitting element 10.

[0055] The pixel driving circuit 20 may be a driver manufactured on a single crystal semiconductor substrate 110 using a metal-oxide-silicon field-effect transistor (MOSFET) manufacturing process. The driver may include multiple pixel driving circuits to drive multiple sub-pixels. When the pixel driving circuit 20 is implemented as a driver, after providing an adhesive layer on the substrate 110, the driver may be mounted on the adhesive layer through a transfer process.

[0056] A buffer layer 121 covering the pixel driving circuit 20 may be provided on the substrate 110. The buffer layer 121 may include an organic insulating material (eg, photosensitive photoacrylic or photosensitive polyimide), but is not limited thereto.

[0057] The inorganic insulating material (such as silicon nitride (SiN)) can be stacked in a multilayer manner. x ), silicon oxide (SiO 2 ), etc.), or by stacking an organic insulating material and an inorganic insulating material in a multi-layer manner.

[0058] The insulating layer 122 may be provided on the buffer layer 121. The insulating layer 122 may include an organic insulating material (e.g., photosensitive photoacrylic or photosensitive polyimide), but is not limited thereto. The connecting wires RT1 and RT2 may be provided on the buffer layer 121. The connecting wires may include a plurality of connecting wires such as a first connecting wire RT1, a second connecting wire RT2, and the like. The connecting wires RT1 and RT2 may be connected to corresponding signal lines TL1 to TL6. The signal lines may include a first signal line TL1 to a sixth signal line TL6, but are not limited thereto. The connecting wires RT1 and RT2 may include a plurality of line patterns provided on different layers, with one or more insulating layers interposed between the different layers. The line patterns provided on different layers may be electrically connected through contact holes passing through the insulating layers.

[0059] A plurality of bank patterns 130 may be provided on the insulating layer 122. At least one light emitting element 10 may be provided on each bank pattern 130. For example, the first light emitting element 11 may be provided on the first bank pattern 130a, the second light emitting element 12 may be provided on the second bank pattern 130b, and the third light emitting element 13 may be provided on the third bank pattern 130c.

[0060] The bank pattern 130 may include an organic insulating material (eg, photosensitive acrylic or photosensitive polyimide), but is not limited thereto. The bank pattern 130 may guide the position where the light emitting element 10 is to be attached during the transfer process of the light emitting element 10. The bank pattern 130 may also be omitted.

[0061] The solder pattern 162 may be disposed on the first electrode 161. The solder pattern 162 may include indium (In), tin (Sn), or an alloy thereof, but is not limited thereto.

[0062] Each of the plurality of light-emitting elements 10 may be mounted on the solder pattern 162. One pixel may include three colors of light-emitting elements 10. The first light-emitting element 11 may be a red light-emitting element, the second light-emitting element 12 may be a green light-emitting element, and the third light-emitting element 13 may be a blue light-emitting element. Two light-emitting elements may be mounted in each sub-pixel.

[0063] The first optical layer 141 may cover a plurality of light emitting elements 10 and the dike pattern 130. Thus, the first optical layer 141 may cover the spaces between the plurality of light emitting elements 10 and the spaces between the plurality of dike patterns 130. The first optical layer 141 may be arranged to extend in a first direction (X) and to be spaced apart in a second direction (Y) to separate the pixels in the second direction. Thus, the first optical layer 141 may be separated between pixel rows. Here, a row may refer to a first direction. In addition, a pixel row consisting of a plurality of pixels arranged in a first direction may be referred to as a pixel group. Thus, the display panel may include a plurality of pixel groups arranged to be spaced apart from each other in the second direction. For example, since the first optical layer 141 arranged in the first direction is arranged around the pixels, and the plurality of first optical layers 141 arranged corresponding to the plurality of pixel groups are arranged to be spaced apart from each other in the second direction, one first optical layer 141 arranged around the pixels forming a row may be separated from another first optical layer 141 arranged around the pixels forming another row.

[0064] The first optical layer 141 may include an organic insulating material in which fine metal particles (eg, titanium dioxide particles) are dispersed. Light emitted from the plurality of light emitting elements 10 may be scattered by the fine metal particles dispersed in the first optical layer 141 and emitted to the outside.

[0065] The second electrode 170 may be provided on the plurality of light emitting elements 10. The second electrode 170 may be commonly connected to the plurality of pixels PXL. The second electrode 170 may be a thin electrode that transmits light. The second electrode 170 may be a transparent electrode material such as indium tin oxide (ITO), but is not necessarily limited thereto.

[0066] The second electrode 170 may extend in a first direction (X-axis direction) and may be spaced apart in a second direction (Y-axis direction). For example, one second electrode 170 may be formed to extend in the first direction, and a plurality of second electrodes 170 extending in the first direction may be spaced apart from each other in the second direction. In this case, the second electrodes 170 may be respectively arranged corresponding to pixels spaced apart from each other in the second direction. The second electrode 170 may include a first region 171 arranged on the upper surface of the light-emitting element 10 and the upper surface of the first optical layer 141, a second region 172 in contact with and electrically connected to the contact electrode 163, and a third region 173 arranged on the side surface of the first optical layer 141 and connecting the first region 171 and the second region 172.

[0067] Each of the plurality of second electrodes 170 may overlap the first optical layer 141 on a plane, and the third region 173 may cover an outer plane of the first optical layer 141 .

[0068] The second optical layer 142 may be an organic insulating material surrounding the first optical layer 141. The second optical layer 142 may be disposed on the insulating layer 122 together with the first optical layer 141. The first optical layer 141 and the second optical layer 142 may include the same material (eg, siloxane). For example, the first optical layer 141 may include titanium oxide (TiO x ) of siloxane, the second optical layer 142 may be a siloxane that does not contain titanium oxide (TiO x However, the present disclosure is not necessarily limited thereto, and the first optical layer 141 and the second optical layer 142 may be formed of the same material or may be formed of different materials.

[0069] According to the embodiment, since the second region 172 of the second electrode 170 is connected to the contact electrode 163 in an overall flat state, excessive stress is not concentrated at the connection position with the contact electrode 163. Therefore, cracks in the second electrode 170 can be effectively prevented.

[0070] The second optical layer 142 may cover the second region 172 and the third region 173 of the second electrode 170. The upper surface of the second optical layer 142 and the upper surface of the first region 171 of the second electrode 170 may form the same plane. In other words, the first region 171 and the second optical layer 142 may function as a planarization layer. Therefore, since there are no steps on the surface where the black matrix 190 is formed, the pattern of the black matrix 190 can be easily formed on the first optical layer 141 and the second optical layer 142. However, the present disclosure is not necessarily limited to this, and the upper surface of the second optical layer 142 and the upper surface of the second electrode 170 may have different heights.

[0071] The black matrix 190 may be an organic insulating material to which black pigment is added. The second electrode 170 may be in contact with the contact electrode 163 below the black matrix 190. Transmission holes 191 may be formed between the patterns of the black matrix 190, and light emitted from the light-emitting element 10 is emitted to the outside through the transmission holes 191. The transmission holes 191 may overlap with the light-emitting element 10 in the Z-axis direction, and a portion of the black matrix 190 may overlap with the first optical layer 141 in the Z-axis direction. Here, the Z-axis direction may be referred to as the third direction. The black matrix 190 can improve the problem of light from each of the adjacent light-emitting elements 10 being mixed by the first optical layer 141 and then emitted.

[0072] The capping layer 180 may be an organic insulating material covering the black matrix 190 and the second electrode 170. Figure 2 and Figure 3 In FIG, the configuration of the black matrix 190 and the cover layer 180 is omitted.

[0073] The contact electrode 163 is electrically connected to the first connection line RT1 disposed therebelow, and the first connection line RT1 can be connected to the pixel driving circuit 20. Therefore, a cathode voltage can be applied to the second electrode 170 through the contact electrode 163. The first electrode 161 can be electrically connected to the second connection line RT2. This will be described below.

[0074] Reference Figure 5 The contact electrode 163 and the signal lines TL1 to TL6 may be arranged on the same plane. The pixel driving circuit 20 may be arranged below the contact electrode 163 and the signal lines TL1 to TL6. When the pixel driving circuit 20 is a driving driver, a plurality of driving drivers may be arranged in the display panel.

[0075] The passivation layer 133 may expose the contact electrode 163 so that the contact electrode 163 and the second electrode 170 are electrically connected. In addition, the passivation layer 133 may insulate the signal lines TL2 to TL5 from the second electrode 170. Here, the passivation layer 133 may be formed of an inorganic material.

[0076] Reference Figure 6 The first electrode 161 may extend to one side surface 131 of the bank pattern 130 through the connection portion 161 a and may be electrically connected to the second connection line RT2 disposed on the insulating layer 122 .

[0077] The first electrode 161 , the connection portion 161 a , the signal line TL, and / or the connection lines RT1 and RT2 may include a single layer or multiple layers of a metal selected from titanium (Ti), molybdenum (Mo), and aluminum (Al).

[0078] The first electrode 161 or the signal line TL may be formed to have a metal stack structure in which a plurality of metal layers are formed using metal materials having different materials, thicknesses, etc. In this case, the first electrode 161, the connection portion 161a, and the signal line TL may be formed simultaneously through the same manufacturing process. Here, the thickness may refer to the width between one side and the other side of the metal layer arranged in the Z direction.

[0079] The first electrode 161 may include a first metal layer ML1 disposed below the solder pattern 162, a second metal layer ML2 disposed below the first metal layer ML1, a third metal layer ML3 disposed below the second metal layer ML2, and a fourth metal layer ML4 disposed below the third metal layer ML3. When the first electrode 161 is formed of the first metal layer ML1, the second metal layer ML2, the third metal layer ML3, and the fourth metal layer ML4, the first electrode 161 may be deposited in the order of fourth metal layer ML4->third metal layer ML3->second metal layer ML2->first metal layer ML1 and then patterned by performing a photolithography process and an etching process.

[0080] The first metal layer ML1 may be disposed to make contact with a lower portion of the solder pattern 162 and be electrically connected to the solder pattern 162 .

[0081] In addition, the first metal layer ML1 may include a transparent conductive oxide layer having excellent adhesive strength and being corrosion-resistant and acid-resistant, such as indium tin oxide (ITO) or indium zinc oxide (IZO). Here, the first metal layer ML1 may be referred to as an adhesive layer.

[0082] The second metal layer ML2 may be formed of a material having a different resistance value from the first metal layer ML1 and the third metal layer ML3. In this case, the second metal layer ML2 may be formed of a material having a lower light reflectivity than the third metal layer ML3 and a higher resistance value than the third metal layer ML3. For example, the second metal layer ML2 may include titanium (Ti) or molybdenum (Mo).

[0083] The third metal layer ML3 may be formed of a material having a higher light reflectivity than the first metal layer ML1. In this case, the third metal layer ML3 may be formed of a material having a higher light reflectivity than the second metal layer ML2. For example, the third metal layer ML3 may include aluminum (Al) or silver (Ag).

[0084] The light reflectivity of the third metal layer ML3 may be higher than that of each of the first and second metal layers ML1 and ML2 .

[0085] The fourth metal layer ML4 may be formed of the same material as the second metal layer ML2. For example, the fourth metal layer ML4 may include titanium (Ti) or molybdenum (Mo).

[0086] After forming the first metal layer ML1, a reflective opening OP may be formed in the first electrode 161. The reflective opening OP may be a region where only a portion of the third metal layer ML3 is exposed by removing the first and second metal layers ML1 and ML2. The reflective opening OP may have a form surrounding the solder pattern 162 on a plane and have a circular shape or a quadrilateral shape, but is not limited thereto.

[0087] Light emitted from the light emitting element 10 is reflected from the surface of the third metal layer ML3 exposed by the reflective opening OP, which may have an effect of increasing light efficiency of the display device.

[0088] The passivation layer 133 may be disposed on the first electrode 161 and the signal line TL and may include an opening hole 133a exposing the solder pattern 162. Here, the opening hole 133a exposing the solder pattern 162 may be referred to as a first opening hole. In this case, the reflective opening OP may be formed to surround the first opening hole.

[0089] The light-emitting element 10 may include a first-conductive-type semiconductor layer 10-1, an active layer 10-2 disposed on the first-conductive-type semiconductor layer 10-1, and a second-conductive-type semiconductor layer 10-3 disposed on the active layer 10-2. The first driving electrode 15 may be disposed under the first-conductive-type semiconductor layer 10-1, and the second driving electrode 14 may be disposed on the second-conductive-type semiconductor layer 10-3.

[0090] The light-emitting element 10 may be formed on a silicon wafer using a method such as metal organic chemical vapor deposition (MOCVD), chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), molecular beam epitaxy (MBE), hydride vapor phase epitaxy (HVPE), sputtering, or the like.

[0091] The first-conductive-type semiconductor layer 10-1 may be implemented with a compound semiconductor such as a III-V group or a II-VI group, and may be doped with a first dopant. The first-conductive-type semiconductor layer 10-1 may be formed of any one or more of semiconductor materials selected from those having a composition formula of Al x1 In y1 Ga (1-x1-y1) N(0 < x1 ≤ 1, 0 ≤ y1 ≤ 1, 0 ≤ x1 + y1 ≤ 1), InAlGaN, AlGaAs, GaP, GaAs, GaAsP, and AlGaInP, but is not limited thereto. When the first dopant is an n-type dopant such as Si, Ge, Sn, Se, Te, etc., the first-conductive-type semiconductor layer 10-1 may be an n-type nitride semiconductor layer. However, when the first dopant is a p-type dopant, the first-conductive-type semiconductor layer 10-1 may be a p-type nitride semiconductor layer.

[0092] The active layer 10-2 is a layer where electrons (or holes) injected through the first-conductive-type semiconductor layer 10-1 meet holes (or electrons) injected through the second-conductive-type semiconductor layer 10-3. As the electrons and holes recombine, the active layer 10-2 transitions to a lower energy level, and light having a wavelength corresponding thereto may be generated.

[0093] The active layer 10-2 may have any one of a single-well structure, a multi-well structure, a single quantum well structure, a multi-quantum well (MQW) structure, a quantum dot structure, and a quantum wire structure, but the structure of the active layer 10-2 is not limited thereto. The active layer 10-2 may generate light in the visible light wavelength band. For example, the active layer 10-2 may output light of any one of a blue wavelength band, a green wavelength band, and a red wavelength band.

[0094] The second-conductivity-type semiconductor layer 10-3 may be provided on the active layer 10-2. The second-conductivity-type semiconductor layer 10-3 may be implemented with a compound semiconductor such as a III-V group or II-VI group semiconductor, and may be doped with a second dopant. The second-conductivity-type semiconductor layer 10-3 may be formed of any one or more of semiconductor materials selected from those having a compositional formula In x2 Al y2 G a1-x2-y2 N(0 < x2 ≤ 1, 0 ≤ y2 ≤ 1, 0 ≤ x2 + y2 ≤ 1), AlInN, AlGaAs, GaP, GaAs, GaAsP, and AlGaInP, but is not limited thereto. When the second dopant is a p-type dopant such as Mg, Zn, Ca, Sr, Ba, etc., the second-conductivity-type semiconductor layer 10-3 doped with the second dopant may be a p-type semiconductor layer. However, when the second dopant is an n-type dopant, the second-conductivity-type semiconductor layer 10-3 may be an n-type nitride semiconductor layer.

[0095] In an embodiment, although a vertical structure in which the driving electrodes 14 and 15 are provided on the top and bottom of the light-emitting structure is described, the light-emitting element may have a lateral structure or a flip-chip structure in addition to the vertical structure.

[0096] Referring to Figure 7 , the main light-emitting element 12a and the sub-light-emitting element 12b of the sub-pixel may be provided on the bank pattern 130. The second light-emitting element 12 will be described as an example. The 1-1 electrode 161-1 connected to the main light-emitting element 12a may extend to one side surface of the bank pattern 130 and may be electrically connected to the 2-1 connection line RT21 provided therebelow. The 1-2 electrode 161-2 connected to the sub-light-emitting element 12b may extend to the other side surface of the bank pattern 130 and may be electrically connected to the 2-2 connection line RT22 provided therebelow.

[0097] The pixel driving circuit 20 may apply an anode voltage to the main light-emitting element 12a through the 2-1 connection line RT21 and apply an anode voltage to the sub-light-emitting element 12b through the 2-2 connection line RT22. The pixel driving circuit 20 may apply a cathode voltage to the main light-emitting element 12a and the sub-light-emitting element 12b through the first connection line RT1 and the second electrode 170.

[0098] The pixel driving circuit 20 may adjust the brightness by driving only the main light-emitting element 12a or may adjust the brightness by driving both the main light-emitting element 12a and the sub-light-emitting element 12b simultaneously. When the main light-emitting element 12a becomes dim, the brightness may be adjusted by driving only the sub-light-emitting element 12b.

[0099] Figure 8 is a view showing a display device according to another embodiment of the present disclosure. Figure 9 It is along Figure 8 A cross-sectional view taken along line IV-IV'.

[0100] Reference Figure 8 and Figure 9 , the second electrode 170 may be electrically connected to the contact electrode 163 through the contact hole TH1 formed in the second optical layer 142. The second optical layer 142 may include a contact hole TH1 exposing the contact electrode 163. The second electrode 170 inserted into the contact hole TH1 of the second optical layer 142 may make contact with the upper surface of the contact electrode 163. The contact hole TH1 may be formed in the outer region of the pixel.

[0101] Figure 10A is a view illustrating a display device according to still another embodiment of the present disclosure. Figure 10B yes Figure 10A Magnified view of area B in FIG. Figure 11 It is along Figure 10B A cross-sectional view taken along line AA' in FIG.

[0102] Figures 12A to 12G 1 is a diagram illustrating a manufacturing process of a display device according to an embodiment of the present disclosure.

[0103] In the following, due to Figures 1 to 9 The contents of the configurations identical to those included in the embodiments described herein are repeated and will be omitted, and the description will focus on other features.

[0104] Reference Figure 10A and Figure 10B The display panel may include a display area AA for displaying an image and a non-display area NA for not displaying an image. Various lines and driving circuits may be mounted in the non-display area NA, and a pad portion PC for connection to an integrated circuit, printed circuit, etc. may be provided. A bending area BE and a connection line area CL may be provided between the non-display area NA and the pad portion PC.

[0105] In the non-display area NA, a data driving circuit or a gate driving circuit may be provided, and lines for supplying control signals for controlling these driving circuits may be provided. Here, the control signals may include various timing signals including a clock signal, an input data enable signal, and a synchronization signal, and may be received from the pad portion PC via lines provided in the connection line area CL.

[0106] Reference Figure 11According to another embodiment, a display device includes a plurality of first electrodes 161 and a contact electrode 163 arranged on a substrate 110, a plurality of light emitting elements 10 arranged on the plurality of first electrodes 161, a first optical layer 141 arranged between the plurality of light emitting elements 10, and a second electrode 170 arranged on the plurality of light emitting elements 10.

[0107] An adhesive layer AD may be provided on the substrate 110. Areas where the adhesive layer AD is removed may exist in the non-display area NA or the bending area BE. This is because the more organic layers present in the bending area BE, the higher the risk of damage or breakage of the organic layers in the bending area BE. For example, the adhesive layer AD may be selected from any one of an adhesive polymer, epoxy resin, ultraviolet (UV) resin, polyimide-based, acrylate-based, urethane-based, and polydimethylsiloxane (PDMS), but is not limited thereto.

[0108] The pixel driving circuit 20 implemented as a driving driver may be disposed on the adhesive layer AD in the display area AA.

[0109] A protective layer 120 may be formed on the adhesive layer AD to protect the pixel driving circuit 20. The protective layer 120 may cover at least a portion or all of the side surfaces of the pixel driving circuit 20 and a portion of the upper surface of the pixel driving circuit 20. The protective layer 120 may cover the entire substrate 110 and a portion of the pad portion PC. The protective layer 120 may include an organic insulating material (e.g., photosensitive photoacrylic or photosensitive polyimide), but is not limited thereto.

[0110] A buffer layer 121 covering the pixel driving circuit 20 may be provided on the protective layer 120. When the protective layer 120 covers only a portion of the pad portion PC, a side surface of the protective layer 120 may be covered by the buffer layer 121.

[0111] The insulating layer 122 may be provided on the buffer layer 121. The connecting wire RT may be provided on the buffer layer 121. The connecting wire RT may be connected to the corresponding signal line TL. The connecting wires RT1 and RT2 may include a plurality of line patterns provided on different layers, with one or more insulating layers interposed between the different layers. The line patterns provided on different layers may be electrically connected via contact holes passing through the insulating layers. The third connecting wire RT3 may be provided on the buffer layer 121, and the signal from the pad portion PC may be transmitted to the display area AA via the third connecting wire RT3. The signal transmitted via the third connecting wire RT3 may be supplied to the pixel driving circuit 20 via the connecting wire RT and the signal line TL.

[0112] A plurality of bank patterns 130 may be provided on the insulating layer 122. At least one light emitting element 10 may be provided on each bank pattern 130. For example, referring to Figure 3, the first light emitting element 11 may be disposed on the first bank pattern 130a, the second light emitting element 12 may be disposed on the second bank pattern 130b, and the third light emitting element 13 may be disposed on the third bank pattern 130c.

[0113] The first electrode 161 may be provided on the bank pattern 130. In an embodiment, the first electrode 161 may include a plurality of metal layers ML2, ML3, and ML4 in addition to the first metal layer ML1 in a formation process, and the first metal layer ML1 may be provided only in a region overlapping the first electrode 161 and the light-emitting element 10 in a separate process. An opening OP may be provided in the first electrode 161. In an embodiment, the opening OP may be formed by removing the second metal layer ML2. The first metal layer ML1 may not be provided on the pad portion PC. In addition, the first metal layer ML1 may not be provided in a region other than the region overlapping the light-emitting element 10.

[0114] The solder pattern 162 may be provided on the first electrode 161. The solder pattern 162 may include indium (In), tin (Sn) or an alloy thereof, but is not limited thereto. The solder pattern 162 may include a first portion 162a and a second portion 162b. The first portion 162a may include indium (In), and the second portion 162b may include gold (Au). When the light-emitting element 10 is transferred, the first portion 162a and the second portion 162b may be bonded by pressure and then eutectic bonded by applying heat. When the second portion 162b is subjected to pressure, a portion of the second portion 162b may cover at least a portion or all of the side surface of the first portion 162a. In this case, since the contact area between the first portion 162a and the second portion 162b increases, the bonding strength may be increased and the transmission of electrical signals may be improved.

[0115] A plurality of light emitting elements 10 may be individually mounted on the solder pattern 162 .

[0116] The 1-1 optical layer 141a may cover the plurality of light emitting elements 10 and the bank patterns 130. Therefore, the 1-1 optical layer 141a may cover the spaces between the plurality of light emitting elements 10 and the spaces between the plurality of bank patterns 130. The arrangement of the 1-1 optical layer 141a on a plane is the same as that of the first optical layer 141 on a plane.

[0117] The second electrode 170 may be disposed on the plurality of light emitting elements 10. The second electrode 170 may be commonly connected to the plurality of pixels PXL.

[0118] The 1-2 optical layer 141b may be disposed to overlap the 1-1 optical layer 141a on the second electrode 170. The 1-2 optical layer 141b may be disposed on the second electrode 170 to increase the amount of light emitted to the front surface.

[0119] The second optical layer 142 may be an organic insulating material surrounding the first optical layer 141. The second optical layer 142 may be disposed on the insulating layer 122 together with the first optical layer 141. The second optical layer 142 may be disposed on the display area AA.

[0120] The black matrix 190 may be disposed on the 1-2 optical layer 141b, the second electrode 170, and the second optical layer 142. Transmission holes may be formed between patterns of the black matrix 190, and light emitted from the light emitting element 10 is emitted to the outside through the transmission holes.

[0121] The capping layer 180 may be an organic insulating material covering the black matrix 190 and the second electrode 170. Figure 11 , the configuration of the cover layer 180 is omitted.

[0122] The circuit component SB may be disposed on the seventh signal line TL7 in the pad portion PC. The circuit component SB may be attached to the pad portion PC in the form of a chip on panel (COP) or a chip on film (COF).

[0123] As described above, the first metal layer ML1 may be formed only in a region overlapping with the light emitting element 10. When the first metal layer ML1 includes indium tin oxide (ITO), since adhesive strength with the 1-1st optical layer 141a and / or the second optical layer 142 is reduced, a lifting phenomenon of the 1-1st optical layer 141a and / or the second optical layer 142 on the first metal layer ML1 may occur.

[0124] In addition, in the pad portion PC, when the circuit component SB is attached to the seventh signal line TL7 through an adhesive containing conductive balls, such as anisotropic conductive film (ACF), a problem of increased contact resistance with the first metal layer ML1 may occur.

[0125] Furthermore, when wet etching is performed to form an opening OP in the first metal layer ML1 including indium tin oxide (ITO) disposed on the bank pattern 130, a problem may occur in which the crystalline indium tin oxide (ITO) is not etched. To prevent this problem, the first metal layer ML1 may be formed only in a region overlapping the light emitting element 10.

[0126] Figures 12A to 12G It shows that according to Figure 11 FIG. 1 is a diagram illustrating a manufacturing process of a display device according to an embodiment of the present disclosure. Figures 12A to 12G The figures are used to describe the process, and unnecessary components such as the detailed electrode connection structure and substrate 110 are omitted. Each figure shows a cross-sectional view of the display area AA and the pad portion PC of the display device. The non-display area NA has the same manufacturing process as the pad portion PC.

[0127] Reference Figure 12A A first electrode 161 is formed on the bank pattern 130 formed on the insulating layer 122 in the display area AA. A seventh signal line TL7 is formed on the insulating layer 122 in the pad portion PC. The first electrode 161 and the seventh signal line TL7 may be formed in the same process and may include a plurality of metal layers ML2, ML3, and ML4 in addition to the first metal layer ML1.

[0128] Reference Figure 12B , an opening OP is formed by removing the second metal layer ML2 included in the first electrode 161 in the display area AA using an etching process.

[0129] Reference Figure 12C and Figure 12D , a photoresist PR is applied to the entire surface of the substrate 110. Furthermore, the photoresist PR located in the region where the first metal layer ML1 of the display area AA will be formed and in a portion of the pad portion PC is patterned. Specifically, when exposure is performed with a difference in hardening degree between the surface and the interior during the photolithography process, an anisotropic shape can be formed after development.

[0130] The patterned area of ​​the photoresist PR applied to the display area AA may have an inverted step. The patterned area of ​​the photoresist PR applied to the pad portion PC may have a circular or concave shape. Thereafter, a metal layer having the same composition as the first metal layer ML1 (i.e., a first metal forming layer) is provided on the entire surface of the patterned area. A portion of the metal layer having the same composition as the first metal layer ML1 is provided on the first electrode 161 in the area where the photoresist PR is patterned in the display area AA and is referred to as the first metal layer ML1. In the pad portion PC, the first metal layer ML1 is provided on the entire surface of the pad portion PC.

[0131] Reference Figure 12E A metal layer (ie, a solder pattern forming layer) having the same composition as the first portion 162a of the solder pattern is provided in the display area AA and the pad portion PC. The first portion 162a of the solder pattern may be provided on the first metal layer ML1 in the area where the photoresist PR is patterned in the display area AA.

[0132] Reference Figure 12F When the photoresist PR coated on the substrate 110 is removed through a stripping process, a metal layer having the same composition as the first metal layer ML1 disposed on the photoresist PR and a metal layer having the same composition as the first portion 162a of the solder pattern may be removed together with the photoresist PR.

[0133] Reference Figure 12G, the light emitting element 10 is transferred to the first portion 162a of the solder pattern. The second portion 162b of the solder pattern may be provided below the light emitting element 10. When the light emitting element 10 is transferred, pressure is applied, and in this case, the first portion 162a may be pressed by the pressure and cover at least a portion of the side surface of the first metal layer ML1. Figures 12A to 12G In one embodiment of the present disclosure shown, the first metal layer ML1 may be disposed on the first electrode 161 in a region overlapping with the light emitting element 10 , and may not be disposed in other regions.

[0134] The manufacturing process of the display device according to the embodiment of the present disclosure further includes the following steps: providing a 1-1 optical layer 141a surrounding the light emitting element 10; providing a second electrode 170 on the light emitting element 10 and the 1-1 optical layer 141a; and providing a 1-2 optical layer 141b on the second electrode 170. These steps are not included in the Figures 12A-12G Shown in.

[0135] In the embodiment, although the vertical structure in which the driving electrodes 14 and 15 are provided at the top and bottom of the light emitting structure is described, the light emitting element may have a lateral structure or a flip-chip structure in addition to the vertical structure.

[0136] The display device according to the embodiments of the present disclosure can be applied to mobile devices, video phones, smart watches, watch phones, wearable devices, foldable devices, rollable devices, bendable devices, flexible devices, curved devices, sliding devices, variable devices, electronic notebooks, electronic books, portable multimedia players (PMPs), personal digital assistants (PDAs), MP3 players, mobile medical devices, desktop PCs, laptop computers, netbook computers, workstations, navigation systems, vehicle display devices, cinema display devices, televisions, wallpaper devices, signage devices, gaming devices, laptop computers, monitors, cameras, camcorders, home appliances, etc. In addition, the display device according to one or more embodiments of the present disclosure can be applied to organic light-emitting lighting devices or inorganic light-emitting lighting devices.

[0137] The display device according to various embodiments of the present disclosure can be described as follows.

[0138] According to one embodiment of the present disclosure, a display device may include: an insulating layer arranged on a substrate; a dam pattern arranged on the insulating layer; a first electrode comprising a plurality of metal layers arranged on the dam pattern; a first metal layer arranged on the first electrode; a solder pattern arranged on the first metal layer; a light-emitting element arranged on the solder pattern; and a second electrode arranged on the light-emitting element, wherein the first metal layer is arranged only in an area overlapping with the light-emitting element.

[0139] The display device according to one embodiment of the present disclosure may further include a first optical layer surrounding the light emitting element.

[0140] According to the display device of one embodiment of the present disclosure, the plurality of metal layers included in the first electrode may sequentially include a second metal layer, a third metal layer, and a fourth metal layer.

[0141] According to a display device of one embodiment of the present disclosure, the solder pattern may include a first portion disposed on the first metal layer and a second portion disposed on the first portion, wherein the first portion covers a side surface of the first metal layer, and wherein the first portion contains indium and the second portion contains gold.

[0142] The display device of one embodiment of the present disclosure may further include a second optical layer disposed on the second electrode, wherein the second optical layer has the same composition as the first optical layer.

[0143] The display device of one embodiment of the present disclosure may further include: an adhesive layer arranged between the substrate and the insulating layer; a pixel driving circuit arranged on the adhesive layer; a buffer layer arranged on the pixel driving circuit; and a plurality of connecting lines arranged between the buffer layer and the insulating layer, wherein the pixel driving circuit is connected to the plurality of connecting lines, and the plurality of connecting lines are electrically connected to the first electrode.

[0144] According to the display device of one embodiment of the present disclosure, an opening may be formed at a position of the first electrode that does not overlap with the first metal layer.

[0145] According to the display device of one embodiment of the present disclosure, the opening may be provided to surround the solder pattern.

[0146] According to the display device of one embodiment of the present disclosure, the first metal layer may include indium tin oxide or indium zinc oxide.

[0147] A manufacturing method of a display device according to an embodiment of the present disclosure may include: setting an insulating layer on a substrate; setting a dam pattern on the insulating layer in a display area; setting a first electrode including multiple metal layers on the dam pattern; forming an opening in the first electrode; setting a first metal layer on the first electrode between the openings; setting a solder pattern on the first metal layer; setting a light-emitting element on the solder pattern, the light-emitting element overlapping with the first metal layer; and setting a second electrode on the light-emitting element.

[0148] The method for manufacturing a display device according to an embodiment of the present disclosure may further include providing a first optical layer surrounding the light emitting element before providing the second electrode on the light emitting element.

[0149] The method for manufacturing a display device according to an embodiment of the present disclosure may further include, after providing a second electrode on the light emitting element, providing a second optical layer on the second electrode.

[0150] According to a method for manufacturing a display device according to an embodiment of the present disclosure, the plurality of metal layers may include a second metal layer, a third metal layer, and a fourth metal layer.

[0151] According to a manufacturing method of a display device according to an embodiment of the present disclosure, setting a first metal layer may include: a process of forming a photoresist on an insulating layer, a first electrode and a dam pattern; a process of patterning the photoresist to expose a portion of the first electrode where the first metal layer is formed; a process of sequentially forming a first metal forming layer and a solder pattern forming layer on the photoresist and the first electrode; and a process of performing a stripping process to remove the photoresist together with the first metal forming layer and the solder pattern forming layer on the photoresist, wherein the first metal forming layer on the first electrode is the first metal layer.

[0152] According to the method for manufacturing a display device according to one embodiment of the present disclosure, the opening may be formed at a position of the first electrode that does not overlap with the first metal layer.

[0153] According to the method of manufacturing a display device according to one embodiment of the present disclosure, the opening may be formed to surround the solder pattern.

[0154] Effects of the present disclosure are not limited to the above-mentioned effects, and other effects that are not mentioned will be clearly understood by those having ordinary skill in the art from the above-mentioned detailed description.

[0155] Although the embodiments of the present disclosure have been described in more detail with reference to the accompanying drawings, the present disclosure is not necessarily limited to the embodiments, and various modifications may be made without departing from the technical spirit of the present disclosure. Therefore, the embodiments disclosed in the present disclosure are not intended to limit but to describe the technical spirit of the present disclosure, and the scope of the technical spirit of the present disclosure is not limited by these embodiments. Therefore, it should be understood that the above-mentioned embodiments are illustrative and non-restrictive in all aspects.

Claims

1. A display device, comprising: An insulating layer, disposed on the substrate; a bank pattern, disposed on the insulating layer; a first electrode including a plurality of metal layers disposed on the bank pattern; A first metal layer, disposed on the first electrode; a solder pattern, disposed on the first metal layer; a light emitting element, disposed on the solder pattern; as well as A second electrode is disposed on the light emitting element, The first metal layer is only arranged in a region overlapping with the light emitting element. 2 . The display device according to claim 1 , further comprising a first optical layer surrounding the light emitting element.

3. The display device according to claim 1, wherein: The plurality of metal layers included in the first electrode sequentially include a second metal layer, a third metal layer, and a fourth metal layer.

4. The display device according to claim 1, wherein: The solder pattern includes a first portion disposed on the first metal layer and a second portion disposed on the first portion, wherein the first portion covers the side surface of the first metal layer, and The first portion contains indium and the second portion contains gold.

5. The display device according to claim 2, further comprising a second optical layer, wherein the second optical layer is disposed on the second electrode. in, The second optical layer has the same composition as the first optical layer.

6. The display device according to claim 1, further comprising: An adhesive layer, disposed between the substrate and the insulating layer; A pixel driving circuit is arranged on the adhesive layer; A buffer layer, disposed on the pixel driving circuit; as well as A plurality of connecting wires are arranged between the buffer layer and the insulating layer, Wherein, the pixel driving circuit is connected to the plurality of connecting lines, and The plurality of connection lines are electrically connected to the first electrode.

7. The display device according to claim 1, wherein: An opening is formed at a position of the first electrode that does not overlap with the first metal layer.

8. The display device according to claim 7, wherein: The opening is provided to surround the solder pattern.

9. The display device according to claim 1, wherein: The first metal layer includes indium tin oxide or indium zinc oxide.

10. A method for manufacturing a display device, comprising: providing an insulating layer on the substrate; providing a bank pattern on the insulating layer in a display area; disposing a first electrode including a plurality of metal layers on the bank pattern; forming an opening in the first electrode; disposing a first metal layer on the first electrode between the openings; disposing a solder pattern on the first metal layer; Disposing a light emitting element on the solder pattern, wherein the light emitting element overlaps the first metal layer; as well as A second electrode is provided on the light emitting element. 11 . The method according to claim 10 , further comprising, before disposing the second electrode on the light emitting element, disposing a first optical layer surrounding the light emitting element. 12 . The method according to claim 11 , further comprising, after disposing the second electrode on the light emitting element, disposing a second optical layer on the second electrode.

13. The method according to claim 10, wherein: The plurality of metal layers include a second metal layer, a third metal layer, and a fourth metal layer.

14. The method according to claim 10, wherein: Providing the first metal layer includes: forming a photoresist on the insulating layer, the first electrode and the bank pattern; The process of patterning the photoresist to expose a portion of the first electrode where the first metal layer is formed; A process of sequentially forming a first metal forming layer and a solder pattern forming layer on the photoresist and the first electrode; and A process of performing a lift-off process to remove the photoresist together with the first metal-forming layer and the solder pattern-forming layer on the photoresist, wherein the first metal-forming layer on the first electrode is the first metal layer.

15. The method according to claim 10, wherein: The opening is formed at a position of the first electrode that does not overlap with the first metal layer.

16. The method according to claim 10, wherein: The opening is formed to surround the solder pattern.

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