Display device and manufacturing method thereof

Abstract

The invention provides a display device and a manufacturing method thereof. A display device according to an embodiment includes: a substrate including a display area; a power line disposed in the display area on the substrate and including a first metal layer and a first transparent conductive layer on the first metal layer; an insulating layer disposed on the power line and including a first hole exposing a portion of the first transparent conductive layer; a pad electrode disposed on the insulating layer and including a second transparent conductive layer in contact with the first transparent conductive layer in a region where the first hole is located; a pixel definition film disposed on the pad electrode and including a second hole exposing a portion of the pad electrode; and a common electrode disposed on the pixel definition film and in contact with the pad electrode in a region where the second hole is located. The first transparent conductive layer has a narrower width than the first metal layer, and an end of the first transparent conductive layer is spaced apart from an end of the first metal layer by a first distance at one end of the power line.

Description

Technical Field

[0001] Embodiments of the present invention relate to a display device and a method for manufacturing the same. Background Art

[0002] With the development of multimedia, the importance of display devices has gradually increased. Accordingly, various display devices including light emitting display devices are being developed. Summary of the invention

[0003] The technical problem to be solved by the present invention is to provide a display device capable of preventing or reducing a voltage drop of a pixel voltage and a manufacturing method thereof.

[0004] The technical problems to be solved by the present invention are not limited to the technical problems mentioned above, and ordinary technicians in the technical field to which the present invention belongs can clearly understand other technical problems not mentioned through the following description.

[0005] A display device according to an embodiment includes: a substrate including a display area; a power line arranged in the display area on the substrate and including a first metal layer and a first transparent conductive layer on the first metal layer; an insulating layer arranged on the power line and including a first hole exposing a portion of the first transparent conductive layer; a pad electrode arranged on the insulating layer and including a second transparent conductive layer in contact with the first transparent conductive layer in a region where the first hole is located; a pixel definition film arranged on the pad electrode and including a second hole exposing a portion of the pad electrode; and a common electrode arranged on the pixel definition film and in contact with the pad electrode in a region where the second hole is located. The first transparent conductive layer has a narrower width than the first metal layer, and at one end of the power line, an end of the first transparent conductive layer is spaced a first distance from an end of the first metal layer.

[0006] In one embodiment, the first distance may be greater than 0.1 μm.

[0007] In one embodiment, the first distance may be 0.1 μm to 0.2 μm.

[0008] In one embodiment, the first transparent conductive layer and the second transparent conductive layer may include one or more elements that are the same as each other.

[0009] In one embodiment, the first transparent conductive layer and the second transparent conductive layer may include a transparent conductive oxide containing indium (In).

[0010] In one embodiment, the first transparent conductive layer may be formed of indium tin oxide (ITO), indium zinc oxide (IZO) or indium gallium zinc oxide (IGZO), and the second transparent conductive layer may be formed of indium tin oxide (ITO).

[0011] In one embodiment, in the width direction of the power line, the first metal layer may protrude toward both sides of the first transparent conductive layer.

[0012] In an embodiment, the first metal layer may have a multi-layered structure including a first layer including a first metal, a second layer disposed on the first layer and including a second metal, and a third layer disposed on the second layer and including a third metal.

[0013] In one embodiment, the first metal and the third metal may be titanium (Ti), and the second metal may be aluminum (Al).

[0014] In one embodiment, the pad electrode may further include: a second metal layer disposed on the second transparent conductive layer; and a third transparent conductive layer disposed on the second metal layer.

[0015] In one embodiment, the second transparent conductive layer and the third transparent conductive layer may include indium tin oxide (ITO), and the second metal layer may include silver (Ag).

[0016] In one embodiment, the display device may further include: a panel circuit layer, arranged on the substrate and including the transistor and the power line located in the display area; a light-emitting element layer, arranged in the display area on the panel circuit layer, and including a pixel electrode arranged in the same layer as the pad electrode and separated from the pad electrode, a light-emitting layer arranged between the pixel electrode and the common electrode, the common electrode and the pixel definition film; and an encapsulation layer, arranged on the light-emitting element layer.

[0017] In one embodiment, the pixel definition film may form an opening in a region where the pixel electrode overlaps with the light-emitting layer in the light-emitting region to expose the pixel electrode.

[0018] In one embodiment, the display area may further include a non-luminous area around the luminous area, the common electrode may be arranged in the entire display area, and the pad electrode and the second hole may be located in the non-luminous area.

[0019] In one embodiment, the display device may further include: at least one common layer disposed between the pixel definition film and the common electrode and overlapping the pad electrode, wherein the second hole may penetrate the pixel definition film and the at least one common layer.

[0020] A method for manufacturing a display device according to an embodiment includes the following steps: forming a multi-layer conductive film by sequentially forming a first metal layer and a first transparent conductive layer on a substrate; arranging a mask on a portion of the conductive film; forming a power line by sequentially etching the first transparent conductive layer and the first metal layer using the mask; forming an insulating layer on the power line, and forming a first hole in the insulating layer to expose a portion of the first transparent conductive layer; forming a pad electrode on the insulating layer that overlaps with the power line and contacts the first transparent conductive layer in a region where the first hole is located; forming a pixel definition film and at least one common layer on the pad electrode, and forming a second hole in the pixel definition film and the at least one common layer to expose a portion of the pad electrode; and forming a common electrode on the pixel definition film that overlaps with the pad electrode and contacts the pad electrode in a region where the second hole is located. The step of etching the first transparent conductive layer may include the following steps: over-etching the first transparent conductive layer by an amount greater than the shrinkage amount of the mask generated in the process of etching the first transparent conductive layer and the first metal layer.

[0021] In one embodiment, the first transparent conductive layer may have a width smaller than that of the mask, and may be etched into a pattern in which an upper surface thereof is completely blocked by the mask.

[0022] In one embodiment, the first transparent conductive layer may be etched to have a lateral deviation amount that is greater than a lateral reduction amount of the mask by 0.1 μm or more.

[0023] In one embodiment, the pad electrode may include a second transparent conductive layer contacting the first transparent conductive layer, and the first transparent conductive layer and the second transparent conductive layer may be formed using transparent conductive oxides including one or more elements identical to each other.

[0024] In one embodiment, the first transparent conductive layer may be formed of indium tin oxide (ITO), indium zinc oxide (IZO), or indium gallium zinc oxide (IGZO), and the second transparent conductive layer may be formed of indium tin oxide (ITO).

[0025] Details of other embodiments are included in the detailed description and accompanying drawings.

[0026] According to the display device and the manufacturing method thereof of the embodiment, the common electrode can be connected to the power line with a low resistance through the pad electrode, thereby preventing or reducing the voltage drop of the pixel voltage supplied to the common electrode.

[0027] In an embodiment, the power line may include a first metal layer and a first transparent conductive layer on the first metal layer, and the pad electrode may include a second transparent conductive layer in contact with the first transparent conductive layer. In an embodiment, the first transparent conductive layer has a narrower width than the first metal layer and may be located inside the first metal layer when viewed on a plane. Thus, in the process of forming the power line, the first transparent conductive layer of the power line is stably covered by the mask, thereby preventing or reducing byproducts that may be generated from the first transparent conductive layer, and improving the yield of the display device.

[0028] In one embodiment, the first transparent conductive layer may be formed using a material that can reduce and / or minimize the contact resistance between the power line and the pad electrode. For example, the first transparent conductive layer and the second transparent conductive layer may contain at least one of the same elements, and may contain transparent conductive oxides that are the same as or different from each other. Thus, the voltage drop of the pixel voltage supplied to the common electrode can be more effectively prevented or reduced.

[0029] The effects according to the embodiment are not limited to the above-exemplified contents, and more various effects are included in this specification. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 is a plan view showing a display device according to an embodiment.

[0031] Figure 2 is a plan view showing a display panel according to an embodiment.

[0032] Figure 3 A portion of a display area according to an embodiment is shown.

[0033] Figure 4 is a cross-sectional view showing a display panel according to an embodiment.

[0034] Figure 5 is a cross-sectional view showing a power line, a pad electrode, and a common electrode according to an embodiment.

[0035] Figure 6 is a cross-sectional view showing a display panel according to an embodiment.

[0036] Figures 7 to 18 is a cross-sectional view illustrating a method for manufacturing a display device according to an embodiment.

[0037] Description of Reference Numerals 100: Display device 110: Display panel AE: pixel electrode CE: common electrode CML: Common Layer DA: Display Area EA: Light Emitting Area EL: Light Emitting Element EML: Emission Layer ENL: Encapsulation Layer H1, H2: first hole, second hole INS1~INS5: First insulation layer~fifth insulation layer LDP: pad electrode LEL: light emitting element layer M: Mask MTL1, MTL2: first metal layer, second metal layer NEA: Non-Emitting Area PCL: Panel Circuit Layer PDL: Pixel Definition Film PX: Pixel SCDL: Conductive film SUB: Substrate TCL1~TCL3: first transparent conductive layer~third transparent conductive layer TR: Transistor VSL: Power Line DETAILED DESCRIPTION

[0038] The advantages and features of the present invention and the methods for achieving the advantages and features will become clear with reference to the accompanying drawings and the embodiments described in detail below. However, the present invention is not limited to the embodiments disclosed below, but can be implemented in a variety of different forms. The present embodiments are provided only to make the disclosure of the present invention complete and to fully inform the scope of the invention to those with ordinary knowledge in the technical field to which the present invention belongs. The present invention is defined only by the scope of the claims.

[0039] When an element or layer is referred to as being "on" another element or layer, all situations are included, which are immediately above the other element or layer or with other layers or other elements sandwiched therebetween. Throughout the specification, the same reference numerals represent the same constituent elements. The shapes, sizes, ratios, angles, quantities, etc. disclosed in the drawings used to illustrate the embodiments are exemplary, and therefore the present invention is not limited to the matters illustrated.

[0040] Each feature of the multiple embodiments of the present invention may be partially or completely combined or combined with each other, and may be technically linked and driven in a variety of ways. The various embodiments may be implemented independently of each other or together in an associated relationship.

[0041] Hereinafter, specific embodiments will be described with reference to the accompanying drawings.

[0042] Figure 1 is a plan view showing a display device 100 according to an embodiment.

[0043] Reference Figure 1As a device for displaying moving images or still images, the display device 100 can be used not only as a display screen of portable electronic devices such as mobile phones, smart phones, tablet personal computers, smart watches, watch phones, mobile communication terminals, electronic notebooks, electronic books, portable multimedia players (PMP: portable multimedia player), navigators, ultra-portable PCs (UMPC: Ultra Mobile PC), but also as a display screen of various products such as televisions, notebook computers, monitors, billboards, and Internet of Things (IOT: internet of things) devices. These are only proposed as embodiments, and the display device 100 can also be applied to other electronic devices.

[0044] In one embodiment, the display device 100 may be a light-emitting display device such as an organic light-emitting display device including an organic light-emitting diode, a quantum dot light-emitting display device including a quantum dot light-emitting layer, an inorganic light-emitting display device including an inorganic semiconductor, or an ultra-small light-emitting display device including an ultra-small light-emitting diode such as a micro light-emitting diode (micro LED) or a nano light-emitting diode (nano LED), but is not limited thereto. For example, the display device 100 may also be a display device of other types other than the light-emitting display device. Hereinafter, an embodiment in which the display device 100 is a light-emitting display device (e.g., an organic light-emitting display device) is disclosed.

[0045] The display device 100 may include a display panel 110 including pixels PX, and a first driving unit 120 and a second driving unit 130 for supplying driving signals to the pixels PX. The display device 100 may also include additional components. For example, the display device 100 may also include: a power supply unit for supplying power supply voltage to the pixels PX, the first driving unit 120, and the second driving unit 130; and a timing control unit for controlling the operation of the first driving unit 120 and the second driving unit 130.

[0046] The display panel 110 may include a display area DA and a non-display area NDA. The display area DA may be an area including pixels PX and displaying an image. The non-display area NDA is a remaining area other than the display area DA, and an image may not be displayed in the non-display area NDA. In an embodiment, the non-display area NDA may be located at the periphery of the display area DA and may surround the display area DA.

[0047] exist Figure 1In the embodiment, a first direction D1, a second direction D2 and a third direction D3 are defined. In one embodiment, the first direction D1 may be a horizontal direction of the display panel 110, the second direction D2 may be a vertical direction of the display panel 110, and the third direction D3 may be a thickness direction of the display panel 110.

[0048] In one embodiment, the display panel 110 may be formed in a rectangular shape on a plane. Figure 1 10 is shown in FIG. 10A to have a longer horizontal length than a longer vertical length, but the shape of the display panel 110 is not limited thereto. For example, the display panel 110 may have a shape in which the vertical length is longer than the horizontal length, or may have a square shape, etc. The display panel 110 may include angled corners, or may include rounded corners.

[0049] The planar shape of the display panel 110 is not limited to the illustrated quadrilateral shape, and may also be applied in other shapes. For example, the display panel 110 may also have a non-quadrilateral polygonal shape, a circular shape, an elliptical shape, an irregular shape, or other shapes in the plane.

[0050] In one embodiment, the display panel 110 may be substantially flat on a plane defined by the first direction D1 and the second direction D2, and may have a uniform thickness in the third direction D3. Alternatively, the display panel 110 may also be configured to have a three-dimensional shape such as a curved surface.

[0051] The display panel 110 may be provided as a rigid panel in a substantially non-deformable manner, or may be provided as a flexible panel that can be deformed in at least a portion in a folded, bent, or rolled form. The display panel 110 may be provided in the display device 100 in an unbent state, or may be provided in the display device 100 in a partially bent state.

[0052] The first driving unit 120 and the second driving unit 130 may generate driving signals for controlling the operation timing and brightness of the pixel PX, and supply the driving signals to the pixel PX. For example, the first driving unit 120 may be a gate driving unit including a scan driving unit, and may be connected to the pixel PX through respective gate lines. The first driving unit 120 may supply respective gate signals (as an example, control signals that control the driving timing of the pixel PX including scan signals and / or light emitting control signals) to the pixel PX. The second driving unit 130 may be a data driving unit including a source driving circuit, and may be connected to the pixel PX through respective data lines. The second driving unit 130 may supply respective data signals to the pixel PX.

[0053] In one embodiment, at least one of the first driving unit 120 and the second driving unit 130 or a portion of the at least one driving unit may be embedded in the display panel 110. For example, the first driving unit 120 or a portion of the first driving unit 120 may be disposed on the substrate SUB of the display panel 110, and may be disposed and / or formed in the non-display area NDA.

[0054] exist Figure 1 , the first driving unit 120 is illustrated as being formed on one side of the display area DA (as an example, the non-display area NDA on the right side of the display area DA), but the embodiment is not limited thereto. For example, the first driving unit 120 may also be located only on the other side of the display area DA (as an example, the non-display area NDA on the left side of the display area DA), or may be located on both sides of the display area DA (as an example, the non-display areas NDA on the left and right sides of the display area DA). Alternatively, a portion of the first driving unit 120 may be located in the non-display area NDA, and another portion of the first driving unit 120 may be located in a non-luminescent area inside the display area DA (as an example, an area between luminescent areas of the pixels PX).

[0055] In one embodiment, the other driving unit of the first driving unit 120 and the second driving unit 130 or a part of the other driving unit may be arranged or formed outside the display panel 110 and electrically connected to the display panel 110. For example, the second driving unit 130 may be implemented using a plurality of integrated circuit chips and may be arranged on a circuit board 140 electrically connected to the pixels PX of the display panel 110. The second driving unit 130 may also be implemented using at least one integrated circuit chip and may be mounted on the non-display area NDA of the display panel 110.

[0056] The circuit board 140 may be disposed on a pad (as an example, Figure 2 The circuit board 140 is disposed on a pad PD of a display panel 110 and can be connected to the display panel 110 through the pad. In one embodiment, the circuit board 140 can be a flexible film such as a flexible printed circuit board (FPCB), a printed circuit board (PCB), or a chip on film (COF), but is not limited thereto. In one embodiment, the circuit board 140 can be connected to the timing control unit and / or the power supply unit through other circuit boards or connectors.

[0057] Figure 2 is a plan view showing a display panel 110 according to an embodiment. For example, Figure 2 Shown for Figure 1An embodiment of the display panel 110.

[0058] Figure 3 FIG. 4 shows a portion of a display area DA according to an embodiment. For example, Figure 3 Shown for Figure 2 An embodiment of the A1 region.

[0059] Combination Figure 1 And refer to Figure 2 and Figure 3 , the display panel 110 may include a substrate SUB and pixels PX arranged on the substrate SUB. The pixels PX may be arranged in a display area DA on the substrate SUB.

[0060] The substrate SUB, as a basic component for manufacturing or setting the display panel 110, may constitute a base surface of the display panel 110. The substrate SUB may include a display area DA and a non-display area NDA around the display area DA.

[0061] According to the embodiment, the display area DA may have a variety of shapes. For example, the display area DA may have a quadrilateral shape, a non-quadrilateral polygonal shape, a circular shape, an elliptical shape, an irregular shape, or other shapes. In one embodiment, the display area DA may have a shape that matches the shape of the display panel 110.

[0062] Pixels PX may be arranged and / or arranged in the display area DA. For example, the display area DA may include a plurality of pixel areas in which the plurality of pixels PX are arranged. Each pixel area may include a respective light emitting area EA. The display area DA may include a light emitting area EA of each pixel PX and a non-light emitting area NEA located around the light emitting area EA. For example, the non-light emitting area NEA may be located between and / or around the light emitting areas EA and may surround each light emitting area EA.

[0063] Each pixel PX may include a pixel electrode AE ​​and a common electrode CE. In one embodiment, the pixel electrode AE ​​may be individually arranged and / or formed in each pixel PX corresponding to the light-emitting area EA of each pixel PX, and the common electrode CE may be formed to be shared by the pixels PX. For example, the pixel electrode AE ​​may be individually patterned in a manner of being located in each light-emitting area EA, and the common electrode CE may be formed in the entire display area DA. In one embodiment, the pixel electrode AE ​​may have a shape and / or size corresponding to each light-emitting area EA, and may have an area above the light-emitting area EA and extend to the outline of the light-emitting area EA. In one embodiment, the common electrode CE may have a shape and / or size corresponding to the display area DA, and may have an area above the display area DA and extend to the outline of the display area DA.

[0064] In one embodiment, the display panel 110 may be a light-emitting display panel (as an example, an organic light-emitting display panel), and each pixel PX may include a light-emitting element located in each light-emitting area EA. The pixel electrode AE ​​may be a first electrode of the light-emitting element provided in each pixel PX, and the common electrode CE may be a second electrode of the light-emitting element. For example, the pixel electrode AE ​​may be an anode electrode (or a cathode electrode), and the common electrode CE may be a cathode electrode (or an anode electrode). A light-emitting layer (as an example, an organic light-emitting layer) may be interposed between the pixel electrode AE ​​and the common electrode CE of each pixel PX. Each pixel PX may include a light-emitting area EA provided with the pixel electrode AE, the light-emitting layer, and the common electrode CE.

[0065] In one embodiment, each pixel PX may further include a pixel circuit connected to each light-emitting element. When describing the embodiment, the term "connection" may include the meaning of electrical connection and / or physical connection. The pixel circuit may include circuit elements for controlling the light-emitting element (as an example, transistors including a driving transistor and a switching transistor and a capacitor including a storage capacitor). Each pixel area may include a light-emitting area EA in which each light-emitting element is provided and a pixel circuit area in which each pixel circuit is provided. The light-emitting area EA and the pixel circuit area of ​​each pixel PX may overlap or not overlap each other.

[0066] Wiring connected to the pixels PX may also be arranged in the display area DA. Figure 2 and Figure 3 , as an example of the wiring, a power line VSL connected to the common electrode CE is shown. In an embodiment, the power line VSL may be connected to the common electrode CE through at least one pad electrode LDP provided in the display area DA.

[0067] In one embodiment, the power line VSL may include a low-resistance conductive material. By using the power line VSL to supply the pixel voltage to the common electrode CE, the voltage drop of the pixel voltage can be prevented, reduced and / or minimized. Thus, the brightness change caused by the voltage drop of the pixel voltage can be prevented or reduced, and the image quality of the display device 100 can be improved.

[0068] In one embodiment, the power line VSL may be a grid-type wiring arranged in the display area DA, but is not limited thereto. For example, the position, form and / or size of the power line VSL may be variously changed according to the design space that can be ensured in the display area DA (as an example, the design space that can be ensured in the layer where the power line VSL is arranged in the display panel 110).

[0069] In one embodiment, the power line VSL may be disposed in a panel circuit layer below the pixel electrode AE ​​and the pad electrode LDP. The power line VSL may be arranged in the non-emission area NEA in a manner overlapping with the emission area EA of at least one pixel PX or not overlapping with the emission area EA of the pixel PX.

[0070] The power line VSL may be connected to at least one pad PD (as an example, a power pad that supplies a pixel voltage (as an example, a low potential pixel voltage)) located in the pad area PA. For example, the power line VSL may extend to the non-display area NDA outside the display area DA and be directly connected to the at least one pad PD, or may be connected to the at least one pad PD through a connection wiring formed in the non-display area NDA.

[0071] At least one pad electrode LDP may also be arranged in the display area DA. For example, at least one pad electrode LDP may be arranged in the non-luminous area NEA. The pad electrode LDP may connect the power line VSL arranged in different layers from each other in the display panel 110 to the common electrode CE. For example, the pad electrode LDP, as an intermediate electrode connecting the power line VSL to the common electrode CE, may be arranged in an intermediate layer between a lower layer in which the power line VSL is arranged and an upper layer in which the common electrode CE is arranged in the display panel 110. In one embodiment, the pad electrode LDP may be formed simultaneously with the pixel electrode AE. For example, the pad electrode LDP may be formed in the same layer as the pixel electrode AE ​​and separated from the pixel electrode AE.

[0072] The pad electrode LDP may overlap with the power line VSL and may be connected to the power line VSL through the first hole H1. The first hole H1 may penetrate the insulating layer (as an example, Figure 4 and Figure 5 The fifth insulating layer INS5 or Figure 6 The first hole H1 may be a through hole VH or a contact hole formed in the insulating layer by an etching process using a mask or the like.

[0073] The pad electrode LDP may overlap with the common electrode CE and may be connected to the common electrode CE through the second hole H2. The second hole H2 may penetrate the insulating layer (as an example, Figures 4 to 6The second hole H2 may be formed in the insulating layer by a pixel definition film PDL and expose a portion of the pad electrode LDP. The second hole H2 may be located in the non-light emitting area NEA. In one embodiment, the second hole H2 may be a laser drilled hole LDH formed by a laser drilling process using a laser, and the pad electrode LDP may be a laser drilled pad connected to the common electrode CE by the laser drilled hole LDH.

[0074] In one embodiment, a plurality of pad electrodes LDP separated from each other may be provided in the display area DA. In one embodiment, each pad electrode LDP may be located between the emission areas EA of adjacent pixels PX. For example, a pad electrode LDP located in the display area DA may be located between the emission areas EA of the first pixel PX1, the second pixel PX2, the third pixel PX3, and the fourth pixel PX4 adjacent to each other (as an example, the first emission area EA1, the second emission area EA2, the third emission area EA3, and the fourth emission area EA4), and may be separated from the pixel electrodes AE of the first pixel PX1, the second pixel PX2, the third pixel PX3, and the fourth pixel PX4 (as an example, the first pixel electrode AE1, the second pixel electrode AE2, the third pixel electrode AE3, and the fourth pixel electrode AE4). The number, arrangement density (or resolution), shape, size, and / or position of the pad electrodes LDP provided in the display area DA may be varied according to the embodiments.

[0075] In one embodiment, the first pixel PX1, the second pixel PX2, the third pixel PX3 and the fourth pixel PX4 can emit light of a specific color. As an example, the first pixel PX1, the second pixel PX2, the third pixel PX3 and the fourth pixel PX4 can emit light of red, green, blue, white or other colors.

[0076] exist Figure 3 , the approximate positions and forms of the light emitting areas EA and the pixel electrodes AE of the first pixel PX1, the second pixel PX2, the third pixel PX3, and the fourth pixel PX4 are shown, but the embodiment is not limited thereto. For example, the forms, arrangement structures, and / or sizes of the light emitting areas EA and / or the pixel electrodes AE of the first pixel PX1, the second pixel PX2, the third pixel PX3, and the fourth pixel PX4 may be variously changed according to the embodiment.

[0077] The non-display area NDA may include a pad area PA where a pad PD is arranged. In one embodiment, the non-display area NDA may further include a driving circuit area located at least on one side of the display area DA. At least one driving part, pad PD and / or wiring etc. may be arranged in the non-display area NDA.

[0078] At least one driving unit or a part of the driving unit for driving the pixel PX may be arranged in the driving circuit area. As an example, circuit elements constituting the first driving unit 120 (as an example, a driving unit transistor and a driving unit capacitor constituting a stage circuit of the first driving unit 120) may be arranged in the driving circuit area on the substrate SUB. In an embodiment, the circuit elements of the first driving unit 120 may be formed in the display panel 110 together with the circuit elements of the pixel PX.

[0079] At least one circuit board 140 may be arranged and / or bonded on the pad area PA. In one embodiment, a plurality of circuit boards 140 connected to different pads PD may be arranged on the pad area PA. The pad PD may include a signal pad and a power pad for transmitting a driving signal and a power supply voltage required for driving the pixel PX and / or the first driving unit 120 to the inside of the display panel 110.

[0080] Figure 4 is a cross-sectional view showing a display panel 110 according to an embodiment. For example, Figure 4 As a cross-sectional view showing a portion of the display area DA of the display panel 110, a light emitting element EL located in the light emitting area EA of one pixel PX, a portion of the power line VSL located around the light emitting area EA, and a pad electrode LDP connected to the power line VSL are shown. Figure 4 , as an example of the display panel 110 to which the embodiment can be applied, a light-emitting display panel including a light-emitting element EL (as an example, an organic light-emitting diode) is shown.

[0081] Combination Figures 1 to 3 Reference Figure 4 , the display panel 110 may include a substrate SUB (also referred to as a "base layer"), a panel circuit layer PCL, a light emitting element layer LEL, and an encapsulation layer ENL. The panel circuit layer PCL, the light emitting element layer LEL, and the encapsulation layer ENL may be arranged on the substrate SUB in an overlapping manner. As an example, with the display area DA as a reference, the panel circuit layer PCL, the light emitting element layer LEL, and the encapsulation layer ENL may be sequentially arranged on the substrate SUB along a third direction D3. However, the embodiment is not limited thereto, and the positions of the panel circuit layer PCL, the light emitting element layer LEL, and / or the encapsulation layer ENL may be changed.

[0082] In one embodiment, the display panel 110 may further include additional elements arranged above and / or below the encapsulation layer ENL. For example, the display panel 110 may further include at least one of a sensor layer (as an example, a touch sensor layer), an optical layer (as an example, a color filter layer and / or a wavelength conversion layer), and a protective layer (as an example, a protective film, an insulating layer, an upper substrate, and / or a window).

[0083] The substrate SUB, as a basic component for forming the display panel 110, may be a rigid or flexible substrate (or film). In one embodiment, the substrate SUB may be a substrate including an insulating material such as glass and having rigid characteristics, and may not be bent. Alternatively, the substrate SUB may be a flexible substrate including polyimide or other insulating materials and capable of bending, folding, rolling, and other deformations, and may be bent or not. The type and / or material of the substrate SUB may be changed according to the embodiment.

[0084] The panel circuit layer PCL may include circuit elements of the pixels PX located in the display area DA (as an example, multiple transistors TR and capacitors including transistors TR connected to the light emitting elements EL of the respective pixels PX) and wiring located in the display area DA and / or the non-display area NDA (as an example, various power lines and signal lines including the power line VSL). In an embodiment, the panel circuit layer PCL may further include circuit elements of the first driving unit 120 and / or additional conductive patterns (as an example, bridge patterns).

[0085] exist Figure 4 , as an example of a circuit element that can be provided in the panel circuit layer PCL, a transistor TR provided in one pixel PX and connected to the light emitting element EL of the pixel PX is shown. Figure 4 The transistor TR may be a driving transistor or a switching transistor provided in a pixel circuit of a corresponding pixel PX.

[0086] The panel circuit layer PCL may include a plurality of conductive layers in which circuit elements and wirings are provided, and at least one semiconductor layer. In the conductive layer, electrodes constituting circuit elements of the panel circuit layer PCL, conductive patterns (as an example, bridge electrodes BRE) and / or wirings connected to the electrodes and / or wirings may be provided. The active layer ACT of the transistor TR provided in the panel circuit layer PCL may be provided in the semiconductor layer.

[0087] Each electrode, conductive pattern and / or wiring disposed in the panel circuit layer PCL may include at least one conductive material. For example, each electrode, conductive pattern and / or wiring disposed in the panel circuit layer PCL may include at least one of copper (Cu), titanium (Ti), molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), silver (Ag), platinum (Pt), palladium (Pd), nickel (Ni), neodymium (Nd), iridium (Ir), tantalum (Ta), tungsten (W), magnesium (Mg) and other metals, their alloys or other conductive substances in addition thereto. In one embodiment, the electrodes, conductive patterns and / or wirings arranged in the same conductive layer may be formed simultaneously using the same conductive substances as each other. In one embodiment, each electrode, conductive pattern and / or wiring disposed in the conductive layer of the panel circuit layer PCL may have a single-layer structure or a multi-layer structure.

[0088] The panel circuit layer PCL may further include a plurality of insulating layers and / or insulating patterns arranged on the substrate SUB. For example, the panel circuit layer PCL may include a first insulating layer INS1, a second insulating layer INS2, a gate insulating layer GI, a third insulating layer INS3, a fourth insulating layer INS4, and a fifth insulating layer INS5 sequentially arranged on the substrate SUB along a third direction D3.

[0089] The first insulating layer INS1 may be disposed on the substrate SUB. The first insulating layer INS1 may include an inorganic insulating layer. The first insulating layer INS1 may protect the pixel PX from moisture penetrating through the substrate SUB susceptible to moisture permeation. The first insulating layer INS1 may be selectively disposed on the substrate SUB. For example, the display panel 110 may include or not include the first insulating layer INS1.

[0090] The second insulating layer INS2 may be disposed on the first insulating layer INS1 (or substrate SUB). The second insulating layer INS2 may cover the pattern of the first conductive layer disposed on the first insulating layer INS1 (or substrate SUB) (as an example, the electrode, conductive pattern and / or at least one wiring of the first conductive layer including the bottom electrode BE of the transistor TR).

[0091] The gate insulating layer GI may be disposed on the second insulating layer INS2. The gate insulating layer GI may cover at least a portion of a pattern of a semiconductor layer disposed on the second insulating layer INS2 (as an example, a semiconductor pattern including a semiconductor layer of the active layer ACT of the transistor TR).

[0092] The third insulating layer INS3 may be disposed on the second insulating layer INS2. The third insulating layer INS3 may cover a pattern of a semiconductor layer disposed on the second insulating layer INS2 (as an example, a semiconductor pattern of a semiconductor layer including an active layer ACT of the transistor TR), a gate insulating layer GI, and a pattern of a second conductive layer disposed on the gate insulating layer GI (as an example, an electrode, a conductive pattern, and / or at least one wiring of the second conductive layer including a gate electrode GE of the transistor TR).

[0093] The fourth insulating layer INS4 may be disposed on the third insulating layer INS3. The fourth insulating layer INS4 may cover the pattern of the third conductive layer disposed on the third insulating layer INS3 (as an example, the electrode, conductive pattern and / or at least one wiring of the third conductive layer including the source electrode SE and / or the drain electrode DE of the transistor TR).

[0094] In an embodiment, the fourth insulating layer INS4 may be a single-layer or multi-layer insulating layer including an organic insulating layer, and may or may not include an inorganic insulating layer. As an example, the fourth insulating layer INS4 may have a multi-layer structure including an inorganic film and an organic film sequentially arranged on the third insulating layer INS3, or may not include an inorganic film and include only an organic film.

[0095] The fifth insulating layer INS5 may be disposed on the fourth insulating layer INS4. The fifth insulating layer INS5 may cover patterns of the fourth conductive layer disposed on the fourth insulating layer INS4 (as an example, electrodes of the fourth conductive layer including the bridge electrode BRE, conductive patterns and / or at least one wiring including the power line VSL).

[0096] In an embodiment, the fifth insulating layer INS5 may be a single-layer or multi-layer insulating layer including an organic insulating layer, and may or may not include an inorganic insulating layer. As an example, the fifth insulating layer INS5 may have a multi-layer structure including an inorganic film and an organic film sequentially arranged on the fourth insulating layer INS4, or may not include an inorganic film and include only an organic film.

[0097] In one embodiment, the first insulating layer INS1, the second insulating layer INS2, the gate insulating layer GI, and the third insulating layer INS3 may respectively include at least one inorganic insulating layer including an inorganic insulating substance (as an example, silicon nitride, silicon oxide, silicon oxynitride, titanium oxide, aluminum oxide, or other inorganic insulating substances in addition thereto). As an example, the first insulating layer INS1, the second insulating layer INS2, the gate insulating layer GI, and the third insulating layer INS3 may respectively be a single-layer or multi-layer inorganic insulating layer. In one embodiment, in the case where at least one of the fourth insulating layer INS4 and the fifth insulating layer INS5 includes an inorganic film, the inorganic film may include at least one inorganic insulating substance exemplified above.

[0098] In an embodiment, the fourth insulating layer INS4 and the fifth insulating layer INS5 may respectively include at least one organic insulating layer including an organic insulating substance (as an example, acryl resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin or other organic insulating substances besides). The surfaces (as an example, the upper surfaces) of the fourth insulating layer INS4 and the fifth insulating layer INS5 may be substantially flat.

[0099] In one embodiment, at least one insulating layer provided in the panel circuit layer PCL may be arranged in the entire display area DA. For example, the first insulating layer INS1, the second insulating layer INS2, the third insulating layer INS3, the fourth insulating layer INS4 and the fifth insulating layer INS5 may be arranged in the entire display area DA.

[0100] In one embodiment, the gate insulating layer GI may be arranged only locally in a portion of each pixel region and / or the display area DA. For example, the gate insulating layer GI may be patterned separately in each transistor region where at least one transistor TR is located, and may be arranged only on a portion of the active layer ACT provided in the transistor TR, and expose the other portions of the active layer ACT. As an example, the gate insulating layer GI may be arranged between a portion of the active layer ACT including the channel region CH and the gate electrode GE, but not on other portions of the active layer ACT including at least a portion of each of the source region SR and the drain region DR. However, the embodiment is not limited thereto. For example, the gate insulating layer GI may also be arranged in the entire region of each transistor region and / or the display area DA.

[0101] The transistor TR may include an active layer ACT and a gate electrode GE (as an example, a top gate electrode) arranged on a portion of the active layer ACT. In one embodiment, the transistor TR may also include at least one of a source electrode SE and a drain electrode DE. For example, the transistor TR may also include a source electrode SE connected to a source region SR of the active layer ACT and a drain electrode DE connected to a drain region DR of the active layer ACT. Alternatively, the transistor TR may not include a separate source electrode and / or drain electrode, and may function as a source electrode and / or drain electrode of the transistor TR by connecting the source region SR and / or drain region DR of the active layer ACT to other circuit elements, wiring and / or conductive patterns.

[0102] In one embodiment, the transistor TR may further include a bottom electrode BE (as an example, a bottom gate electrode) disposed at a lower portion of the active layer ACT. In one embodiment, the bottom electrode BE may be connected to an electrode of the transistor TR and may be used as a back gate electrode for adjusting the characteristics of the transistor TR. By disposing the bottom electrode BE at a lower portion of the active layer ACT, external light may be blocked from being incident on the channel region CH of the active layer ACT, etc., and the operating characteristics of the transistor TR may be stabilized.

[0103] In one embodiment, the transistor TR may be an N-type transistor. As an example, the transistor TR may be an N-type oxide transistor.

[0104] The bottom electrode BE may be arranged between the first insulating layer INS1 and the second insulating layer INS2. For example, the bottom electrode BE may be arranged on the first insulating layer INS1 and may be covered by the second insulating layer INS2. The bottom electrode BE may overlap the active layer ACT and the gate electrode GE. For example, the bottom electrode BE may be arranged at a lower portion of the active layer ACT in a manner overlapping at least a portion of the active layer ACT including the channel region CH, and may face the gate electrode GE across the active layer ACT.

[0105] In one embodiment, the bottom electrode BE may be connected to the source electrode SE or the gate electrode GE of the corresponding transistor TR. For example, the transistor TR may be a driving transistor of the pixel PX, and the bottom electrode BE of the transistor TR may be connected to the source electrode SE of the transistor TR through at least one contact hole CNT penetrating the second insulating layer INS2 and the third insulating layer INS3. Alternatively, the transistor TR may be a switching transistor of the pixel PX, and the bottom electrode BE of the transistor TR may be connected to the gate electrode GE of the transistor TR.

[0106] The active layer ACT may be disposed between the second insulating layer INS2 and the gate insulating layer GI. For example, the active layer ACT may be disposed on the second insulating layer INS2 and may be covered by the gate insulating layer GI and the third insulating layer INS3.

[0107] The active layer ACT may include a channel region CH and a source region SR and a drain region DR separated from each other across the channel region CH. For example, the source region SR and the drain region DR may be located on both sides of the channel region CH. The channel region CH may be a region that is not made conductive and maintains semiconductor characteristics. The source region SR and the drain region DR, as regions made conductive, may have a higher carrier concentration (electron concentration as an example) than the channel region CH.

[0108] The active layer ACT may overlap the bottom electrode BE and the gate electrode GE. For example, a portion of the active layer ACT including the channel region CH may overlap the bottom electrode BE and the gate electrode GE.

[0109] In one embodiment, the active layer ACT may include an oxide semiconductor. For example, the active layer ACT may include an oxide semiconductor including at least one of indium (In), gallium (Ga), zinc (Zn), tin (Sn), and hafnium (Hf), or other oxide semiconductors. In one embodiment, the active layer ACT may include an oxide semiconductor including zinc oxide (ZnO), zinc tin oxide (ZTO), indium zinc oxide (IZO), indium oxide (InO or In 2 O 3 ), titanium oxide (TiO or TiO 2 ), indium gallium oxide (IGO), indium gallium zinc oxide (IGZO), indium gallium tin oxide (IGTO), indium zinc tin oxide (IZTO), indium tin gallium zinc oxide (ITGZO) or other oxide semiconductors.

[0110] A gate insulating layer GI may be disposed on the active layer ACT. In one embodiment, the gate insulating layer GI may be disposed only on a portion of the active layer ACT, and not on other portions of the active layer ACT. For example, the gate insulating layer GI may be disposed on a portion of the active layer ACT including the channel region CH, and expose the source region SR and the drain region DR of the active layer ACT.

[0111] Since the gate insulating layer GI exposes the source region SR and the drain region DR, the source region SR and the drain region DR can be appropriately and / or easily conductive during the manufacturing process of the display panel 110. For example, in the step of etching the gate insulating layer GI in a manner that exposes at least a portion of each of the source region SR and the drain region DR, oxygen vacancies may be generated in the source region SR and the drain region DR due to etching gas, etc. Thus, even if an additional doping process is not performed, the source region SR and the drain region DR can be appropriately conductive in a subsequent process (as an example, a formation process of the third insulating layer INS3, etc.).

[0112] The gate electrode GE may be disposed between the gate insulating layer GI and the third insulating layer INS3. For example, the gate electrode GE may be disposed on the gate insulating layer GI and may be covered by the third insulating layer INS3.

[0113] The gate electrode GE may be disposed on the active layer ACT in such a manner as to overlap with the channel region CH. The gate electrode GE and the active layer ACT may be separated and / or spaced apart from each other with a gate insulating layer GI interposed therebetween.

[0114] A third insulating layer INS3 may be disposed on the gate electrode GE. The third insulating layer INS3 may cover the active layer ACT, the gate insulating layer GI, and the gate electrode GE.

[0115] The source electrode SE and the drain electrode DE may be disposed between the third insulating layer INS3 and the fourth insulating layer INS4. For example, the source electrode SE and the drain electrode DE may be disposed on the third insulating layer INS3 and may be covered by the fourth insulating layer INS4.

[0116] The source electrode SE may be connected to a portion of the active layer ACT. For example, the source electrode SE may be connected to the source region SR of the active layer ACT through at least one contact hole CNT penetrating the third insulating layer INS3. In one embodiment, the source electrode SE may also be connected to the bottom electrode BE through another contact hole CNT penetrating the second insulating layer INS2 and the third insulating layer INS3.

[0117] The drain electrode DE may be connected to another portion of the active layer ACT. For example, the drain electrode DE may be connected to the drain region DR of the active layer ACT through at least one contact hole CNT penetrating the third insulating layer INS3.

[0118] In one embodiment, at least one transistor TR provided in each pixel PX may be connected to a bridge electrode BRE disposed on the fourth insulating layer INS4, and may be connected to the light emitting element EL of the corresponding pixel PX through the bridge electrode BRE. For example, the source electrode SE (or the drain electrode DE) of at least one transistor TR provided in each pixel PX may be connected to the bridge electrode BRE on the fourth insulating layer INS4 through at least one through hole VH (or contact hole) penetrating the fourth insulating layer INS4.

[0119] The bridging electrode BRE may be disposed between the fourth insulating layer INS4 and the fifth insulating layer INS5. For example, the bridging electrode BRE may be disposed on the fourth insulating layer INS4 and may be covered by the fifth insulating layer INS5. The bridging electrode BRE may be connected to the pixel electrode AE ​​disposed in the light emitting element layer LEL through at least one through hole VH (or contact hole) penetrating the fifth insulating layer INS5.

[0120] In one embodiment, a power line VSL may be further disposed between the fourth insulating layer INS4 and the fifth insulating layer INS5 . For example, the power line VSL may be disposed on the fourth insulating layer INS4 and may be covered by the fifth insulating layer INS5 .

[0121] In one embodiment, the bridging electrode BRE and the power line VSL may be formed simultaneously with each other. For example, the bridging electrode BRE and the power line VSL may be formed in the same layer in the panel circuit layer PCL using the same conductive material. As an example, a single-layer or multi-layer conductive film is formed on the fourth insulating layer INS4, and the conductive film is etched by an etching process using a mask, so that the bridging electrode BRE and the power line VSL are separated from each other.

[0122] A light emitting element layer LEL may be disposed on the panel circuit layer PCL. For example, the light emitting element layer LEL may be disposed on the fifth insulating layer INS5 and may be located at least in the display area DA.

[0123] The light emitting element layer LEL may include a light emitting element EL for each pixel PX. For example, the light emitting element layer LEL may include a pixel definition film PDL (also referred to as a "bank" or a "sixth insulating layer") that divides the light emitting area EA of each pixel PX and a light emitting element EL located in each light emitting area EA. In an embodiment, the light emitting element layer LEL may further include a spacer SPC disposed on a portion of the pixel definition film PDL.

[0124] Each light emitting element EL may include a pixel electrode AE ​​(as an example, a first electrode or anode electrode of the light emitting element EL) located in each light emitting area EA, and a light emitting layer EML and a common electrode CE (as an example, a second electrode or cathode electrode of the light emitting element EL) sequentially arranged on the pixel electrode AE. The pixel electrode AE ​​may be connected to at least one transistor TR included in the corresponding pixel PX. In an embodiment, the light emitting element EL may further include at least one common layer. For example, the light emitting element EL may include at least one of a first common layer CML1 (as an example, a hole injection layer and / or a hole transport layer, etc.) arranged between the pixel electrode AE ​​and the light emitting layer EML and formed in the entire display area DA, and a second common layer CML2 (as an example, an electron injection layer and / or an electron transport layer, etc.) arranged between the light emitting layer EML and the common electrode CE and formed in the entire display area DA.

[0125] The pixel electrode AE ​​may be disposed on the fifth insulating layer INS5. For example, the pixel electrode AE ​​may be disposed between the fifth insulating layer INS5 and the pixel definition film PDL.

[0126] The pixel electrode AE ​​may be a single-layer or multi-layer electrode including at least one conductive material. In one embodiment, the display panel 110 may be a front-emitting display panel, and the pixel electrode AE ​​may include a reflective electrode layer with high reflectivity (as an example, Figure 5 The second metal layer MTL2).

[0127] In an embodiment, a pad electrode LDP may be further disposed between the fifth insulating layer INS5 and the pixel definition film PDL. For example, the pad electrode LDP may be disposed on the fifth insulating layer INS5 and may be covered by the pixel definition film PDL.

[0128] In one embodiment, the pixel electrode AE ​​and the pad electrode LDP may be arranged apart from each other in the same layer within the display panel 110, and may be formed at the same time. For example, the pixel electrode AE ​​and the pad electrode LDP may be formed simultaneously in the same layer of the light emitting element layer LEL using the same conductive material. In one embodiment, a single-layer or multi-layer conductive film is formed on the fifth insulating layer INS5, and the conductive film is etched by an etching process using a mask, so that the pixel electrode AE ​​and the pad electrode LDP may be separated from each other. For example, the pixel electrode AE ​​may be formed to be located in each light emitting area EA, and the pad electrode LDP may be formed to be located in a portion of the non-light emitting area NEA.

[0129] The pad electrode LDP may overlap with the power line VSL, and may be connected with the power line VSL through a first hole H1 passing through the fifth insulating layer INS5 (as an example, at least one through hole VH or contact hole passing through the fifth insulating layer INS5 ).

[0130] The light emitting layer EML may be disposed on the pixel electrode AE. For example, the light emitting layer EML may be disposed between the pixel electrode AE ​​and the common electrode CE. The light emitting layer EML may contain a high molecular substance or a low molecular substance. Light emitted from the light emitting layer EML may contribute to displaying an image.

[0131] The common electrode CE may be disposed on the light emitting layer EML. In one embodiment, the common electrode CE may be a common film formed in the entire display area DA in a form covering the light emitting layer EML and the pixel definition film PDL. In one embodiment, the display panel 110 may be a front light emitting display panel, and the common electrode CE may be transparent or translucent.

[0132] In an embodiment, the common electrode CE may overlap with the pad electrode LDP and may include a second hole H2 (as an example, at least one laser drilled hole LDH that penetrates the pixel definition film PDL) that penetrates the pixel definition film PDL to be connected to the pad electrode LDP. In the display panel 110 including at least one common layer arranged between the pixel definition film PDL and the common electrode CE, the second hole H2 may be formed to further penetrate the common layer. For example, the second hole H2 may be formed to penetrate the pixel definition film PDL, the first common layer CML1, and the second common layer CML2, thereby connecting the pad electrode LDP to the common electrode CE. Thus, the pixel voltage (as an example, the low potential pixel voltage or the cathode voltage) applied to the power line VSL may be applied to the common electrode CE.

[0133] The pixel definition film PDL may have an opening corresponding to each light emitting area EA and surround the light emitting area EA. For example, the pixel definition film PDL may be formed to cover the edge of the pixel electrode AE ​​of the light emitting element EL, and may be opened to expose the rest of the pixel electrode AE. The area where the exposed pixel electrode AE ​​overlaps with the light emitting layer EML may be the light emitting area EA of each pixel PX. In one embodiment, the pixel definition film PDL may include at least one organic insulating layer containing an organic insulating substance.

[0134] The spacer SPC may be arranged on a portion of the pixel definition film PDL. The spacer SPC may include at least one organic insulating layer containing an organic insulating substance. The spacer SPC may contain the same substance as the pixel definition film PDL, or may contain a substance different from the pixel definition film PDL. The pixel definition film PDL and the spacer SPC may be formed sequentially by respective mask processes, or may be formed simultaneously and / or integrally using a halftone mask.

[0135] The encapsulation layer ENL may be disposed on the light emitting element layer LEL. The encapsulation layer ENL may cover the light emitting element layer LEL in the display area DA, and may extend to the non-display area NDA to be connected to the panel circuit layer PCL. The encapsulation layer ENL may block the penetration of oxygen or moisture to the light emitting element layer LEL, and may mitigate electrical and / or physical impacts to the panel circuit layer PCL and the light emitting element layer LEL.

[0136] In one embodiment, the encapsulation layer ENL may include a first encapsulation layer ENL1, a second encapsulation layer ENL2, and a third encapsulation layer ENL3 sequentially arranged on the light emitting element layer LEL. The first encapsulation layer ENL1 and the third encapsulation layer ENL3 may be inorganic encapsulation layers including inorganic substances, respectively. The second encapsulation layer ENL2 may be an organic encapsulation layer including organic substances.

[0137] Figure 5 is a cross-sectional view showing a power line VSL, a pad electrode LDP, and a common electrode CE according to an embodiment. Figure 5 Shown for Figure 4 Example of the A2 region.

[0138] Combination Figures 1 to 4 Reference Figure 5 The power line VSL may include a first metal layer MTL1 and a first transparent conductive layer TCL1 disposed on the first metal layer MTL1. In one embodiment, the first transparent conductive layer TCL1 may be directly disposed on the first metal layer MTL1.

[0139] The first metal layer MTL1 may be formed using a single layer or multiple layers of metal layers. In one embodiment, the first metal layer MTL1 may have a multilayer structure including a first layer MTL11 including a first metal, a second layer MTL12 disposed on the first layer MTL11 and including a second metal, and a third layer MTL13 disposed on the second layer MTL12 and including a third metal. The second metal may be a metal different from the first metal and the third metal. The third metal may be a metal that is the same as or different from the first metal. In one embodiment, in order to improve manufacturing efficiency, the third metal may be a metal that is the same as the first metal.

[0140] The first layer MTL 11 may include a first metal suitable for protecting the second layer MTL 12 and improving adhesion. As an example, the first metal may be titanium (Ti), but is not limited thereto.

[0141] The second layer MTL 12 may include a second metal having high conductivity and may have a relatively large thickness compared to the first layer MTL 11 and the third layer MTL 13. In one embodiment, the second metal may be a metal suitable for easy patterning by dry etching, etc. As an example, the second metal may be aluminum (Al), but is not limited thereto.

[0142] The third layer MTL13 may include a third metal suitable for protecting the second layer MTL12 and improving adhesion and / or contact resistance. As an example, the third metal may be titanium (Ti), but is not limited thereto. In one embodiment, when the first layer MTL11, the second layer MTL12, and the third layer MTL13 are formed using titanium (Ti), aluminum (Al), and titanium (Ti), respectively, the first metal layer MTL1 may have a three-layer structure of Ti / Al / Ti.

[0143] The first transparent conductive layer TCL1 may include a conductive material suitable for reducing the contact resistance between the power line VSL and the pad electrode LDP. As an example, the first transparent conductive layer TCL1 may include the same conductive material as the conductive material forming the lower layer portion of the pad electrode LDP in contact with the power line VSL (as an example, the conductive material forming the second transparent conductive layer TCL2), or may include a conductive material having a work function similar to that of the conductive material forming the lower layer portion of the pad electrode LD.

[0144] In one embodiment, the first transparent conductive layer TCL1 and the second transparent conductive layer TCL2 may be formed using the same or different types of conductive materials that contain a specific element. As an example, the first transparent conductive layer TCL1 and the second transparent conductive layer TCL2 may be formed using transparent conductive oxide (TCO) and may contain one or more elements that are the same as each other.

[0145] In an embodiment, the first transparent conductive layer TCL1 may have a narrower width than the first metal layer MTL1, and when viewed on a plane, the region where the first transparent conductive layer TCL1 is formed may be located inside the region where the first metal layer MTL1 is formed. For example, when viewed with the contact surface between the first transparent conductive layer TCL1 and the first metal layer MTL1 as a reference, at one end of the power line VSL (as an example, the left end or the right end), the end of the first transparent conductive layer TCL1 may be separated from the end of the first metal layer MTL1 by a first distance d1 and located further inside. As an example, in the width direction of the power line VSL, the first metal layer MTL1 may protrude to both sides of the first transparent conductive layer TCL1, and the power line VSL may include a step formed at the boundary between the first metal layer MTL1 and the first transparent conductive layer TCL1.

[0146] The first distance d1 refers to a value corresponding to a process margin that enables the first transparent conductive layer TCL1 to be stably covered by a mask until the etching process for patterning the power line VSL (or the etching process for the multi-layer conductive film for forming the power line VSL) is completed, wherein the etching process for the power line VSL includes the etching process for the first transparent conductive layer TCL1 and the first metal layer MTL1. For example, the first distance d1 may be greater than 0.1 μm. Thus, even if a process error (as an example, a process error within 0.1 μm) occurs during the etching process for patterning the power line VSL, the first transparent conductive layer TCL1 of the power line VSL may be stably covered by a mask until the etching process is completed. Thus, the first transparent conductive layer TCL1 etched earlier than the first metal layer MTL1 may be prevented from being exposed in the etching process of the first metal layer MTL1, thereby preventing contamination of the process chamber and / or contamination of the display panel 110 being manufactured due to byproducts that may be generated due to the exposure of the first transparent conductive layer TCL1. Thus, the display panel 110 can be prevented from being defective and the manufacturing efficiency can be improved. In one embodiment, the first distance d1 can be 0.1 μm to 0.2 μm. By controlling the first distance d1 within 0.2 μm, the thickness of the first transparent conductive layer TCL1 and / or the etching time can be appropriately limited to improve the manufacturing efficiency.

[0147] The pad electrode LDP may be disposed on an insulating layer (as an example, a fifth insulating layer INS5) disposed on the power line VSL. The pad electrode LDP may include a second transparent conductive layer TCL2 and a second metal layer MTL2 disposed on the second transparent conductive layer TCL2. In an embodiment, the pad electrode LDP may further include a third transparent conductive layer TCL3 disposed on the second metal layer MTL2.

[0148] The pad electrode LDP may contact the first transparent conductive layer TCL1 of the power line VSL in the region where the first hole H1 of the fifth insulating layer INS5 is located. For example, the second transparent conductive layer TCL2 of the pad electrode LDP may be formed to penetrate the fifth insulating layer INS5 and may contact the first transparent conductive layer TCL1 through the first hole H1 exposing a portion of the first transparent conductive layer TCL1.

[0149] The second transparent conductive layer TCL2 may include a conductive substance suitable for improving adhesion and / or contact resistance. For example, the second transparent conductive layer TCL2 may include a transparent conductive oxide of at least one element of the conductive substance constituting the first transparent conductive layer TCL1.

[0150] In one embodiment, the first transparent conductive layer TCL1 and the second transparent conductive layer TCL2 may include a transparent conductive oxide containing indium (In). For example, the first transparent conductive layer TCL1 may be formed using indium tin oxide (ITO), indium zinc oxide (IZO) or indium gallium zinc oxide (IGZO), and the second transparent conductive layer TCL2 may be formed using indium tin oxide (ITO). Thus, the contact resistance between the first transparent conductive layer TCL1 and the second transparent conductive layer TCL2 may be reduced.

[0151] As the contact resistance between the first transparent conductive layer TCL1 and the second transparent conductive layer TCL2 decreases, the voltage drop of the pixel voltage supplied to the common electrode CE through the power line VSL can be prevented or reduced. For example, the voltage drop effect of the pixel voltage achieved by connecting the low-resistance power line VSL to the common electrode CE through the pad electrode LDP can be further improved.

[0152] The second metal layer MTL2 may include a metal with high reflectivity. For example, the second metal layer MTL2 may include a metal such as silver (Ag), molybdenum (Mo), titanium (Ti), copper (Cu), aluminum (Al), etc. In one embodiment, the second metal layer MTL2 may be composed of a single metal layer including silver (Ag), but is not limited thereto.

[0153] The third transparent conductive layer TCL3 may include a conductive substance suitable for improving adhesion and / or contact resistance. In addition, the third transparent conductive layer TCL3 may include a conductive substance suitable for optical characteristics (as an example, a resonant structure) required in the pixel electrode AE ​​arranged in the light emitting area EA of each pixel PX and having the same material and / or cross-sectional structure as the pad electrode LDP. As an example, the third transparent conductive layer TCL3 may include a transparent conductive oxide.

[0154] In one embodiment, the second transparent conductive layer TCL2 and the third transparent conductive layer TCL3 may be formed using the same conductive material, thereby improving manufacturing efficiency. For example, the second transparent conductive layer TCL2 and the third transparent conductive layer TCL3 may be formed using indium tin oxide (ITO). In one embodiment, when the second metal layer MTL2 is formed of a single metal layer including silver (Ag), the pixel electrode AE ​​located in the light emitting area EA and the pad electrode LDP located in the non-light emitting area NEA may have a three-layer structure of ITO / Ag / ITO, respectively.

[0155] The common electrode CE may be arranged on an insulating layer (as an example, a pixel definition film PDL) arranged on the pad electrode LDP. The common electrode CE may contact the pad electrode LDP in a region where the second hole H2 of the pixel definition film PDL is located. For example, the common electrode CE may contact the third transparent conductive layer TCL3 of the pad electrode LDP through the second hole H2 formed to penetrate the pixel definition film PDL and expose a portion of the pad electrode LDP (as an example, a portion of the third transparent conductive layer TCL3).

[0156] The common electrode CE may be connected to the power line VSL via the pad electrode LDP. In one embodiment, the display panel 110 may be a front light-emitting display panel, and the common electrode CE may be formed using a transparent conductive material (as an example, a transparent conductive oxide) capable of transmitting light, or may be formed using a translucent conductive material (as an example, a semi-transparent metal material) such as magnesium (Mg), silver (Ag), or an alloy of magnesium (Mg) and silver (Ag).

[0157] In one embodiment, the light emitting element EL may include Figure 4 At least one common layer CML (as an example, a first common layer CML1 and a second common layer CML2) is formed between the pixel electrode AE ​​and the common electrode CE in the entire display area DA, and the common layer CML may be arranged between the pixel definition film PDL and the common electrode CE in the non-emission area NEA. In this case, the second hole H2 may be formed to penetrate the common layer CML and the pixel definition film PDL.

[0158] Figure 6 is a cross-sectional view showing a display panel 110 according to an embodiment. For example, Figure 6 As a cross-sectional view showing a portion of the display area DA of the display panel 110, a portion not including Figure 4 The bridge electrode BRE and the fifth insulating layer INS5 of the display panel 110 are shown in FIG. Figure 6 In the embodiment of Figure 4 and Figure 5The description of the embodiments with similar or identical configurations will be repeated.

[0159] Combination Figures 1 to 5 And refer to Figure 6 , the panel circuit layer PCL may not include the bridge electrode BRE and the fifth insulating layer INS5, and the light emitting element layer LEL may be arranged on the fourth insulating layer INS4. For example, the pixel electrode AE ​​may be arranged on the fourth insulating layer INS4, and may be directly connected to an electrode (as an example, the source electrode SE) of the transistor TR through at least one through hole VH penetrating the fourth insulating layer INS4.

[0160] The pad electrode LDP may be disposed on the fourth insulating layer INS4 together with the pixel electrode AE. For example, the pad electrode LDP may be disposed on the fourth insulating layer INS4 and may be connected to the power line VSL through the first hole H1 penetrating the fourth insulating layer INS4.

[0161] The power line VSL may be disposed on the third insulating layer INS3. For example, the power line VSL may be disposed on the third insulating layer INS3 together with the source electrode SE and / or the drain electrode DE of the transistor TR.

[0162] Figures 7 to 18 is a cross-sectional view showing a method for manufacturing a display device 100 according to an embodiment. For example, Figures 7 to 18 The manufacturing Figure 4 The step of forming the display panel 110 is as follows.

[0163] Combination Figures 1 to 6 And refer to Figure 7 , a substrate SUB including at least a display area DA may be provided. The display area DA may include a light emitting area EA of each pixel PX and a non-light emitting area NEA around the light emitting area EA.

[0164] Afterwards, a transistor TR and a first insulating layer INS1, a second insulating layer INS2, and a third insulating layer INS3 may be formed on the substrate SUB. For example, a first insulating layer INS1, a bottom electrode BE, a second insulating layer INS2, and an active layer ACT may be sequentially formed on the substrate SUB. Afterwards, a gate insulating layer GI and a gate electrode GE may be formed on the active layer ACT. In one embodiment, after an insulating film for forming a gate insulating layer GI and a conductive film for forming a gate electrode GE are sequentially formed on the second insulating layer INS2 on which the active layer ACT and the like are formed, the gate electrode GE and the gate insulating layer GI may be sequentially and / or continuously formed by sequentially and / or continuously etching the conductive film and the insulating film. Afterwards, a third insulating layer INS3 covering the active layer ACT, the gate insulating layer GI, and the gate electrode GE may be formed on the second insulating layer INS2, and a contact hole CNT (as an example, the contact hole CNT exposing the bottom electrode BE, the source region SR of the active layer ACT, and the drain region DR of the active layer ACT, respectively) may be formed in the third insulating layer INS3. Thereafter, a source electrode SE and / or a drain electrode DE may be formed on the third insulating layer INS3 , thereby forming a transistor TR on the substrate SUB.

[0165] In such Figure 6 In the case of manufacturing the display panel 110 including the power line VSL arranged on the third insulating layer INS3 as in the embodiment of the present invention, the power line VSL may be formed on the third insulating layer INS3. For example, the source electrode SE and / or the drain electrode DE and the power line VSL may be formed at the same time.

[0166] Combination Figures 1 to 7 And refer to Figure 8 A fourth insulating layer INS4 may be formed on the third insulating layer INS3, and at least one through hole VH penetrating the fourth insulating layer INS4 may be formed. The fourth insulating layer INS4 may be formed as a pattern covering the conductive layer provided with the source electrode SE and / or the drain electrode DE.

[0167] For example, a fourth insulating layer INS4 covering the source electrode SE and / or the drain electrode DE etc. may be formed on the third insulating layer INS3, and at least one through hole VH penetrating the fourth insulating layer INS4 may be formed (as an example, the through hole VH exposing the source electrode SE). Figure 6 In the case of manufacturing the display panel 110 including the power line VSL disposed on the third insulating layer INS3 as in the embodiment of FIG. 1 , a first hole H1 exposing the power line VSL may be further formed in the fourth insulating layer INS4.

[0168] Combination Figures 1 to 8 And refer to Fig. 9 and Fig.10 , a bridge electrode BRE and a power line VSL may be formed on the fourth insulating layer INS4. Fig. 9 As shown, a conductive film SCDL may be formed on the fourth insulating layer INS4, and the bridge electrode BRE and the power line VSL may be formed by patterning the conductive film SCDL through an etching process using a mask M.

[0169] Figures 11 to 14 by Fig. 9 and Fig.10 An embodiment of a method for forming a power line VSL is shown with reference to the A3 region of FIG. 1 . The bridge electrode BRE may be formed together with the power line VSL in the formation process and etching process of the conductive film SCDL for forming the power line VSL. Figures 1 to 10 And refer to Figures 11 to 14 A method of forming the bridge electrode BRE and the power line VSL will be described in more detail.

[0170] First, if Fig. 9 and Fig.11 As shown, a multi-layered conductive film SCDL may be formed on the substrate SUB formed with the fourth insulating layer INS4, etc. The conductive film SCDL may be formed in the entire display area DA, etc.

[0171] For example, by sequentially forming a first metal layer MTL1 and a first transparent conductive layer TCL1 on the fourth insulating layer INS4, a multi-layer conductive film SCDL including a first metal layer MTL1 and a first transparent conductive layer TCL1 on the first metal layer MTL1 may be formed. In one embodiment, by sequentially forming a first layer MTL11 including a first metal, a second layer MTL12 including a second metal, and a third layer MTL13 including a third metal on the fourth insulating layer INS4, a multi-layer first metal layer MTL1 including a first layer MTL11, a second layer MTL12 on the first layer MTL11, and a third layer MTL13 on the second layer MTL12 may be formed.

[0172] The first metal layer MTL1 may be formed using the conductive materials exemplified above (for example, the first metal, the second metal, and the third metal). The first transparent conductive layer TCL1 may be formed using the conductive materials exemplified above (for example, transparent conductive oxide including indium (In) or the like).

[0173] Thereafter, a mask M may be disposed on a portion of the conductive film SCDL. The mask M may be disposed on the conductive film SCDL corresponding to a pattern shape, size, and / or position of the bridge electrode BRE and the power line VSL to be formed on the display panel 110 .

[0174] Afterwards, if Fig.12 and Fig.13 As shown, the power line VSL may be formed by sequentially etching the first transparent conductive layer TCL1 and the first metal layer MTL1 using a mask M. In addition, the bridge electrode BRE may be formed while forming the power line VSL by sequentially etching the first transparent conductive layer TCL1 and the first metal layer MTL1.

[0175] In an embodiment, Fig.12 As shown, the first transparent conductive layer TCL1 may be over-etched so that the first transparent conductive layer TCL1 has a width smaller than the mask M. For example, the first transparent conductive layer TCL1 may have a width smaller than the mask M and may be etched into a pattern completely blocked by the mask M.

[0176] In one embodiment, the first transparent conductive layer TCL1 may be over-etched by an amount greater than a reduction amount of the mask M generated during etching of the first transparent conductive layer TCL1 and the first metal layer MTL1 (as an example, a reduction amount of the area of ​​the mask M caused by consumption or wear of the mask M). For example, the first transparent conductive layer TCL1 may be over-etched to have a size smaller than the mask M in consideration of an expected reduction amount of the mask M (as an example, smaller than the width and / or area of ​​the mask M).

[0177] In one embodiment, the first transparent conductive layer TCL1 may be etched by a wet etching process using the mask M. Thus, the first transparent conductive layer TCL1 may be isotropically overetched so that the first transparent conductive layer TCL1 has a smaller perimeter than the mask M and is located further inside than the mask M. As an example, when viewed on a plane, the perimeter of the first transparent conductive layer TCL1 may be located inside the periphery of the mask M, and an end of the first transparent conductive layer TCL1 may be spaced apart from an end of the mask M.

[0178] For example, the first transparent conductive layer TCL1 of the power line VSL may be spaced apart from the end of the mask M at one end by a distance corresponding to the lateral shrinkage amount (or retreat amount) of the mask M based on the width direction (as an example, Fig.13 A third distance d3) and a first distance d1 corresponding to a process margin (as an example, Figure 5 and Fig.14 In one embodiment, the first distance d1 may be greater than 0.1 μm, and the first transparent conductive layer TCL1 may be etched to have a lateral deflection amount greater than 0.1 μm than the lateral reduction amount of the mask M (as an example, corresponding to the second distance d2).

[0179] In one embodiment, the degree to which the first transparent conductive layer TCL1 is overetched can be adjusted by adjusting at least one of the thickness of the first transparent conductive layer TCL1 and the etching time. As an example, the first transparent conductive layer TCL1 can be overetched by increasing at least one of the thickness of the first transparent conductive layer TCL1 and the etching time, so that the first transparent conductive layer TCL1 has a width and / or area smaller than the reduced mask M. However, if the thickness of the first transparent conductive layer TCL1 is thin, even if the etching time is increased, the overetching amount of the first transparent conductive layer TCL1 may be limited.

[0180] In one embodiment, the first transparent conductive layer TCL1 may be formed using the same material as the second transparent conductive layer TCL2. As an example, the first transparent conductive layer TCL1 may be formed using indium tin oxide (ITO). Thus, the contact resistance between the first transparent conductive layer TCL1 and the second transparent conductive layer TCL2 may be reduced and / or minimized.

[0181] In one embodiment, the first transparent conductive layer TCL1 may be formed using a substance having a work function similar to that of the substance of the second transparent conductive layer TCL2 and different from that of the second transparent conductive layer TCL2 (as an example, a different substance containing at least one element contained in the substance of the second transparent conductive layer TCL2). As an example, the first transparent conductive layer TCL1 may be formed using indium zinc oxide (IZO) or indium gallium zinc oxide (IGZO). Thus, the first transparent conductive layer TCL1 may be easily over-etched to a target size while reducing and / or minimizing the contact resistance between the first transparent conductive layer TCL1 and the second transparent conductive layer TCL2. For example, in the case of indium tin oxide (ITO), when the first transparent conductive layer TCL1 is formed at a specific thickness (as an example, 150 ) or more, crystallization occurs during film formation, resulting in a sharp decrease in the wet etching rate. On the contrary, in the case of indium zinc oxide (IZO) and indium gallium zinc oxide (IGZO), the wet etching rate does not decrease significantly even if it is formed to a greater thickness. Thus, the first transparent conductive layer TCL1 can be formed with an appropriate or sufficient thickness, and the first transparent conductive layer TCL1 can be appropriately and / or easily over-etched to the target thickness. In addition, compared with indium tin oxide (ITO), indium zinc oxide (IZO) and indium gallium zinc oxide (IGZO) can be substances with high etching resistance to the etching gas (as an example, chlorine gas) used to etch the first metal layer MTL1. Thus, in the case of forming the first transparent conductive layer TCL1 using indium zinc oxide (IZO) or indium gallium zinc oxide (IGZO), the formation of by-products can be more effectively suppressed during the etching process of the first metal layer MTL1. The work function of indium zinc oxide (IZO) (as an example, about 5.0 eV) and the work function of indium gallium zinc oxide (IGZO) (as an example, about 4.5 eV) may have a value similar to the work function of indium tin oxide (ITO) (as an example, about 4.7 eV). Thus, even if the first transparent conductive layer TCL1 is formed using indium zinc oxide (IZO) or indium gallium zinc oxide (IGZO), the contact resistance reduction effect between the power line VSL and the pad electrode LDP can be obtained. For example, in the case where the first transparent conductive layer TCL1 and the second transparent conductive layer TCL2 are formed using indium tin oxide (ITO), the contact resistance between the power line VSL and the pad electrode LDP can be greatly reduced to less than about 1Ω. When the first transparent conductive layer TCL1 is formed using indium tin oxide (ITO) and the second transparent conductive layer TCL2 is formed using indium zinc oxide (IZO) or indium gallium zinc oxide (IGZO), a contact resistance reduction effect corresponding to approximately 80% or more of the contact resistance reduction effect that can be obtained when the first transparent conductive layer TCL1 and the second transparent conductive layer TCL2 are formed using indium tin oxide (ITO) can also be obtained.

[0182] After etching the first transparent conductive layer TCL1, the first metal layer MTL1 may be etched using the mask M without removing the mask M. Fig.13 As shown, a power supply line VSL may be formed.

[0183] In one embodiment, the first metal layer MTL1 may be etched through a dry etching process using the mask M. During the etching process of the first metal layer MTL1 , the mask M may be consumed or worn away to be reduced.

[0184] In one embodiment, the first metal layer MTL1 may be formed to have a relatively small size in the upper portion. For example, the lower portion of the first metal layer MTL1 (as an example, the first layer MTL11) may have a size corresponding to the size (as an example, the width and / or area) of the mask M at the time point when the etching of the first metal layer MTL1 is started, and the upper layer of the first metal layer MTL1 (as an example, the third layer MTL13) may have a size corresponding to the size of the mask M at the time point when the etching of the first metal layer MTL1 is finished. As an example, with the width direction of the first metal layer MTL1 as a reference, at one end of the first metal layer MTL1, the end of the first layer MTL11 may be located at a position separated by a third distance d3 from the end of the third layer MTL13.

[0185] If the etching process of the conductive film SCDL for forming the power line VSL and the like (as an example, the etching process of the first transparent conductive layer TCL1 and the first metal layer MTL1) is completed, Fig.14 As shown, the mask M may be removed. As an example, the mask M may be removed by a lift-off process.

[0186] In the embodiment, the first transparent conductive layer TCL1 is over-etched by a process margin corresponding to the first distance d1 compared to the reduction amount of the mask M, with the side corresponding to one end of the power line VSL as a reference, and therefore, until the etching process of the first metal layer MTL1 is completed, the first transparent conductive layer TCL1 can be stably covered by the mask M in a form with an undercut at the lower portion of the mask M. Thus, during the etching process of the first metal layer MTL1, exposure of the first transparent conductive layer TCL1 to etching gas and / or plasma, etc., can be prevented or minimized. Furthermore, byproducts due to additional etching of the first transparent conductive layer TCL1 in the etching process of the first metal layer MTL1, etc. can be prevented, and chamber contamination and the resulting defect of the display panel 110 can be prevented.

[0187] Thus, based on the bonding surface between the first metal layer MTL1 and the first transparent conductive layer TCL1 , the end of the first transparent conductive layer TCL1 may be located a first distance d1 away from the end of the first metal layer MTL1 (for example, the end of the third layer MTL13 ).

[0188] Combination Figures 1 to 14 And refer to Fig.15 , a fifth insulating layer INS5 may be formed on the fourth insulating layer INS4, and at least one through hole VH penetrating the fifth insulating layer INS5 may be formed. The fifth insulating layer INS5 may be formed as a pattern covering the conductive layer provided with the bridge electrode BRE and / or the power line VSL, etc. Thus, a panel circuit layer PCL may be formed on the substrate SUB.

[0189] For example, a fifth insulating layer INS5 covering the bridge electrode BRE and the power line VSL, etc. may be formed on the fourth insulating layer INS4, and at least one through hole VH penetrating the fifth insulating layer INS5 may be formed. As an example, a through hole VH exposing a portion of the bridge electrode BRE and a first hole H1 exposing a portion of the power line VSL may be formed in the fifth insulating layer INS5. Since the first transparent conductive layer TCL1 is arranged in the upper layer of the power line VSL, a portion of the first transparent conductive layer TCL1 may be exposed in the region where the first hole H1 is formed.

[0190] Combination Figures 1 to 15 And refer to Fig.16 , the pixel electrode AE ​​and the pad electrode LDP can be formed on the panel circuit layer PCL. For example, the pixel electrode AE ​​and the pad electrode LDP can be formed by a conductive film (as an example, Figure 4 The pixel electrode AE ​​and the pad electrode LDP are formed on the fifth insulating layer INS5 by a film forming process of a multilayer conductive film including a second transparent conductive layer TCL2, a second metal layer MTL2 on the second transparent conductive layer TCL2, and a third transparent conductive layer TCL3 on the second metal layer MTL2 and an etching process of the conductive film.

[0191] The pixel electrode AE ​​may overlap the bridge electrode BRE and be connected to the bridge electrode BRE through a via hole VH formed on the bridge electrode BRE.

[0192] The pad electrode LDP may overlap the power line VSL and be connected to the power line VSL through a first hole H1 formed on the power line VSL. For example, the pad electrode LDP may contact the first transparent conductive layer TCL1 of the power line VSL in a region where the first hole H1 is located.

[0193] In an embodiment, the pad electrode LDP may include a second transparent conductive layer TCL2 in contact with the first transparent conductive layer TCL1 of the power line VSL. The first transparent conductive layer TCL1 and the second transparent conductive layer TCL2 may be formed using transparent conductive oxides containing one or more elements that are the same as each other. For example, the first transparent conductive layer TCL1 and the second transparent conductive layer TCL2 may be formed using transparent conductive oxides containing indium (In). In an embodiment, the first transparent conductive layer TCL1 may be formed using indium tin oxide (ITO), indium zinc oxide (IZO), or indium gallium zinc oxide (IGZO), and the second transparent conductive layer TCL2 may be formed using indium tin oxide (ITO).

[0194] Combination Figures 1 to 16 And refer to Fig.17, a pixel definition film PDL may be formed on the panel circuit layer PCL, the pixel electrode AE, and the pad electrode LDP. The pixel definition film PDL has an opening corresponding to the light-emitting area EA, and may be formed to expose the pixel electrode AE ​​in the light-emitting area EA. In one embodiment, the pixel definition film PDL and the spacer SPC may be formed simultaneously using a halftone mask, etc., but are not limited thereto. After forming the pixel definition film PDL, a light-emitting layer EML may be formed on the pixel electrode AE. In one embodiment, the light-emitting layer EML may be formed at least in the light-emitting area EA. In one embodiment, at least one common layer CML may be formed before and after forming the light-emitting layer EML. As an example, after forming the pixel definition film PDL, a first common layer CML1, a light-emitting layer EML, and a second common layer CML2 may be sequentially formed on the pixel electrode AE.

[0195] In one embodiment, the second hole H2 may be formed in the pixel definition film PDL in a manner that exposes a portion of the pad electrode LDP. In one embodiment, the second hole H2 may be formed by a laser drilling process. For example, an organic film including the pixel definition film PDL is removed on a portion of the pad electrode LDP using a laser, so that the second hole H2 may be formed in the pixel definition film PDL. The second hole H2 may be formed before or after the formation of the light emitting layer EML. As an example, the second hole H2 may be formed after the formation of the second common layer CML2, and may be formed to pass through the pixel definition film PDL, the first common layer CML1, and the second common layer CML2.

[0196] Combination Figures 1 to 17 And refer to Fig.18 , a common electrode CE may be formed on the pixel definition layer PDL and the light emitting layer EML. Thus, a light emitting element layer LEL may be formed on the panel circuit layer PCL.

[0197] The common electrode CE may overlap the pixel electrode AE ​​and the emission layer EML in the emission area EA, and may overlap the pad electrode LDP in the non-emission area NEA. The common electrode CE may contact the pad electrode LDP in a region where the second hole H2 is located.

[0198] The display panel 110 includes Figure 4 In the case of the encapsulation layer ENL shown in FIG. 1 , the encapsulation layer ENL may be formed on the light emitting element layer LEL. In this way, the display panel 110 may be manufactured.

[0199] The embodiments of the present invention are described above with reference to the accompanying drawings, but a person with ordinary knowledge in the technical field to which the present invention belongs can understand that the present invention can be implemented in other specific forms without changing the technical concept or essential features of the present invention. Therefore, it should be understood that the embodiments described above are exemplary in all aspects and are not restrictive.

Claims

1. A display device, comprising: a substrate including a display area; A power supply line, arranged in the display area on the substrate, and comprising a first metal layer and a first transparent conductive layer on the first metal layer; an insulating layer disposed on the power line and comprising a first hole exposing a portion of the first transparent conductive layer; a pad electrode disposed on the insulating layer and including a second transparent conductive layer in contact with the first transparent conductive layer in a region where the first hole is located; a pixel definition film disposed on the pad electrode and including a second hole exposing a portion of the pad electrode; as well as a common electrode disposed on the pixel definition film and contacting the pad electrode in a region where the second hole is located, The first transparent conductive layer has a width narrower than that of the first metal layer, and at one end of the power line, an end of the first transparent conductive layer is separated from an end of the first metal layer by a first distance.

2. The display device according to claim 1, wherein: The first distance is greater than or equal to 0.1 μm.

3. The display device according to claim 2, wherein: The first distance is 0.1 μm to 0.2 μm.

4. The display device according to claim 1, wherein: The first transparent conductive layer and the second transparent conductive layer include one or more elements that are the same as each other.

5. The display device according to claim 4, wherein: The first transparent conductive layer and the second transparent conductive layer include a transparent conductive oxide containing indium.

6. The display device according to claim 5, wherein: The first transparent conductive layer is formed of indium tin oxide, indium zinc oxide or indium gallium zinc oxide. The second transparent conductive layer is formed of indium tin oxide.

7. The display device according to claim 1, wherein: In a width direction of the power line, the first metal layer protrudes toward both sides of the first transparent conductive layer.

8. The display device according to claim 1, wherein: The first metal layer has a multi-layered structure including a first layer including a first metal, a second layer disposed on the first layer and including a second metal, and a third layer disposed on the second layer and including a third metal.

9. The display device according to claim 8, wherein: The first metal and the third metal are titanium, The second metal is aluminum.

10. The display device according to claim 1, wherein: The pad electrode further includes: a second metal layer disposed on the second transparent conductive layer; and a third transparent conductive layer disposed on the second metal layer.

11. The display device according to claim 10, wherein: The second transparent conductive layer and the third transparent conductive layer include indium tin oxide, The second metal layer includes silver.

12. The display device according to claim 1, further comprising: A panel circuit layer, arranged on the substrate and comprising transistors and the power lines located in the display area; a light emitting element layer arranged in the display area on the panel circuit layer, and comprising a pixel electrode arranged in the same layer as the pad electrode and separated from the pad electrode, a light emitting layer arranged between the pixel electrode and the common electrode, the common electrode and the pixel definition film; as well as The encapsulation layer is arranged on the light emitting element layer.

13. The display device according to claim 12, wherein: The pixel definition film forms an opening in a region where the pixel electrode overlaps the light emitting layer in the light emitting region to expose the pixel electrode.

14. The display device according to claim 13, wherein: The display area also includes a non-luminous area around the luminous area. The common electrode is arranged in the entire display area, The pad electrode and the second hole are located in the non-light emitting area.

15. The display device according to claim 14, further comprising: at least one common layer disposed between the pixel definition film and the common electrode and overlapping the pad electrode, Wherein, the second hole penetrates the pixel definition film and the at least one common layer.

16. A method for manufacturing a display device, comprising the following steps: Forming a multi-layer conductive film by sequentially forming a first metal layer and a first transparent conductive layer on a substrate; disposing a mask on a portion of the conductive film; forming a power line by sequentially etching the first transparent conductive layer and the first metal layer using the mask; forming an insulating layer on the power line, and forming a first hole in the insulating layer that exposes a portion of the first transparent conductive layer; forming a pad electrode on the insulating layer that overlaps the power line and contacts the first transparent conductive layer in a region where the first hole is located; forming a pixel definition film and at least one common layer on the pad electrode, and forming a second hole exposing a portion of the pad electrode in the pixel definition film and the at least one common layer; as well as forming a common electrode on the pixel definition film so as to overlap with the pad electrode and contact the pad electrode in a region where the second hole is located, The step of etching the first transparent conductive layer includes the following step: over-etching the first transparent conductive layer by an amount greater than a shrinkage amount of the mask generated during etching of the first transparent conductive layer and the first metal layer.

17. The method for manufacturing a display device according to claim 16, wherein: The first transparent conductive layer has a width smaller than that of the mask, and is etched into a pattern in which an upper surface thereof is completely blocked by the mask.

18. The method for manufacturing a display device according to claim 16, wherein: The first transparent conductive layer is etched to have a lateral deviation amount that is greater than a lateral reduction amount of the mask by 0.1 μm or more.

19. The method for manufacturing a display device according to claim 16, wherein: The pad electrode includes a second transparent conductive layer in contact with the first transparent conductive layer, The first transparent conductive layer and the second transparent conductive layer are formed using transparent conductive oxides containing one or more elements that are the same as each other.

20. The method for manufacturing a display device according to claim 19, wherein: The first transparent conductive layer is formed of indium tin oxide, indium zinc oxide, or indium gallium zinc oxide. The second transparent conductive layer is formed of indium tin oxide.

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